1 /*
2 * Copyright © 2006-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/time.h>
25
26 #include "intel_atomic.h"
27 #include "intel_bw.h"
28 #include "intel_cdclk.h"
29 #include "intel_de.h"
30 #include "intel_display_types.h"
31 #include "intel_psr.h"
32 #include "intel_sideband.h"
33
34 /**
35 * DOC: CDCLK / RAWCLK
36 *
37 * The display engine uses several different clocks to do its work. There
38 * are two main clocks involved that aren't directly related to the actual
39 * pixel clock or any symbol/bit clock of the actual output port. These
40 * are the core display clock (CDCLK) and RAWCLK.
41 *
42 * CDCLK clocks most of the display pipe logic, and thus its frequency
43 * must be high enough to support the rate at which pixels are flowing
44 * through the pipes. Downscaling must also be accounted as that increases
45 * the effective pixel rate.
46 *
47 * On several platforms the CDCLK frequency can be changed dynamically
48 * to minimize power consumption for a given display configuration.
49 * Typically changes to the CDCLK frequency require all the display pipes
50 * to be shut down while the frequency is being changed.
51 *
52 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
53 * DMC will not change the active CDCLK frequency however, so that part
54 * will still be performed by the driver directly.
55 *
56 * RAWCLK is a fixed frequency clock, often used by various auxiliary
57 * blocks such as AUX CH or backlight PWM. Hence the only thing we
58 * really need to know about RAWCLK is its frequency so that various
59 * dividers can be programmed correctly.
60 */
61
fixed_133mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)62 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
63 struct intel_cdclk_config *cdclk_config)
64 {
65 cdclk_config->cdclk = 133333;
66 }
67
fixed_200mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)68 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
69 struct intel_cdclk_config *cdclk_config)
70 {
71 cdclk_config->cdclk = 200000;
72 }
73
fixed_266mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)74 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
75 struct intel_cdclk_config *cdclk_config)
76 {
77 cdclk_config->cdclk = 266667;
78 }
79
fixed_333mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)80 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
81 struct intel_cdclk_config *cdclk_config)
82 {
83 cdclk_config->cdclk = 333333;
84 }
85
fixed_400mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)86 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
87 struct intel_cdclk_config *cdclk_config)
88 {
89 cdclk_config->cdclk = 400000;
90 }
91
fixed_450mhz_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)92 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
93 struct intel_cdclk_config *cdclk_config)
94 {
95 cdclk_config->cdclk = 450000;
96 }
97
i85x_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)98 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
99 struct intel_cdclk_config *cdclk_config)
100 {
101 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
102 u16 hpllcc = 0;
103
104 /*
105 * 852GM/852GMV only supports 133 MHz and the HPLLCC
106 * encoding is different :(
107 * FIXME is this the right way to detect 852GM/852GMV?
108 */
109 if (pdev->revision == 0x1) {
110 cdclk_config->cdclk = 133333;
111 return;
112 }
113
114 pci_bus_read_config_word(pdev->bus,
115 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
116
117 /* Assume that the hardware is in the high speed state. This
118 * should be the default.
119 */
120 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
121 case GC_CLOCK_133_200:
122 case GC_CLOCK_133_200_2:
123 case GC_CLOCK_100_200:
124 cdclk_config->cdclk = 200000;
125 break;
126 case GC_CLOCK_166_250:
127 cdclk_config->cdclk = 250000;
128 break;
129 case GC_CLOCK_100_133:
130 cdclk_config->cdclk = 133333;
131 break;
132 case GC_CLOCK_133_266:
133 case GC_CLOCK_133_266_2:
134 case GC_CLOCK_166_266:
135 cdclk_config->cdclk = 266667;
136 break;
137 }
138 }
139
i915gm_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)140 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
141 struct intel_cdclk_config *cdclk_config)
142 {
143 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
144 u16 gcfgc = 0;
145
146 pci_read_config_word(pdev, GCFGC, &gcfgc);
147
148 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
149 cdclk_config->cdclk = 133333;
150 return;
151 }
152
153 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
154 case GC_DISPLAY_CLOCK_333_320_MHZ:
155 cdclk_config->cdclk = 333333;
156 break;
157 default:
158 case GC_DISPLAY_CLOCK_190_200_MHZ:
159 cdclk_config->cdclk = 190000;
160 break;
161 }
162 }
163
i945gm_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)164 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
165 struct intel_cdclk_config *cdclk_config)
166 {
167 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
168 u16 gcfgc = 0;
169
170 pci_read_config_word(pdev, GCFGC, &gcfgc);
171
172 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
173 cdclk_config->cdclk = 133333;
174 return;
175 }
176
177 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
178 case GC_DISPLAY_CLOCK_333_320_MHZ:
179 cdclk_config->cdclk = 320000;
180 break;
181 default:
182 case GC_DISPLAY_CLOCK_190_200_MHZ:
183 cdclk_config->cdclk = 200000;
184 break;
185 }
186 }
187
intel_hpll_vco(struct drm_i915_private * dev_priv)188 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
189 {
190 static const unsigned int blb_vco[8] = {
191 [0] = 3200000,
192 [1] = 4000000,
193 [2] = 5333333,
194 [3] = 4800000,
195 [4] = 6400000,
196 };
197 static const unsigned int pnv_vco[8] = {
198 [0] = 3200000,
199 [1] = 4000000,
200 [2] = 5333333,
201 [3] = 4800000,
202 [4] = 2666667,
203 };
204 static const unsigned int cl_vco[8] = {
205 [0] = 3200000,
206 [1] = 4000000,
207 [2] = 5333333,
208 [3] = 6400000,
209 [4] = 3333333,
210 [5] = 3566667,
211 [6] = 4266667,
212 };
213 static const unsigned int elk_vco[8] = {
214 [0] = 3200000,
215 [1] = 4000000,
216 [2] = 5333333,
217 [3] = 4800000,
218 };
219 static const unsigned int ctg_vco[8] = {
220 [0] = 3200000,
221 [1] = 4000000,
222 [2] = 5333333,
223 [3] = 6400000,
224 [4] = 2666667,
225 [5] = 4266667,
226 };
227 const unsigned int *vco_table;
228 unsigned int vco;
229 u8 tmp = 0;
230
231 /* FIXME other chipsets? */
232 if (IS_GM45(dev_priv))
233 vco_table = ctg_vco;
234 else if (IS_G45(dev_priv))
235 vco_table = elk_vco;
236 else if (IS_I965GM(dev_priv))
237 vco_table = cl_vco;
238 else if (IS_PINEVIEW(dev_priv))
239 vco_table = pnv_vco;
240 else if (IS_G33(dev_priv))
241 vco_table = blb_vco;
242 else
243 return 0;
244
245 tmp = intel_de_read(dev_priv,
246 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
247
248 vco = vco_table[tmp & 0x7];
249 if (vco == 0)
250 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
251 tmp);
252 else
253 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
254
255 return vco;
256 }
257
g33_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)258 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
259 struct intel_cdclk_config *cdclk_config)
260 {
261 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
262 static const u8 div_3200[] = { 12, 10, 8, 7, 5, 16 };
263 static const u8 div_4000[] = { 14, 12, 10, 8, 6, 20 };
264 static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
265 static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
266 const u8 *div_table;
267 unsigned int cdclk_sel;
268 u16 tmp = 0;
269
270 cdclk_config->vco = intel_hpll_vco(dev_priv);
271
272 pci_read_config_word(pdev, GCFGC, &tmp);
273
274 cdclk_sel = (tmp >> 4) & 0x7;
275
276 if (cdclk_sel >= ARRAY_SIZE(div_3200))
277 goto fail;
278
279 switch (cdclk_config->vco) {
280 case 3200000:
281 div_table = div_3200;
282 break;
283 case 4000000:
284 div_table = div_4000;
285 break;
286 case 4800000:
287 div_table = div_4800;
288 break;
289 case 5333333:
290 div_table = div_5333;
291 break;
292 default:
293 goto fail;
294 }
295
296 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
297 div_table[cdclk_sel]);
298 return;
299
300 fail:
301 drm_err(&dev_priv->drm,
302 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
303 cdclk_config->vco, tmp);
304 cdclk_config->cdclk = 190476;
305 }
306
pnv_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)307 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
308 struct intel_cdclk_config *cdclk_config)
309 {
310 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
311 u16 gcfgc = 0;
312
313 pci_read_config_word(pdev, GCFGC, &gcfgc);
314
315 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
316 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
317 cdclk_config->cdclk = 266667;
318 break;
319 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
320 cdclk_config->cdclk = 333333;
321 break;
322 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
323 cdclk_config->cdclk = 444444;
324 break;
325 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
326 cdclk_config->cdclk = 200000;
327 break;
328 default:
329 drm_err(&dev_priv->drm,
330 "Unknown pnv display core clock 0x%04x\n", gcfgc);
331 fallthrough;
332 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
333 cdclk_config->cdclk = 133333;
334 break;
335 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
336 cdclk_config->cdclk = 166667;
337 break;
338 }
339 }
340
i965gm_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)341 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
342 struct intel_cdclk_config *cdclk_config)
343 {
344 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
345 static const u8 div_3200[] = { 16, 10, 8 };
346 static const u8 div_4000[] = { 20, 12, 10 };
347 static const u8 div_5333[] = { 24, 16, 14 };
348 const u8 *div_table;
349 unsigned int cdclk_sel;
350 u16 tmp = 0;
351
352 cdclk_config->vco = intel_hpll_vco(dev_priv);
353
354 pci_read_config_word(pdev, GCFGC, &tmp);
355
356 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
357
358 if (cdclk_sel >= ARRAY_SIZE(div_3200))
359 goto fail;
360
361 switch (cdclk_config->vco) {
362 case 3200000:
363 div_table = div_3200;
364 break;
365 case 4000000:
366 div_table = div_4000;
367 break;
368 case 5333333:
369 div_table = div_5333;
370 break;
371 default:
372 goto fail;
373 }
374
375 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
376 div_table[cdclk_sel]);
377 return;
378
379 fail:
380 drm_err(&dev_priv->drm,
381 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
382 cdclk_config->vco, tmp);
383 cdclk_config->cdclk = 200000;
384 }
385
gm45_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)386 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
387 struct intel_cdclk_config *cdclk_config)
388 {
389 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
390 unsigned int cdclk_sel;
391 u16 tmp = 0;
392
393 cdclk_config->vco = intel_hpll_vco(dev_priv);
394
395 pci_read_config_word(pdev, GCFGC, &tmp);
396
397 cdclk_sel = (tmp >> 12) & 0x1;
398
399 switch (cdclk_config->vco) {
400 case 2666667:
401 case 4000000:
402 case 5333333:
403 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
404 break;
405 case 3200000:
406 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
407 break;
408 default:
409 drm_err(&dev_priv->drm,
410 "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
411 cdclk_config->vco, tmp);
412 cdclk_config->cdclk = 222222;
413 break;
414 }
415 }
416
hsw_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)417 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
418 struct intel_cdclk_config *cdclk_config)
419 {
420 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
421 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
422
423 if (lcpll & LCPLL_CD_SOURCE_FCLK)
424 cdclk_config->cdclk = 800000;
425 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
426 cdclk_config->cdclk = 450000;
427 else if (freq == LCPLL_CLK_FREQ_450)
428 cdclk_config->cdclk = 450000;
429 else if (IS_HSW_ULT(dev_priv))
430 cdclk_config->cdclk = 337500;
431 else
432 cdclk_config->cdclk = 540000;
433 }
434
vlv_calc_cdclk(struct drm_i915_private * dev_priv,int min_cdclk)435 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
436 {
437 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
438 333333 : 320000;
439
440 /*
441 * We seem to get an unstable or solid color picture at 200MHz.
442 * Not sure what's wrong. For now use 200MHz only when all pipes
443 * are off.
444 */
445 if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
446 return 400000;
447 else if (min_cdclk > 266667)
448 return freq_320;
449 else if (min_cdclk > 0)
450 return 266667;
451 else
452 return 200000;
453 }
454
vlv_calc_voltage_level(struct drm_i915_private * dev_priv,int cdclk)455 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
456 {
457 if (IS_VALLEYVIEW(dev_priv)) {
458 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
459 return 2;
460 else if (cdclk >= 266667)
461 return 1;
462 else
463 return 0;
464 } else {
465 /*
466 * Specs are full of misinformation, but testing on actual
467 * hardware has shown that we just need to write the desired
468 * CCK divider into the Punit register.
469 */
470 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
471 }
472 }
473
vlv_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)474 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
475 struct intel_cdclk_config *cdclk_config)
476 {
477 u32 val;
478
479 vlv_iosf_sb_get(dev_priv,
480 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
481
482 cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
483 cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
484 CCK_DISPLAY_CLOCK_CONTROL,
485 cdclk_config->vco);
486
487 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
488
489 vlv_iosf_sb_put(dev_priv,
490 BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
491
492 if (IS_VALLEYVIEW(dev_priv))
493 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
494 DSPFREQGUAR_SHIFT;
495 else
496 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
497 DSPFREQGUAR_SHIFT_CHV;
498 }
499
vlv_program_pfi_credits(struct drm_i915_private * dev_priv)500 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
501 {
502 unsigned int credits, default_credits;
503
504 if (IS_CHERRYVIEW(dev_priv))
505 default_credits = PFI_CREDIT(12);
506 else
507 default_credits = PFI_CREDIT(8);
508
509 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
510 /* CHV suggested value is 31 or 63 */
511 if (IS_CHERRYVIEW(dev_priv))
512 credits = PFI_CREDIT_63;
513 else
514 credits = PFI_CREDIT(15);
515 } else {
516 credits = default_credits;
517 }
518
519 /*
520 * WA - write default credits before re-programming
521 * FIXME: should we also set the resend bit here?
522 */
523 intel_de_write(dev_priv, GCI_CONTROL,
524 VGA_FAST_MODE_DISABLE | default_credits);
525
526 intel_de_write(dev_priv, GCI_CONTROL,
527 VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
528
529 /*
530 * FIXME is this guaranteed to clear
531 * immediately or should we poll for it?
532 */
533 drm_WARN_ON(&dev_priv->drm,
534 intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
535 }
536
vlv_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)537 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
538 const struct intel_cdclk_config *cdclk_config,
539 enum pipe pipe)
540 {
541 int cdclk = cdclk_config->cdclk;
542 u32 val, cmd = cdclk_config->voltage_level;
543 intel_wakeref_t wakeref;
544
545 switch (cdclk) {
546 case 400000:
547 case 333333:
548 case 320000:
549 case 266667:
550 case 200000:
551 break;
552 default:
553 MISSING_CASE(cdclk);
554 return;
555 }
556
557 /* There are cases where we can end up here with power domains
558 * off and a CDCLK frequency other than the minimum, like when
559 * issuing a modeset without actually changing any display after
560 * a system suspend. So grab the display core domain, which covers
561 * the HW blocks needed for the following programming.
562 */
563 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
564
565 vlv_iosf_sb_get(dev_priv,
566 BIT(VLV_IOSF_SB_CCK) |
567 BIT(VLV_IOSF_SB_BUNIT) |
568 BIT(VLV_IOSF_SB_PUNIT));
569
570 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
571 val &= ~DSPFREQGUAR_MASK;
572 val |= (cmd << DSPFREQGUAR_SHIFT);
573 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
574 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
575 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
576 50)) {
577 drm_err(&dev_priv->drm,
578 "timed out waiting for CDclk change\n");
579 }
580
581 if (cdclk == 400000) {
582 u32 divider;
583
584 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
585 cdclk) - 1;
586
587 /* adjust cdclk divider */
588 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
589 val &= ~CCK_FREQUENCY_VALUES;
590 val |= divider;
591 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
592
593 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
594 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
595 50))
596 drm_err(&dev_priv->drm,
597 "timed out waiting for CDclk change\n");
598 }
599
600 /* adjust self-refresh exit latency value */
601 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
602 val &= ~0x7f;
603
604 /*
605 * For high bandwidth configs, we set a higher latency in the bunit
606 * so that the core display fetch happens in time to avoid underruns.
607 */
608 if (cdclk == 400000)
609 val |= 4500 / 250; /* 4.5 usec */
610 else
611 val |= 3000 / 250; /* 3.0 usec */
612 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
613
614 vlv_iosf_sb_put(dev_priv,
615 BIT(VLV_IOSF_SB_CCK) |
616 BIT(VLV_IOSF_SB_BUNIT) |
617 BIT(VLV_IOSF_SB_PUNIT));
618
619 intel_update_cdclk(dev_priv);
620
621 vlv_program_pfi_credits(dev_priv);
622
623 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
624 }
625
chv_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)626 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
627 const struct intel_cdclk_config *cdclk_config,
628 enum pipe pipe)
629 {
630 int cdclk = cdclk_config->cdclk;
631 u32 val, cmd = cdclk_config->voltage_level;
632 intel_wakeref_t wakeref;
633
634 switch (cdclk) {
635 case 333333:
636 case 320000:
637 case 266667:
638 case 200000:
639 break;
640 default:
641 MISSING_CASE(cdclk);
642 return;
643 }
644
645 /* There are cases where we can end up here with power domains
646 * off and a CDCLK frequency other than the minimum, like when
647 * issuing a modeset without actually changing any display after
648 * a system suspend. So grab the display core domain, which covers
649 * the HW blocks needed for the following programming.
650 */
651 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
652
653 vlv_punit_get(dev_priv);
654 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
655 val &= ~DSPFREQGUAR_MASK_CHV;
656 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
657 vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
658 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
659 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
660 50)) {
661 drm_err(&dev_priv->drm,
662 "timed out waiting for CDclk change\n");
663 }
664
665 vlv_punit_put(dev_priv);
666
667 intel_update_cdclk(dev_priv);
668
669 vlv_program_pfi_credits(dev_priv);
670
671 intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
672 }
673
bdw_calc_cdclk(int min_cdclk)674 static int bdw_calc_cdclk(int min_cdclk)
675 {
676 if (min_cdclk > 540000)
677 return 675000;
678 else if (min_cdclk > 450000)
679 return 540000;
680 else if (min_cdclk > 337500)
681 return 450000;
682 else
683 return 337500;
684 }
685
bdw_calc_voltage_level(int cdclk)686 static u8 bdw_calc_voltage_level(int cdclk)
687 {
688 switch (cdclk) {
689 default:
690 case 337500:
691 return 2;
692 case 450000:
693 return 0;
694 case 540000:
695 return 1;
696 case 675000:
697 return 3;
698 }
699 }
700
bdw_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)701 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
702 struct intel_cdclk_config *cdclk_config)
703 {
704 u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
705 u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
706
707 if (lcpll & LCPLL_CD_SOURCE_FCLK)
708 cdclk_config->cdclk = 800000;
709 else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
710 cdclk_config->cdclk = 450000;
711 else if (freq == LCPLL_CLK_FREQ_450)
712 cdclk_config->cdclk = 450000;
713 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
714 cdclk_config->cdclk = 540000;
715 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
716 cdclk_config->cdclk = 337500;
717 else
718 cdclk_config->cdclk = 675000;
719
720 /*
721 * Can't read this out :( Let's assume it's
722 * at least what the CDCLK frequency requires.
723 */
724 cdclk_config->voltage_level =
725 bdw_calc_voltage_level(cdclk_config->cdclk);
726 }
727
bdw_cdclk_freq_sel(int cdclk)728 static u32 bdw_cdclk_freq_sel(int cdclk)
729 {
730 switch (cdclk) {
731 default:
732 MISSING_CASE(cdclk);
733 fallthrough;
734 case 337500:
735 return LCPLL_CLK_FREQ_337_5_BDW;
736 case 450000:
737 return LCPLL_CLK_FREQ_450;
738 case 540000:
739 return LCPLL_CLK_FREQ_54O_BDW;
740 case 675000:
741 return LCPLL_CLK_FREQ_675_BDW;
742 }
743 }
744
bdw_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)745 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
746 const struct intel_cdclk_config *cdclk_config,
747 enum pipe pipe)
748 {
749 int cdclk = cdclk_config->cdclk;
750 int ret;
751
752 if (drm_WARN(&dev_priv->drm,
753 (intel_de_read(dev_priv, LCPLL_CTL) &
754 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
755 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
756 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
757 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
758 "trying to change cdclk frequency with cdclk not enabled\n"))
759 return;
760
761 ret = sandybridge_pcode_write(dev_priv,
762 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
763 if (ret) {
764 drm_err(&dev_priv->drm,
765 "failed to inform pcode about cdclk change\n");
766 return;
767 }
768
769 intel_de_rmw(dev_priv, LCPLL_CTL,
770 0, LCPLL_CD_SOURCE_FCLK);
771
772 /*
773 * According to the spec, it should be enough to poll for this 1 us.
774 * However, extensive testing shows that this can take longer.
775 */
776 if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
777 LCPLL_CD_SOURCE_FCLK_DONE, 100))
778 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
779
780 intel_de_rmw(dev_priv, LCPLL_CTL,
781 LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
782
783 intel_de_rmw(dev_priv, LCPLL_CTL,
784 LCPLL_CD_SOURCE_FCLK, 0);
785
786 if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
787 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
788 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
789
790 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
791 cdclk_config->voltage_level);
792
793 intel_de_write(dev_priv, CDCLK_FREQ,
794 DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
795
796 intel_update_cdclk(dev_priv);
797 }
798
skl_calc_cdclk(int min_cdclk,int vco)799 static int skl_calc_cdclk(int min_cdclk, int vco)
800 {
801 if (vco == 8640000) {
802 if (min_cdclk > 540000)
803 return 617143;
804 else if (min_cdclk > 432000)
805 return 540000;
806 else if (min_cdclk > 308571)
807 return 432000;
808 else
809 return 308571;
810 } else {
811 if (min_cdclk > 540000)
812 return 675000;
813 else if (min_cdclk > 450000)
814 return 540000;
815 else if (min_cdclk > 337500)
816 return 450000;
817 else
818 return 337500;
819 }
820 }
821
skl_calc_voltage_level(int cdclk)822 static u8 skl_calc_voltage_level(int cdclk)
823 {
824 if (cdclk > 540000)
825 return 3;
826 else if (cdclk > 450000)
827 return 2;
828 else if (cdclk > 337500)
829 return 1;
830 else
831 return 0;
832 }
833
skl_dpll0_update(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)834 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
835 struct intel_cdclk_config *cdclk_config)
836 {
837 u32 val;
838
839 cdclk_config->ref = 24000;
840 cdclk_config->vco = 0;
841
842 val = intel_de_read(dev_priv, LCPLL1_CTL);
843 if ((val & LCPLL_PLL_ENABLE) == 0)
844 return;
845
846 if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
847 return;
848
849 val = intel_de_read(dev_priv, DPLL_CTRL1);
850
851 if (drm_WARN_ON(&dev_priv->drm,
852 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
853 DPLL_CTRL1_SSC(SKL_DPLL0) |
854 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
855 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
856 return;
857
858 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
859 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
860 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
861 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
862 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
863 cdclk_config->vco = 8100000;
864 break;
865 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
866 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
867 cdclk_config->vco = 8640000;
868 break;
869 default:
870 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
871 break;
872 }
873 }
874
skl_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)875 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
876 struct intel_cdclk_config *cdclk_config)
877 {
878 u32 cdctl;
879
880 skl_dpll0_update(dev_priv, cdclk_config);
881
882 cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
883
884 if (cdclk_config->vco == 0)
885 goto out;
886
887 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
888
889 if (cdclk_config->vco == 8640000) {
890 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
891 case CDCLK_FREQ_450_432:
892 cdclk_config->cdclk = 432000;
893 break;
894 case CDCLK_FREQ_337_308:
895 cdclk_config->cdclk = 308571;
896 break;
897 case CDCLK_FREQ_540:
898 cdclk_config->cdclk = 540000;
899 break;
900 case CDCLK_FREQ_675_617:
901 cdclk_config->cdclk = 617143;
902 break;
903 default:
904 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
905 break;
906 }
907 } else {
908 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
909 case CDCLK_FREQ_450_432:
910 cdclk_config->cdclk = 450000;
911 break;
912 case CDCLK_FREQ_337_308:
913 cdclk_config->cdclk = 337500;
914 break;
915 case CDCLK_FREQ_540:
916 cdclk_config->cdclk = 540000;
917 break;
918 case CDCLK_FREQ_675_617:
919 cdclk_config->cdclk = 675000;
920 break;
921 default:
922 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
923 break;
924 }
925 }
926
927 out:
928 /*
929 * Can't read this out :( Let's assume it's
930 * at least what the CDCLK frequency requires.
931 */
932 cdclk_config->voltage_level =
933 skl_calc_voltage_level(cdclk_config->cdclk);
934 }
935
936 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
skl_cdclk_decimal(int cdclk)937 static int skl_cdclk_decimal(int cdclk)
938 {
939 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
940 }
941
skl_set_preferred_cdclk_vco(struct drm_i915_private * dev_priv,int vco)942 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
943 int vco)
944 {
945 bool changed = dev_priv->skl_preferred_vco_freq != vco;
946
947 dev_priv->skl_preferred_vco_freq = vco;
948
949 if (changed)
950 intel_update_max_cdclk(dev_priv);
951 }
952
skl_dpll0_link_rate(struct drm_i915_private * dev_priv,int vco)953 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
954 {
955 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
956
957 /*
958 * We always enable DPLL0 with the lowest link rate possible, but still
959 * taking into account the VCO required to operate the eDP panel at the
960 * desired frequency. The usual DP link rates operate with a VCO of
961 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
962 * The modeset code is responsible for the selection of the exact link
963 * rate later on, with the constraint of choosing a frequency that
964 * works with vco.
965 */
966 if (vco == 8640000)
967 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
968 else
969 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
970 }
971
skl_dpll0_enable(struct drm_i915_private * dev_priv,int vco)972 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
973 {
974 intel_de_rmw(dev_priv, DPLL_CTRL1,
975 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
976 DPLL_CTRL1_SSC(SKL_DPLL0) |
977 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
978 DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
979 skl_dpll0_link_rate(dev_priv, vco));
980 intel_de_posting_read(dev_priv, DPLL_CTRL1);
981
982 intel_de_rmw(dev_priv, LCPLL1_CTL,
983 0, LCPLL_PLL_ENABLE);
984
985 if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
986 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
987
988 dev_priv->cdclk.hw.vco = vco;
989
990 /* We'll want to keep using the current vco from now on. */
991 skl_set_preferred_cdclk_vco(dev_priv, vco);
992 }
993
skl_dpll0_disable(struct drm_i915_private * dev_priv)994 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
995 {
996 intel_de_rmw(dev_priv, LCPLL1_CTL,
997 LCPLL_PLL_ENABLE, 0);
998
999 if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1000 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1001
1002 dev_priv->cdclk.hw.vco = 0;
1003 }
1004
skl_cdclk_freq_sel(struct drm_i915_private * dev_priv,int cdclk,int vco)1005 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
1006 int cdclk, int vco)
1007 {
1008 switch (cdclk) {
1009 default:
1010 drm_WARN_ON(&dev_priv->drm,
1011 cdclk != dev_priv->cdclk.hw.bypass);
1012 drm_WARN_ON(&dev_priv->drm, vco != 0);
1013 fallthrough;
1014 case 308571:
1015 case 337500:
1016 return CDCLK_FREQ_337_308;
1017 case 450000:
1018 case 432000:
1019 return CDCLK_FREQ_450_432;
1020 case 540000:
1021 return CDCLK_FREQ_540;
1022 case 617143:
1023 case 675000:
1024 return CDCLK_FREQ_675_617;
1025 }
1026 }
1027
skl_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)1028 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1029 const struct intel_cdclk_config *cdclk_config,
1030 enum pipe pipe)
1031 {
1032 int cdclk = cdclk_config->cdclk;
1033 int vco = cdclk_config->vco;
1034 u32 freq_select, cdclk_ctl;
1035 int ret;
1036
1037 /*
1038 * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1039 * unsupported on SKL. In theory this should never happen since only
1040 * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1041 * supported on SKL either, see the above WA. WARN whenever trying to
1042 * use the corresponding VCO freq as that always leads to using the
1043 * minimum 308MHz CDCLK.
1044 */
1045 drm_WARN_ON_ONCE(&dev_priv->drm,
1046 IS_SKYLAKE(dev_priv) && vco == 8640000);
1047
1048 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1049 SKL_CDCLK_PREPARE_FOR_CHANGE,
1050 SKL_CDCLK_READY_FOR_CHANGE,
1051 SKL_CDCLK_READY_FOR_CHANGE, 3);
1052 if (ret) {
1053 drm_err(&dev_priv->drm,
1054 "Failed to inform PCU about cdclk change (%d)\n", ret);
1055 return;
1056 }
1057
1058 freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1059
1060 if (dev_priv->cdclk.hw.vco != 0 &&
1061 dev_priv->cdclk.hw.vco != vco)
1062 skl_dpll0_disable(dev_priv);
1063
1064 cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1065
1066 if (dev_priv->cdclk.hw.vco != vco) {
1067 /* Wa Display #1183: skl,kbl,cfl */
1068 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1069 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1070 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1071 }
1072
1073 /* Wa Display #1183: skl,kbl,cfl */
1074 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1075 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1076 intel_de_posting_read(dev_priv, CDCLK_CTL);
1077
1078 if (dev_priv->cdclk.hw.vco != vco)
1079 skl_dpll0_enable(dev_priv, vco);
1080
1081 /* Wa Display #1183: skl,kbl,cfl */
1082 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1083 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1084
1085 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1086 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1087
1088 /* Wa Display #1183: skl,kbl,cfl */
1089 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1090 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1091 intel_de_posting_read(dev_priv, CDCLK_CTL);
1092
1093 /* inform PCU of the change */
1094 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1095 cdclk_config->voltage_level);
1096
1097 intel_update_cdclk(dev_priv);
1098 }
1099
skl_sanitize_cdclk(struct drm_i915_private * dev_priv)1100 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1101 {
1102 u32 cdctl, expected;
1103
1104 /*
1105 * check if the pre-os initialized the display
1106 * There is SWF18 scratchpad register defined which is set by the
1107 * pre-os which can be used by the OS drivers to check the status
1108 */
1109 if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1110 goto sanitize;
1111
1112 intel_update_cdclk(dev_priv);
1113 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1114
1115 /* Is PLL enabled and locked ? */
1116 if (dev_priv->cdclk.hw.vco == 0 ||
1117 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1118 goto sanitize;
1119
1120 /* DPLL okay; verify the cdclock
1121 *
1122 * Noticed in some instances that the freq selection is correct but
1123 * decimal part is programmed wrong from BIOS where pre-os does not
1124 * enable display. Verify the same as well.
1125 */
1126 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1127 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1128 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1129 if (cdctl == expected)
1130 /* All well; nothing to sanitize */
1131 return;
1132
1133 sanitize:
1134 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1135
1136 /* force cdclk programming */
1137 dev_priv->cdclk.hw.cdclk = 0;
1138 /* force full PLL disable + enable */
1139 dev_priv->cdclk.hw.vco = -1;
1140 }
1141
skl_cdclk_init_hw(struct drm_i915_private * dev_priv)1142 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1143 {
1144 struct intel_cdclk_config cdclk_config;
1145
1146 skl_sanitize_cdclk(dev_priv);
1147
1148 if (dev_priv->cdclk.hw.cdclk != 0 &&
1149 dev_priv->cdclk.hw.vco != 0) {
1150 /*
1151 * Use the current vco as our initial
1152 * guess as to what the preferred vco is.
1153 */
1154 if (dev_priv->skl_preferred_vco_freq == 0)
1155 skl_set_preferred_cdclk_vco(dev_priv,
1156 dev_priv->cdclk.hw.vco);
1157 return;
1158 }
1159
1160 cdclk_config = dev_priv->cdclk.hw;
1161
1162 cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1163 if (cdclk_config.vco == 0)
1164 cdclk_config.vco = 8100000;
1165 cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1166 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1167
1168 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1169 }
1170
skl_cdclk_uninit_hw(struct drm_i915_private * dev_priv)1171 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1172 {
1173 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1174
1175 cdclk_config.cdclk = cdclk_config.bypass;
1176 cdclk_config.vco = 0;
1177 cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1178
1179 skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1180 }
1181
1182 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1183 { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1184 { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1185 { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1186 { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1187 { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1188 {}
1189 };
1190
1191 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1192 { .refclk = 19200, .cdclk = 79200, .divider = 8, .ratio = 33 },
1193 { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1194 { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1195 {}
1196 };
1197
1198 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1199 { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1200 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1201 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1202 { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1203 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1204 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1205
1206 { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1207 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1208 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1209 { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1210 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1211 { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1212
1213 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1214 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1215 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1216 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1217 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1218 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1219 {}
1220 };
1221
1222 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1223 { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio = 36 },
1224 { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio = 40 },
1225 { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio = 64 },
1226 { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1227 { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1228 { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1229
1230 { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio = 30 },
1231 { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio = 32 },
1232 { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio = 52 },
1233 { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1234 { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio = 92 },
1235 { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1236
1237 { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1238 { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1239 { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1240 { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1241 { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1242 { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1243 {}
1244 };
1245
1246 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1247 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1248 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1249 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1250
1251 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1252 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1253 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1254
1255 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1256 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1257 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1258 {}
1259 };
1260
1261 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1262 { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1263 { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1264 { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1265 { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1266 { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1267
1268 { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1269 { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1270 { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1271 { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1272 { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1273
1274 { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1275 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1276 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1277 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1278 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1279 {}
1280 };
1281
1282 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1283 { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 9 },
1284 { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1285 { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1286 { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1287 { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1288 { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1289 {}
1290 };
1291
bxt_calc_cdclk(struct drm_i915_private * dev_priv,int min_cdclk)1292 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1293 {
1294 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1295 int i;
1296
1297 for (i = 0; table[i].refclk; i++)
1298 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1299 table[i].cdclk >= min_cdclk)
1300 return table[i].cdclk;
1301
1302 drm_WARN(&dev_priv->drm, 1,
1303 "Cannot satisfy minimum cdclk %d with refclk %u\n",
1304 min_cdclk, dev_priv->cdclk.hw.ref);
1305 return 0;
1306 }
1307
bxt_calc_cdclk_pll_vco(struct drm_i915_private * dev_priv,int cdclk)1308 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1309 {
1310 const struct intel_cdclk_vals *table = dev_priv->cdclk.table;
1311 int i;
1312
1313 if (cdclk == dev_priv->cdclk.hw.bypass)
1314 return 0;
1315
1316 for (i = 0; table[i].refclk; i++)
1317 if (table[i].refclk == dev_priv->cdclk.hw.ref &&
1318 table[i].cdclk == cdclk)
1319 return dev_priv->cdclk.hw.ref * table[i].ratio;
1320
1321 drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1322 cdclk, dev_priv->cdclk.hw.ref);
1323 return 0;
1324 }
1325
bxt_calc_voltage_level(int cdclk)1326 static u8 bxt_calc_voltage_level(int cdclk)
1327 {
1328 return DIV_ROUND_UP(cdclk, 25000);
1329 }
1330
icl_calc_voltage_level(int cdclk)1331 static u8 icl_calc_voltage_level(int cdclk)
1332 {
1333 if (cdclk > 556800)
1334 return 2;
1335 else if (cdclk > 312000)
1336 return 1;
1337 else
1338 return 0;
1339 }
1340
ehl_calc_voltage_level(int cdclk)1341 static u8 ehl_calc_voltage_level(int cdclk)
1342 {
1343 if (cdclk > 326400)
1344 return 3;
1345 else if (cdclk > 312000)
1346 return 2;
1347 else if (cdclk > 180000)
1348 return 1;
1349 else
1350 return 0;
1351 }
1352
tgl_calc_voltage_level(int cdclk)1353 static u8 tgl_calc_voltage_level(int cdclk)
1354 {
1355 if (cdclk > 556800)
1356 return 3;
1357 else if (cdclk > 326400)
1358 return 2;
1359 else if (cdclk > 312000)
1360 return 1;
1361 else
1362 return 0;
1363 }
1364
icl_readout_refclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)1365 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1366 struct intel_cdclk_config *cdclk_config)
1367 {
1368 u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1369
1370 switch (dssm) {
1371 default:
1372 MISSING_CASE(dssm);
1373 fallthrough;
1374 case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1375 cdclk_config->ref = 24000;
1376 break;
1377 case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1378 cdclk_config->ref = 19200;
1379 break;
1380 case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1381 cdclk_config->ref = 38400;
1382 break;
1383 }
1384 }
1385
bxt_de_pll_readout(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)1386 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1387 struct intel_cdclk_config *cdclk_config)
1388 {
1389 u32 val, ratio;
1390
1391 if (IS_DG2(dev_priv))
1392 cdclk_config->ref = 38400;
1393 else if (DISPLAY_VER(dev_priv) >= 11)
1394 icl_readout_refclk(dev_priv, cdclk_config);
1395 else
1396 cdclk_config->ref = 19200;
1397
1398 val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1399 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1400 (val & BXT_DE_PLL_LOCK) == 0) {
1401 /*
1402 * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1403 * setting it to zero is a way to signal that.
1404 */
1405 cdclk_config->vco = 0;
1406 return;
1407 }
1408
1409 /*
1410 * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1411 * gen9lp had it in a separate PLL control register.
1412 */
1413 if (DISPLAY_VER(dev_priv) >= 11)
1414 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1415 else
1416 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1417
1418 cdclk_config->vco = ratio * cdclk_config->ref;
1419 }
1420
bxt_get_cdclk(struct drm_i915_private * dev_priv,struct intel_cdclk_config * cdclk_config)1421 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1422 struct intel_cdclk_config *cdclk_config)
1423 {
1424 u32 divider;
1425 int div;
1426
1427 bxt_de_pll_readout(dev_priv, cdclk_config);
1428
1429 if (DISPLAY_VER(dev_priv) >= 12)
1430 cdclk_config->bypass = cdclk_config->ref / 2;
1431 else if (DISPLAY_VER(dev_priv) >= 11)
1432 cdclk_config->bypass = 50000;
1433 else
1434 cdclk_config->bypass = cdclk_config->ref;
1435
1436 if (cdclk_config->vco == 0) {
1437 cdclk_config->cdclk = cdclk_config->bypass;
1438 goto out;
1439 }
1440
1441 divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1442
1443 switch (divider) {
1444 case BXT_CDCLK_CD2X_DIV_SEL_1:
1445 div = 2;
1446 break;
1447 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1448 div = 3;
1449 break;
1450 case BXT_CDCLK_CD2X_DIV_SEL_2:
1451 div = 4;
1452 break;
1453 case BXT_CDCLK_CD2X_DIV_SEL_4:
1454 div = 8;
1455 break;
1456 default:
1457 MISSING_CASE(divider);
1458 return;
1459 }
1460
1461 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1462
1463 out:
1464 /*
1465 * Can't read this out :( Let's assume it's
1466 * at least what the CDCLK frequency requires.
1467 */
1468 cdclk_config->voltage_level =
1469 dev_priv->display.calc_voltage_level(cdclk_config->cdclk);
1470 }
1471
bxt_de_pll_disable(struct drm_i915_private * dev_priv)1472 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1473 {
1474 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1475
1476 /* Timeout 200us */
1477 if (intel_de_wait_for_clear(dev_priv,
1478 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1479 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1480
1481 dev_priv->cdclk.hw.vco = 0;
1482 }
1483
bxt_de_pll_enable(struct drm_i915_private * dev_priv,int vco)1484 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1485 {
1486 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1487
1488 intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
1489 BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1490
1491 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1492
1493 /* Timeout 200us */
1494 if (intel_de_wait_for_set(dev_priv,
1495 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1496 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1497
1498 dev_priv->cdclk.hw.vco = vco;
1499 }
1500
icl_cdclk_pll_disable(struct drm_i915_private * dev_priv)1501 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1502 {
1503 intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
1504 BXT_DE_PLL_PLL_ENABLE, 0);
1505
1506 /* Timeout 200us */
1507 if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1508 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1509
1510 dev_priv->cdclk.hw.vco = 0;
1511 }
1512
icl_cdclk_pll_enable(struct drm_i915_private * dev_priv,int vco)1513 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1514 {
1515 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1516 u32 val;
1517
1518 val = ICL_CDCLK_PLL_RATIO(ratio);
1519 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1520
1521 val |= BXT_DE_PLL_PLL_ENABLE;
1522 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1523
1524 /* Timeout 200us */
1525 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1526 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1527
1528 dev_priv->cdclk.hw.vco = vco;
1529 }
1530
adlp_cdclk_pll_crawl(struct drm_i915_private * dev_priv,int vco)1531 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
1532 {
1533 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1534 u32 val;
1535
1536 /* Write PLL ratio without disabling */
1537 val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1538 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1539
1540 /* Submit freq change request */
1541 val |= BXT_DE_PLL_FREQ_REQ;
1542 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1543
1544 /* Timeout 200us */
1545 if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
1546 BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1547 DRM_ERROR("timeout waiting for FREQ change request ack\n");
1548
1549 val &= ~BXT_DE_PLL_FREQ_REQ;
1550 intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1551
1552 dev_priv->cdclk.hw.vco = vco;
1553 }
1554
bxt_cdclk_cd2x_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1555 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1556 {
1557 if (DISPLAY_VER(dev_priv) >= 12) {
1558 if (pipe == INVALID_PIPE)
1559 return TGL_CDCLK_CD2X_PIPE_NONE;
1560 else
1561 return TGL_CDCLK_CD2X_PIPE(pipe);
1562 } else if (DISPLAY_VER(dev_priv) >= 11) {
1563 if (pipe == INVALID_PIPE)
1564 return ICL_CDCLK_CD2X_PIPE_NONE;
1565 else
1566 return ICL_CDCLK_CD2X_PIPE(pipe);
1567 } else {
1568 if (pipe == INVALID_PIPE)
1569 return BXT_CDCLK_CD2X_PIPE_NONE;
1570 else
1571 return BXT_CDCLK_CD2X_PIPE(pipe);
1572 }
1573 }
1574
bxt_cdclk_cd2x_div_sel(struct drm_i915_private * dev_priv,int cdclk,int vco)1575 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
1576 int cdclk, int vco)
1577 {
1578 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1579 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1580 default:
1581 drm_WARN_ON(&dev_priv->drm,
1582 cdclk != dev_priv->cdclk.hw.bypass);
1583 drm_WARN_ON(&dev_priv->drm, vco != 0);
1584 fallthrough;
1585 case 2:
1586 return BXT_CDCLK_CD2X_DIV_SEL_1;
1587 case 3:
1588 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1589 case 4:
1590 return BXT_CDCLK_CD2X_DIV_SEL_2;
1591 case 8:
1592 return BXT_CDCLK_CD2X_DIV_SEL_4;
1593 }
1594 }
1595
bxt_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)1596 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1597 const struct intel_cdclk_config *cdclk_config,
1598 enum pipe pipe)
1599 {
1600 int cdclk = cdclk_config->cdclk;
1601 int vco = cdclk_config->vco;
1602 u32 val;
1603 int ret;
1604
1605 /* Inform power controller of upcoming frequency change. */
1606 if (DISPLAY_VER(dev_priv) >= 11)
1607 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1608 SKL_CDCLK_PREPARE_FOR_CHANGE,
1609 SKL_CDCLK_READY_FOR_CHANGE,
1610 SKL_CDCLK_READY_FOR_CHANGE, 3);
1611 else
1612 /*
1613 * BSpec requires us to wait up to 150usec, but that leads to
1614 * timeouts; the 2ms used here is based on experiment.
1615 */
1616 ret = sandybridge_pcode_write_timeout(dev_priv,
1617 HSW_PCODE_DE_WRITE_FREQ_REQ,
1618 0x80000000, 150, 2);
1619
1620 if (ret) {
1621 drm_err(&dev_priv->drm,
1622 "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1623 ret, cdclk);
1624 return;
1625 }
1626
1627 if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
1628 if (dev_priv->cdclk.hw.vco != vco)
1629 adlp_cdclk_pll_crawl(dev_priv, vco);
1630 } else if (DISPLAY_VER(dev_priv) >= 11) {
1631 if (dev_priv->cdclk.hw.vco != 0 &&
1632 dev_priv->cdclk.hw.vco != vco)
1633 icl_cdclk_pll_disable(dev_priv);
1634
1635 if (dev_priv->cdclk.hw.vco != vco)
1636 icl_cdclk_pll_enable(dev_priv, vco);
1637 } else {
1638 if (dev_priv->cdclk.hw.vco != 0 &&
1639 dev_priv->cdclk.hw.vco != vco)
1640 bxt_de_pll_disable(dev_priv);
1641
1642 if (dev_priv->cdclk.hw.vco != vco)
1643 bxt_de_pll_enable(dev_priv, vco);
1644 }
1645
1646 val = bxt_cdclk_cd2x_div_sel(dev_priv, cdclk, vco) |
1647 bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
1648 skl_cdclk_decimal(cdclk);
1649
1650 /*
1651 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1652 * enable otherwise.
1653 */
1654 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1655 cdclk >= 500000)
1656 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1657 intel_de_write(dev_priv, CDCLK_CTL, val);
1658
1659 if (pipe != INVALID_PIPE)
1660 intel_wait_for_vblank(dev_priv, pipe);
1661
1662 if (DISPLAY_VER(dev_priv) >= 11) {
1663 ret = sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1664 cdclk_config->voltage_level);
1665 } else {
1666 /*
1667 * The timeout isn't specified, the 2ms used here is based on
1668 * experiment.
1669 * FIXME: Waiting for the request completion could be delayed
1670 * until the next PCODE request based on BSpec.
1671 */
1672 ret = sandybridge_pcode_write_timeout(dev_priv,
1673 HSW_PCODE_DE_WRITE_FREQ_REQ,
1674 cdclk_config->voltage_level,
1675 150, 2);
1676 }
1677
1678 if (ret) {
1679 drm_err(&dev_priv->drm,
1680 "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1681 ret, cdclk);
1682 return;
1683 }
1684
1685 intel_update_cdclk(dev_priv);
1686
1687 if (DISPLAY_VER(dev_priv) >= 11)
1688 /*
1689 * Can't read out the voltage level :(
1690 * Let's just assume everything is as expected.
1691 */
1692 dev_priv->cdclk.hw.voltage_level = cdclk_config->voltage_level;
1693 }
1694
bxt_sanitize_cdclk(struct drm_i915_private * dev_priv)1695 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1696 {
1697 u32 cdctl, expected;
1698 int cdclk, vco;
1699
1700 intel_update_cdclk(dev_priv);
1701 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "Current CDCLK");
1702
1703 if (dev_priv->cdclk.hw.vco == 0 ||
1704 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.bypass)
1705 goto sanitize;
1706
1707 /* DPLL okay; verify the cdclock
1708 *
1709 * Some BIOS versions leave an incorrect decimal frequency value and
1710 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1711 * so sanitize this register.
1712 */
1713 cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1714 /*
1715 * Let's ignore the pipe field, since BIOS could have configured the
1716 * dividers both synching to an active pipe, or asynchronously
1717 * (PIPE_NONE).
1718 */
1719 cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
1720
1721 /* Make sure this is a legal cdclk value for the platform */
1722 cdclk = bxt_calc_cdclk(dev_priv, dev_priv->cdclk.hw.cdclk);
1723 if (cdclk != dev_priv->cdclk.hw.cdclk)
1724 goto sanitize;
1725
1726 /* Make sure the VCO is correct for the cdclk */
1727 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
1728 if (vco != dev_priv->cdclk.hw.vco)
1729 goto sanitize;
1730
1731 expected = skl_cdclk_decimal(cdclk);
1732
1733 /* Figure out what CD2X divider we should be using for this cdclk */
1734 expected |= bxt_cdclk_cd2x_div_sel(dev_priv,
1735 dev_priv->cdclk.hw.cdclk,
1736 dev_priv->cdclk.hw.vco);
1737
1738 /*
1739 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1740 * enable otherwise.
1741 */
1742 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1743 dev_priv->cdclk.hw.cdclk >= 500000)
1744 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1745
1746 if (cdctl == expected)
1747 /* All well; nothing to sanitize */
1748 return;
1749
1750 sanitize:
1751 drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1752
1753 /* force cdclk programming */
1754 dev_priv->cdclk.hw.cdclk = 0;
1755
1756 /* force full PLL disable + enable */
1757 dev_priv->cdclk.hw.vco = -1;
1758 }
1759
bxt_cdclk_init_hw(struct drm_i915_private * dev_priv)1760 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
1761 {
1762 struct intel_cdclk_config cdclk_config;
1763
1764 bxt_sanitize_cdclk(dev_priv);
1765
1766 if (dev_priv->cdclk.hw.cdclk != 0 &&
1767 dev_priv->cdclk.hw.vco != 0)
1768 return;
1769
1770 cdclk_config = dev_priv->cdclk.hw;
1771
1772 /*
1773 * FIXME:
1774 * - The initial CDCLK needs to be read from VBT.
1775 * Need to make this change after VBT has changes for BXT.
1776 */
1777 cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
1778 cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
1779 cdclk_config.voltage_level =
1780 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1781
1782 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1783 }
1784
bxt_cdclk_uninit_hw(struct drm_i915_private * dev_priv)1785 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1786 {
1787 struct intel_cdclk_config cdclk_config = dev_priv->cdclk.hw;
1788
1789 cdclk_config.cdclk = cdclk_config.bypass;
1790 cdclk_config.vco = 0;
1791 cdclk_config.voltage_level =
1792 dev_priv->display.calc_voltage_level(cdclk_config.cdclk);
1793
1794 bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1795 }
1796
1797 /**
1798 * intel_cdclk_init_hw - Initialize CDCLK hardware
1799 * @i915: i915 device
1800 *
1801 * Initialize CDCLK. This consists mainly of initializing dev_priv->cdclk.hw and
1802 * sanitizing the state of the hardware if needed. This is generally done only
1803 * during the display core initialization sequence, after which the DMC will
1804 * take care of turning CDCLK off/on as needed.
1805 */
intel_cdclk_init_hw(struct drm_i915_private * i915)1806 void intel_cdclk_init_hw(struct drm_i915_private *i915)
1807 {
1808 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
1809 bxt_cdclk_init_hw(i915);
1810 else if (DISPLAY_VER(i915) == 9)
1811 skl_cdclk_init_hw(i915);
1812 }
1813
1814 /**
1815 * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
1816 * @i915: i915 device
1817 *
1818 * Uninitialize CDCLK. This is done only during the display core
1819 * uninitialization sequence.
1820 */
intel_cdclk_uninit_hw(struct drm_i915_private * i915)1821 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
1822 {
1823 if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
1824 bxt_cdclk_uninit_hw(i915);
1825 else if (DISPLAY_VER(i915) == 9)
1826 skl_cdclk_uninit_hw(i915);
1827 }
1828
intel_cdclk_can_crawl(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)1829 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
1830 const struct intel_cdclk_config *a,
1831 const struct intel_cdclk_config *b)
1832 {
1833 int a_div, b_div;
1834
1835 if (!HAS_CDCLK_CRAWL(dev_priv))
1836 return false;
1837
1838 /*
1839 * The vco and cd2x divider will change independently
1840 * from each, so we disallow cd2x change when crawling.
1841 */
1842 a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
1843 b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
1844
1845 return a->vco != 0 && b->vco != 0 &&
1846 a->vco != b->vco &&
1847 a_div == b_div &&
1848 a->ref == b->ref;
1849 }
1850
1851 /**
1852 * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
1853 * configurations requires a modeset on all pipes
1854 * @a: first CDCLK configuration
1855 * @b: second CDCLK configuration
1856 *
1857 * Returns:
1858 * True if changing between the two CDCLK configurations
1859 * requires all pipes to be off, false if not.
1860 */
intel_cdclk_needs_modeset(const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)1861 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
1862 const struct intel_cdclk_config *b)
1863 {
1864 return a->cdclk != b->cdclk ||
1865 a->vco != b->vco ||
1866 a->ref != b->ref;
1867 }
1868
1869 /**
1870 * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
1871 * configurations requires only a cd2x divider update
1872 * @dev_priv: i915 device
1873 * @a: first CDCLK configuration
1874 * @b: second CDCLK configuration
1875 *
1876 * Returns:
1877 * True if changing between the two CDCLK configurations
1878 * can be done with just a cd2x divider update, false if not.
1879 */
intel_cdclk_can_cd2x_update(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)1880 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
1881 const struct intel_cdclk_config *a,
1882 const struct intel_cdclk_config *b)
1883 {
1884 /* Older hw doesn't have the capability */
1885 if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
1886 return false;
1887
1888 return a->cdclk != b->cdclk &&
1889 a->vco == b->vco &&
1890 a->ref == b->ref;
1891 }
1892
1893 /**
1894 * intel_cdclk_changed - Determine if two CDCLK configurations are different
1895 * @a: first CDCLK configuration
1896 * @b: second CDCLK configuration
1897 *
1898 * Returns:
1899 * True if the CDCLK configurations don't match, false if they do.
1900 */
intel_cdclk_changed(const struct intel_cdclk_config * a,const struct intel_cdclk_config * b)1901 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
1902 const struct intel_cdclk_config *b)
1903 {
1904 return intel_cdclk_needs_modeset(a, b) ||
1905 a->voltage_level != b->voltage_level;
1906 }
1907
intel_dump_cdclk_config(const struct intel_cdclk_config * cdclk_config,const char * context)1908 void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
1909 const char *context)
1910 {
1911 DRM_DEBUG_DRIVER("%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
1912 context, cdclk_config->cdclk, cdclk_config->vco,
1913 cdclk_config->ref, cdclk_config->bypass,
1914 cdclk_config->voltage_level);
1915 }
1916
1917 /**
1918 * intel_set_cdclk - Push the CDCLK configuration to the hardware
1919 * @dev_priv: i915 device
1920 * @cdclk_config: new CDCLK configuration
1921 * @pipe: pipe with which to synchronize the update
1922 *
1923 * Program the hardware based on the passed in CDCLK state,
1924 * if necessary.
1925 */
intel_set_cdclk(struct drm_i915_private * dev_priv,const struct intel_cdclk_config * cdclk_config,enum pipe pipe)1926 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
1927 const struct intel_cdclk_config *cdclk_config,
1928 enum pipe pipe)
1929 {
1930 struct intel_encoder *encoder;
1931
1932 if (!intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config))
1933 return;
1934
1935 if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.set_cdclk))
1936 return;
1937
1938 intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to");
1939
1940 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
1941 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1942
1943 intel_psr_pause(intel_dp);
1944 }
1945
1946 /*
1947 * Lock aux/gmbus while we change cdclk in case those
1948 * functions use cdclk. Not all platforms/ports do,
1949 * but we'll lock them all for simplicity.
1950 */
1951 mutex_lock(&dev_priv->gmbus_mutex);
1952 for_each_intel_dp(&dev_priv->drm, encoder) {
1953 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1954
1955 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
1956 &dev_priv->gmbus_mutex);
1957 }
1958
1959 dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);
1960
1961 for_each_intel_dp(&dev_priv->drm, encoder) {
1962 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1963
1964 mutex_unlock(&intel_dp->aux.hw_mutex);
1965 }
1966 mutex_unlock(&dev_priv->gmbus_mutex);
1967
1968 for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
1969 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1970
1971 intel_psr_resume(intel_dp);
1972 }
1973
1974 if (drm_WARN(&dev_priv->drm,
1975 intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config),
1976 "cdclk state doesn't match!\n")) {
1977 intel_dump_cdclk_config(&dev_priv->cdclk.hw, "[hw state]");
1978 intel_dump_cdclk_config(cdclk_config, "[sw state]");
1979 }
1980 }
1981
1982 /**
1983 * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
1984 * @state: intel atomic state
1985 *
1986 * Program the hardware before updating the HW plane state based on the
1987 * new CDCLK state, if necessary.
1988 */
1989 void
intel_set_cdclk_pre_plane_update(struct intel_atomic_state * state)1990 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
1991 {
1992 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1993 const struct intel_cdclk_state *old_cdclk_state =
1994 intel_atomic_get_old_cdclk_state(state);
1995 const struct intel_cdclk_state *new_cdclk_state =
1996 intel_atomic_get_new_cdclk_state(state);
1997 enum pipe pipe = new_cdclk_state->pipe;
1998
1999 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2000 &new_cdclk_state->actual))
2001 return;
2002
2003 if (pipe == INVALID_PIPE ||
2004 old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
2005 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
2006
2007 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
2008 }
2009 }
2010
2011 /**
2012 * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2013 * @state: intel atomic state
2014 *
2015 * Program the hardware after updating the HW plane state based on the
2016 * new CDCLK state, if necessary.
2017 */
2018 void
intel_set_cdclk_post_plane_update(struct intel_atomic_state * state)2019 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2020 {
2021 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2022 const struct intel_cdclk_state *old_cdclk_state =
2023 intel_atomic_get_old_cdclk_state(state);
2024 const struct intel_cdclk_state *new_cdclk_state =
2025 intel_atomic_get_new_cdclk_state(state);
2026 enum pipe pipe = new_cdclk_state->pipe;
2027
2028 if (!intel_cdclk_changed(&old_cdclk_state->actual,
2029 &new_cdclk_state->actual))
2030 return;
2031
2032 if (pipe != INVALID_PIPE &&
2033 old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
2034 drm_WARN_ON(&dev_priv->drm, !new_cdclk_state->base.changed);
2035
2036 intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
2037 }
2038 }
2039
intel_pixel_rate_to_cdclk(const struct intel_crtc_state * crtc_state)2040 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2041 {
2042 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2043 int pixel_rate = crtc_state->pixel_rate;
2044
2045 if (DISPLAY_VER(dev_priv) >= 10)
2046 return DIV_ROUND_UP(pixel_rate, 2);
2047 else if (DISPLAY_VER(dev_priv) == 9 ||
2048 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2049 return pixel_rate;
2050 else if (IS_CHERRYVIEW(dev_priv))
2051 return DIV_ROUND_UP(pixel_rate * 100, 95);
2052 else if (crtc_state->double_wide)
2053 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2054 else
2055 return DIV_ROUND_UP(pixel_rate * 100, 90);
2056 }
2057
intel_planes_min_cdclk(const struct intel_crtc_state * crtc_state)2058 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2059 {
2060 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2062 struct intel_plane *plane;
2063 int min_cdclk = 0;
2064
2065 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
2066 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2067
2068 return min_cdclk;
2069 }
2070
intel_crtc_compute_min_cdclk(const struct intel_crtc_state * crtc_state)2071 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2072 {
2073 struct drm_i915_private *dev_priv =
2074 to_i915(crtc_state->uapi.crtc->dev);
2075 int min_cdclk;
2076
2077 if (!crtc_state->hw.enable)
2078 return 0;
2079
2080 min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2081
2082 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2083 if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2084 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2085
2086 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2087 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2088 * there may be audio corruption or screen corruption." This cdclk
2089 * restriction for GLK is 316.8 MHz.
2090 */
2091 if (intel_crtc_has_dp_encoder(crtc_state) &&
2092 crtc_state->has_audio &&
2093 crtc_state->port_clock >= 540000 &&
2094 crtc_state->lane_count == 4) {
2095 if (DISPLAY_VER(dev_priv) == 10) {
2096 /* Display WA #1145: glk */
2097 min_cdclk = max(316800, min_cdclk);
2098 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2099 /* Display WA #1144: skl,bxt */
2100 min_cdclk = max(432000, min_cdclk);
2101 }
2102 }
2103
2104 /*
2105 * According to BSpec, "The CD clock frequency must be at least twice
2106 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2107 */
2108 if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2109 min_cdclk = max(2 * 96000, min_cdclk);
2110
2111 /*
2112 * "For DP audio configuration, cdclk frequency shall be set to
2113 * meet the following requirements:
2114 * DP Link Frequency(MHz) | Cdclk frequency(MHz)
2115 * 270 | 320 or higher
2116 * 162 | 200 or higher"
2117 */
2118 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2119 intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2120 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2121
2122 /*
2123 * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2124 * than 320000KHz.
2125 */
2126 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2127 IS_VALLEYVIEW(dev_priv))
2128 min_cdclk = max(320000, min_cdclk);
2129
2130 /*
2131 * On Geminilake once the CDCLK gets as low as 79200
2132 * picture gets unstable, despite that values are
2133 * correct for DSI PLL and DE PLL.
2134 */
2135 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2136 IS_GEMINILAKE(dev_priv))
2137 min_cdclk = max(158400, min_cdclk);
2138
2139 /* Account for additional needs from the planes */
2140 min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2141
2142 /*
2143 * HACK. Currently for TGL platforms we calculate
2144 * min_cdclk initially based on pixel_rate divided
2145 * by 2, accounting for also plane requirements,
2146 * however in some cases the lowest possible CDCLK
2147 * doesn't work and causing the underruns.
2148 * Explicitly stating here that this seems to be currently
2149 * rather a Hack, than final solution.
2150 */
2151 if (IS_TIGERLAKE(dev_priv)) {
2152 /*
2153 * Clamp to max_cdclk_freq in case pixel rate is higher,
2154 * in order not to break an 8K, but still leave W/A at place.
2155 */
2156 min_cdclk = max_t(int, min_cdclk,
2157 min_t(int, crtc_state->pixel_rate,
2158 dev_priv->max_cdclk_freq));
2159 }
2160
2161 if (min_cdclk > dev_priv->max_cdclk_freq) {
2162 drm_dbg_kms(&dev_priv->drm,
2163 "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2164 min_cdclk, dev_priv->max_cdclk_freq);
2165 return -EINVAL;
2166 }
2167
2168 return min_cdclk;
2169 }
2170
intel_compute_min_cdclk(struct intel_cdclk_state * cdclk_state)2171 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2172 {
2173 struct intel_atomic_state *state = cdclk_state->base.state;
2174 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2175 struct intel_bw_state *bw_state = NULL;
2176 struct intel_crtc *crtc;
2177 struct intel_crtc_state *crtc_state;
2178 int min_cdclk, i;
2179 enum pipe pipe;
2180
2181 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2182 int ret;
2183
2184 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2185 if (min_cdclk < 0)
2186 return min_cdclk;
2187
2188 bw_state = intel_atomic_get_bw_state(state);
2189 if (IS_ERR(bw_state))
2190 return PTR_ERR(bw_state);
2191
2192 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2193 continue;
2194
2195 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2196
2197 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2198 if (ret)
2199 return ret;
2200 }
2201
2202 min_cdclk = cdclk_state->force_min_cdclk;
2203 for_each_pipe(dev_priv, pipe) {
2204 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2205
2206 if (!bw_state)
2207 continue;
2208
2209 min_cdclk = max(bw_state->min_cdclk, min_cdclk);
2210 }
2211
2212 return min_cdclk;
2213 }
2214
2215 /*
2216 * Account for port clock min voltage level requirements.
2217 * This only really does something on DISPLA_VER >= 11 but can be
2218 * called on earlier platforms as well.
2219 *
2220 * Note that this functions assumes that 0 is
2221 * the lowest voltage value, and higher values
2222 * correspond to increasingly higher voltages.
2223 *
2224 * Should that relationship no longer hold on
2225 * future platforms this code will need to be
2226 * adjusted.
2227 */
bxt_compute_min_voltage_level(struct intel_cdclk_state * cdclk_state)2228 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2229 {
2230 struct intel_atomic_state *state = cdclk_state->base.state;
2231 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2232 struct intel_crtc *crtc;
2233 struct intel_crtc_state *crtc_state;
2234 u8 min_voltage_level;
2235 int i;
2236 enum pipe pipe;
2237
2238 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2239 int ret;
2240
2241 if (crtc_state->hw.enable)
2242 min_voltage_level = crtc_state->min_voltage_level;
2243 else
2244 min_voltage_level = 0;
2245
2246 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2247 continue;
2248
2249 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2250
2251 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2252 if (ret)
2253 return ret;
2254 }
2255
2256 min_voltage_level = 0;
2257 for_each_pipe(dev_priv, pipe)
2258 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2259 min_voltage_level);
2260
2261 return min_voltage_level;
2262 }
2263
vlv_modeset_calc_cdclk(struct intel_cdclk_state * cdclk_state)2264 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2265 {
2266 struct intel_atomic_state *state = cdclk_state->base.state;
2267 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2268 int min_cdclk, cdclk;
2269
2270 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2271 if (min_cdclk < 0)
2272 return min_cdclk;
2273
2274 cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2275
2276 cdclk_state->logical.cdclk = cdclk;
2277 cdclk_state->logical.voltage_level =
2278 vlv_calc_voltage_level(dev_priv, cdclk);
2279
2280 if (!cdclk_state->active_pipes) {
2281 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2282
2283 cdclk_state->actual.cdclk = cdclk;
2284 cdclk_state->actual.voltage_level =
2285 vlv_calc_voltage_level(dev_priv, cdclk);
2286 } else {
2287 cdclk_state->actual = cdclk_state->logical;
2288 }
2289
2290 return 0;
2291 }
2292
bdw_modeset_calc_cdclk(struct intel_cdclk_state * cdclk_state)2293 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2294 {
2295 int min_cdclk, cdclk;
2296
2297 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2298 if (min_cdclk < 0)
2299 return min_cdclk;
2300
2301 /*
2302 * FIXME should also account for plane ratio
2303 * once 64bpp pixel formats are supported.
2304 */
2305 cdclk = bdw_calc_cdclk(min_cdclk);
2306
2307 cdclk_state->logical.cdclk = cdclk;
2308 cdclk_state->logical.voltage_level =
2309 bdw_calc_voltage_level(cdclk);
2310
2311 if (!cdclk_state->active_pipes) {
2312 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2313
2314 cdclk_state->actual.cdclk = cdclk;
2315 cdclk_state->actual.voltage_level =
2316 bdw_calc_voltage_level(cdclk);
2317 } else {
2318 cdclk_state->actual = cdclk_state->logical;
2319 }
2320
2321 return 0;
2322 }
2323
skl_dpll0_vco(struct intel_cdclk_state * cdclk_state)2324 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2325 {
2326 struct intel_atomic_state *state = cdclk_state->base.state;
2327 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2328 struct intel_crtc *crtc;
2329 struct intel_crtc_state *crtc_state;
2330 int vco, i;
2331
2332 vco = cdclk_state->logical.vco;
2333 if (!vco)
2334 vco = dev_priv->skl_preferred_vco_freq;
2335
2336 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2337 if (!crtc_state->hw.enable)
2338 continue;
2339
2340 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2341 continue;
2342
2343 /*
2344 * DPLL0 VCO may need to be adjusted to get the correct
2345 * clock for eDP. This will affect cdclk as well.
2346 */
2347 switch (crtc_state->port_clock / 2) {
2348 case 108000:
2349 case 216000:
2350 vco = 8640000;
2351 break;
2352 default:
2353 vco = 8100000;
2354 break;
2355 }
2356 }
2357
2358 return vco;
2359 }
2360
skl_modeset_calc_cdclk(struct intel_cdclk_state * cdclk_state)2361 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2362 {
2363 int min_cdclk, cdclk, vco;
2364
2365 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2366 if (min_cdclk < 0)
2367 return min_cdclk;
2368
2369 vco = skl_dpll0_vco(cdclk_state);
2370
2371 /*
2372 * FIXME should also account for plane ratio
2373 * once 64bpp pixel formats are supported.
2374 */
2375 cdclk = skl_calc_cdclk(min_cdclk, vco);
2376
2377 cdclk_state->logical.vco = vco;
2378 cdclk_state->logical.cdclk = cdclk;
2379 cdclk_state->logical.voltage_level =
2380 skl_calc_voltage_level(cdclk);
2381
2382 if (!cdclk_state->active_pipes) {
2383 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2384
2385 cdclk_state->actual.vco = vco;
2386 cdclk_state->actual.cdclk = cdclk;
2387 cdclk_state->actual.voltage_level =
2388 skl_calc_voltage_level(cdclk);
2389 } else {
2390 cdclk_state->actual = cdclk_state->logical;
2391 }
2392
2393 return 0;
2394 }
2395
bxt_modeset_calc_cdclk(struct intel_cdclk_state * cdclk_state)2396 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2397 {
2398 struct intel_atomic_state *state = cdclk_state->base.state;
2399 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2400 int min_cdclk, min_voltage_level, cdclk, vco;
2401
2402 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2403 if (min_cdclk < 0)
2404 return min_cdclk;
2405
2406 min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
2407 if (min_voltage_level < 0)
2408 return min_voltage_level;
2409
2410 cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2411 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2412
2413 cdclk_state->logical.vco = vco;
2414 cdclk_state->logical.cdclk = cdclk;
2415 cdclk_state->logical.voltage_level =
2416 max_t(int, min_voltage_level,
2417 dev_priv->display.calc_voltage_level(cdclk));
2418
2419 if (!cdclk_state->active_pipes) {
2420 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2421 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2422
2423 cdclk_state->actual.vco = vco;
2424 cdclk_state->actual.cdclk = cdclk;
2425 cdclk_state->actual.voltage_level =
2426 dev_priv->display.calc_voltage_level(cdclk);
2427 } else {
2428 cdclk_state->actual = cdclk_state->logical;
2429 }
2430
2431 return 0;
2432 }
2433
fixed_modeset_calc_cdclk(struct intel_cdclk_state * cdclk_state)2434 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2435 {
2436 int min_cdclk;
2437
2438 /*
2439 * We can't change the cdclk frequency, but we still want to
2440 * check that the required minimum frequency doesn't exceed
2441 * the actual cdclk frequency.
2442 */
2443 min_cdclk = intel_compute_min_cdclk(cdclk_state);
2444 if (min_cdclk < 0)
2445 return min_cdclk;
2446
2447 return 0;
2448 }
2449
intel_cdclk_duplicate_state(struct intel_global_obj * obj)2450 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2451 {
2452 struct intel_cdclk_state *cdclk_state;
2453
2454 cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2455 if (!cdclk_state)
2456 return NULL;
2457
2458 cdclk_state->pipe = INVALID_PIPE;
2459
2460 return &cdclk_state->base;
2461 }
2462
intel_cdclk_destroy_state(struct intel_global_obj * obj,struct intel_global_state * state)2463 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2464 struct intel_global_state *state)
2465 {
2466 kfree(state);
2467 }
2468
2469 static const struct intel_global_state_funcs intel_cdclk_funcs = {
2470 .atomic_duplicate_state = intel_cdclk_duplicate_state,
2471 .atomic_destroy_state = intel_cdclk_destroy_state,
2472 };
2473
2474 struct intel_cdclk_state *
intel_atomic_get_cdclk_state(struct intel_atomic_state * state)2475 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2476 {
2477 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2478 struct intel_global_state *cdclk_state;
2479
2480 cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
2481 if (IS_ERR(cdclk_state))
2482 return ERR_CAST(cdclk_state);
2483
2484 return to_intel_cdclk_state(cdclk_state);
2485 }
2486
intel_cdclk_init(struct drm_i915_private * dev_priv)2487 int intel_cdclk_init(struct drm_i915_private *dev_priv)
2488 {
2489 struct intel_cdclk_state *cdclk_state;
2490
2491 cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2492 if (!cdclk_state)
2493 return -ENOMEM;
2494
2495 intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
2496 &cdclk_state->base, &intel_cdclk_funcs);
2497
2498 return 0;
2499 }
2500
intel_modeset_calc_cdclk(struct intel_atomic_state * state)2501 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
2502 {
2503 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2504 const struct intel_cdclk_state *old_cdclk_state;
2505 struct intel_cdclk_state *new_cdclk_state;
2506 enum pipe pipe = INVALID_PIPE;
2507 int ret;
2508
2509 new_cdclk_state = intel_atomic_get_cdclk_state(state);
2510 if (IS_ERR(new_cdclk_state))
2511 return PTR_ERR(new_cdclk_state);
2512
2513 old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
2514
2515 new_cdclk_state->active_pipes =
2516 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
2517
2518 ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
2519 if (ret)
2520 return ret;
2521
2522 if (intel_cdclk_changed(&old_cdclk_state->actual,
2523 &new_cdclk_state->actual)) {
2524 /*
2525 * Also serialize commits across all crtcs
2526 * if the actual hw needs to be poked.
2527 */
2528 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
2529 if (ret)
2530 return ret;
2531 } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
2532 old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
2533 intel_cdclk_changed(&old_cdclk_state->logical,
2534 &new_cdclk_state->logical)) {
2535 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
2536 if (ret)
2537 return ret;
2538 } else {
2539 return 0;
2540 }
2541
2542 if (is_power_of_2(new_cdclk_state->active_pipes) &&
2543 intel_cdclk_can_cd2x_update(dev_priv,
2544 &old_cdclk_state->actual,
2545 &new_cdclk_state->actual)) {
2546 struct intel_crtc *crtc;
2547 struct intel_crtc_state *crtc_state;
2548
2549 pipe = ilog2(new_cdclk_state->active_pipes);
2550 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
2551
2552 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
2553 if (IS_ERR(crtc_state))
2554 return PTR_ERR(crtc_state);
2555
2556 if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
2557 pipe = INVALID_PIPE;
2558 }
2559
2560 if (intel_cdclk_can_crawl(dev_priv,
2561 &old_cdclk_state->actual,
2562 &new_cdclk_state->actual)) {
2563 drm_dbg_kms(&dev_priv->drm,
2564 "Can change cdclk via crawl\n");
2565 } else if (pipe != INVALID_PIPE) {
2566 new_cdclk_state->pipe = pipe;
2567
2568 drm_dbg_kms(&dev_priv->drm,
2569 "Can change cdclk cd2x divider with pipe %c active\n",
2570 pipe_name(pipe));
2571 } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
2572 &new_cdclk_state->actual)) {
2573 /* All pipes must be switched off while we change the cdclk. */
2574 ret = intel_modeset_all_pipes(state);
2575 if (ret)
2576 return ret;
2577
2578 drm_dbg_kms(&dev_priv->drm,
2579 "Modeset required for cdclk change\n");
2580 }
2581
2582 drm_dbg_kms(&dev_priv->drm,
2583 "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
2584 new_cdclk_state->logical.cdclk,
2585 new_cdclk_state->actual.cdclk);
2586 drm_dbg_kms(&dev_priv->drm,
2587 "New voltage level calculated to be logical %u, actual %u\n",
2588 new_cdclk_state->logical.voltage_level,
2589 new_cdclk_state->actual.voltage_level);
2590
2591 return 0;
2592 }
2593
intel_compute_max_dotclk(struct drm_i915_private * dev_priv)2594 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2595 {
2596 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2597
2598 if (DISPLAY_VER(dev_priv) >= 10)
2599 return 2 * max_cdclk_freq;
2600 else if (DISPLAY_VER(dev_priv) == 9 ||
2601 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2602 return max_cdclk_freq;
2603 else if (IS_CHERRYVIEW(dev_priv))
2604 return max_cdclk_freq*95/100;
2605 else if (DISPLAY_VER(dev_priv) < 4)
2606 return 2*max_cdclk_freq*90/100;
2607 else
2608 return max_cdclk_freq*90/100;
2609 }
2610
2611 /**
2612 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2613 * @dev_priv: i915 device
2614 *
2615 * Determine the maximum CDCLK frequency the platform supports, and also
2616 * derive the maximum dot clock frequency the maximum CDCLK frequency
2617 * allows.
2618 */
intel_update_max_cdclk(struct drm_i915_private * dev_priv)2619 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2620 {
2621 if (IS_JSL_EHL(dev_priv)) {
2622 if (dev_priv->cdclk.hw.ref == 24000)
2623 dev_priv->max_cdclk_freq = 552000;
2624 else
2625 dev_priv->max_cdclk_freq = 556800;
2626 } else if (DISPLAY_VER(dev_priv) >= 11) {
2627 if (dev_priv->cdclk.hw.ref == 24000)
2628 dev_priv->max_cdclk_freq = 648000;
2629 else
2630 dev_priv->max_cdclk_freq = 652800;
2631 } else if (IS_GEMINILAKE(dev_priv)) {
2632 dev_priv->max_cdclk_freq = 316800;
2633 } else if (IS_BROXTON(dev_priv)) {
2634 dev_priv->max_cdclk_freq = 624000;
2635 } else if (DISPLAY_VER(dev_priv) == 9) {
2636 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2637 int max_cdclk, vco;
2638
2639 vco = dev_priv->skl_preferred_vco_freq;
2640 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
2641
2642 /*
2643 * Use the lower (vco 8640) cdclk values as a
2644 * first guess. skl_calc_cdclk() will correct it
2645 * if the preferred vco is 8100 instead.
2646 */
2647 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2648 max_cdclk = 617143;
2649 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2650 max_cdclk = 540000;
2651 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2652 max_cdclk = 432000;
2653 else
2654 max_cdclk = 308571;
2655
2656 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2657 } else if (IS_BROADWELL(dev_priv)) {
2658 /*
2659 * FIXME with extra cooling we can allow
2660 * 540 MHz for ULX and 675 Mhz for ULT.
2661 * How can we know if extra cooling is
2662 * available? PCI ID, VTB, something else?
2663 */
2664 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
2665 dev_priv->max_cdclk_freq = 450000;
2666 else if (IS_BDW_ULX(dev_priv))
2667 dev_priv->max_cdclk_freq = 450000;
2668 else if (IS_BDW_ULT(dev_priv))
2669 dev_priv->max_cdclk_freq = 540000;
2670 else
2671 dev_priv->max_cdclk_freq = 675000;
2672 } else if (IS_CHERRYVIEW(dev_priv)) {
2673 dev_priv->max_cdclk_freq = 320000;
2674 } else if (IS_VALLEYVIEW(dev_priv)) {
2675 dev_priv->max_cdclk_freq = 400000;
2676 } else {
2677 /* otherwise assume cdclk is fixed */
2678 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2679 }
2680
2681 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2682
2683 drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
2684 dev_priv->max_cdclk_freq);
2685
2686 drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
2687 dev_priv->max_dotclk_freq);
2688 }
2689
2690 /**
2691 * intel_update_cdclk - Determine the current CDCLK frequency
2692 * @dev_priv: i915 device
2693 *
2694 * Determine the current CDCLK frequency.
2695 */
intel_update_cdclk(struct drm_i915_private * dev_priv)2696 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2697 {
2698 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2699
2700 /*
2701 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2702 * Programmng [sic] note: bit[9:2] should be programmed to the number
2703 * of cdclk that generates 4MHz reference clock freq which is used to
2704 * generate GMBus clock. This will vary with the cdclk freq.
2705 */
2706 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2707 intel_de_write(dev_priv, GMBUSFREQ_VLV,
2708 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2709 }
2710
dg1_rawclk(struct drm_i915_private * dev_priv)2711 static int dg1_rawclk(struct drm_i915_private *dev_priv)
2712 {
2713 /*
2714 * DG1 always uses a 38.4 MHz rawclk. The bspec tells us
2715 * "Program Numerator=2, Denominator=4, Divider=37 decimal."
2716 */
2717 intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
2718 CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
2719
2720 return 38400;
2721 }
2722
cnp_rawclk(struct drm_i915_private * dev_priv)2723 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2724 {
2725 u32 rawclk;
2726 int divider, fraction;
2727
2728 if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2729 /* 24 MHz */
2730 divider = 24000;
2731 fraction = 0;
2732 } else {
2733 /* 19.2 MHz */
2734 divider = 19000;
2735 fraction = 200;
2736 }
2737
2738 rawclk = CNP_RAWCLK_DIV(divider / 1000);
2739 if (fraction) {
2740 int numerator = 1;
2741
2742 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
2743 fraction) - 1);
2744 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2745 rawclk |= ICP_RAWCLK_NUM(numerator);
2746 }
2747
2748 intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
2749 return divider + fraction;
2750 }
2751
pch_rawclk(struct drm_i915_private * dev_priv)2752 static int pch_rawclk(struct drm_i915_private *dev_priv)
2753 {
2754 return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2755 }
2756
vlv_hrawclk(struct drm_i915_private * dev_priv)2757 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2758 {
2759 /* RAWCLK_FREQ_VLV register updated from power well code */
2760 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2761 CCK_DISPLAY_REF_CLOCK_CONTROL);
2762 }
2763
i9xx_hrawclk(struct drm_i915_private * dev_priv)2764 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
2765 {
2766 u32 clkcfg;
2767
2768 /*
2769 * hrawclock is 1/4 the FSB frequency
2770 *
2771 * Note that this only reads the state of the FSB
2772 * straps, not the actual FSB frequency. Some BIOSen
2773 * let you configure each independently. Ideally we'd
2774 * read out the actual FSB frequency but sadly we
2775 * don't know which registers have that information,
2776 * and all the relevant docs have gone to bit heaven :(
2777 */
2778 clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
2779
2780 if (IS_MOBILE(dev_priv)) {
2781 switch (clkcfg) {
2782 case CLKCFG_FSB_400:
2783 return 100000;
2784 case CLKCFG_FSB_533:
2785 return 133333;
2786 case CLKCFG_FSB_667:
2787 return 166667;
2788 case CLKCFG_FSB_800:
2789 return 200000;
2790 case CLKCFG_FSB_1067:
2791 return 266667;
2792 case CLKCFG_FSB_1333:
2793 return 333333;
2794 default:
2795 MISSING_CASE(clkcfg);
2796 return 133333;
2797 }
2798 } else {
2799 switch (clkcfg) {
2800 case CLKCFG_FSB_400_ALT:
2801 return 100000;
2802 case CLKCFG_FSB_533:
2803 return 133333;
2804 case CLKCFG_FSB_667:
2805 return 166667;
2806 case CLKCFG_FSB_800:
2807 return 200000;
2808 case CLKCFG_FSB_1067_ALT:
2809 return 266667;
2810 case CLKCFG_FSB_1333_ALT:
2811 return 333333;
2812 case CLKCFG_FSB_1600_ALT:
2813 return 400000;
2814 default:
2815 return 133333;
2816 }
2817 }
2818 }
2819
2820 /**
2821 * intel_read_rawclk - Determine the current RAWCLK frequency
2822 * @dev_priv: i915 device
2823 *
2824 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2825 * frequency clock so this needs to done only once.
2826 */
intel_read_rawclk(struct drm_i915_private * dev_priv)2827 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
2828 {
2829 u32 freq;
2830
2831 if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2832 freq = dg1_rawclk(dev_priv);
2833 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
2834 freq = cnp_rawclk(dev_priv);
2835 else if (HAS_PCH_SPLIT(dev_priv))
2836 freq = pch_rawclk(dev_priv);
2837 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2838 freq = vlv_hrawclk(dev_priv);
2839 else if (DISPLAY_VER(dev_priv) >= 3)
2840 freq = i9xx_hrawclk(dev_priv);
2841 else
2842 /* no rawclk on other platforms, or no need to know it */
2843 return 0;
2844
2845 return freq;
2846 }
2847
2848 /**
2849 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2850 * @dev_priv: i915 device
2851 */
intel_init_cdclk_hooks(struct drm_i915_private * dev_priv)2852 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2853 {
2854 if (IS_DG2(dev_priv)) {
2855 dev_priv->display.set_cdclk = bxt_set_cdclk;
2856 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2857 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2858 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2859 dev_priv->cdclk.table = dg2_cdclk_table;
2860 } else if (IS_ALDERLAKE_P(dev_priv)) {
2861 dev_priv->display.set_cdclk = bxt_set_cdclk;
2862 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2863 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2864 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2865 /* Wa_22011320316:adl-p[a0] */
2866 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
2867 dev_priv->cdclk.table = adlp_a_step_cdclk_table;
2868 else
2869 dev_priv->cdclk.table = adlp_cdclk_table;
2870 } else if (IS_ROCKETLAKE(dev_priv)) {
2871 dev_priv->display.set_cdclk = bxt_set_cdclk;
2872 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2873 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2874 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2875 dev_priv->cdclk.table = rkl_cdclk_table;
2876 } else if (DISPLAY_VER(dev_priv) >= 12) {
2877 dev_priv->display.set_cdclk = bxt_set_cdclk;
2878 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2879 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2880 dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
2881 dev_priv->cdclk.table = icl_cdclk_table;
2882 } else if (IS_JSL_EHL(dev_priv)) {
2883 dev_priv->display.set_cdclk = bxt_set_cdclk;
2884 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2885 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2886 dev_priv->display.calc_voltage_level = ehl_calc_voltage_level;
2887 dev_priv->cdclk.table = icl_cdclk_table;
2888 } else if (DISPLAY_VER(dev_priv) >= 11) {
2889 dev_priv->display.set_cdclk = bxt_set_cdclk;
2890 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2891 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2892 dev_priv->display.calc_voltage_level = icl_calc_voltage_level;
2893 dev_priv->cdclk.table = icl_cdclk_table;
2894 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
2895 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2896 dev_priv->display.set_cdclk = bxt_set_cdclk;
2897 dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
2898 dev_priv->display.calc_voltage_level = bxt_calc_voltage_level;
2899 if (IS_GEMINILAKE(dev_priv))
2900 dev_priv->cdclk.table = glk_cdclk_table;
2901 else
2902 dev_priv->cdclk.table = bxt_cdclk_table;
2903 } else if (DISPLAY_VER(dev_priv) == 9) {
2904 dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
2905 dev_priv->display.set_cdclk = skl_set_cdclk;
2906 dev_priv->display.modeset_calc_cdclk = skl_modeset_calc_cdclk;
2907 } else if (IS_BROADWELL(dev_priv)) {
2908 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2909 dev_priv->display.set_cdclk = bdw_set_cdclk;
2910 dev_priv->display.modeset_calc_cdclk = bdw_modeset_calc_cdclk;
2911 } else if (IS_CHERRYVIEW(dev_priv)) {
2912 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2913 dev_priv->display.set_cdclk = chv_set_cdclk;
2914 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2915 } else if (IS_VALLEYVIEW(dev_priv)) {
2916 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2917 dev_priv->display.set_cdclk = vlv_set_cdclk;
2918 dev_priv->display.modeset_calc_cdclk = vlv_modeset_calc_cdclk;
2919 } else {
2920 dev_priv->display.bw_calc_min_cdclk = intel_bw_calc_min_cdclk;
2921 dev_priv->display.modeset_calc_cdclk = fixed_modeset_calc_cdclk;
2922 }
2923
2924 if (DISPLAY_VER(dev_priv) >= 10 || IS_BROXTON(dev_priv))
2925 dev_priv->display.get_cdclk = bxt_get_cdclk;
2926 else if (DISPLAY_VER(dev_priv) == 9)
2927 dev_priv->display.get_cdclk = skl_get_cdclk;
2928 else if (IS_BROADWELL(dev_priv))
2929 dev_priv->display.get_cdclk = bdw_get_cdclk;
2930 else if (IS_HASWELL(dev_priv))
2931 dev_priv->display.get_cdclk = hsw_get_cdclk;
2932 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2933 dev_priv->display.get_cdclk = vlv_get_cdclk;
2934 else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
2935 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2936 else if (IS_IRONLAKE(dev_priv))
2937 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2938 else if (IS_GM45(dev_priv))
2939 dev_priv->display.get_cdclk = gm45_get_cdclk;
2940 else if (IS_G45(dev_priv))
2941 dev_priv->display.get_cdclk = g33_get_cdclk;
2942 else if (IS_I965GM(dev_priv))
2943 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2944 else if (IS_I965G(dev_priv))
2945 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2946 else if (IS_PINEVIEW(dev_priv))
2947 dev_priv->display.get_cdclk = pnv_get_cdclk;
2948 else if (IS_G33(dev_priv))
2949 dev_priv->display.get_cdclk = g33_get_cdclk;
2950 else if (IS_I945GM(dev_priv))
2951 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2952 else if (IS_I945G(dev_priv))
2953 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2954 else if (IS_I915GM(dev_priv))
2955 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2956 else if (IS_I915G(dev_priv))
2957 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2958 else if (IS_I865G(dev_priv))
2959 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2960 else if (IS_I85X(dev_priv))
2961 dev_priv->display.get_cdclk = i85x_get_cdclk;
2962 else if (IS_I845G(dev_priv))
2963 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2964 else if (IS_I830(dev_priv))
2965 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2966
2967 if (drm_WARN(&dev_priv->drm, !dev_priv->display.get_cdclk,
2968 "Unknown platform. Assuming 133 MHz CDCLK\n"))
2969 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2970 }
2971