1 /*
2 * Copyright © 2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25 #include "intel_uc.h"
26 #include "intel_guc_submission.h"
27 #include "intel_guc.h"
28 #include "i915_drv.h"
29
30 static void guc_free_load_err_log(struct intel_guc *guc);
31
32 /* Reset GuC providing us with fresh state for both GuC and HuC.
33 */
__intel_uc_reset_hw(struct drm_i915_private * dev_priv)34 static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
35 {
36 int ret;
37 u32 guc_status;
38
39 ret = intel_reset_guc(dev_priv);
40 if (ret) {
41 DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
42 return ret;
43 }
44
45 guc_status = I915_READ(GUC_STATUS);
46 WARN(!(guc_status & GS_MIA_IN_RESET),
47 "GuC status: 0x%x, MIA core expected to be in reset\n",
48 guc_status);
49
50 return ret;
51 }
52
__get_platform_enable_guc(struct drm_i915_private * i915)53 static int __get_platform_enable_guc(struct drm_i915_private *i915)
54 {
55 struct intel_uc_fw *guc_fw = &i915->guc.fw;
56 struct intel_uc_fw *huc_fw = &i915->huc.fw;
57 int enable_guc = 0;
58
59 /* Default is to enable GuC/HuC if we know their firmwares */
60 if (intel_uc_fw_is_selected(guc_fw))
61 enable_guc |= ENABLE_GUC_SUBMISSION;
62 if (intel_uc_fw_is_selected(huc_fw))
63 enable_guc |= ENABLE_GUC_LOAD_HUC;
64
65 /* Any platform specific fine-tuning can be done here */
66
67 return enable_guc;
68 }
69
__get_default_guc_log_level(struct drm_i915_private * i915)70 static int __get_default_guc_log_level(struct drm_i915_private *i915)
71 {
72 int guc_log_level;
73
74 if (!HAS_GUC(i915) || !intel_uc_is_using_guc())
75 guc_log_level = GUC_LOG_LEVEL_DISABLED;
76 else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
77 IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
78 guc_log_level = GUC_LOG_LEVEL_MAX;
79 else
80 guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
81
82 /* Any platform specific fine-tuning can be done here */
83
84 return guc_log_level;
85 }
86
87 /**
88 * sanitize_options_early - sanitize uC related modparam options
89 * @i915: device private
90 *
91 * In case of "enable_guc" option this function will attempt to modify
92 * it only if it was initially set to "auto(-1)". Default value for this
93 * modparam varies between platforms and it is hardcoded in driver code.
94 * Any other modparam value is only monitored against availability of the
95 * related hardware or firmware definitions.
96 *
97 * In case of "guc_log_level" option this function will attempt to modify
98 * it only if it was initially set to "auto(-1)" or if initial value was
99 * "enable(1..4)" on platforms without the GuC. Default value for this
100 * modparam varies between platforms and is usually set to "disable(0)"
101 * unless GuC is enabled on given platform and the driver is compiled with
102 * debug config when this modparam will default to "enable(1..4)".
103 */
sanitize_options_early(struct drm_i915_private * i915)104 static void sanitize_options_early(struct drm_i915_private *i915)
105 {
106 struct intel_uc_fw *guc_fw = &i915->guc.fw;
107 struct intel_uc_fw *huc_fw = &i915->huc.fw;
108
109 /* A negative value means "use platform default" */
110 if (i915_modparams.enable_guc < 0)
111 i915_modparams.enable_guc = __get_platform_enable_guc(i915);
112
113 DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
114 i915_modparams.enable_guc,
115 yesno(intel_uc_is_using_guc_submission()),
116 yesno(intel_uc_is_using_huc()));
117
118 /* Verify GuC firmware availability */
119 if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
120 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
121 "enable_guc", i915_modparams.enable_guc,
122 !HAS_GUC(i915) ? "no GuC hardware" :
123 "no GuC firmware");
124 }
125
126 /* Verify HuC firmware availability */
127 if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
128 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
129 "enable_guc", i915_modparams.enable_guc,
130 !HAS_HUC(i915) ? "no HuC hardware" :
131 "no HuC firmware");
132 }
133
134 /* A negative value means "use platform/config default" */
135 if (i915_modparams.guc_log_level < 0)
136 i915_modparams.guc_log_level =
137 __get_default_guc_log_level(i915);
138
139 if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {
140 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
141 "guc_log_level", i915_modparams.guc_log_level,
142 !HAS_GUC(i915) ? "no GuC hardware" :
143 "GuC not enabled");
144 i915_modparams.guc_log_level = 0;
145 }
146
147 if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
148 DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
149 "guc_log_level", i915_modparams.guc_log_level,
150 "verbosity too high");
151 i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
152 }
153
154 DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
155 i915_modparams.guc_log_level,
156 yesno(i915_modparams.guc_log_level),
157 yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
158 GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
159
160 /* Make sure that sanitization was done */
161 GEM_BUG_ON(i915_modparams.enable_guc < 0);
162 GEM_BUG_ON(i915_modparams.guc_log_level < 0);
163 }
164
intel_uc_init_early(struct drm_i915_private * i915)165 void intel_uc_init_early(struct drm_i915_private *i915)
166 {
167 struct intel_guc *guc = &i915->guc;
168 struct intel_huc *huc = &i915->huc;
169
170 intel_guc_init_early(guc);
171 intel_huc_init_early(huc);
172
173 sanitize_options_early(i915);
174 }
175
intel_uc_cleanup_early(struct drm_i915_private * i915)176 void intel_uc_cleanup_early(struct drm_i915_private *i915)
177 {
178 struct intel_guc *guc = &i915->guc;
179
180 guc_free_load_err_log(guc);
181 }
182
183 /**
184 * intel_uc_init_mmio - setup uC MMIO access
185 * @i915: device private
186 *
187 * Setup minimal state necessary for MMIO accesses later in the
188 * initialization sequence.
189 */
intel_uc_init_mmio(struct drm_i915_private * i915)190 void intel_uc_init_mmio(struct drm_i915_private *i915)
191 {
192 intel_guc_init_send_regs(&i915->guc);
193 }
194
guc_capture_load_err_log(struct intel_guc * guc)195 static void guc_capture_load_err_log(struct intel_guc *guc)
196 {
197 if (!guc->log.vma || !intel_guc_log_get_level(&guc->log))
198 return;
199
200 if (!guc->load_err_log)
201 guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
202
203 return;
204 }
205
guc_free_load_err_log(struct intel_guc * guc)206 static void guc_free_load_err_log(struct intel_guc *guc)
207 {
208 if (guc->load_err_log)
209 i915_gem_object_put(guc->load_err_log);
210 }
211
guc_enable_communication(struct intel_guc * guc)212 static int guc_enable_communication(struct intel_guc *guc)
213 {
214 struct drm_i915_private *i915 = guc_to_i915(guc);
215
216 gen9_enable_guc_interrupts(i915);
217
218 if (HAS_GUC_CT(i915))
219 return intel_guc_ct_enable(&guc->ct);
220
221 guc->send = intel_guc_send_mmio;
222 guc->handler = intel_guc_to_host_event_handler_mmio;
223 return 0;
224 }
225
guc_disable_communication(struct intel_guc * guc)226 static void guc_disable_communication(struct intel_guc *guc)
227 {
228 struct drm_i915_private *i915 = guc_to_i915(guc);
229
230 if (HAS_GUC_CT(i915))
231 intel_guc_ct_disable(&guc->ct);
232
233 gen9_disable_guc_interrupts(i915);
234
235 guc->send = intel_guc_send_nop;
236 guc->handler = intel_guc_to_host_event_handler_nop;
237 }
238
intel_uc_init_misc(struct drm_i915_private * i915)239 int intel_uc_init_misc(struct drm_i915_private *i915)
240 {
241 struct intel_guc *guc = &i915->guc;
242 struct intel_huc *huc = &i915->huc;
243 int ret;
244
245 if (!USES_GUC(i915))
246 return 0;
247
248 ret = intel_guc_init_misc(guc);
249 if (ret)
250 return ret;
251
252 if (USES_HUC(i915)) {
253 ret = intel_huc_init_misc(huc);
254 if (ret)
255 goto err_guc;
256 }
257
258 return 0;
259
260 err_guc:
261 intel_guc_fini_misc(guc);
262 return ret;
263 }
264
intel_uc_fini_misc(struct drm_i915_private * i915)265 void intel_uc_fini_misc(struct drm_i915_private *i915)
266 {
267 struct intel_guc *guc = &i915->guc;
268 struct intel_huc *huc = &i915->huc;
269
270 if (!USES_GUC(i915))
271 return;
272
273 if (USES_HUC(i915))
274 intel_huc_fini_misc(huc);
275
276 intel_guc_fini_misc(guc);
277 }
278
intel_uc_init(struct drm_i915_private * i915)279 int intel_uc_init(struct drm_i915_private *i915)
280 {
281 struct intel_guc *guc = &i915->guc;
282 int ret;
283
284 if (!USES_GUC(i915))
285 return 0;
286
287 if (!HAS_GUC(i915))
288 return -ENODEV;
289
290 ret = intel_guc_init(guc);
291 if (ret)
292 return ret;
293
294 if (USES_GUC_SUBMISSION(i915)) {
295 /*
296 * This is stuff we need to have available at fw load time
297 * if we are planning to enable submission later
298 */
299 ret = intel_guc_submission_init(guc);
300 if (ret) {
301 intel_guc_fini(guc);
302 return ret;
303 }
304 }
305
306 return 0;
307 }
308
intel_uc_fini(struct drm_i915_private * i915)309 void intel_uc_fini(struct drm_i915_private *i915)
310 {
311 struct intel_guc *guc = &i915->guc;
312
313 if (!USES_GUC(i915))
314 return;
315
316 GEM_BUG_ON(!HAS_GUC(i915));
317
318 if (USES_GUC_SUBMISSION(i915))
319 intel_guc_submission_fini(guc);
320
321 intel_guc_fini(guc);
322 }
323
intel_uc_sanitize(struct drm_i915_private * i915)324 void intel_uc_sanitize(struct drm_i915_private *i915)
325 {
326 struct intel_guc *guc = &i915->guc;
327 struct intel_huc *huc = &i915->huc;
328
329 if (!USES_GUC(i915))
330 return;
331
332 GEM_BUG_ON(!HAS_GUC(i915));
333
334 guc_disable_communication(guc);
335
336 intel_huc_sanitize(huc);
337 intel_guc_sanitize(guc);
338
339 __intel_uc_reset_hw(i915);
340 }
341
intel_uc_init_hw(struct drm_i915_private * i915)342 int intel_uc_init_hw(struct drm_i915_private *i915)
343 {
344 struct intel_guc *guc = &i915->guc;
345 struct intel_huc *huc = &i915->huc;
346 int ret, attempts;
347
348 if (!USES_GUC(i915))
349 return 0;
350
351 GEM_BUG_ON(!HAS_GUC(i915));
352
353 gen9_reset_guc_interrupts(i915);
354
355 /* WaEnableuKernelHeaderValidFix:skl */
356 /* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
357 if (IS_GEN9(i915))
358 attempts = 3;
359 else
360 attempts = 1;
361
362 while (attempts--) {
363 /*
364 * Always reset the GuC just before (re)loading, so
365 * that the state and timing are fairly predictable
366 */
367 ret = __intel_uc_reset_hw(i915);
368 if (ret)
369 goto err_out;
370
371 if (USES_HUC(i915)) {
372 ret = intel_huc_fw_upload(huc);
373 if (ret)
374 goto err_out;
375 }
376
377 intel_guc_init_params(guc);
378 ret = intel_guc_fw_upload(guc);
379 if (ret == 0 || ret != -EAGAIN)
380 break;
381
382 DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
383 "retry %d more time(s)\n", ret, attempts);
384 }
385
386 /* Did we succeded or run out of retries? */
387 if (ret)
388 goto err_log_capture;
389
390 ret = guc_enable_communication(guc);
391 if (ret)
392 goto err_log_capture;
393
394 if (USES_HUC(i915)) {
395 ret = intel_huc_auth(huc);
396 if (ret)
397 goto err_communication;
398 }
399
400 if (USES_GUC_SUBMISSION(i915)) {
401 ret = intel_guc_submission_enable(guc);
402 if (ret)
403 goto err_communication;
404 }
405
406 dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
407 guc->fw.major_ver_found, guc->fw.minor_ver_found);
408 dev_info(i915->drm.dev, "GuC submission %s\n",
409 enableddisabled(USES_GUC_SUBMISSION(i915)));
410 dev_info(i915->drm.dev, "HuC %s\n",
411 enableddisabled(USES_HUC(i915)));
412
413 return 0;
414
415 /*
416 * We've failed to load the firmware :(
417 */
418 err_communication:
419 guc_disable_communication(guc);
420 err_log_capture:
421 guc_capture_load_err_log(guc);
422 err_out:
423 /*
424 * Note that there is no fallback as either user explicitly asked for
425 * the GuC or driver default option was to run with the GuC enabled.
426 */
427 if (GEM_WARN_ON(ret == -EIO))
428 ret = -EINVAL;
429
430 dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
431 return ret;
432 }
433
intel_uc_fini_hw(struct drm_i915_private * i915)434 void intel_uc_fini_hw(struct drm_i915_private *i915)
435 {
436 struct intel_guc *guc = &i915->guc;
437
438 if (!USES_GUC(i915))
439 return;
440
441 GEM_BUG_ON(!HAS_GUC(i915));
442
443 if (USES_GUC_SUBMISSION(i915))
444 intel_guc_submission_disable(guc);
445
446 guc_disable_communication(guc);
447 }
448
intel_uc_suspend(struct drm_i915_private * i915)449 int intel_uc_suspend(struct drm_i915_private *i915)
450 {
451 struct intel_guc *guc = &i915->guc;
452 int err;
453
454 if (!USES_GUC(i915))
455 return 0;
456
457 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
458 return 0;
459
460 err = intel_guc_suspend(guc);
461 if (err) {
462 DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
463 return err;
464 }
465
466 gen9_disable_guc_interrupts(i915);
467
468 return 0;
469 }
470
intel_uc_resume(struct drm_i915_private * i915)471 int intel_uc_resume(struct drm_i915_private *i915)
472 {
473 struct intel_guc *guc = &i915->guc;
474 int err;
475
476 if (!USES_GUC(i915))
477 return 0;
478
479 if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
480 return 0;
481
482 gen9_enable_guc_interrupts(i915);
483
484 err = intel_guc_resume(guc);
485 if (err) {
486 DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
487 return err;
488 }
489
490 return 0;
491 }
492
