1 /*
2 * Intel PCH/PCU SPI flash driver.
3 *
4 * Copyright (C) 2016, Intel Corporation
5 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/module.h>
16 #include <linux/sched.h>
17 #include <linux/sizes.h>
18 #include <linux/mtd/mtd.h>
19 #include <linux/mtd/partitions.h>
20 #include <linux/mtd/spi-nor.h>
21 #include <linux/platform_data/intel-spi.h>
22
23 #include "intel-spi.h"
24
25 /* Offsets are from @ispi->base */
26 #define BFPREG 0x00
27
28 #define HSFSTS_CTL 0x04
29 #define HSFSTS_CTL_FSMIE BIT(31)
30 #define HSFSTS_CTL_FDBC_SHIFT 24
31 #define HSFSTS_CTL_FDBC_MASK (0x3f << HSFSTS_CTL_FDBC_SHIFT)
32
33 #define HSFSTS_CTL_FCYCLE_SHIFT 17
34 #define HSFSTS_CTL_FCYCLE_MASK (0x0f << HSFSTS_CTL_FCYCLE_SHIFT)
35 /* HW sequencer opcodes */
36 #define HSFSTS_CTL_FCYCLE_READ (0x00 << HSFSTS_CTL_FCYCLE_SHIFT)
37 #define HSFSTS_CTL_FCYCLE_WRITE (0x02 << HSFSTS_CTL_FCYCLE_SHIFT)
38 #define HSFSTS_CTL_FCYCLE_ERASE (0x03 << HSFSTS_CTL_FCYCLE_SHIFT)
39 #define HSFSTS_CTL_FCYCLE_ERASE_64K (0x04 << HSFSTS_CTL_FCYCLE_SHIFT)
40 #define HSFSTS_CTL_FCYCLE_RDID (0x06 << HSFSTS_CTL_FCYCLE_SHIFT)
41 #define HSFSTS_CTL_FCYCLE_WRSR (0x07 << HSFSTS_CTL_FCYCLE_SHIFT)
42 #define HSFSTS_CTL_FCYCLE_RDSR (0x08 << HSFSTS_CTL_FCYCLE_SHIFT)
43
44 #define HSFSTS_CTL_FGO BIT(16)
45 #define HSFSTS_CTL_FLOCKDN BIT(15)
46 #define HSFSTS_CTL_FDV BIT(14)
47 #define HSFSTS_CTL_SCIP BIT(5)
48 #define HSFSTS_CTL_AEL BIT(2)
49 #define HSFSTS_CTL_FCERR BIT(1)
50 #define HSFSTS_CTL_FDONE BIT(0)
51
52 #define FADDR 0x08
53 #define DLOCK 0x0c
54 #define FDATA(n) (0x10 + ((n) * 4))
55
56 #define FRACC 0x50
57
58 #define FREG(n) (0x54 + ((n) * 4))
59 #define FREG_BASE_MASK 0x3fff
60 #define FREG_LIMIT_SHIFT 16
61 #define FREG_LIMIT_MASK (0x03fff << FREG_LIMIT_SHIFT)
62
63 /* Offset is from @ispi->pregs */
64 #define PR(n) ((n) * 4)
65 #define PR_WPE BIT(31)
66 #define PR_LIMIT_SHIFT 16
67 #define PR_LIMIT_MASK (0x3fff << PR_LIMIT_SHIFT)
68 #define PR_RPE BIT(15)
69 #define PR_BASE_MASK 0x3fff
70
71 /* Offsets are from @ispi->sregs */
72 #define SSFSTS_CTL 0x00
73 #define SSFSTS_CTL_FSMIE BIT(23)
74 #define SSFSTS_CTL_DS BIT(22)
75 #define SSFSTS_CTL_DBC_SHIFT 16
76 #define SSFSTS_CTL_SPOP BIT(11)
77 #define SSFSTS_CTL_ACS BIT(10)
78 #define SSFSTS_CTL_SCGO BIT(9)
79 #define SSFSTS_CTL_COP_SHIFT 12
80 #define SSFSTS_CTL_FRS BIT(7)
81 #define SSFSTS_CTL_DOFRS BIT(6)
82 #define SSFSTS_CTL_AEL BIT(4)
83 #define SSFSTS_CTL_FCERR BIT(3)
84 #define SSFSTS_CTL_FDONE BIT(2)
85 #define SSFSTS_CTL_SCIP BIT(0)
86
87 #define PREOP_OPTYPE 0x04
88 #define OPMENU0 0x08
89 #define OPMENU1 0x0c
90
91 #define OPTYPE_READ_NO_ADDR 0
92 #define OPTYPE_WRITE_NO_ADDR 1
93 #define OPTYPE_READ_WITH_ADDR 2
94 #define OPTYPE_WRITE_WITH_ADDR 3
95
96 /* CPU specifics */
97 #define BYT_PR 0x74
98 #define BYT_SSFSTS_CTL 0x90
99 #define BYT_BCR 0xfc
100 #define BYT_BCR_WPD BIT(0)
101 #define BYT_FREG_NUM 5
102 #define BYT_PR_NUM 5
103
104 #define LPT_PR 0x74
105 #define LPT_SSFSTS_CTL 0x90
106 #define LPT_FREG_NUM 5
107 #define LPT_PR_NUM 5
108
109 #define BXT_PR 0x84
110 #define BXT_SSFSTS_CTL 0xa0
111 #define BXT_FREG_NUM 12
112 #define BXT_PR_NUM 6
113
114 #define LVSCC 0xc4
115 #define UVSCC 0xc8
116 #define ERASE_OPCODE_SHIFT 8
117 #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
118 #define ERASE_64K_OPCODE_SHIFT 16
119 #define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
120
121 #define INTEL_SPI_TIMEOUT 5000 /* ms */
122 #define INTEL_SPI_FIFO_SZ 64
123
124 /**
125 * struct intel_spi - Driver private data
126 * @dev: Device pointer
127 * @info: Pointer to board specific info
128 * @nor: SPI NOR layer structure
129 * @base: Beginning of MMIO space
130 * @pregs: Start of protection registers
131 * @sregs: Start of software sequencer registers
132 * @nregions: Maximum number of regions
133 * @pr_num: Maximum number of protected range registers
134 * @writeable: Is the chip writeable
135 * @locked: Is SPI setting locked
136 * @swseq_reg: Use SW sequencer in register reads/writes
137 * @swseq_erase: Use SW sequencer in erase operation
138 * @erase_64k: 64k erase supported
139 * @atomic_preopcode: Holds preopcode when atomic sequence is requested
140 * @opcodes: Opcodes which are supported. This are programmed by BIOS
141 * before it locks down the controller.
142 */
143 struct intel_spi {
144 struct device *dev;
145 const struct intel_spi_boardinfo *info;
146 struct spi_nor nor;
147 void __iomem *base;
148 void __iomem *pregs;
149 void __iomem *sregs;
150 size_t nregions;
151 size_t pr_num;
152 bool writeable;
153 bool locked;
154 bool swseq_reg;
155 bool swseq_erase;
156 bool erase_64k;
157 u8 atomic_preopcode;
158 u8 opcodes[8];
159 };
160
161 static bool writeable;
162 module_param(writeable, bool, 0);
163 MODULE_PARM_DESC(writeable, "Enable write access to SPI flash chip (default=0)");
164
intel_spi_dump_regs(struct intel_spi * ispi)165 static void intel_spi_dump_regs(struct intel_spi *ispi)
166 {
167 u32 value;
168 int i;
169
170 dev_dbg(ispi->dev, "BFPREG=0x%08x\n", readl(ispi->base + BFPREG));
171
172 value = readl(ispi->base + HSFSTS_CTL);
173 dev_dbg(ispi->dev, "HSFSTS_CTL=0x%08x\n", value);
174 if (value & HSFSTS_CTL_FLOCKDN)
175 dev_dbg(ispi->dev, "-> Locked\n");
176
177 dev_dbg(ispi->dev, "FADDR=0x%08x\n", readl(ispi->base + FADDR));
178 dev_dbg(ispi->dev, "DLOCK=0x%08x\n", readl(ispi->base + DLOCK));
179
180 for (i = 0; i < 16; i++)
181 dev_dbg(ispi->dev, "FDATA(%d)=0x%08x\n",
182 i, readl(ispi->base + FDATA(i)));
183
184 dev_dbg(ispi->dev, "FRACC=0x%08x\n", readl(ispi->base + FRACC));
185
186 for (i = 0; i < ispi->nregions; i++)
187 dev_dbg(ispi->dev, "FREG(%d)=0x%08x\n", i,
188 readl(ispi->base + FREG(i)));
189 for (i = 0; i < ispi->pr_num; i++)
190 dev_dbg(ispi->dev, "PR(%d)=0x%08x\n", i,
191 readl(ispi->pregs + PR(i)));
192
193 value = readl(ispi->sregs + SSFSTS_CTL);
194 dev_dbg(ispi->dev, "SSFSTS_CTL=0x%08x\n", value);
195 dev_dbg(ispi->dev, "PREOP_OPTYPE=0x%08x\n",
196 readl(ispi->sregs + PREOP_OPTYPE));
197 dev_dbg(ispi->dev, "OPMENU0=0x%08x\n", readl(ispi->sregs + OPMENU0));
198 dev_dbg(ispi->dev, "OPMENU1=0x%08x\n", readl(ispi->sregs + OPMENU1));
199
200 if (ispi->info->type == INTEL_SPI_BYT)
201 dev_dbg(ispi->dev, "BCR=0x%08x\n", readl(ispi->base + BYT_BCR));
202
203 dev_dbg(ispi->dev, "LVSCC=0x%08x\n", readl(ispi->base + LVSCC));
204 dev_dbg(ispi->dev, "UVSCC=0x%08x\n", readl(ispi->base + UVSCC));
205
206 dev_dbg(ispi->dev, "Protected regions:\n");
207 for (i = 0; i < ispi->pr_num; i++) {
208 u32 base, limit;
209
210 value = readl(ispi->pregs + PR(i));
211 if (!(value & (PR_WPE | PR_RPE)))
212 continue;
213
214 limit = (value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
215 base = value & PR_BASE_MASK;
216
217 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x [%c%c]\n",
218 i, base << 12, (limit << 12) | 0xfff,
219 value & PR_WPE ? 'W' : '.',
220 value & PR_RPE ? 'R' : '.');
221 }
222
223 dev_dbg(ispi->dev, "Flash regions:\n");
224 for (i = 0; i < ispi->nregions; i++) {
225 u32 region, base, limit;
226
227 region = readl(ispi->base + FREG(i));
228 base = region & FREG_BASE_MASK;
229 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
230
231 if (base >= limit || (i > 0 && limit == 0))
232 dev_dbg(ispi->dev, " %02d disabled\n", i);
233 else
234 dev_dbg(ispi->dev, " %02d base: 0x%08x limit: 0x%08x\n",
235 i, base << 12, (limit << 12) | 0xfff);
236 }
237
238 dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",
239 ispi->swseq_reg ? 'S' : 'H');
240 dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",
241 ispi->swseq_erase ? 'S' : 'H');
242 }
243
244 /* Reads max INTEL_SPI_FIFO_SZ bytes from the device fifo */
intel_spi_read_block(struct intel_spi * ispi,void * buf,size_t size)245 static int intel_spi_read_block(struct intel_spi *ispi, void *buf, size_t size)
246 {
247 size_t bytes;
248 int i = 0;
249
250 if (size > INTEL_SPI_FIFO_SZ)
251 return -EINVAL;
252
253 while (size > 0) {
254 bytes = min_t(size_t, size, 4);
255 memcpy_fromio(buf, ispi->base + FDATA(i), bytes);
256 size -= bytes;
257 buf += bytes;
258 i++;
259 }
260
261 return 0;
262 }
263
264 /* Writes max INTEL_SPI_FIFO_SZ bytes to the device fifo */
intel_spi_write_block(struct intel_spi * ispi,const void * buf,size_t size)265 static int intel_spi_write_block(struct intel_spi *ispi, const void *buf,
266 size_t size)
267 {
268 size_t bytes;
269 int i = 0;
270
271 if (size > INTEL_SPI_FIFO_SZ)
272 return -EINVAL;
273
274 while (size > 0) {
275 bytes = min_t(size_t, size, 4);
276 memcpy_toio(ispi->base + FDATA(i), buf, bytes);
277 size -= bytes;
278 buf += bytes;
279 i++;
280 }
281
282 return 0;
283 }
284
intel_spi_wait_hw_busy(struct intel_spi * ispi)285 static int intel_spi_wait_hw_busy(struct intel_spi *ispi)
286 {
287 u32 val;
288
289 return readl_poll_timeout(ispi->base + HSFSTS_CTL, val,
290 !(val & HSFSTS_CTL_SCIP), 40,
291 INTEL_SPI_TIMEOUT * 1000);
292 }
293
intel_spi_wait_sw_busy(struct intel_spi * ispi)294 static int intel_spi_wait_sw_busy(struct intel_spi *ispi)
295 {
296 u32 val;
297
298 return readl_poll_timeout(ispi->sregs + SSFSTS_CTL, val,
299 !(val & SSFSTS_CTL_SCIP), 40,
300 INTEL_SPI_TIMEOUT * 1000);
301 }
302
intel_spi_init(struct intel_spi * ispi)303 static int intel_spi_init(struct intel_spi *ispi)
304 {
305 u32 opmenu0, opmenu1, lvscc, uvscc, val;
306 int i;
307
308 switch (ispi->info->type) {
309 case INTEL_SPI_BYT:
310 ispi->sregs = ispi->base + BYT_SSFSTS_CTL;
311 ispi->pregs = ispi->base + BYT_PR;
312 ispi->nregions = BYT_FREG_NUM;
313 ispi->pr_num = BYT_PR_NUM;
314 ispi->swseq_reg = true;
315
316 if (writeable) {
317 /* Disable write protection */
318 val = readl(ispi->base + BYT_BCR);
319 if (!(val & BYT_BCR_WPD)) {
320 val |= BYT_BCR_WPD;
321 writel(val, ispi->base + BYT_BCR);
322 val = readl(ispi->base + BYT_BCR);
323 }
324
325 ispi->writeable = !!(val & BYT_BCR_WPD);
326 }
327
328 break;
329
330 case INTEL_SPI_LPT:
331 ispi->sregs = ispi->base + LPT_SSFSTS_CTL;
332 ispi->pregs = ispi->base + LPT_PR;
333 ispi->nregions = LPT_FREG_NUM;
334 ispi->pr_num = LPT_PR_NUM;
335 ispi->swseq_reg = true;
336 break;
337
338 case INTEL_SPI_BXT:
339 ispi->sregs = ispi->base + BXT_SSFSTS_CTL;
340 ispi->pregs = ispi->base + BXT_PR;
341 ispi->nregions = BXT_FREG_NUM;
342 ispi->pr_num = BXT_PR_NUM;
343 ispi->erase_64k = true;
344 break;
345
346 default:
347 return -EINVAL;
348 }
349
350 /* Disable #SMI generation from HW sequencer */
351 val = readl(ispi->base + HSFSTS_CTL);
352 val &= ~HSFSTS_CTL_FSMIE;
353 writel(val, ispi->base + HSFSTS_CTL);
354
355 /*
356 * Determine whether erase operation should use HW or SW sequencer.
357 *
358 * The HW sequencer has a predefined list of opcodes, with only the
359 * erase opcode being programmable in LVSCC and UVSCC registers.
360 * If these registers don't contain a valid erase opcode, erase
361 * cannot be done using HW sequencer.
362 */
363 lvscc = readl(ispi->base + LVSCC);
364 uvscc = readl(ispi->base + UVSCC);
365 if (!(lvscc & ERASE_OPCODE_MASK) || !(uvscc & ERASE_OPCODE_MASK))
366 ispi->swseq_erase = true;
367 /* SPI controller on Intel BXT supports 64K erase opcode */
368 if (ispi->info->type == INTEL_SPI_BXT && !ispi->swseq_erase)
369 if (!(lvscc & ERASE_64K_OPCODE_MASK) ||
370 !(uvscc & ERASE_64K_OPCODE_MASK))
371 ispi->erase_64k = false;
372
373 /*
374 * Some controllers can only do basic operations using hardware
375 * sequencer. All other operations are supposed to be carried out
376 * using software sequencer.
377 */
378 if (ispi->swseq_reg) {
379 /* Disable #SMI generation from SW sequencer */
380 val = readl(ispi->sregs + SSFSTS_CTL);
381 val &= ~SSFSTS_CTL_FSMIE;
382 writel(val, ispi->sregs + SSFSTS_CTL);
383 }
384
385 /* Check controller's lock status */
386 val = readl(ispi->base + HSFSTS_CTL);
387 ispi->locked = !!(val & HSFSTS_CTL_FLOCKDN);
388
389 if (ispi->locked) {
390 /*
391 * BIOS programs allowed opcodes and then locks down the
392 * register. So read back what opcodes it decided to support.
393 * That's the set we are going to support as well.
394 */
395 opmenu0 = readl(ispi->sregs + OPMENU0);
396 opmenu1 = readl(ispi->sregs + OPMENU1);
397
398 if (opmenu0 && opmenu1) {
399 for (i = 0; i < ARRAY_SIZE(ispi->opcodes) / 2; i++) {
400 ispi->opcodes[i] = opmenu0 >> i * 8;
401 ispi->opcodes[i + 4] = opmenu1 >> i * 8;
402 }
403 }
404 }
405
406 intel_spi_dump_regs(ispi);
407
408 return 0;
409 }
410
intel_spi_opcode_index(struct intel_spi * ispi,u8 opcode,int optype)411 static int intel_spi_opcode_index(struct intel_spi *ispi, u8 opcode, int optype)
412 {
413 int i;
414 int preop;
415
416 if (ispi->locked) {
417 for (i = 0; i < ARRAY_SIZE(ispi->opcodes); i++)
418 if (ispi->opcodes[i] == opcode)
419 return i;
420
421 return -EINVAL;
422 }
423
424 /* The lock is off, so just use index 0 */
425 writel(opcode, ispi->sregs + OPMENU0);
426 preop = readw(ispi->sregs + PREOP_OPTYPE);
427 writel(optype << 16 | preop, ispi->sregs + PREOP_OPTYPE);
428
429 return 0;
430 }
431
intel_spi_hw_cycle(struct intel_spi * ispi,u8 opcode,int len)432 static int intel_spi_hw_cycle(struct intel_spi *ispi, u8 opcode, int len)
433 {
434 u32 val, status;
435 int ret;
436
437 val = readl(ispi->base + HSFSTS_CTL);
438 val &= ~(HSFSTS_CTL_FCYCLE_MASK | HSFSTS_CTL_FDBC_MASK);
439
440 switch (opcode) {
441 case SPINOR_OP_RDID:
442 val |= HSFSTS_CTL_FCYCLE_RDID;
443 break;
444 case SPINOR_OP_WRSR:
445 val |= HSFSTS_CTL_FCYCLE_WRSR;
446 break;
447 case SPINOR_OP_RDSR:
448 val |= HSFSTS_CTL_FCYCLE_RDSR;
449 break;
450 default:
451 return -EINVAL;
452 }
453
454 if (len > INTEL_SPI_FIFO_SZ)
455 return -EINVAL;
456
457 val |= (len - 1) << HSFSTS_CTL_FDBC_SHIFT;
458 val |= HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
459 val |= HSFSTS_CTL_FGO;
460 writel(val, ispi->base + HSFSTS_CTL);
461
462 ret = intel_spi_wait_hw_busy(ispi);
463 if (ret)
464 return ret;
465
466 status = readl(ispi->base + HSFSTS_CTL);
467 if (status & HSFSTS_CTL_FCERR)
468 return -EIO;
469 else if (status & HSFSTS_CTL_AEL)
470 return -EACCES;
471
472 return 0;
473 }
474
intel_spi_sw_cycle(struct intel_spi * ispi,u8 opcode,int len,int optype)475 static int intel_spi_sw_cycle(struct intel_spi *ispi, u8 opcode, int len,
476 int optype)
477 {
478 u32 val = 0, status;
479 u8 atomic_preopcode;
480 int ret;
481
482 ret = intel_spi_opcode_index(ispi, opcode, optype);
483 if (ret < 0)
484 return ret;
485
486 if (len > INTEL_SPI_FIFO_SZ)
487 return -EINVAL;
488
489 /*
490 * Always clear it after each SW sequencer operation regardless
491 * of whether it is successful or not.
492 */
493 atomic_preopcode = ispi->atomic_preopcode;
494 ispi->atomic_preopcode = 0;
495
496 /* Only mark 'Data Cycle' bit when there is data to be transferred */
497 if (len > 0)
498 val = ((len - 1) << SSFSTS_CTL_DBC_SHIFT) | SSFSTS_CTL_DS;
499 val |= ret << SSFSTS_CTL_COP_SHIFT;
500 val |= SSFSTS_CTL_FCERR | SSFSTS_CTL_FDONE;
501 val |= SSFSTS_CTL_SCGO;
502 if (atomic_preopcode) {
503 u16 preop;
504
505 switch (optype) {
506 case OPTYPE_WRITE_NO_ADDR:
507 case OPTYPE_WRITE_WITH_ADDR:
508 /* Pick matching preopcode for the atomic sequence */
509 preop = readw(ispi->sregs + PREOP_OPTYPE);
510 if ((preop & 0xff) == atomic_preopcode)
511 ; /* Do nothing */
512 else if ((preop >> 8) == atomic_preopcode)
513 val |= SSFSTS_CTL_SPOP;
514 else
515 return -EINVAL;
516
517 /* Enable atomic sequence */
518 val |= SSFSTS_CTL_ACS;
519 break;
520
521 default:
522 return -EINVAL;
523 }
524
525 }
526 writel(val, ispi->sregs + SSFSTS_CTL);
527
528 ret = intel_spi_wait_sw_busy(ispi);
529 if (ret)
530 return ret;
531
532 status = readl(ispi->sregs + SSFSTS_CTL);
533 if (status & SSFSTS_CTL_FCERR)
534 return -EIO;
535 else if (status & SSFSTS_CTL_AEL)
536 return -EACCES;
537
538 return 0;
539 }
540
intel_spi_read_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)541 static int intel_spi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
542 {
543 struct intel_spi *ispi = nor->priv;
544 int ret;
545
546 /* Address of the first chip */
547 writel(0, ispi->base + FADDR);
548
549 if (ispi->swseq_reg)
550 ret = intel_spi_sw_cycle(ispi, opcode, len,
551 OPTYPE_READ_NO_ADDR);
552 else
553 ret = intel_spi_hw_cycle(ispi, opcode, len);
554
555 if (ret)
556 return ret;
557
558 return intel_spi_read_block(ispi, buf, len);
559 }
560
intel_spi_write_reg(struct spi_nor * nor,u8 opcode,u8 * buf,int len)561 static int intel_spi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
562 {
563 struct intel_spi *ispi = nor->priv;
564 int ret;
565
566 /*
567 * This is handled with atomic operation and preop code in Intel
568 * controller so we only verify that it is available. If the
569 * controller is not locked, program the opcode to the PREOP
570 * register for later use.
571 *
572 * When hardware sequencer is used there is no need to program
573 * any opcodes (it handles them automatically as part of a command).
574 */
575 if (opcode == SPINOR_OP_WREN) {
576 u16 preop;
577
578 if (!ispi->swseq_reg)
579 return 0;
580
581 preop = readw(ispi->sregs + PREOP_OPTYPE);
582 if ((preop & 0xff) != opcode && (preop >> 8) != opcode) {
583 if (ispi->locked)
584 return -EINVAL;
585 writel(opcode, ispi->sregs + PREOP_OPTYPE);
586 }
587
588 /*
589 * This enables atomic sequence on next SW sycle. Will
590 * be cleared after next operation.
591 */
592 ispi->atomic_preopcode = opcode;
593 return 0;
594 }
595
596 writel(0, ispi->base + FADDR);
597
598 /* Write the value beforehand */
599 ret = intel_spi_write_block(ispi, buf, len);
600 if (ret)
601 return ret;
602
603 if (ispi->swseq_reg)
604 return intel_spi_sw_cycle(ispi, opcode, len,
605 OPTYPE_WRITE_NO_ADDR);
606 return intel_spi_hw_cycle(ispi, opcode, len);
607 }
608
intel_spi_read(struct spi_nor * nor,loff_t from,size_t len,u_char * read_buf)609 static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
610 u_char *read_buf)
611 {
612 struct intel_spi *ispi = nor->priv;
613 size_t block_size, retlen = 0;
614 u32 val, status;
615 ssize_t ret;
616
617 /*
618 * Atomic sequence is not expected with HW sequencer reads. Make
619 * sure it is cleared regardless.
620 */
621 if (WARN_ON_ONCE(ispi->atomic_preopcode))
622 ispi->atomic_preopcode = 0;
623
624 switch (nor->read_opcode) {
625 case SPINOR_OP_READ:
626 case SPINOR_OP_READ_FAST:
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 while (len > 0) {
633 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
634
635 writel(from, ispi->base + FADDR);
636
637 val = readl(ispi->base + HSFSTS_CTL);
638 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
639 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
640 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
641 val |= HSFSTS_CTL_FCYCLE_READ;
642 val |= HSFSTS_CTL_FGO;
643 writel(val, ispi->base + HSFSTS_CTL);
644
645 ret = intel_spi_wait_hw_busy(ispi);
646 if (ret)
647 return ret;
648
649 status = readl(ispi->base + HSFSTS_CTL);
650 if (status & HSFSTS_CTL_FCERR)
651 ret = -EIO;
652 else if (status & HSFSTS_CTL_AEL)
653 ret = -EACCES;
654
655 if (ret < 0) {
656 dev_err(ispi->dev, "read error: %llx: %#x\n", from,
657 status);
658 return ret;
659 }
660
661 ret = intel_spi_read_block(ispi, read_buf, block_size);
662 if (ret)
663 return ret;
664
665 len -= block_size;
666 from += block_size;
667 retlen += block_size;
668 read_buf += block_size;
669 }
670
671 return retlen;
672 }
673
intel_spi_write(struct spi_nor * nor,loff_t to,size_t len,const u_char * write_buf)674 static ssize_t intel_spi_write(struct spi_nor *nor, loff_t to, size_t len,
675 const u_char *write_buf)
676 {
677 struct intel_spi *ispi = nor->priv;
678 size_t block_size, retlen = 0;
679 u32 val, status;
680 ssize_t ret;
681
682 /* Not needed with HW sequencer write, make sure it is cleared */
683 ispi->atomic_preopcode = 0;
684
685 while (len > 0) {
686 block_size = min_t(size_t, len, INTEL_SPI_FIFO_SZ);
687
688 writel(to, ispi->base + FADDR);
689
690 val = readl(ispi->base + HSFSTS_CTL);
691 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
692 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
693 val |= (block_size - 1) << HSFSTS_CTL_FDBC_SHIFT;
694 val |= HSFSTS_CTL_FCYCLE_WRITE;
695
696 ret = intel_spi_write_block(ispi, write_buf, block_size);
697 if (ret) {
698 dev_err(ispi->dev, "failed to write block\n");
699 return ret;
700 }
701
702 /* Start the write now */
703 val |= HSFSTS_CTL_FGO;
704 writel(val, ispi->base + HSFSTS_CTL);
705
706 ret = intel_spi_wait_hw_busy(ispi);
707 if (ret) {
708 dev_err(ispi->dev, "timeout\n");
709 return ret;
710 }
711
712 status = readl(ispi->base + HSFSTS_CTL);
713 if (status & HSFSTS_CTL_FCERR)
714 ret = -EIO;
715 else if (status & HSFSTS_CTL_AEL)
716 ret = -EACCES;
717
718 if (ret < 0) {
719 dev_err(ispi->dev, "write error: %llx: %#x\n", to,
720 status);
721 return ret;
722 }
723
724 len -= block_size;
725 to += block_size;
726 retlen += block_size;
727 write_buf += block_size;
728 }
729
730 return retlen;
731 }
732
intel_spi_erase(struct spi_nor * nor,loff_t offs)733 static int intel_spi_erase(struct spi_nor *nor, loff_t offs)
734 {
735 size_t erase_size, len = nor->mtd.erasesize;
736 struct intel_spi *ispi = nor->priv;
737 u32 val, status, cmd;
738 int ret;
739
740 /* If the hardware can do 64k erase use that when possible */
741 if (len >= SZ_64K && ispi->erase_64k) {
742 cmd = HSFSTS_CTL_FCYCLE_ERASE_64K;
743 erase_size = SZ_64K;
744 } else {
745 cmd = HSFSTS_CTL_FCYCLE_ERASE;
746 erase_size = SZ_4K;
747 }
748
749 if (ispi->swseq_erase) {
750 while (len > 0) {
751 writel(offs, ispi->base + FADDR);
752
753 ret = intel_spi_sw_cycle(ispi, nor->erase_opcode,
754 0, OPTYPE_WRITE_WITH_ADDR);
755 if (ret)
756 return ret;
757
758 offs += erase_size;
759 len -= erase_size;
760 }
761
762 return 0;
763 }
764
765 /* Not needed with HW sequencer erase, make sure it is cleared */
766 ispi->atomic_preopcode = 0;
767
768 while (len > 0) {
769 writel(offs, ispi->base + FADDR);
770
771 val = readl(ispi->base + HSFSTS_CTL);
772 val &= ~(HSFSTS_CTL_FDBC_MASK | HSFSTS_CTL_FCYCLE_MASK);
773 val |= HSFSTS_CTL_AEL | HSFSTS_CTL_FCERR | HSFSTS_CTL_FDONE;
774 val |= cmd;
775 val |= HSFSTS_CTL_FGO;
776 writel(val, ispi->base + HSFSTS_CTL);
777
778 ret = intel_spi_wait_hw_busy(ispi);
779 if (ret)
780 return ret;
781
782 status = readl(ispi->base + HSFSTS_CTL);
783 if (status & HSFSTS_CTL_FCERR)
784 return -EIO;
785 else if (status & HSFSTS_CTL_AEL)
786 return -EACCES;
787
788 offs += erase_size;
789 len -= erase_size;
790 }
791
792 return 0;
793 }
794
intel_spi_is_protected(const struct intel_spi * ispi,unsigned int base,unsigned int limit)795 static bool intel_spi_is_protected(const struct intel_spi *ispi,
796 unsigned int base, unsigned int limit)
797 {
798 int i;
799
800 for (i = 0; i < ispi->pr_num; i++) {
801 u32 pr_base, pr_limit, pr_value;
802
803 pr_value = readl(ispi->pregs + PR(i));
804 if (!(pr_value & (PR_WPE | PR_RPE)))
805 continue;
806
807 pr_limit = (pr_value & PR_LIMIT_MASK) >> PR_LIMIT_SHIFT;
808 pr_base = pr_value & PR_BASE_MASK;
809
810 if (pr_base >= base && pr_limit <= limit)
811 return true;
812 }
813
814 return false;
815 }
816
817 /*
818 * There will be a single partition holding all enabled flash regions. We
819 * call this "BIOS".
820 */
intel_spi_fill_partition(struct intel_spi * ispi,struct mtd_partition * part)821 static void intel_spi_fill_partition(struct intel_spi *ispi,
822 struct mtd_partition *part)
823 {
824 u64 end;
825 int i;
826
827 memset(part, 0, sizeof(*part));
828
829 /* Start from the mandatory descriptor region */
830 part->size = 4096;
831 part->name = "BIOS";
832
833 /*
834 * Now try to find where this partition ends based on the flash
835 * region registers.
836 */
837 for (i = 1; i < ispi->nregions; i++) {
838 u32 region, base, limit;
839
840 region = readl(ispi->base + FREG(i));
841 base = region & FREG_BASE_MASK;
842 limit = (region & FREG_LIMIT_MASK) >> FREG_LIMIT_SHIFT;
843
844 if (base >= limit || limit == 0)
845 continue;
846
847 /*
848 * If any of the regions have protection bits set, make the
849 * whole partition read-only to be on the safe side.
850 */
851 if (intel_spi_is_protected(ispi, base, limit))
852 ispi->writeable = false;
853
854 end = (limit << 12) + 4096;
855 if (end > part->size)
856 part->size = end;
857 }
858 }
859
intel_spi_probe(struct device * dev,struct resource * mem,const struct intel_spi_boardinfo * info)860 struct intel_spi *intel_spi_probe(struct device *dev,
861 struct resource *mem, const struct intel_spi_boardinfo *info)
862 {
863 const struct spi_nor_hwcaps hwcaps = {
864 .mask = SNOR_HWCAPS_READ |
865 SNOR_HWCAPS_READ_FAST |
866 SNOR_HWCAPS_PP,
867 };
868 struct mtd_partition part;
869 struct intel_spi *ispi;
870 int ret;
871
872 if (!info || !mem)
873 return ERR_PTR(-EINVAL);
874
875 ispi = devm_kzalloc(dev, sizeof(*ispi), GFP_KERNEL);
876 if (!ispi)
877 return ERR_PTR(-ENOMEM);
878
879 ispi->base = devm_ioremap_resource(dev, mem);
880 if (IS_ERR(ispi->base))
881 return ERR_CAST(ispi->base);
882
883 ispi->dev = dev;
884 ispi->info = info;
885 ispi->writeable = info->writeable;
886
887 ret = intel_spi_init(ispi);
888 if (ret)
889 return ERR_PTR(ret);
890
891 ispi->nor.dev = ispi->dev;
892 ispi->nor.priv = ispi;
893 ispi->nor.read_reg = intel_spi_read_reg;
894 ispi->nor.write_reg = intel_spi_write_reg;
895 ispi->nor.read = intel_spi_read;
896 ispi->nor.write = intel_spi_write;
897 ispi->nor.erase = intel_spi_erase;
898
899 ret = spi_nor_scan(&ispi->nor, NULL, &hwcaps);
900 if (ret) {
901 dev_info(dev, "failed to locate the chip\n");
902 return ERR_PTR(ret);
903 }
904
905 intel_spi_fill_partition(ispi, &part);
906
907 /* Prevent writes if not explicitly enabled */
908 if (!ispi->writeable || !writeable)
909 ispi->nor.mtd.flags &= ~MTD_WRITEABLE;
910
911 ret = mtd_device_register(&ispi->nor.mtd, &part, 1);
912 if (ret)
913 return ERR_PTR(ret);
914
915 return ispi;
916 }
917 EXPORT_SYMBOL_GPL(intel_spi_probe);
918
intel_spi_remove(struct intel_spi * ispi)919 int intel_spi_remove(struct intel_spi *ispi)
920 {
921 return mtd_device_unregister(&ispi->nor.mtd);
922 }
923 EXPORT_SYMBOL_GPL(intel_spi_remove);
924
925 MODULE_DESCRIPTION("Intel PCH/PCU SPI flash core driver");
926 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
927 MODULE_LICENSE("GPL v2");
928
