1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
28 */
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_hdcp.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
36 #include "i915_drv.h"
37
38 struct gmbus_pin {
39 const char *name;
40 i915_reg_t reg;
41 };
42
43 /* Map gmbus pin pairs to names and registers. */
44 static const struct gmbus_pin gmbus_pins[] = {
45 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
46 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
47 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
48 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
49 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
50 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
51 };
52
53 static const struct gmbus_pin gmbus_pins_bdw[] = {
54 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
55 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
56 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
57 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
58 };
59
60 static const struct gmbus_pin gmbus_pins_skl[] = {
61 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
62 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
63 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
64 };
65
66 static const struct gmbus_pin gmbus_pins_bxt[] = {
67 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
68 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
69 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
70 };
71
72 static const struct gmbus_pin gmbus_pins_cnp[] = {
73 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
74 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
75 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
76 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
77 };
78
79 static const struct gmbus_pin gmbus_pins_icp[] = {
80 [GMBUS_PIN_1_BXT] = { "dpa", GPIOB },
81 [GMBUS_PIN_2_BXT] = { "dpb", GPIOC },
82 [GMBUS_PIN_9_TC1_ICP] = { "tc1", GPIOJ },
83 [GMBUS_PIN_10_TC2_ICP] = { "tc2", GPIOK },
84 [GMBUS_PIN_11_TC3_ICP] = { "tc3", GPIOL },
85 [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
86 };
87
88 /* pin is expected to be valid */
get_gmbus_pin(struct drm_i915_private * dev_priv,unsigned int pin)89 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
90 unsigned int pin)
91 {
92 if (HAS_PCH_ICP(dev_priv))
93 return &gmbus_pins_icp[pin];
94 else if (HAS_PCH_CNP(dev_priv))
95 return &gmbus_pins_cnp[pin];
96 else if (IS_GEN9_LP(dev_priv))
97 return &gmbus_pins_bxt[pin];
98 else if (IS_GEN9_BC(dev_priv))
99 return &gmbus_pins_skl[pin];
100 else if (IS_BROADWELL(dev_priv))
101 return &gmbus_pins_bdw[pin];
102 else
103 return &gmbus_pins[pin];
104 }
105
intel_gmbus_is_valid_pin(struct drm_i915_private * dev_priv,unsigned int pin)106 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
107 unsigned int pin)
108 {
109 unsigned int size;
110
111 if (HAS_PCH_ICP(dev_priv))
112 size = ARRAY_SIZE(gmbus_pins_icp);
113 else if (HAS_PCH_CNP(dev_priv))
114 size = ARRAY_SIZE(gmbus_pins_cnp);
115 else if (IS_GEN9_LP(dev_priv))
116 size = ARRAY_SIZE(gmbus_pins_bxt);
117 else if (IS_GEN9_BC(dev_priv))
118 size = ARRAY_SIZE(gmbus_pins_skl);
119 else if (IS_BROADWELL(dev_priv))
120 size = ARRAY_SIZE(gmbus_pins_bdw);
121 else
122 size = ARRAY_SIZE(gmbus_pins);
123
124 return pin < size &&
125 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
126 }
127
128 /* Intel GPIO access functions */
129
130 #define I2C_RISEFALL_TIME 10
131
132 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)133 to_intel_gmbus(struct i2c_adapter *i2c)
134 {
135 return container_of(i2c, struct intel_gmbus, adapter);
136 }
137
138 void
intel_i2c_reset(struct drm_i915_private * dev_priv)139 intel_i2c_reset(struct drm_i915_private *dev_priv)
140 {
141 I915_WRITE(GMBUS0, 0);
142 I915_WRITE(GMBUS4, 0);
143 }
144
pnv_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)145 static void pnv_gmbus_clock_gating(struct drm_i915_private *dev_priv,
146 bool enable)
147 {
148 u32 val;
149
150 /* When using bit bashing for I2C, this bit needs to be set to 1 */
151 val = I915_READ(DSPCLK_GATE_D);
152 if (!enable)
153 val |= PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
154 else
155 val &= ~PNV_GMBUSUNIT_CLOCK_GATE_DISABLE;
156 I915_WRITE(DSPCLK_GATE_D, val);
157 }
158
pch_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)159 static void pch_gmbus_clock_gating(struct drm_i915_private *dev_priv,
160 bool enable)
161 {
162 u32 val;
163
164 val = I915_READ(SOUTH_DSPCLK_GATE_D);
165 if (!enable)
166 val |= PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
167 else
168 val &= ~PCH_GMBUSUNIT_CLOCK_GATE_DISABLE;
169 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
170 }
171
bxt_gmbus_clock_gating(struct drm_i915_private * dev_priv,bool enable)172 static void bxt_gmbus_clock_gating(struct drm_i915_private *dev_priv,
173 bool enable)
174 {
175 u32 val;
176
177 val = I915_READ(GEN9_CLKGATE_DIS_4);
178 if (!enable)
179 val |= BXT_GMBUS_GATING_DIS;
180 else
181 val &= ~BXT_GMBUS_GATING_DIS;
182 I915_WRITE(GEN9_CLKGATE_DIS_4, val);
183 }
184
get_reserved(struct intel_gmbus * bus)185 static u32 get_reserved(struct intel_gmbus *bus)
186 {
187 struct drm_i915_private *dev_priv = bus->dev_priv;
188 u32 reserved = 0;
189
190 /* On most chips, these bits must be preserved in software. */
191 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
192 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
193 (GPIO_DATA_PULLUP_DISABLE |
194 GPIO_CLOCK_PULLUP_DISABLE);
195
196 return reserved;
197 }
198
get_clock(void * data)199 static int get_clock(void *data)
200 {
201 struct intel_gmbus *bus = data;
202 struct drm_i915_private *dev_priv = bus->dev_priv;
203 u32 reserved = get_reserved(bus);
204 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
205 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
206 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
207 }
208
get_data(void * data)209 static int get_data(void *data)
210 {
211 struct intel_gmbus *bus = data;
212 struct drm_i915_private *dev_priv = bus->dev_priv;
213 u32 reserved = get_reserved(bus);
214 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
215 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
216 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
217 }
218
set_clock(void * data,int state_high)219 static void set_clock(void *data, int state_high)
220 {
221 struct intel_gmbus *bus = data;
222 struct drm_i915_private *dev_priv = bus->dev_priv;
223 u32 reserved = get_reserved(bus);
224 u32 clock_bits;
225
226 if (state_high)
227 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
228 else
229 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
230 GPIO_CLOCK_VAL_MASK;
231
232 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
233 POSTING_READ(bus->gpio_reg);
234 }
235
set_data(void * data,int state_high)236 static void set_data(void *data, int state_high)
237 {
238 struct intel_gmbus *bus = data;
239 struct drm_i915_private *dev_priv = bus->dev_priv;
240 u32 reserved = get_reserved(bus);
241 u32 data_bits;
242
243 if (state_high)
244 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
245 else
246 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
247 GPIO_DATA_VAL_MASK;
248
249 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
250 POSTING_READ(bus->gpio_reg);
251 }
252
253 static int
intel_gpio_pre_xfer(struct i2c_adapter * adapter)254 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
255 {
256 struct intel_gmbus *bus = container_of(adapter,
257 struct intel_gmbus,
258 adapter);
259 struct drm_i915_private *dev_priv = bus->dev_priv;
260
261 intel_i2c_reset(dev_priv);
262
263 if (IS_PINEVIEW(dev_priv))
264 pnv_gmbus_clock_gating(dev_priv, false);
265
266 set_data(bus, 1);
267 set_clock(bus, 1);
268 udelay(I2C_RISEFALL_TIME);
269 return 0;
270 }
271
272 static void
intel_gpio_post_xfer(struct i2c_adapter * adapter)273 intel_gpio_post_xfer(struct i2c_adapter *adapter)
274 {
275 struct intel_gmbus *bus = container_of(adapter,
276 struct intel_gmbus,
277 adapter);
278 struct drm_i915_private *dev_priv = bus->dev_priv;
279
280 set_data(bus, 1);
281 set_clock(bus, 1);
282
283 if (IS_PINEVIEW(dev_priv))
284 pnv_gmbus_clock_gating(dev_priv, true);
285 }
286
287 static void
intel_gpio_setup(struct intel_gmbus * bus,unsigned int pin)288 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
289 {
290 struct drm_i915_private *dev_priv = bus->dev_priv;
291 struct i2c_algo_bit_data *algo;
292
293 algo = &bus->bit_algo;
294
295 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
296 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
297 bus->adapter.algo_data = algo;
298 algo->setsda = set_data;
299 algo->setscl = set_clock;
300 algo->getsda = get_data;
301 algo->getscl = get_clock;
302 algo->pre_xfer = intel_gpio_pre_xfer;
303 algo->post_xfer = intel_gpio_post_xfer;
304 algo->udelay = I2C_RISEFALL_TIME;
305 algo->timeout = usecs_to_jiffies(2200);
306 algo->data = bus;
307 }
308
gmbus_wait(struct drm_i915_private * dev_priv,u32 status,u32 irq_en)309 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
310 {
311 DEFINE_WAIT(wait);
312 u32 gmbus2;
313 int ret;
314
315 /* Important: The hw handles only the first bit, so set only one! Since
316 * we also need to check for NAKs besides the hw ready/idle signal, we
317 * need to wake up periodically and check that ourselves.
318 */
319 if (!HAS_GMBUS_IRQ(dev_priv))
320 irq_en = 0;
321
322 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
323 I915_WRITE_FW(GMBUS4, irq_en);
324
325 status |= GMBUS_SATOER;
326 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
327 if (ret)
328 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
329
330 I915_WRITE_FW(GMBUS4, 0);
331 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
332
333 if (gmbus2 & GMBUS_SATOER)
334 return -ENXIO;
335
336 return ret;
337 }
338
339 static int
gmbus_wait_idle(struct drm_i915_private * dev_priv)340 gmbus_wait_idle(struct drm_i915_private *dev_priv)
341 {
342 DEFINE_WAIT(wait);
343 u32 irq_enable;
344 int ret;
345
346 /* Important: The hw handles only the first bit, so set only one! */
347 irq_enable = 0;
348 if (HAS_GMBUS_IRQ(dev_priv))
349 irq_enable = GMBUS_IDLE_EN;
350
351 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
352 I915_WRITE_FW(GMBUS4, irq_enable);
353
354 ret = intel_wait_for_register_fw(dev_priv,
355 GMBUS2, GMBUS_ACTIVE, 0,
356 10);
357
358 I915_WRITE_FW(GMBUS4, 0);
359 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
360
361 return ret;
362 }
363
364 static inline
gmbus_max_xfer_size(struct drm_i915_private * dev_priv)365 unsigned int gmbus_max_xfer_size(struct drm_i915_private *dev_priv)
366 {
367 return INTEL_GEN(dev_priv) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
368 GMBUS_BYTE_COUNT_MAX;
369 }
370
371 static int
gmbus_xfer_read_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus0_reg,u32 gmbus1_index)372 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
373 unsigned short addr, u8 *buf, unsigned int len,
374 u32 gmbus0_reg, u32 gmbus1_index)
375 {
376 unsigned int size = len;
377 bool burst_read = len > gmbus_max_xfer_size(dev_priv);
378 bool extra_byte_added = false;
379
380 if (burst_read) {
381 /*
382 * As per HW Spec, for 512Bytes need to read extra Byte and
383 * Ignore the extra byte read.
384 */
385 if (len == 512) {
386 extra_byte_added = true;
387 len++;
388 }
389 size = len % 256 + 256;
390 I915_WRITE_FW(GMBUS0, gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
391 }
392
393 I915_WRITE_FW(GMBUS1,
394 gmbus1_index |
395 GMBUS_CYCLE_WAIT |
396 (size << GMBUS_BYTE_COUNT_SHIFT) |
397 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
398 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
399 while (len) {
400 int ret;
401 u32 val, loop = 0;
402
403 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
404 if (ret)
405 return ret;
406
407 val = I915_READ_FW(GMBUS3);
408 do {
409 if (extra_byte_added && len == 1)
410 break;
411
412 *buf++ = val & 0xff;
413 val >>= 8;
414 } while (--len && ++loop < 4);
415
416 if (burst_read && len == size - 4)
417 /* Reset the override bit */
418 I915_WRITE_FW(GMBUS0, gmbus0_reg);
419 }
420
421 return 0;
422 }
423
424 /*
425 * HW spec says that 512Bytes in Burst read need special treatment.
426 * But it doesn't talk about other multiple of 256Bytes. And couldn't locate
427 * an I2C slave, which supports such a lengthy burst read too for experiments.
428 *
429 * So until things get clarified on HW support, to avoid the burst read length
430 * in fold of 256Bytes except 512, max burst read length is fixed at 767Bytes.
431 */
432 #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
433
434 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus0_reg,u32 gmbus1_index)435 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
436 u32 gmbus0_reg, u32 gmbus1_index)
437 {
438 u8 *buf = msg->buf;
439 unsigned int rx_size = msg->len;
440 unsigned int len;
441 int ret;
442
443 do {
444 if (HAS_GMBUS_BURST_READ(dev_priv))
445 len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
446 else
447 len = min(rx_size, gmbus_max_xfer_size(dev_priv));
448
449 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr, buf, len,
450 gmbus0_reg, gmbus1_index);
451 if (ret)
452 return ret;
453
454 rx_size -= len;
455 buf += len;
456 } while (rx_size != 0);
457
458 return 0;
459 }
460
461 static int
gmbus_xfer_write_chunk(struct drm_i915_private * dev_priv,unsigned short addr,u8 * buf,unsigned int len,u32 gmbus1_index)462 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
463 unsigned short addr, u8 *buf, unsigned int len,
464 u32 gmbus1_index)
465 {
466 unsigned int chunk_size = len;
467 u32 val, loop;
468
469 val = loop = 0;
470 while (len && loop < 4) {
471 val |= *buf++ << (8 * loop++);
472 len -= 1;
473 }
474
475 I915_WRITE_FW(GMBUS3, val);
476 I915_WRITE_FW(GMBUS1,
477 gmbus1_index | GMBUS_CYCLE_WAIT |
478 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
479 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
480 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
481 while (len) {
482 int ret;
483
484 val = loop = 0;
485 do {
486 val |= *buf++ << (8 * loop);
487 } while (--len && ++loop < 4);
488
489 I915_WRITE_FW(GMBUS3, val);
490
491 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
492 if (ret)
493 return ret;
494 }
495
496 return 0;
497 }
498
499 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus1_index)500 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
501 u32 gmbus1_index)
502 {
503 u8 *buf = msg->buf;
504 unsigned int tx_size = msg->len;
505 unsigned int len;
506 int ret;
507
508 do {
509 len = min(tx_size, gmbus_max_xfer_size(dev_priv));
510
511 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
512 gmbus1_index);
513 if (ret)
514 return ret;
515
516 buf += len;
517 tx_size -= len;
518 } while (tx_size != 0);
519
520 return 0;
521 }
522
523 /*
524 * The gmbus controller can combine a 1 or 2 byte write with another read/write
525 * that immediately follows it by using an "INDEX" cycle.
526 */
527 static bool
gmbus_is_index_xfer(struct i2c_msg * msgs,int i,int num)528 gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
529 {
530 return (i + 1 < num &&
531 msgs[i].addr == msgs[i + 1].addr &&
532 !(msgs[i].flags & I2C_M_RD) &&
533 (msgs[i].len == 1 || msgs[i].len == 2) &&
534 msgs[i + 1].len > 0);
535 }
536
537 static int
gmbus_index_xfer(struct drm_i915_private * dev_priv,struct i2c_msg * msgs,u32 gmbus0_reg)538 gmbus_index_xfer(struct drm_i915_private *dev_priv, struct i2c_msg *msgs,
539 u32 gmbus0_reg)
540 {
541 u32 gmbus1_index = 0;
542 u32 gmbus5 = 0;
543 int ret;
544
545 if (msgs[0].len == 2)
546 gmbus5 = GMBUS_2BYTE_INDEX_EN |
547 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
548 if (msgs[0].len == 1)
549 gmbus1_index = GMBUS_CYCLE_INDEX |
550 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
551
552 /* GMBUS5 holds 16-bit index */
553 if (gmbus5)
554 I915_WRITE_FW(GMBUS5, gmbus5);
555
556 if (msgs[1].flags & I2C_M_RD)
557 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus0_reg,
558 gmbus1_index);
559 else
560 ret = gmbus_xfer_write(dev_priv, &msgs[1], gmbus1_index);
561
562 /* Clear GMBUS5 after each index transfer */
563 if (gmbus5)
564 I915_WRITE_FW(GMBUS5, 0);
565
566 return ret;
567 }
568
569 static int
do_gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num,u32 gmbus0_source)570 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
571 u32 gmbus0_source)
572 {
573 struct intel_gmbus *bus = container_of(adapter,
574 struct intel_gmbus,
575 adapter);
576 struct drm_i915_private *dev_priv = bus->dev_priv;
577 int i = 0, inc, try = 0;
578 int ret = 0;
579
580 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
581 if (IS_GEN9_LP(dev_priv))
582 bxt_gmbus_clock_gating(dev_priv, false);
583 else if (HAS_PCH_SPT(dev_priv) ||
584 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
585 pch_gmbus_clock_gating(dev_priv, false);
586
587 retry:
588 I915_WRITE_FW(GMBUS0, gmbus0_source | bus->reg0);
589
590 for (; i < num; i += inc) {
591 inc = 1;
592 if (gmbus_is_index_xfer(msgs, i, num)) {
593 ret = gmbus_index_xfer(dev_priv, &msgs[i],
594 gmbus0_source | bus->reg0);
595 inc = 2; /* an index transmission is two msgs */
596 } else if (msgs[i].flags & I2C_M_RD) {
597 ret = gmbus_xfer_read(dev_priv, &msgs[i],
598 gmbus0_source | bus->reg0, 0);
599 } else {
600 ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
601 }
602
603 if (!ret)
604 ret = gmbus_wait(dev_priv,
605 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
606 if (ret == -ETIMEDOUT)
607 goto timeout;
608 else if (ret)
609 goto clear_err;
610 }
611
612 /* Generate a STOP condition on the bus. Note that gmbus can't generata
613 * a STOP on the very first cycle. To simplify the code we
614 * unconditionally generate the STOP condition with an additional gmbus
615 * cycle. */
616 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
617
618 /* Mark the GMBUS interface as disabled after waiting for idle.
619 * We will re-enable it at the start of the next xfer,
620 * till then let it sleep.
621 */
622 if (gmbus_wait_idle(dev_priv)) {
623 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
624 adapter->name);
625 ret = -ETIMEDOUT;
626 }
627 I915_WRITE_FW(GMBUS0, 0);
628 ret = ret ?: i;
629 goto out;
630
631 clear_err:
632 /*
633 * Wait for bus to IDLE before clearing NAK.
634 * If we clear the NAK while bus is still active, then it will stay
635 * active and the next transaction may fail.
636 *
637 * If no ACK is received during the address phase of a transaction, the
638 * adapter must report -ENXIO. It is not clear what to return if no ACK
639 * is received at other times. But we have to be careful to not return
640 * spurious -ENXIO because that will prevent i2c and drm edid functions
641 * from retrying. So return -ENXIO only when gmbus properly quiescents -
642 * timing out seems to happen when there _is_ a ddc chip present, but
643 * it's slow responding and only answers on the 2nd retry.
644 */
645 ret = -ENXIO;
646 if (gmbus_wait_idle(dev_priv)) {
647 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
648 adapter->name);
649 ret = -ETIMEDOUT;
650 }
651
652 /* Toggle the Software Clear Interrupt bit. This has the effect
653 * of resetting the GMBUS controller and so clearing the
654 * BUS_ERROR raised by the slave's NAK.
655 */
656 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
657 I915_WRITE_FW(GMBUS1, 0);
658 I915_WRITE_FW(GMBUS0, 0);
659
660 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
661 adapter->name, msgs[i].addr,
662 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
663
664 /*
665 * Passive adapters sometimes NAK the first probe. Retry the first
666 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
667 * has retries internally. See also the retry loop in
668 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
669 */
670 if (ret == -ENXIO && i == 0 && try++ == 0) {
671 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
672 adapter->name);
673 goto retry;
674 }
675
676 goto out;
677
678 timeout:
679 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
680 bus->adapter.name, bus->reg0 & 0xff);
681 I915_WRITE_FW(GMBUS0, 0);
682
683 /*
684 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
685 * instead. Use EAGAIN to have i2c core retry.
686 */
687 ret = -EAGAIN;
688
689 out:
690 /* Display WA #0868: skl,bxt,kbl,cfl,glk,cnl */
691 if (IS_GEN9_LP(dev_priv))
692 bxt_gmbus_clock_gating(dev_priv, true);
693 else if (HAS_PCH_SPT(dev_priv) ||
694 HAS_PCH_KBP(dev_priv) || HAS_PCH_CNP(dev_priv))
695 pch_gmbus_clock_gating(dev_priv, true);
696
697 return ret;
698 }
699
700 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)701 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
702 {
703 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
704 adapter);
705 struct drm_i915_private *dev_priv = bus->dev_priv;
706 int ret;
707
708 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
709
710 if (bus->force_bit) {
711 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
712 if (ret < 0)
713 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
714 } else {
715 ret = do_gmbus_xfer(adapter, msgs, num, 0);
716 if (ret == -EAGAIN)
717 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
718 }
719
720 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
721
722 return ret;
723 }
724
intel_gmbus_output_aksv(struct i2c_adapter * adapter)725 int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
726 {
727 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
728 adapter);
729 struct drm_i915_private *dev_priv = bus->dev_priv;
730 int ret;
731 u8 cmd = DRM_HDCP_DDC_AKSV;
732 u8 buf[DRM_HDCP_KSV_LEN] = { 0 };
733 struct i2c_msg msgs[] = {
734 {
735 .addr = DRM_HDCP_DDC_ADDR,
736 .flags = 0,
737 .len = sizeof(cmd),
738 .buf = &cmd,
739 },
740 {
741 .addr = DRM_HDCP_DDC_ADDR,
742 .flags = 0,
743 .len = sizeof(buf),
744 .buf = buf,
745 }
746 };
747
748 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
749 mutex_lock(&dev_priv->gmbus_mutex);
750
751 /*
752 * In order to output Aksv to the receiver, use an indexed write to
753 * pass the i2c command, and tell GMBUS to use the HW-provided value
754 * instead of sourcing GMBUS3 for the data.
755 */
756 ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
757
758 mutex_unlock(&dev_priv->gmbus_mutex);
759 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
760
761 return ret;
762 }
763
gmbus_func(struct i2c_adapter * adapter)764 static u32 gmbus_func(struct i2c_adapter *adapter)
765 {
766 return i2c_bit_algo.functionality(adapter) &
767 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
768 /* I2C_FUNC_10BIT_ADDR | */
769 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
770 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
771 }
772
773 static const struct i2c_algorithm gmbus_algorithm = {
774 .master_xfer = gmbus_xfer,
775 .functionality = gmbus_func
776 };
777
gmbus_lock_bus(struct i2c_adapter * adapter,unsigned int flags)778 static void gmbus_lock_bus(struct i2c_adapter *adapter,
779 unsigned int flags)
780 {
781 struct intel_gmbus *bus = to_intel_gmbus(adapter);
782 struct drm_i915_private *dev_priv = bus->dev_priv;
783
784 mutex_lock(&dev_priv->gmbus_mutex);
785 }
786
gmbus_trylock_bus(struct i2c_adapter * adapter,unsigned int flags)787 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
788 unsigned int flags)
789 {
790 struct intel_gmbus *bus = to_intel_gmbus(adapter);
791 struct drm_i915_private *dev_priv = bus->dev_priv;
792
793 return mutex_trylock(&dev_priv->gmbus_mutex);
794 }
795
gmbus_unlock_bus(struct i2c_adapter * adapter,unsigned int flags)796 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
797 unsigned int flags)
798 {
799 struct intel_gmbus *bus = to_intel_gmbus(adapter);
800 struct drm_i915_private *dev_priv = bus->dev_priv;
801
802 mutex_unlock(&dev_priv->gmbus_mutex);
803 }
804
805 static const struct i2c_lock_operations gmbus_lock_ops = {
806 .lock_bus = gmbus_lock_bus,
807 .trylock_bus = gmbus_trylock_bus,
808 .unlock_bus = gmbus_unlock_bus,
809 };
810
811 /**
812 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
813 * @dev_priv: i915 device private
814 */
intel_setup_gmbus(struct drm_i915_private * dev_priv)815 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
816 {
817 struct pci_dev *pdev = dev_priv->drm.pdev;
818 struct intel_gmbus *bus;
819 unsigned int pin;
820 int ret;
821
822 if (INTEL_INFO(dev_priv)->num_pipes == 0)
823 return 0;
824
825 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
826 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
827 else if (!HAS_GMCH_DISPLAY(dev_priv))
828 dev_priv->gpio_mmio_base =
829 i915_mmio_reg_offset(PCH_GPIOA) -
830 i915_mmio_reg_offset(GPIOA);
831
832 mutex_init(&dev_priv->gmbus_mutex);
833 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
834
835 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
836 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
837 continue;
838
839 bus = &dev_priv->gmbus[pin];
840
841 bus->adapter.owner = THIS_MODULE;
842 bus->adapter.class = I2C_CLASS_DDC;
843 snprintf(bus->adapter.name,
844 sizeof(bus->adapter.name),
845 "i915 gmbus %s",
846 get_gmbus_pin(dev_priv, pin)->name);
847
848 bus->adapter.dev.parent = &pdev->dev;
849 bus->dev_priv = dev_priv;
850
851 bus->adapter.algo = &gmbus_algorithm;
852 bus->adapter.lock_ops = &gmbus_lock_ops;
853
854 /*
855 * We wish to retry with bit banging
856 * after a timed out GMBUS attempt.
857 */
858 bus->adapter.retries = 1;
859
860 /* By default use a conservative clock rate */
861 bus->reg0 = pin | GMBUS_RATE_100KHZ;
862
863 /* gmbus seems to be broken on i830 */
864 if (IS_I830(dev_priv))
865 bus->force_bit = 1;
866
867 intel_gpio_setup(bus, pin);
868
869 ret = i2c_add_adapter(&bus->adapter);
870 if (ret)
871 goto err;
872 }
873
874 intel_i2c_reset(dev_priv);
875
876 return 0;
877
878 err:
879 while (pin--) {
880 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
881 continue;
882
883 bus = &dev_priv->gmbus[pin];
884 i2c_del_adapter(&bus->adapter);
885 }
886 return ret;
887 }
888
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned int pin)889 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
890 unsigned int pin)
891 {
892 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
893 return NULL;
894
895 return &dev_priv->gmbus[pin].adapter;
896 }
897
intel_gmbus_set_speed(struct i2c_adapter * adapter,int speed)898 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
899 {
900 struct intel_gmbus *bus = to_intel_gmbus(adapter);
901
902 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
903 }
904
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)905 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
906 {
907 struct intel_gmbus *bus = to_intel_gmbus(adapter);
908 struct drm_i915_private *dev_priv = bus->dev_priv;
909
910 mutex_lock(&dev_priv->gmbus_mutex);
911
912 bus->force_bit += force_bit ? 1 : -1;
913 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
914 force_bit ? "en" : "dis", adapter->name,
915 bus->force_bit);
916
917 mutex_unlock(&dev_priv->gmbus_mutex);
918 }
919
intel_teardown_gmbus(struct drm_i915_private * dev_priv)920 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
921 {
922 struct intel_gmbus *bus;
923 unsigned int pin;
924
925 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
926 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
927 continue;
928
929 bus = &dev_priv->gmbus[pin];
930 i2c_del_adapter(&bus->adapter);
931 }
932 }
933
