1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Per core/cpu state
4 *
5 * Used to coordinate shared registers between HT threads or
6 * among events on a single PMU.
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/stddef.h>
12 #include <linux/types.h>
13 #include <linux/init.h>
14 #include <linux/slab.h>
15 #include <linux/export.h>
16 #include <linux/nmi.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/hardirq.h>
20 #include <asm/intel-family.h>
21 #include <asm/intel_pt.h>
22 #include <asm/apic.h>
23 #include <asm/cpu_device_id.h>
24
25 #include "../perf_event.h"
26
27 /*
28 * Intel PerfMon, used on Core and later.
29 */
30 static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
31 {
32 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
33 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
34 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
35 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
36 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
37 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
38 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
39 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
40 };
41
42 static struct event_constraint intel_core_event_constraints[] __read_mostly =
43 {
44 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
45 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
46 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
47 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
48 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
49 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
50 EVENT_CONSTRAINT_END
51 };
52
53 static struct event_constraint intel_core2_event_constraints[] __read_mostly =
54 {
55 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
56 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
57 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
58 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
59 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
60 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
61 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
62 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
63 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
64 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
65 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
66 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
67 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
68 EVENT_CONSTRAINT_END
69 };
70
71 static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
72 {
73 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
74 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
75 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
76 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
77 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
78 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
79 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
80 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
81 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
82 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
83 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
84 EVENT_CONSTRAINT_END
85 };
86
87 static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
88 {
89 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
90 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
91 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
92 EVENT_EXTRA_END
93 };
94
95 static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
96 {
97 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
98 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
99 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
100 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
101 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
102 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
103 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
104 EVENT_CONSTRAINT_END
105 };
106
107 static struct event_constraint intel_snb_event_constraints[] __read_mostly =
108 {
109 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
110 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
111 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
112 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
113 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
114 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
115 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
116 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
117 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
118 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
119 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
120 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
121
122 /*
123 * When HT is off these events can only run on the bottom 4 counters
124 * When HT is on, they are impacted by the HT bug and require EXCL access
125 */
126 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
127 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
128 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
129 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
130
131 EVENT_CONSTRAINT_END
132 };
133
134 static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
135 {
136 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
137 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
138 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
139 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
140 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
141 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
142 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
144 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
146 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
147 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
148 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
149
150 /*
151 * When HT is off these events can only run on the bottom 4 counters
152 * When HT is on, they are impacted by the HT bug and require EXCL access
153 */
154 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
155 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
156 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
157 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
158
159 EVENT_CONSTRAINT_END
160 };
161
162 static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
163 {
164 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
165 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
167 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
168 EVENT_EXTRA_END
169 };
170
171 static struct event_constraint intel_v1_event_constraints[] __read_mostly =
172 {
173 EVENT_CONSTRAINT_END
174 };
175
176 static struct event_constraint intel_gen_event_constraints[] __read_mostly =
177 {
178 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
179 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
180 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
181 EVENT_CONSTRAINT_END
182 };
183
184 static struct event_constraint intel_slm_event_constraints[] __read_mostly =
185 {
186 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
187 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
188 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
189 EVENT_CONSTRAINT_END
190 };
191
192 static struct event_constraint intel_skl_event_constraints[] = {
193 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
194 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
195 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
196 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
197
198 /*
199 * when HT is off, these can only run on the bottom 4 counters
200 */
201 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
203 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
204 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
205 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
206
207 EVENT_CONSTRAINT_END
208 };
209
210 static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
211 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
213 EVENT_EXTRA_END
214 };
215
216 static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
217 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
218 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
220 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
221 EVENT_EXTRA_END
222 };
223
224 static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
225 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
226 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
228 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
229 EVENT_EXTRA_END
230 };
231
232 static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
233 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
235 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
236 /*
237 * Note the low 8 bits eventsel code is not a continuous field, containing
238 * some #GPing bits. These are masked out.
239 */
240 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
241 EVENT_EXTRA_END
242 };
243
244 static struct event_constraint intel_icl_event_constraints[] = {
245 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
246 FIXED_EVENT_CONSTRAINT(0x01c0, 0), /* INST_RETIRED.PREC_DIST */
247 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
248 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
249 FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
250 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_RETIRING, 0),
251 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BAD_SPEC, 1),
252 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_FE_BOUND, 2),
253 METRIC_EVENT_CONSTRAINT(INTEL_TD_METRIC_BE_BOUND, 3),
254 INTEL_EVENT_CONSTRAINT_RANGE(0x03, 0x0a, 0xf),
255 INTEL_EVENT_CONSTRAINT_RANGE(0x1f, 0x28, 0xf),
256 INTEL_EVENT_CONSTRAINT(0x32, 0xf), /* SW_PREFETCH_ACCESS.* */
257 INTEL_EVENT_CONSTRAINT_RANGE(0x48, 0x54, 0xf),
258 INTEL_EVENT_CONSTRAINT_RANGE(0x60, 0x8b, 0xf),
259 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xff), /* CYCLE_ACTIVITY.STALLS_TOTAL */
260 INTEL_UEVENT_CONSTRAINT(0x10a3, 0xff), /* CYCLE_ACTIVITY.STALLS_MEM_ANY */
261 INTEL_EVENT_CONSTRAINT(0xa3, 0xf), /* CYCLE_ACTIVITY.* */
262 INTEL_EVENT_CONSTRAINT_RANGE(0xa8, 0xb0, 0xf),
263 INTEL_EVENT_CONSTRAINT_RANGE(0xb7, 0xbd, 0xf),
264 INTEL_EVENT_CONSTRAINT_RANGE(0xd0, 0xe6, 0xf),
265 INTEL_EVENT_CONSTRAINT_RANGE(0xf0, 0xf4, 0xf),
266 EVENT_CONSTRAINT_END
267 };
268
269 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
270 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
271 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
272 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
273 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
274 EVENT_EXTRA_END
275 };
276
277 EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
278 EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
279 EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
280
281 static struct attribute *nhm_mem_events_attrs[] = {
282 EVENT_PTR(mem_ld_nhm),
283 NULL,
284 };
285
286 /*
287 * topdown events for Intel Core CPUs.
288 *
289 * The events are all in slots, which is a free slot in a 4 wide
290 * pipeline. Some events are already reported in slots, for cycle
291 * events we multiply by the pipeline width (4).
292 *
293 * With Hyper Threading on, topdown metrics are either summed or averaged
294 * between the threads of a core: (count_t0 + count_t1).
295 *
296 * For the average case the metric is always scaled to pipeline width,
297 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
298 */
299
300 EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
301 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
302 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
303 EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
304 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
305 "event=0xe,umask=0x1"); /* uops_issued.any */
306 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
307 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
308 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
309 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
310 EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
311 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
312 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
313 EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
314 "4", "2");
315
316 EVENT_ATTR_STR(slots, slots, "event=0x00,umask=0x4");
317 EVENT_ATTR_STR(topdown-retiring, td_retiring, "event=0x00,umask=0x80");
318 EVENT_ATTR_STR(topdown-bad-spec, td_bad_spec, "event=0x00,umask=0x81");
319 EVENT_ATTR_STR(topdown-fe-bound, td_fe_bound, "event=0x00,umask=0x82");
320 EVENT_ATTR_STR(topdown-be-bound, td_be_bound, "event=0x00,umask=0x83");
321
322 static struct attribute *snb_events_attrs[] = {
323 EVENT_PTR(td_slots_issued),
324 EVENT_PTR(td_slots_retired),
325 EVENT_PTR(td_fetch_bubbles),
326 EVENT_PTR(td_total_slots),
327 EVENT_PTR(td_total_slots_scale),
328 EVENT_PTR(td_recovery_bubbles),
329 EVENT_PTR(td_recovery_bubbles_scale),
330 NULL,
331 };
332
333 static struct attribute *snb_mem_events_attrs[] = {
334 EVENT_PTR(mem_ld_snb),
335 EVENT_PTR(mem_st_snb),
336 NULL,
337 };
338
339 static struct event_constraint intel_hsw_event_constraints[] = {
340 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
341 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
342 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
343 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
344 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
345 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
346 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
347 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
348 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
349 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
350 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
351 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
352
353 /*
354 * When HT is off these events can only run on the bottom 4 counters
355 * When HT is on, they are impacted by the HT bug and require EXCL access
356 */
357 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
358 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
359 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
360 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
361
362 EVENT_CONSTRAINT_END
363 };
364
365 static struct event_constraint intel_bdw_event_constraints[] = {
366 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
367 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
368 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
369 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
370 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
371 /*
372 * when HT is off, these can only run on the bottom 4 counters
373 */
374 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
375 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
376 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
377 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
378 EVENT_CONSTRAINT_END
379 };
380
intel_pmu_event_map(int hw_event)381 static u64 intel_pmu_event_map(int hw_event)
382 {
383 return intel_perfmon_event_map[hw_event];
384 }
385
386 /*
387 * Notes on the events:
388 * - data reads do not include code reads (comparable to earlier tables)
389 * - data counts include speculative execution (except L1 write, dtlb, bpu)
390 * - remote node access includes remote memory, remote cache, remote mmio.
391 * - prefetches are not included in the counts.
392 * - icache miss does not include decoded icache
393 */
394
395 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
396 #define SKL_DEMAND_RFO BIT_ULL(1)
397 #define SKL_ANY_RESPONSE BIT_ULL(16)
398 #define SKL_SUPPLIER_NONE BIT_ULL(17)
399 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
400 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
401 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
402 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
403 #define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
404 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
405 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
406 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
407 #define SKL_SPL_HIT BIT_ULL(30)
408 #define SKL_SNOOP_NONE BIT_ULL(31)
409 #define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
410 #define SKL_SNOOP_MISS BIT_ULL(33)
411 #define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
412 #define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
413 #define SKL_SNOOP_HITM BIT_ULL(36)
414 #define SKL_SNOOP_NON_DRAM BIT_ULL(37)
415 #define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
416 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
417 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
418 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
419 #define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
420 #define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
421 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
422 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
423 SKL_SNOOP_HITM|SKL_SPL_HIT)
424 #define SKL_DEMAND_WRITE SKL_DEMAND_RFO
425 #define SKL_LLC_ACCESS SKL_ANY_RESPONSE
426 #define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
427 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
428 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
429
430 static __initconst const u64 skl_hw_cache_event_ids
431 [PERF_COUNT_HW_CACHE_MAX]
432 [PERF_COUNT_HW_CACHE_OP_MAX]
433 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
434 {
435 [ C(L1D ) ] = {
436 [ C(OP_READ) ] = {
437 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
438 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
439 },
440 [ C(OP_WRITE) ] = {
441 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 [ C(OP_PREFETCH) ] = {
445 [ C(RESULT_ACCESS) ] = 0x0,
446 [ C(RESULT_MISS) ] = 0x0,
447 },
448 },
449 [ C(L1I ) ] = {
450 [ C(OP_READ) ] = {
451 [ C(RESULT_ACCESS) ] = 0x0,
452 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
453 },
454 [ C(OP_WRITE) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 [ C(OP_PREFETCH) ] = {
459 [ C(RESULT_ACCESS) ] = 0x0,
460 [ C(RESULT_MISS) ] = 0x0,
461 },
462 },
463 [ C(LL ) ] = {
464 [ C(OP_READ) ] = {
465 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
466 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
467 },
468 [ C(OP_WRITE) ] = {
469 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
470 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
471 },
472 [ C(OP_PREFETCH) ] = {
473 [ C(RESULT_ACCESS) ] = 0x0,
474 [ C(RESULT_MISS) ] = 0x0,
475 },
476 },
477 [ C(DTLB) ] = {
478 [ C(OP_READ) ] = {
479 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
480 [ C(RESULT_MISS) ] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
481 },
482 [ C(OP_WRITE) ] = {
483 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
484 [ C(RESULT_MISS) ] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
485 },
486 [ C(OP_PREFETCH) ] = {
487 [ C(RESULT_ACCESS) ] = 0x0,
488 [ C(RESULT_MISS) ] = 0x0,
489 },
490 },
491 [ C(ITLB) ] = {
492 [ C(OP_READ) ] = {
493 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
494 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
495 },
496 [ C(OP_WRITE) ] = {
497 [ C(RESULT_ACCESS) ] = -1,
498 [ C(RESULT_MISS) ] = -1,
499 },
500 [ C(OP_PREFETCH) ] = {
501 [ C(RESULT_ACCESS) ] = -1,
502 [ C(RESULT_MISS) ] = -1,
503 },
504 },
505 [ C(BPU ) ] = {
506 [ C(OP_READ) ] = {
507 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
508 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
509 },
510 [ C(OP_WRITE) ] = {
511 [ C(RESULT_ACCESS) ] = -1,
512 [ C(RESULT_MISS) ] = -1,
513 },
514 [ C(OP_PREFETCH) ] = {
515 [ C(RESULT_ACCESS) ] = -1,
516 [ C(RESULT_MISS) ] = -1,
517 },
518 },
519 [ C(NODE) ] = {
520 [ C(OP_READ) ] = {
521 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
522 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
523 },
524 [ C(OP_WRITE) ] = {
525 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
526 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
527 },
528 [ C(OP_PREFETCH) ] = {
529 [ C(RESULT_ACCESS) ] = 0x0,
530 [ C(RESULT_MISS) ] = 0x0,
531 },
532 },
533 };
534
535 static __initconst const u64 skl_hw_cache_extra_regs
536 [PERF_COUNT_HW_CACHE_MAX]
537 [PERF_COUNT_HW_CACHE_OP_MAX]
538 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
539 {
540 [ C(LL ) ] = {
541 [ C(OP_READ) ] = {
542 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
543 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
544 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
545 SKL_L3_MISS|SKL_ANY_SNOOP|
546 SKL_SUPPLIER_NONE,
547 },
548 [ C(OP_WRITE) ] = {
549 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
550 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
551 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
552 SKL_L3_MISS|SKL_ANY_SNOOP|
553 SKL_SUPPLIER_NONE,
554 },
555 [ C(OP_PREFETCH) ] = {
556 [ C(RESULT_ACCESS) ] = 0x0,
557 [ C(RESULT_MISS) ] = 0x0,
558 },
559 },
560 [ C(NODE) ] = {
561 [ C(OP_READ) ] = {
562 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
563 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
564 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
565 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
566 },
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
569 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
570 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
571 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
572 },
573 [ C(OP_PREFETCH) ] = {
574 [ C(RESULT_ACCESS) ] = 0x0,
575 [ C(RESULT_MISS) ] = 0x0,
576 },
577 },
578 };
579
580 #define SNB_DMND_DATA_RD (1ULL << 0)
581 #define SNB_DMND_RFO (1ULL << 1)
582 #define SNB_DMND_IFETCH (1ULL << 2)
583 #define SNB_DMND_WB (1ULL << 3)
584 #define SNB_PF_DATA_RD (1ULL << 4)
585 #define SNB_PF_RFO (1ULL << 5)
586 #define SNB_PF_IFETCH (1ULL << 6)
587 #define SNB_LLC_DATA_RD (1ULL << 7)
588 #define SNB_LLC_RFO (1ULL << 8)
589 #define SNB_LLC_IFETCH (1ULL << 9)
590 #define SNB_BUS_LOCKS (1ULL << 10)
591 #define SNB_STRM_ST (1ULL << 11)
592 #define SNB_OTHER (1ULL << 15)
593 #define SNB_RESP_ANY (1ULL << 16)
594 #define SNB_NO_SUPP (1ULL << 17)
595 #define SNB_LLC_HITM (1ULL << 18)
596 #define SNB_LLC_HITE (1ULL << 19)
597 #define SNB_LLC_HITS (1ULL << 20)
598 #define SNB_LLC_HITF (1ULL << 21)
599 #define SNB_LOCAL (1ULL << 22)
600 #define SNB_REMOTE (0xffULL << 23)
601 #define SNB_SNP_NONE (1ULL << 31)
602 #define SNB_SNP_NOT_NEEDED (1ULL << 32)
603 #define SNB_SNP_MISS (1ULL << 33)
604 #define SNB_NO_FWD (1ULL << 34)
605 #define SNB_SNP_FWD (1ULL << 35)
606 #define SNB_HITM (1ULL << 36)
607 #define SNB_NON_DRAM (1ULL << 37)
608
609 #define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
610 #define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
611 #define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
612
613 #define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
614 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
615 SNB_HITM)
616
617 #define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
618 #define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
619
620 #define SNB_L3_ACCESS SNB_RESP_ANY
621 #define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
622
623 static __initconst const u64 snb_hw_cache_extra_regs
624 [PERF_COUNT_HW_CACHE_MAX]
625 [PERF_COUNT_HW_CACHE_OP_MAX]
626 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
627 {
628 [ C(LL ) ] = {
629 [ C(OP_READ) ] = {
630 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
631 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
632 },
633 [ C(OP_WRITE) ] = {
634 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
635 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
636 },
637 [ C(OP_PREFETCH) ] = {
638 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
639 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
640 },
641 },
642 [ C(NODE) ] = {
643 [ C(OP_READ) ] = {
644 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
645 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
646 },
647 [ C(OP_WRITE) ] = {
648 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
649 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
650 },
651 [ C(OP_PREFETCH) ] = {
652 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
653 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
654 },
655 },
656 };
657
658 static __initconst const u64 snb_hw_cache_event_ids
659 [PERF_COUNT_HW_CACHE_MAX]
660 [PERF_COUNT_HW_CACHE_OP_MAX]
661 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
662 {
663 [ C(L1D) ] = {
664 [ C(OP_READ) ] = {
665 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
666 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
667 },
668 [ C(OP_WRITE) ] = {
669 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
670 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
671 },
672 [ C(OP_PREFETCH) ] = {
673 [ C(RESULT_ACCESS) ] = 0x0,
674 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
675 },
676 },
677 [ C(L1I ) ] = {
678 [ C(OP_READ) ] = {
679 [ C(RESULT_ACCESS) ] = 0x0,
680 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
681 },
682 [ C(OP_WRITE) ] = {
683 [ C(RESULT_ACCESS) ] = -1,
684 [ C(RESULT_MISS) ] = -1,
685 },
686 [ C(OP_PREFETCH) ] = {
687 [ C(RESULT_ACCESS) ] = 0x0,
688 [ C(RESULT_MISS) ] = 0x0,
689 },
690 },
691 [ C(LL ) ] = {
692 [ C(OP_READ) ] = {
693 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
694 [ C(RESULT_ACCESS) ] = 0x01b7,
695 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
696 [ C(RESULT_MISS) ] = 0x01b7,
697 },
698 [ C(OP_WRITE) ] = {
699 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
700 [ C(RESULT_ACCESS) ] = 0x01b7,
701 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
702 [ C(RESULT_MISS) ] = 0x01b7,
703 },
704 [ C(OP_PREFETCH) ] = {
705 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
706 [ C(RESULT_ACCESS) ] = 0x01b7,
707 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
708 [ C(RESULT_MISS) ] = 0x01b7,
709 },
710 },
711 [ C(DTLB) ] = {
712 [ C(OP_READ) ] = {
713 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
714 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
715 },
716 [ C(OP_WRITE) ] = {
717 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
718 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
719 },
720 [ C(OP_PREFETCH) ] = {
721 [ C(RESULT_ACCESS) ] = 0x0,
722 [ C(RESULT_MISS) ] = 0x0,
723 },
724 },
725 [ C(ITLB) ] = {
726 [ C(OP_READ) ] = {
727 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
728 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
729 },
730 [ C(OP_WRITE) ] = {
731 [ C(RESULT_ACCESS) ] = -1,
732 [ C(RESULT_MISS) ] = -1,
733 },
734 [ C(OP_PREFETCH) ] = {
735 [ C(RESULT_ACCESS) ] = -1,
736 [ C(RESULT_MISS) ] = -1,
737 },
738 },
739 [ C(BPU ) ] = {
740 [ C(OP_READ) ] = {
741 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
742 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
743 },
744 [ C(OP_WRITE) ] = {
745 [ C(RESULT_ACCESS) ] = -1,
746 [ C(RESULT_MISS) ] = -1,
747 },
748 [ C(OP_PREFETCH) ] = {
749 [ C(RESULT_ACCESS) ] = -1,
750 [ C(RESULT_MISS) ] = -1,
751 },
752 },
753 [ C(NODE) ] = {
754 [ C(OP_READ) ] = {
755 [ C(RESULT_ACCESS) ] = 0x01b7,
756 [ C(RESULT_MISS) ] = 0x01b7,
757 },
758 [ C(OP_WRITE) ] = {
759 [ C(RESULT_ACCESS) ] = 0x01b7,
760 [ C(RESULT_MISS) ] = 0x01b7,
761 },
762 [ C(OP_PREFETCH) ] = {
763 [ C(RESULT_ACCESS) ] = 0x01b7,
764 [ C(RESULT_MISS) ] = 0x01b7,
765 },
766 },
767
768 };
769
770 /*
771 * Notes on the events:
772 * - data reads do not include code reads (comparable to earlier tables)
773 * - data counts include speculative execution (except L1 write, dtlb, bpu)
774 * - remote node access includes remote memory, remote cache, remote mmio.
775 * - prefetches are not included in the counts because they are not
776 * reliably counted.
777 */
778
779 #define HSW_DEMAND_DATA_RD BIT_ULL(0)
780 #define HSW_DEMAND_RFO BIT_ULL(1)
781 #define HSW_ANY_RESPONSE BIT_ULL(16)
782 #define HSW_SUPPLIER_NONE BIT_ULL(17)
783 #define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
784 #define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
785 #define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
786 #define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
787 #define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
788 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
789 HSW_L3_MISS_REMOTE_HOP2P)
790 #define HSW_SNOOP_NONE BIT_ULL(31)
791 #define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
792 #define HSW_SNOOP_MISS BIT_ULL(33)
793 #define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
794 #define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
795 #define HSW_SNOOP_HITM BIT_ULL(36)
796 #define HSW_SNOOP_NON_DRAM BIT_ULL(37)
797 #define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
798 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
799 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
800 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
801 #define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
802 #define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
803 #define HSW_DEMAND_WRITE HSW_DEMAND_RFO
804 #define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
805 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
806 #define HSW_LLC_ACCESS HSW_ANY_RESPONSE
807
808 #define BDW_L3_MISS_LOCAL BIT(26)
809 #define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
810 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
811 HSW_L3_MISS_REMOTE_HOP2P)
812
813
814 static __initconst const u64 hsw_hw_cache_event_ids
815 [PERF_COUNT_HW_CACHE_MAX]
816 [PERF_COUNT_HW_CACHE_OP_MAX]
817 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
818 {
819 [ C(L1D ) ] = {
820 [ C(OP_READ) ] = {
821 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
822 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
823 },
824 [ C(OP_WRITE) ] = {
825 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 [ C(OP_PREFETCH) ] = {
829 [ C(RESULT_ACCESS) ] = 0x0,
830 [ C(RESULT_MISS) ] = 0x0,
831 },
832 },
833 [ C(L1I ) ] = {
834 [ C(OP_READ) ] = {
835 [ C(RESULT_ACCESS) ] = 0x0,
836 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
837 },
838 [ C(OP_WRITE) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 [ C(OP_PREFETCH) ] = {
843 [ C(RESULT_ACCESS) ] = 0x0,
844 [ C(RESULT_MISS) ] = 0x0,
845 },
846 },
847 [ C(LL ) ] = {
848 [ C(OP_READ) ] = {
849 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
850 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
851 },
852 [ C(OP_WRITE) ] = {
853 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
854 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
855 },
856 [ C(OP_PREFETCH) ] = {
857 [ C(RESULT_ACCESS) ] = 0x0,
858 [ C(RESULT_MISS) ] = 0x0,
859 },
860 },
861 [ C(DTLB) ] = {
862 [ C(OP_READ) ] = {
863 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
864 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
865 },
866 [ C(OP_WRITE) ] = {
867 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
868 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
869 },
870 [ C(OP_PREFETCH) ] = {
871 [ C(RESULT_ACCESS) ] = 0x0,
872 [ C(RESULT_MISS) ] = 0x0,
873 },
874 },
875 [ C(ITLB) ] = {
876 [ C(OP_READ) ] = {
877 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
878 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
879 },
880 [ C(OP_WRITE) ] = {
881 [ C(RESULT_ACCESS) ] = -1,
882 [ C(RESULT_MISS) ] = -1,
883 },
884 [ C(OP_PREFETCH) ] = {
885 [ C(RESULT_ACCESS) ] = -1,
886 [ C(RESULT_MISS) ] = -1,
887 },
888 },
889 [ C(BPU ) ] = {
890 [ C(OP_READ) ] = {
891 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
892 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
893 },
894 [ C(OP_WRITE) ] = {
895 [ C(RESULT_ACCESS) ] = -1,
896 [ C(RESULT_MISS) ] = -1,
897 },
898 [ C(OP_PREFETCH) ] = {
899 [ C(RESULT_ACCESS) ] = -1,
900 [ C(RESULT_MISS) ] = -1,
901 },
902 },
903 [ C(NODE) ] = {
904 [ C(OP_READ) ] = {
905 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
906 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
907 },
908 [ C(OP_WRITE) ] = {
909 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
910 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
911 },
912 [ C(OP_PREFETCH) ] = {
913 [ C(RESULT_ACCESS) ] = 0x0,
914 [ C(RESULT_MISS) ] = 0x0,
915 },
916 },
917 };
918
919 static __initconst const u64 hsw_hw_cache_extra_regs
920 [PERF_COUNT_HW_CACHE_MAX]
921 [PERF_COUNT_HW_CACHE_OP_MAX]
922 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
923 {
924 [ C(LL ) ] = {
925 [ C(OP_READ) ] = {
926 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
927 HSW_LLC_ACCESS,
928 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
929 HSW_L3_MISS|HSW_ANY_SNOOP,
930 },
931 [ C(OP_WRITE) ] = {
932 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
933 HSW_LLC_ACCESS,
934 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
935 HSW_L3_MISS|HSW_ANY_SNOOP,
936 },
937 [ C(OP_PREFETCH) ] = {
938 [ C(RESULT_ACCESS) ] = 0x0,
939 [ C(RESULT_MISS) ] = 0x0,
940 },
941 },
942 [ C(NODE) ] = {
943 [ C(OP_READ) ] = {
944 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
945 HSW_L3_MISS_LOCAL_DRAM|
946 HSW_SNOOP_DRAM,
947 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
948 HSW_L3_MISS_REMOTE|
949 HSW_SNOOP_DRAM,
950 },
951 [ C(OP_WRITE) ] = {
952 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
953 HSW_L3_MISS_LOCAL_DRAM|
954 HSW_SNOOP_DRAM,
955 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
956 HSW_L3_MISS_REMOTE|
957 HSW_SNOOP_DRAM,
958 },
959 [ C(OP_PREFETCH) ] = {
960 [ C(RESULT_ACCESS) ] = 0x0,
961 [ C(RESULT_MISS) ] = 0x0,
962 },
963 },
964 };
965
966 static __initconst const u64 westmere_hw_cache_event_ids
967 [PERF_COUNT_HW_CACHE_MAX]
968 [PERF_COUNT_HW_CACHE_OP_MAX]
969 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
970 {
971 [ C(L1D) ] = {
972 [ C(OP_READ) ] = {
973 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
974 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
975 },
976 [ C(OP_WRITE) ] = {
977 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
978 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
979 },
980 [ C(OP_PREFETCH) ] = {
981 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
982 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
983 },
984 },
985 [ C(L1I ) ] = {
986 [ C(OP_READ) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
988 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
989 },
990 [ C(OP_WRITE) ] = {
991 [ C(RESULT_ACCESS) ] = -1,
992 [ C(RESULT_MISS) ] = -1,
993 },
994 [ C(OP_PREFETCH) ] = {
995 [ C(RESULT_ACCESS) ] = 0x0,
996 [ C(RESULT_MISS) ] = 0x0,
997 },
998 },
999 [ C(LL ) ] = {
1000 [ C(OP_READ) ] = {
1001 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1002 [ C(RESULT_ACCESS) ] = 0x01b7,
1003 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1004 [ C(RESULT_MISS) ] = 0x01b7,
1005 },
1006 /*
1007 * Use RFO, not WRITEBACK, because a write miss would typically occur
1008 * on RFO.
1009 */
1010 [ C(OP_WRITE) ] = {
1011 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1012 [ C(RESULT_ACCESS) ] = 0x01b7,
1013 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1014 [ C(RESULT_MISS) ] = 0x01b7,
1015 },
1016 [ C(OP_PREFETCH) ] = {
1017 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1018 [ C(RESULT_ACCESS) ] = 0x01b7,
1019 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1020 [ C(RESULT_MISS) ] = 0x01b7,
1021 },
1022 },
1023 [ C(DTLB) ] = {
1024 [ C(OP_READ) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1026 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1027 },
1028 [ C(OP_WRITE) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1030 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1031 },
1032 [ C(OP_PREFETCH) ] = {
1033 [ C(RESULT_ACCESS) ] = 0x0,
1034 [ C(RESULT_MISS) ] = 0x0,
1035 },
1036 },
1037 [ C(ITLB) ] = {
1038 [ C(OP_READ) ] = {
1039 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1040 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
1041 },
1042 [ C(OP_WRITE) ] = {
1043 [ C(RESULT_ACCESS) ] = -1,
1044 [ C(RESULT_MISS) ] = -1,
1045 },
1046 [ C(OP_PREFETCH) ] = {
1047 [ C(RESULT_ACCESS) ] = -1,
1048 [ C(RESULT_MISS) ] = -1,
1049 },
1050 },
1051 [ C(BPU ) ] = {
1052 [ C(OP_READ) ] = {
1053 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1054 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1055 },
1056 [ C(OP_WRITE) ] = {
1057 [ C(RESULT_ACCESS) ] = -1,
1058 [ C(RESULT_MISS) ] = -1,
1059 },
1060 [ C(OP_PREFETCH) ] = {
1061 [ C(RESULT_ACCESS) ] = -1,
1062 [ C(RESULT_MISS) ] = -1,
1063 },
1064 },
1065 [ C(NODE) ] = {
1066 [ C(OP_READ) ] = {
1067 [ C(RESULT_ACCESS) ] = 0x01b7,
1068 [ C(RESULT_MISS) ] = 0x01b7,
1069 },
1070 [ C(OP_WRITE) ] = {
1071 [ C(RESULT_ACCESS) ] = 0x01b7,
1072 [ C(RESULT_MISS) ] = 0x01b7,
1073 },
1074 [ C(OP_PREFETCH) ] = {
1075 [ C(RESULT_ACCESS) ] = 0x01b7,
1076 [ C(RESULT_MISS) ] = 0x01b7,
1077 },
1078 },
1079 };
1080
1081 /*
1082 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1083 * See IA32 SDM Vol 3B 30.6.1.3
1084 */
1085
1086 #define NHM_DMND_DATA_RD (1 << 0)
1087 #define NHM_DMND_RFO (1 << 1)
1088 #define NHM_DMND_IFETCH (1 << 2)
1089 #define NHM_DMND_WB (1 << 3)
1090 #define NHM_PF_DATA_RD (1 << 4)
1091 #define NHM_PF_DATA_RFO (1 << 5)
1092 #define NHM_PF_IFETCH (1 << 6)
1093 #define NHM_OFFCORE_OTHER (1 << 7)
1094 #define NHM_UNCORE_HIT (1 << 8)
1095 #define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1096 #define NHM_OTHER_CORE_HITM (1 << 10)
1097 /* reserved */
1098 #define NHM_REMOTE_CACHE_FWD (1 << 12)
1099 #define NHM_REMOTE_DRAM (1 << 13)
1100 #define NHM_LOCAL_DRAM (1 << 14)
1101 #define NHM_NON_DRAM (1 << 15)
1102
1103 #define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1104 #define NHM_REMOTE (NHM_REMOTE_DRAM)
1105
1106 #define NHM_DMND_READ (NHM_DMND_DATA_RD)
1107 #define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1108 #define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1109
1110 #define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
1111 #define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
1112 #define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
1113
1114 static __initconst const u64 nehalem_hw_cache_extra_regs
1115 [PERF_COUNT_HW_CACHE_MAX]
1116 [PERF_COUNT_HW_CACHE_OP_MAX]
1117 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1118 {
1119 [ C(LL ) ] = {
1120 [ C(OP_READ) ] = {
1121 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1122 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
1123 },
1124 [ C(OP_WRITE) ] = {
1125 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1126 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
1127 },
1128 [ C(OP_PREFETCH) ] = {
1129 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1130 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
1131 },
1132 },
1133 [ C(NODE) ] = {
1134 [ C(OP_READ) ] = {
1135 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1136 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
1137 },
1138 [ C(OP_WRITE) ] = {
1139 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1140 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
1141 },
1142 [ C(OP_PREFETCH) ] = {
1143 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1144 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
1145 },
1146 },
1147 };
1148
1149 static __initconst const u64 nehalem_hw_cache_event_ids
1150 [PERF_COUNT_HW_CACHE_MAX]
1151 [PERF_COUNT_HW_CACHE_OP_MAX]
1152 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1153 {
1154 [ C(L1D) ] = {
1155 [ C(OP_READ) ] = {
1156 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1157 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
1158 },
1159 [ C(OP_WRITE) ] = {
1160 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1161 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
1162 },
1163 [ C(OP_PREFETCH) ] = {
1164 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1165 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1166 },
1167 },
1168 [ C(L1I ) ] = {
1169 [ C(OP_READ) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1171 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1172 },
1173 [ C(OP_WRITE) ] = {
1174 [ C(RESULT_ACCESS) ] = -1,
1175 [ C(RESULT_MISS) ] = -1,
1176 },
1177 [ C(OP_PREFETCH) ] = {
1178 [ C(RESULT_ACCESS) ] = 0x0,
1179 [ C(RESULT_MISS) ] = 0x0,
1180 },
1181 },
1182 [ C(LL ) ] = {
1183 [ C(OP_READ) ] = {
1184 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1185 [ C(RESULT_ACCESS) ] = 0x01b7,
1186 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1187 [ C(RESULT_MISS) ] = 0x01b7,
1188 },
1189 /*
1190 * Use RFO, not WRITEBACK, because a write miss would typically occur
1191 * on RFO.
1192 */
1193 [ C(OP_WRITE) ] = {
1194 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1195 [ C(RESULT_ACCESS) ] = 0x01b7,
1196 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1197 [ C(RESULT_MISS) ] = 0x01b7,
1198 },
1199 [ C(OP_PREFETCH) ] = {
1200 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1201 [ C(RESULT_ACCESS) ] = 0x01b7,
1202 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1203 [ C(RESULT_MISS) ] = 0x01b7,
1204 },
1205 },
1206 [ C(DTLB) ] = {
1207 [ C(OP_READ) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1209 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1210 },
1211 [ C(OP_WRITE) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1213 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1214 },
1215 [ C(OP_PREFETCH) ] = {
1216 [ C(RESULT_ACCESS) ] = 0x0,
1217 [ C(RESULT_MISS) ] = 0x0,
1218 },
1219 },
1220 [ C(ITLB) ] = {
1221 [ C(OP_READ) ] = {
1222 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1223 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1224 },
1225 [ C(OP_WRITE) ] = {
1226 [ C(RESULT_ACCESS) ] = -1,
1227 [ C(RESULT_MISS) ] = -1,
1228 },
1229 [ C(OP_PREFETCH) ] = {
1230 [ C(RESULT_ACCESS) ] = -1,
1231 [ C(RESULT_MISS) ] = -1,
1232 },
1233 },
1234 [ C(BPU ) ] = {
1235 [ C(OP_READ) ] = {
1236 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1237 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1238 },
1239 [ C(OP_WRITE) ] = {
1240 [ C(RESULT_ACCESS) ] = -1,
1241 [ C(RESULT_MISS) ] = -1,
1242 },
1243 [ C(OP_PREFETCH) ] = {
1244 [ C(RESULT_ACCESS) ] = -1,
1245 [ C(RESULT_MISS) ] = -1,
1246 },
1247 },
1248 [ C(NODE) ] = {
1249 [ C(OP_READ) ] = {
1250 [ C(RESULT_ACCESS) ] = 0x01b7,
1251 [ C(RESULT_MISS) ] = 0x01b7,
1252 },
1253 [ C(OP_WRITE) ] = {
1254 [ C(RESULT_ACCESS) ] = 0x01b7,
1255 [ C(RESULT_MISS) ] = 0x01b7,
1256 },
1257 [ C(OP_PREFETCH) ] = {
1258 [ C(RESULT_ACCESS) ] = 0x01b7,
1259 [ C(RESULT_MISS) ] = 0x01b7,
1260 },
1261 },
1262 };
1263
1264 static __initconst const u64 core2_hw_cache_event_ids
1265 [PERF_COUNT_HW_CACHE_MAX]
1266 [PERF_COUNT_HW_CACHE_OP_MAX]
1267 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1268 {
1269 [ C(L1D) ] = {
1270 [ C(OP_READ) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1272 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1273 },
1274 [ C(OP_WRITE) ] = {
1275 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1276 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1277 },
1278 [ C(OP_PREFETCH) ] = {
1279 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1280 [ C(RESULT_MISS) ] = 0,
1281 },
1282 },
1283 [ C(L1I ) ] = {
1284 [ C(OP_READ) ] = {
1285 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1286 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1287 },
1288 [ C(OP_WRITE) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 [ C(OP_PREFETCH) ] = {
1293 [ C(RESULT_ACCESS) ] = 0,
1294 [ C(RESULT_MISS) ] = 0,
1295 },
1296 },
1297 [ C(LL ) ] = {
1298 [ C(OP_READ) ] = {
1299 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1300 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1301 },
1302 [ C(OP_WRITE) ] = {
1303 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1304 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1305 },
1306 [ C(OP_PREFETCH) ] = {
1307 [ C(RESULT_ACCESS) ] = 0,
1308 [ C(RESULT_MISS) ] = 0,
1309 },
1310 },
1311 [ C(DTLB) ] = {
1312 [ C(OP_READ) ] = {
1313 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1314 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1315 },
1316 [ C(OP_WRITE) ] = {
1317 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1318 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1319 },
1320 [ C(OP_PREFETCH) ] = {
1321 [ C(RESULT_ACCESS) ] = 0,
1322 [ C(RESULT_MISS) ] = 0,
1323 },
1324 },
1325 [ C(ITLB) ] = {
1326 [ C(OP_READ) ] = {
1327 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1328 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1329 },
1330 [ C(OP_WRITE) ] = {
1331 [ C(RESULT_ACCESS) ] = -1,
1332 [ C(RESULT_MISS) ] = -1,
1333 },
1334 [ C(OP_PREFETCH) ] = {
1335 [ C(RESULT_ACCESS) ] = -1,
1336 [ C(RESULT_MISS) ] = -1,
1337 },
1338 },
1339 [ C(BPU ) ] = {
1340 [ C(OP_READ) ] = {
1341 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1342 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1343 },
1344 [ C(OP_WRITE) ] = {
1345 [ C(RESULT_ACCESS) ] = -1,
1346 [ C(RESULT_MISS) ] = -1,
1347 },
1348 [ C(OP_PREFETCH) ] = {
1349 [ C(RESULT_ACCESS) ] = -1,
1350 [ C(RESULT_MISS) ] = -1,
1351 },
1352 },
1353 };
1354
1355 static __initconst const u64 atom_hw_cache_event_ids
1356 [PERF_COUNT_HW_CACHE_MAX]
1357 [PERF_COUNT_HW_CACHE_OP_MAX]
1358 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1359 {
1360 [ C(L1D) ] = {
1361 [ C(OP_READ) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1363 [ C(RESULT_MISS) ] = 0,
1364 },
1365 [ C(OP_WRITE) ] = {
1366 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 [ C(OP_PREFETCH) ] = {
1370 [ C(RESULT_ACCESS) ] = 0x0,
1371 [ C(RESULT_MISS) ] = 0,
1372 },
1373 },
1374 [ C(L1I ) ] = {
1375 [ C(OP_READ) ] = {
1376 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1377 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1378 },
1379 [ C(OP_WRITE) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 [ C(OP_PREFETCH) ] = {
1384 [ C(RESULT_ACCESS) ] = 0,
1385 [ C(RESULT_MISS) ] = 0,
1386 },
1387 },
1388 [ C(LL ) ] = {
1389 [ C(OP_READ) ] = {
1390 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1391 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1392 },
1393 [ C(OP_WRITE) ] = {
1394 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1395 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1396 },
1397 [ C(OP_PREFETCH) ] = {
1398 [ C(RESULT_ACCESS) ] = 0,
1399 [ C(RESULT_MISS) ] = 0,
1400 },
1401 },
1402 [ C(DTLB) ] = {
1403 [ C(OP_READ) ] = {
1404 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1405 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1406 },
1407 [ C(OP_WRITE) ] = {
1408 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1409 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1410 },
1411 [ C(OP_PREFETCH) ] = {
1412 [ C(RESULT_ACCESS) ] = 0,
1413 [ C(RESULT_MISS) ] = 0,
1414 },
1415 },
1416 [ C(ITLB) ] = {
1417 [ C(OP_READ) ] = {
1418 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1419 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1420 },
1421 [ C(OP_WRITE) ] = {
1422 [ C(RESULT_ACCESS) ] = -1,
1423 [ C(RESULT_MISS) ] = -1,
1424 },
1425 [ C(OP_PREFETCH) ] = {
1426 [ C(RESULT_ACCESS) ] = -1,
1427 [ C(RESULT_MISS) ] = -1,
1428 },
1429 },
1430 [ C(BPU ) ] = {
1431 [ C(OP_READ) ] = {
1432 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1433 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1434 },
1435 [ C(OP_WRITE) ] = {
1436 [ C(RESULT_ACCESS) ] = -1,
1437 [ C(RESULT_MISS) ] = -1,
1438 },
1439 [ C(OP_PREFETCH) ] = {
1440 [ C(RESULT_ACCESS) ] = -1,
1441 [ C(RESULT_MISS) ] = -1,
1442 },
1443 },
1444 };
1445
1446 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1447 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1448 /* no_alloc_cycles.not_delivered */
1449 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1450 "event=0xca,umask=0x50");
1451 EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1452 /* uops_retired.all */
1453 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1454 "event=0xc2,umask=0x10");
1455 /* uops_retired.all */
1456 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1457 "event=0xc2,umask=0x10");
1458
1459 static struct attribute *slm_events_attrs[] = {
1460 EVENT_PTR(td_total_slots_slm),
1461 EVENT_PTR(td_total_slots_scale_slm),
1462 EVENT_PTR(td_fetch_bubbles_slm),
1463 EVENT_PTR(td_fetch_bubbles_scale_slm),
1464 EVENT_PTR(td_slots_issued_slm),
1465 EVENT_PTR(td_slots_retired_slm),
1466 NULL
1467 };
1468
1469 static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1470 {
1471 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1472 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
1473 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1474 EVENT_EXTRA_END
1475 };
1476
1477 #define SLM_DMND_READ SNB_DMND_DATA_RD
1478 #define SLM_DMND_WRITE SNB_DMND_RFO
1479 #define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1480
1481 #define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1482 #define SLM_LLC_ACCESS SNB_RESP_ANY
1483 #define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1484
1485 static __initconst const u64 slm_hw_cache_extra_regs
1486 [PERF_COUNT_HW_CACHE_MAX]
1487 [PERF_COUNT_HW_CACHE_OP_MAX]
1488 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1489 {
1490 [ C(LL ) ] = {
1491 [ C(OP_READ) ] = {
1492 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
1493 [ C(RESULT_MISS) ] = 0,
1494 },
1495 [ C(OP_WRITE) ] = {
1496 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1497 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1498 },
1499 [ C(OP_PREFETCH) ] = {
1500 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1501 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1502 },
1503 },
1504 };
1505
1506 static __initconst const u64 slm_hw_cache_event_ids
1507 [PERF_COUNT_HW_CACHE_MAX]
1508 [PERF_COUNT_HW_CACHE_OP_MAX]
1509 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1510 {
1511 [ C(L1D) ] = {
1512 [ C(OP_READ) ] = {
1513 [ C(RESULT_ACCESS) ] = 0,
1514 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1515 },
1516 [ C(OP_WRITE) ] = {
1517 [ C(RESULT_ACCESS) ] = 0,
1518 [ C(RESULT_MISS) ] = 0,
1519 },
1520 [ C(OP_PREFETCH) ] = {
1521 [ C(RESULT_ACCESS) ] = 0,
1522 [ C(RESULT_MISS) ] = 0,
1523 },
1524 },
1525 [ C(L1I ) ] = {
1526 [ C(OP_READ) ] = {
1527 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1528 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1529 },
1530 [ C(OP_WRITE) ] = {
1531 [ C(RESULT_ACCESS) ] = -1,
1532 [ C(RESULT_MISS) ] = -1,
1533 },
1534 [ C(OP_PREFETCH) ] = {
1535 [ C(RESULT_ACCESS) ] = 0,
1536 [ C(RESULT_MISS) ] = 0,
1537 },
1538 },
1539 [ C(LL ) ] = {
1540 [ C(OP_READ) ] = {
1541 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1542 [ C(RESULT_ACCESS) ] = 0x01b7,
1543 [ C(RESULT_MISS) ] = 0,
1544 },
1545 [ C(OP_WRITE) ] = {
1546 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1547 [ C(RESULT_ACCESS) ] = 0x01b7,
1548 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1549 [ C(RESULT_MISS) ] = 0x01b7,
1550 },
1551 [ C(OP_PREFETCH) ] = {
1552 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1553 [ C(RESULT_ACCESS) ] = 0x01b7,
1554 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1555 [ C(RESULT_MISS) ] = 0x01b7,
1556 },
1557 },
1558 [ C(DTLB) ] = {
1559 [ C(OP_READ) ] = {
1560 [ C(RESULT_ACCESS) ] = 0,
1561 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1562 },
1563 [ C(OP_WRITE) ] = {
1564 [ C(RESULT_ACCESS) ] = 0,
1565 [ C(RESULT_MISS) ] = 0,
1566 },
1567 [ C(OP_PREFETCH) ] = {
1568 [ C(RESULT_ACCESS) ] = 0,
1569 [ C(RESULT_MISS) ] = 0,
1570 },
1571 },
1572 [ C(ITLB) ] = {
1573 [ C(OP_READ) ] = {
1574 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1575 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1576 },
1577 [ C(OP_WRITE) ] = {
1578 [ C(RESULT_ACCESS) ] = -1,
1579 [ C(RESULT_MISS) ] = -1,
1580 },
1581 [ C(OP_PREFETCH) ] = {
1582 [ C(RESULT_ACCESS) ] = -1,
1583 [ C(RESULT_MISS) ] = -1,
1584 },
1585 },
1586 [ C(BPU ) ] = {
1587 [ C(OP_READ) ] = {
1588 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1589 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1590 },
1591 [ C(OP_WRITE) ] = {
1592 [ C(RESULT_ACCESS) ] = -1,
1593 [ C(RESULT_MISS) ] = -1,
1594 },
1595 [ C(OP_PREFETCH) ] = {
1596 [ C(RESULT_ACCESS) ] = -1,
1597 [ C(RESULT_MISS) ] = -1,
1598 },
1599 },
1600 };
1601
1602 EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
1603 EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
1604 /* UOPS_NOT_DELIVERED.ANY */
1605 EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm, "event=0x9c");
1606 /* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
1607 EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm, "event=0xca,umask=0x02");
1608 /* UOPS_RETIRED.ANY */
1609 EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm, "event=0xc2");
1610 /* UOPS_ISSUED.ANY */
1611 EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm, "event=0x0e");
1612
1613 static struct attribute *glm_events_attrs[] = {
1614 EVENT_PTR(td_total_slots_glm),
1615 EVENT_PTR(td_total_slots_scale_glm),
1616 EVENT_PTR(td_fetch_bubbles_glm),
1617 EVENT_PTR(td_recovery_bubbles_glm),
1618 EVENT_PTR(td_slots_issued_glm),
1619 EVENT_PTR(td_slots_retired_glm),
1620 NULL
1621 };
1622
1623 static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1624 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1625 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1626 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1627 EVENT_EXTRA_END
1628 };
1629
1630 #define GLM_DEMAND_DATA_RD BIT_ULL(0)
1631 #define GLM_DEMAND_RFO BIT_ULL(1)
1632 #define GLM_ANY_RESPONSE BIT_ULL(16)
1633 #define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1634 #define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1635 #define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1636 #define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1637 #define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1638 #define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1639 #define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1640
1641 static __initconst const u64 glm_hw_cache_event_ids
1642 [PERF_COUNT_HW_CACHE_MAX]
1643 [PERF_COUNT_HW_CACHE_OP_MAX]
1644 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1645 [C(L1D)] = {
1646 [C(OP_READ)] = {
1647 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1648 [C(RESULT_MISS)] = 0x0,
1649 },
1650 [C(OP_WRITE)] = {
1651 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1652 [C(RESULT_MISS)] = 0x0,
1653 },
1654 [C(OP_PREFETCH)] = {
1655 [C(RESULT_ACCESS)] = 0x0,
1656 [C(RESULT_MISS)] = 0x0,
1657 },
1658 },
1659 [C(L1I)] = {
1660 [C(OP_READ)] = {
1661 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1662 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1663 },
1664 [C(OP_WRITE)] = {
1665 [C(RESULT_ACCESS)] = -1,
1666 [C(RESULT_MISS)] = -1,
1667 },
1668 [C(OP_PREFETCH)] = {
1669 [C(RESULT_ACCESS)] = 0x0,
1670 [C(RESULT_MISS)] = 0x0,
1671 },
1672 },
1673 [C(LL)] = {
1674 [C(OP_READ)] = {
1675 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1676 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1677 },
1678 [C(OP_WRITE)] = {
1679 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1680 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1681 },
1682 [C(OP_PREFETCH)] = {
1683 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1684 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1685 },
1686 },
1687 [C(DTLB)] = {
1688 [C(OP_READ)] = {
1689 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1690 [C(RESULT_MISS)] = 0x0,
1691 },
1692 [C(OP_WRITE)] = {
1693 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1694 [C(RESULT_MISS)] = 0x0,
1695 },
1696 [C(OP_PREFETCH)] = {
1697 [C(RESULT_ACCESS)] = 0x0,
1698 [C(RESULT_MISS)] = 0x0,
1699 },
1700 },
1701 [C(ITLB)] = {
1702 [C(OP_READ)] = {
1703 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1704 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1705 },
1706 [C(OP_WRITE)] = {
1707 [C(RESULT_ACCESS)] = -1,
1708 [C(RESULT_MISS)] = -1,
1709 },
1710 [C(OP_PREFETCH)] = {
1711 [C(RESULT_ACCESS)] = -1,
1712 [C(RESULT_MISS)] = -1,
1713 },
1714 },
1715 [C(BPU)] = {
1716 [C(OP_READ)] = {
1717 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1718 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1719 },
1720 [C(OP_WRITE)] = {
1721 [C(RESULT_ACCESS)] = -1,
1722 [C(RESULT_MISS)] = -1,
1723 },
1724 [C(OP_PREFETCH)] = {
1725 [C(RESULT_ACCESS)] = -1,
1726 [C(RESULT_MISS)] = -1,
1727 },
1728 },
1729 };
1730
1731 static __initconst const u64 glm_hw_cache_extra_regs
1732 [PERF_COUNT_HW_CACHE_MAX]
1733 [PERF_COUNT_HW_CACHE_OP_MAX]
1734 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1735 [C(LL)] = {
1736 [C(OP_READ)] = {
1737 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1738 GLM_LLC_ACCESS,
1739 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1740 GLM_LLC_MISS,
1741 },
1742 [C(OP_WRITE)] = {
1743 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1744 GLM_LLC_ACCESS,
1745 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1746 GLM_LLC_MISS,
1747 },
1748 [C(OP_PREFETCH)] = {
1749 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1750 GLM_LLC_ACCESS,
1751 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1752 GLM_LLC_MISS,
1753 },
1754 },
1755 };
1756
1757 static __initconst const u64 glp_hw_cache_event_ids
1758 [PERF_COUNT_HW_CACHE_MAX]
1759 [PERF_COUNT_HW_CACHE_OP_MAX]
1760 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1761 [C(L1D)] = {
1762 [C(OP_READ)] = {
1763 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1764 [C(RESULT_MISS)] = 0x0,
1765 },
1766 [C(OP_WRITE)] = {
1767 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1768 [C(RESULT_MISS)] = 0x0,
1769 },
1770 [C(OP_PREFETCH)] = {
1771 [C(RESULT_ACCESS)] = 0x0,
1772 [C(RESULT_MISS)] = 0x0,
1773 },
1774 },
1775 [C(L1I)] = {
1776 [C(OP_READ)] = {
1777 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1778 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1779 },
1780 [C(OP_WRITE)] = {
1781 [C(RESULT_ACCESS)] = -1,
1782 [C(RESULT_MISS)] = -1,
1783 },
1784 [C(OP_PREFETCH)] = {
1785 [C(RESULT_ACCESS)] = 0x0,
1786 [C(RESULT_MISS)] = 0x0,
1787 },
1788 },
1789 [C(LL)] = {
1790 [C(OP_READ)] = {
1791 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1792 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1793 },
1794 [C(OP_WRITE)] = {
1795 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1796 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1797 },
1798 [C(OP_PREFETCH)] = {
1799 [C(RESULT_ACCESS)] = 0x0,
1800 [C(RESULT_MISS)] = 0x0,
1801 },
1802 },
1803 [C(DTLB)] = {
1804 [C(OP_READ)] = {
1805 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1806 [C(RESULT_MISS)] = 0xe08, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
1807 },
1808 [C(OP_WRITE)] = {
1809 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1810 [C(RESULT_MISS)] = 0xe49, /* DTLB_STORE_MISSES.WALK_COMPLETED */
1811 },
1812 [C(OP_PREFETCH)] = {
1813 [C(RESULT_ACCESS)] = 0x0,
1814 [C(RESULT_MISS)] = 0x0,
1815 },
1816 },
1817 [C(ITLB)] = {
1818 [C(OP_READ)] = {
1819 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1820 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1821 },
1822 [C(OP_WRITE)] = {
1823 [C(RESULT_ACCESS)] = -1,
1824 [C(RESULT_MISS)] = -1,
1825 },
1826 [C(OP_PREFETCH)] = {
1827 [C(RESULT_ACCESS)] = -1,
1828 [C(RESULT_MISS)] = -1,
1829 },
1830 },
1831 [C(BPU)] = {
1832 [C(OP_READ)] = {
1833 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1834 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1835 },
1836 [C(OP_WRITE)] = {
1837 [C(RESULT_ACCESS)] = -1,
1838 [C(RESULT_MISS)] = -1,
1839 },
1840 [C(OP_PREFETCH)] = {
1841 [C(RESULT_ACCESS)] = -1,
1842 [C(RESULT_MISS)] = -1,
1843 },
1844 },
1845 };
1846
1847 static __initconst const u64 glp_hw_cache_extra_regs
1848 [PERF_COUNT_HW_CACHE_MAX]
1849 [PERF_COUNT_HW_CACHE_OP_MAX]
1850 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1851 [C(LL)] = {
1852 [C(OP_READ)] = {
1853 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1854 GLM_LLC_ACCESS,
1855 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1856 GLM_LLC_MISS,
1857 },
1858 [C(OP_WRITE)] = {
1859 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1860 GLM_LLC_ACCESS,
1861 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1862 GLM_LLC_MISS,
1863 },
1864 [C(OP_PREFETCH)] = {
1865 [C(RESULT_ACCESS)] = 0x0,
1866 [C(RESULT_MISS)] = 0x0,
1867 },
1868 },
1869 };
1870
1871 #define TNT_LOCAL_DRAM BIT_ULL(26)
1872 #define TNT_DEMAND_READ GLM_DEMAND_DATA_RD
1873 #define TNT_DEMAND_WRITE GLM_DEMAND_RFO
1874 #define TNT_LLC_ACCESS GLM_ANY_RESPONSE
1875 #define TNT_SNP_ANY (SNB_SNP_NOT_NEEDED|SNB_SNP_MISS| \
1876 SNB_NO_FWD|SNB_SNP_FWD|SNB_HITM)
1877 #define TNT_LLC_MISS (TNT_SNP_ANY|SNB_NON_DRAM|TNT_LOCAL_DRAM)
1878
1879 static __initconst const u64 tnt_hw_cache_extra_regs
1880 [PERF_COUNT_HW_CACHE_MAX]
1881 [PERF_COUNT_HW_CACHE_OP_MAX]
1882 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1883 [C(LL)] = {
1884 [C(OP_READ)] = {
1885 [C(RESULT_ACCESS)] = TNT_DEMAND_READ|
1886 TNT_LLC_ACCESS,
1887 [C(RESULT_MISS)] = TNT_DEMAND_READ|
1888 TNT_LLC_MISS,
1889 },
1890 [C(OP_WRITE)] = {
1891 [C(RESULT_ACCESS)] = TNT_DEMAND_WRITE|
1892 TNT_LLC_ACCESS,
1893 [C(RESULT_MISS)] = TNT_DEMAND_WRITE|
1894 TNT_LLC_MISS,
1895 },
1896 [C(OP_PREFETCH)] = {
1897 [C(RESULT_ACCESS)] = 0x0,
1898 [C(RESULT_MISS)] = 0x0,
1899 },
1900 },
1901 };
1902
1903 static struct extra_reg intel_tnt_extra_regs[] __read_mostly = {
1904 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1905 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x800ff0ffffff9fffull, RSP_0),
1906 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xff0ffffff9fffull, RSP_1),
1907 EVENT_EXTRA_END
1908 };
1909
1910 #define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1911 #define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1912 #define KNL_MCDRAM_LOCAL BIT_ULL(21)
1913 #define KNL_MCDRAM_FAR BIT_ULL(22)
1914 #define KNL_DDR_LOCAL BIT_ULL(23)
1915 #define KNL_DDR_FAR BIT_ULL(24)
1916 #define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1917 KNL_DDR_LOCAL | KNL_DDR_FAR)
1918 #define KNL_L2_READ SLM_DMND_READ
1919 #define KNL_L2_WRITE SLM_DMND_WRITE
1920 #define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1921 #define KNL_L2_ACCESS SLM_LLC_ACCESS
1922 #define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1923 KNL_DRAM_ANY | SNB_SNP_ANY | \
1924 SNB_NON_DRAM)
1925
1926 static __initconst const u64 knl_hw_cache_extra_regs
1927 [PERF_COUNT_HW_CACHE_MAX]
1928 [PERF_COUNT_HW_CACHE_OP_MAX]
1929 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1930 [C(LL)] = {
1931 [C(OP_READ)] = {
1932 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1933 [C(RESULT_MISS)] = 0,
1934 },
1935 [C(OP_WRITE)] = {
1936 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1937 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1938 },
1939 [C(OP_PREFETCH)] = {
1940 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1941 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1942 },
1943 },
1944 };
1945
1946 /*
1947 * Used from PMIs where the LBRs are already disabled.
1948 *
1949 * This function could be called consecutively. It is required to remain in
1950 * disabled state if called consecutively.
1951 *
1952 * During consecutive calls, the same disable value will be written to related
1953 * registers, so the PMU state remains unchanged.
1954 *
1955 * intel_bts events don't coexist with intel PMU's BTS events because of
1956 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1957 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1958 *
1959 * Avoid PEBS_ENABLE MSR access in PMIs.
1960 * The GLOBAL_CTRL has been disabled. All the counters do not count anymore.
1961 * It doesn't matter if the PEBS is enabled or not.
1962 * Usually, the PEBS status are not changed in PMIs. It's unnecessary to
1963 * access PEBS_ENABLE MSR in disable_all()/enable_all().
1964 * However, there are some cases which may change PEBS status, e.g. PMI
1965 * throttle. The PEBS_ENABLE should be updated where the status changes.
1966 */
__intel_pmu_disable_all(void)1967 static void __intel_pmu_disable_all(void)
1968 {
1969 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1970
1971 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1972
1973 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1974 intel_pmu_disable_bts();
1975 }
1976
intel_pmu_disable_all(void)1977 static void intel_pmu_disable_all(void)
1978 {
1979 __intel_pmu_disable_all();
1980 intel_pmu_pebs_disable_all();
1981 intel_pmu_lbr_disable_all();
1982 }
1983
__intel_pmu_enable_all(int added,bool pmi)1984 static void __intel_pmu_enable_all(int added, bool pmi)
1985 {
1986 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1987
1988 intel_pmu_lbr_enable_all(pmi);
1989 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1990 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
1991
1992 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1993 struct perf_event *event =
1994 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
1995
1996 if (WARN_ON_ONCE(!event))
1997 return;
1998
1999 intel_pmu_enable_bts(event->hw.config);
2000 }
2001 }
2002
intel_pmu_enable_all(int added)2003 static void intel_pmu_enable_all(int added)
2004 {
2005 intel_pmu_pebs_enable_all();
2006 __intel_pmu_enable_all(added, false);
2007 }
2008
2009 /*
2010 * Workaround for:
2011 * Intel Errata AAK100 (model 26)
2012 * Intel Errata AAP53 (model 30)
2013 * Intel Errata BD53 (model 44)
2014 *
2015 * The official story:
2016 * These chips need to be 'reset' when adding counters by programming the
2017 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
2018 * in sequence on the same PMC or on different PMCs.
2019 *
2020 * In practise it appears some of these events do in fact count, and
2021 * we need to program all 4 events.
2022 */
intel_pmu_nhm_workaround(void)2023 static void intel_pmu_nhm_workaround(void)
2024 {
2025 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2026 static const unsigned long nhm_magic[4] = {
2027 0x4300B5,
2028 0x4300D2,
2029 0x4300B1,
2030 0x4300B1
2031 };
2032 struct perf_event *event;
2033 int i;
2034
2035 /*
2036 * The Errata requires below steps:
2037 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
2038 * 2) Configure 4 PERFEVTSELx with the magic events and clear
2039 * the corresponding PMCx;
2040 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
2041 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
2042 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
2043 */
2044
2045 /*
2046 * The real steps we choose are a little different from above.
2047 * A) To reduce MSR operations, we don't run step 1) as they
2048 * are already cleared before this function is called;
2049 * B) Call x86_perf_event_update to save PMCx before configuring
2050 * PERFEVTSELx with magic number;
2051 * C) With step 5), we do clear only when the PERFEVTSELx is
2052 * not used currently.
2053 * D) Call x86_perf_event_set_period to restore PMCx;
2054 */
2055
2056 /* We always operate 4 pairs of PERF Counters */
2057 for (i = 0; i < 4; i++) {
2058 event = cpuc->events[i];
2059 if (event)
2060 x86_perf_event_update(event);
2061 }
2062
2063 for (i = 0; i < 4; i++) {
2064 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
2065 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
2066 }
2067
2068 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
2069 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
2070
2071 for (i = 0; i < 4; i++) {
2072 event = cpuc->events[i];
2073
2074 if (event) {
2075 x86_perf_event_set_period(event);
2076 __x86_pmu_enable_event(&event->hw,
2077 ARCH_PERFMON_EVENTSEL_ENABLE);
2078 } else
2079 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
2080 }
2081 }
2082
intel_pmu_nhm_enable_all(int added)2083 static void intel_pmu_nhm_enable_all(int added)
2084 {
2085 if (added)
2086 intel_pmu_nhm_workaround();
2087 intel_pmu_enable_all(added);
2088 }
2089
intel_set_tfa(struct cpu_hw_events * cpuc,bool on)2090 static void intel_set_tfa(struct cpu_hw_events *cpuc, bool on)
2091 {
2092 u64 val = on ? MSR_TFA_RTM_FORCE_ABORT : 0;
2093
2094 if (cpuc->tfa_shadow != val) {
2095 cpuc->tfa_shadow = val;
2096 wrmsrl(MSR_TSX_FORCE_ABORT, val);
2097 }
2098 }
2099
intel_tfa_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)2100 static void intel_tfa_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2101 {
2102 /*
2103 * We're going to use PMC3, make sure TFA is set before we touch it.
2104 */
2105 if (cntr == 3)
2106 intel_set_tfa(cpuc, true);
2107 }
2108
intel_tfa_pmu_enable_all(int added)2109 static void intel_tfa_pmu_enable_all(int added)
2110 {
2111 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2112
2113 /*
2114 * If we find PMC3 is no longer used when we enable the PMU, we can
2115 * clear TFA.
2116 */
2117 if (!test_bit(3, cpuc->active_mask))
2118 intel_set_tfa(cpuc, false);
2119
2120 intel_pmu_enable_all(added);
2121 }
2122
enable_counter_freeze(void)2123 static void enable_counter_freeze(void)
2124 {
2125 update_debugctlmsr(get_debugctlmsr() |
2126 DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2127 }
2128
disable_counter_freeze(void)2129 static void disable_counter_freeze(void)
2130 {
2131 update_debugctlmsr(get_debugctlmsr() &
2132 ~DEBUGCTLMSR_FREEZE_PERFMON_ON_PMI);
2133 }
2134
intel_pmu_get_status(void)2135 static inline u64 intel_pmu_get_status(void)
2136 {
2137 u64 status;
2138
2139 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
2140
2141 return status;
2142 }
2143
intel_pmu_ack_status(u64 ack)2144 static inline void intel_pmu_ack_status(u64 ack)
2145 {
2146 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
2147 }
2148
event_is_checkpointed(struct perf_event * event)2149 static inline bool event_is_checkpointed(struct perf_event *event)
2150 {
2151 return unlikely(event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
2152 }
2153
intel_set_masks(struct perf_event * event,int idx)2154 static inline void intel_set_masks(struct perf_event *event, int idx)
2155 {
2156 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2157
2158 if (event->attr.exclude_host)
2159 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2160 if (event->attr.exclude_guest)
2161 __set_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2162 if (event_is_checkpointed(event))
2163 __set_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2164 }
2165
intel_clear_masks(struct perf_event * event,int idx)2166 static inline void intel_clear_masks(struct perf_event *event, int idx)
2167 {
2168 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2169
2170 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_guest_mask);
2171 __clear_bit(idx, (unsigned long *)&cpuc->intel_ctrl_host_mask);
2172 __clear_bit(idx, (unsigned long *)&cpuc->intel_cp_status);
2173 }
2174
intel_pmu_disable_fixed(struct perf_event * event)2175 static void intel_pmu_disable_fixed(struct perf_event *event)
2176 {
2177 struct hw_perf_event *hwc = &event->hw;
2178 u64 ctrl_val, mask;
2179 int idx = hwc->idx;
2180
2181 if (is_topdown_idx(idx)) {
2182 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2183
2184 /*
2185 * When there are other active TopDown events,
2186 * don't disable the fixed counter 3.
2187 */
2188 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2189 return;
2190 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2191 }
2192
2193 intel_clear_masks(event, idx);
2194
2195 mask = 0xfULL << ((idx - INTEL_PMC_IDX_FIXED) * 4);
2196 rdmsrl(hwc->config_base, ctrl_val);
2197 ctrl_val &= ~mask;
2198 wrmsrl(hwc->config_base, ctrl_val);
2199 }
2200
intel_pmu_disable_event(struct perf_event * event)2201 static void intel_pmu_disable_event(struct perf_event *event)
2202 {
2203 struct hw_perf_event *hwc = &event->hw;
2204 int idx = hwc->idx;
2205
2206 switch (idx) {
2207 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2208 intel_clear_masks(event, idx);
2209 x86_pmu_disable_event(event);
2210 break;
2211 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2212 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2213 intel_pmu_disable_fixed(event);
2214 break;
2215 case INTEL_PMC_IDX_FIXED_BTS:
2216 intel_pmu_disable_bts();
2217 intel_pmu_drain_bts_buffer();
2218 return;
2219 case INTEL_PMC_IDX_FIXED_VLBR:
2220 intel_clear_masks(event, idx);
2221 break;
2222 default:
2223 intel_clear_masks(event, idx);
2224 pr_warn("Failed to disable the event with invalid index %d\n",
2225 idx);
2226 return;
2227 }
2228
2229 /*
2230 * Needs to be called after x86_pmu_disable_event,
2231 * so we don't trigger the event without PEBS bit set.
2232 */
2233 if (unlikely(event->attr.precise_ip))
2234 intel_pmu_pebs_disable(event);
2235 }
2236
intel_pmu_del_event(struct perf_event * event)2237 static void intel_pmu_del_event(struct perf_event *event)
2238 {
2239 if (needs_branch_stack(event))
2240 intel_pmu_lbr_del(event);
2241 if (event->attr.precise_ip)
2242 intel_pmu_pebs_del(event);
2243 }
2244
icl_set_topdown_event_period(struct perf_event * event)2245 static int icl_set_topdown_event_period(struct perf_event *event)
2246 {
2247 struct hw_perf_event *hwc = &event->hw;
2248 s64 left = local64_read(&hwc->period_left);
2249
2250 /*
2251 * The values in PERF_METRICS MSR are derived from fixed counter 3.
2252 * Software should start both registers, PERF_METRICS and fixed
2253 * counter 3, from zero.
2254 * Clear PERF_METRICS and Fixed counter 3 in initialization.
2255 * After that, both MSRs will be cleared for each read.
2256 * Don't need to clear them again.
2257 */
2258 if (left == x86_pmu.max_period) {
2259 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2260 wrmsrl(MSR_PERF_METRICS, 0);
2261 hwc->saved_slots = 0;
2262 hwc->saved_metric = 0;
2263 }
2264
2265 if ((hwc->saved_slots) && is_slots_event(event)) {
2266 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, hwc->saved_slots);
2267 wrmsrl(MSR_PERF_METRICS, hwc->saved_metric);
2268 }
2269
2270 perf_event_update_userpage(event);
2271
2272 return 0;
2273 }
2274
icl_get_metrics_event_value(u64 metric,u64 slots,int idx)2275 static inline u64 icl_get_metrics_event_value(u64 metric, u64 slots, int idx)
2276 {
2277 u32 val;
2278
2279 /*
2280 * The metric is reported as an 8bit integer fraction
2281 * suming up to 0xff.
2282 * slots-in-metric = (Metric / 0xff) * slots
2283 */
2284 val = (metric >> ((idx - INTEL_PMC_IDX_METRIC_BASE) * 8)) & 0xff;
2285 return mul_u64_u32_div(slots, val, 0xff);
2286 }
2287
icl_get_topdown_value(struct perf_event * event,u64 slots,u64 metrics)2288 static u64 icl_get_topdown_value(struct perf_event *event,
2289 u64 slots, u64 metrics)
2290 {
2291 int idx = event->hw.idx;
2292 u64 delta;
2293
2294 if (is_metric_idx(idx))
2295 delta = icl_get_metrics_event_value(metrics, slots, idx);
2296 else
2297 delta = slots;
2298
2299 return delta;
2300 }
2301
__icl_update_topdown_event(struct perf_event * event,u64 slots,u64 metrics,u64 last_slots,u64 last_metrics)2302 static void __icl_update_topdown_event(struct perf_event *event,
2303 u64 slots, u64 metrics,
2304 u64 last_slots, u64 last_metrics)
2305 {
2306 u64 delta, last = 0;
2307
2308 delta = icl_get_topdown_value(event, slots, metrics);
2309 if (last_slots)
2310 last = icl_get_topdown_value(event, last_slots, last_metrics);
2311
2312 /*
2313 * The 8bit integer fraction of metric may be not accurate,
2314 * especially when the changes is very small.
2315 * For example, if only a few bad_spec happens, the fraction
2316 * may be reduced from 1 to 0. If so, the bad_spec event value
2317 * will be 0 which is definitely less than the last value.
2318 * Avoid update event->count for this case.
2319 */
2320 if (delta > last) {
2321 delta -= last;
2322 local64_add(delta, &event->count);
2323 }
2324 }
2325
update_saved_topdown_regs(struct perf_event * event,u64 slots,u64 metrics)2326 static void update_saved_topdown_regs(struct perf_event *event,
2327 u64 slots, u64 metrics)
2328 {
2329 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2330 struct perf_event *other;
2331 int idx;
2332
2333 event->hw.saved_slots = slots;
2334 event->hw.saved_metric = metrics;
2335
2336 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) {
2337 if (!is_topdown_idx(idx))
2338 continue;
2339 other = cpuc->events[idx];
2340 other->hw.saved_slots = slots;
2341 other->hw.saved_metric = metrics;
2342 }
2343 }
2344
2345 /*
2346 * Update all active Topdown events.
2347 *
2348 * The PERF_METRICS and Fixed counter 3 are read separately. The values may be
2349 * modify by a NMI. PMU has to be disabled before calling this function.
2350 */
icl_update_topdown_event(struct perf_event * event)2351 static u64 icl_update_topdown_event(struct perf_event *event)
2352 {
2353 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2354 struct perf_event *other;
2355 u64 slots, metrics;
2356 bool reset = true;
2357 int idx;
2358
2359 /* read Fixed counter 3 */
2360 rdpmcl((3 | INTEL_PMC_FIXED_RDPMC_BASE), slots);
2361 if (!slots)
2362 return 0;
2363
2364 /* read PERF_METRICS */
2365 rdpmcl(INTEL_PMC_FIXED_RDPMC_METRICS, metrics);
2366
2367 for_each_set_bit(idx, cpuc->active_mask, INTEL_PMC_IDX_TD_BE_BOUND + 1) {
2368 if (!is_topdown_idx(idx))
2369 continue;
2370 other = cpuc->events[idx];
2371 __icl_update_topdown_event(other, slots, metrics,
2372 event ? event->hw.saved_slots : 0,
2373 event ? event->hw.saved_metric : 0);
2374 }
2375
2376 /*
2377 * Check and update this event, which may have been cleared
2378 * in active_mask e.g. x86_pmu_stop()
2379 */
2380 if (event && !test_bit(event->hw.idx, cpuc->active_mask)) {
2381 __icl_update_topdown_event(event, slots, metrics,
2382 event->hw.saved_slots,
2383 event->hw.saved_metric);
2384
2385 /*
2386 * In x86_pmu_stop(), the event is cleared in active_mask first,
2387 * then drain the delta, which indicates context switch for
2388 * counting.
2389 * Save metric and slots for context switch.
2390 * Don't need to reset the PERF_METRICS and Fixed counter 3.
2391 * Because the values will be restored in next schedule in.
2392 */
2393 update_saved_topdown_regs(event, slots, metrics);
2394 reset = false;
2395 }
2396
2397 if (reset) {
2398 /* The fixed counter 3 has to be written before the PERF_METRICS. */
2399 wrmsrl(MSR_CORE_PERF_FIXED_CTR3, 0);
2400 wrmsrl(MSR_PERF_METRICS, 0);
2401 if (event)
2402 update_saved_topdown_regs(event, 0, 0);
2403 }
2404
2405 return slots;
2406 }
2407
intel_pmu_read_topdown_event(struct perf_event * event)2408 static void intel_pmu_read_topdown_event(struct perf_event *event)
2409 {
2410 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2411
2412 /* Only need to call update_topdown_event() once for group read. */
2413 if ((cpuc->txn_flags & PERF_PMU_TXN_READ) &&
2414 !is_slots_event(event))
2415 return;
2416
2417 perf_pmu_disable(event->pmu);
2418 x86_pmu.update_topdown_event(event);
2419 perf_pmu_enable(event->pmu);
2420 }
2421
intel_pmu_read_event(struct perf_event * event)2422 static void intel_pmu_read_event(struct perf_event *event)
2423 {
2424 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2425 intel_pmu_auto_reload_read(event);
2426 else if (is_topdown_count(event) && x86_pmu.update_topdown_event)
2427 intel_pmu_read_topdown_event(event);
2428 else
2429 x86_perf_event_update(event);
2430 }
2431
intel_pmu_enable_fixed(struct perf_event * event)2432 static void intel_pmu_enable_fixed(struct perf_event *event)
2433 {
2434 struct hw_perf_event *hwc = &event->hw;
2435 u64 ctrl_val, mask, bits = 0;
2436 int idx = hwc->idx;
2437
2438 if (is_topdown_idx(idx)) {
2439 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2440 /*
2441 * When there are other active TopDown events,
2442 * don't enable the fixed counter 3 again.
2443 */
2444 if (*(u64 *)cpuc->active_mask & INTEL_PMC_OTHER_TOPDOWN_BITS(idx))
2445 return;
2446
2447 idx = INTEL_PMC_IDX_FIXED_SLOTS;
2448 }
2449
2450 intel_set_masks(event, idx);
2451
2452 /*
2453 * Enable IRQ generation (0x8), if not PEBS,
2454 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
2455 * if requested:
2456 */
2457 if (!event->attr.precise_ip)
2458 bits |= 0x8;
2459 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
2460 bits |= 0x2;
2461 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
2462 bits |= 0x1;
2463
2464 /*
2465 * ANY bit is supported in v3 and up
2466 */
2467 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
2468 bits |= 0x4;
2469
2470 idx -= INTEL_PMC_IDX_FIXED;
2471 bits <<= (idx * 4);
2472 mask = 0xfULL << (idx * 4);
2473
2474 if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
2475 bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2476 mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
2477 }
2478
2479 rdmsrl(hwc->config_base, ctrl_val);
2480 ctrl_val &= ~mask;
2481 ctrl_val |= bits;
2482 wrmsrl(hwc->config_base, ctrl_val);
2483 }
2484
intel_pmu_enable_event(struct perf_event * event)2485 static void intel_pmu_enable_event(struct perf_event *event)
2486 {
2487 struct hw_perf_event *hwc = &event->hw;
2488 int idx = hwc->idx;
2489
2490 if (unlikely(event->attr.precise_ip))
2491 intel_pmu_pebs_enable(event);
2492
2493 switch (idx) {
2494 case 0 ... INTEL_PMC_IDX_FIXED - 1:
2495 intel_set_masks(event, idx);
2496 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2497 break;
2498 case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:
2499 case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END:
2500 intel_pmu_enable_fixed(event);
2501 break;
2502 case INTEL_PMC_IDX_FIXED_BTS:
2503 if (!__this_cpu_read(cpu_hw_events.enabled))
2504 return;
2505 intel_pmu_enable_bts(hwc->config);
2506 break;
2507 case INTEL_PMC_IDX_FIXED_VLBR:
2508 intel_set_masks(event, idx);
2509 break;
2510 default:
2511 pr_warn("Failed to enable the event with invalid index %d\n",
2512 idx);
2513 }
2514 }
2515
intel_pmu_add_event(struct perf_event * event)2516 static void intel_pmu_add_event(struct perf_event *event)
2517 {
2518 if (event->attr.precise_ip)
2519 intel_pmu_pebs_add(event);
2520 if (needs_branch_stack(event))
2521 intel_pmu_lbr_add(event);
2522 }
2523
2524 /*
2525 * Save and restart an expired event. Called by NMI contexts,
2526 * so it has to be careful about preempting normal event ops:
2527 */
intel_pmu_save_and_restart(struct perf_event * event)2528 int intel_pmu_save_and_restart(struct perf_event *event)
2529 {
2530 x86_perf_event_update(event);
2531 /*
2532 * For a checkpointed counter always reset back to 0. This
2533 * avoids a situation where the counter overflows, aborts the
2534 * transaction and is then set back to shortly before the
2535 * overflow, and overflows and aborts again.
2536 */
2537 if (unlikely(event_is_checkpointed(event))) {
2538 /* No race with NMIs because the counter should not be armed */
2539 wrmsrl(event->hw.event_base, 0);
2540 local64_set(&event->hw.prev_count, 0);
2541 }
2542 return x86_perf_event_set_period(event);
2543 }
2544
intel_pmu_reset(void)2545 static void intel_pmu_reset(void)
2546 {
2547 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2548 unsigned long flags;
2549 int idx;
2550
2551 if (!x86_pmu.num_counters)
2552 return;
2553
2554 local_irq_save(flags);
2555
2556 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
2557
2558 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2559 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2560 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
2561 }
2562 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
2563 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
2564
2565 if (ds)
2566 ds->bts_index = ds->bts_buffer_base;
2567
2568 /* Ack all overflows and disable fixed counters */
2569 if (x86_pmu.version >= 2) {
2570 intel_pmu_ack_status(intel_pmu_get_status());
2571 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2572 }
2573
2574 /* Reset LBRs and LBR freezing */
2575 if (x86_pmu.lbr_nr) {
2576 update_debugctlmsr(get_debugctlmsr() &
2577 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2578 }
2579
2580 local_irq_restore(flags);
2581 }
2582
handle_pmi_common(struct pt_regs * regs,u64 status)2583 static int handle_pmi_common(struct pt_regs *regs, u64 status)
2584 {
2585 struct perf_sample_data data;
2586 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2587 int bit;
2588 int handled = 0;
2589
2590 inc_irq_stat(apic_perf_irqs);
2591
2592 /*
2593 * Ignore a range of extra bits in status that do not indicate
2594 * overflow by themselves.
2595 */
2596 status &= ~(GLOBAL_STATUS_COND_CHG |
2597 GLOBAL_STATUS_ASIF |
2598 GLOBAL_STATUS_LBRS_FROZEN);
2599 if (!status)
2600 return 0;
2601 /*
2602 * In case multiple PEBS events are sampled at the same time,
2603 * it is possible to have GLOBAL_STATUS bit 62 set indicating
2604 * PEBS buffer overflow and also seeing at most 3 PEBS counters
2605 * having their bits set in the status register. This is a sign
2606 * that there was at least one PEBS record pending at the time
2607 * of the PMU interrupt. PEBS counters must only be processed
2608 * via the drain_pebs() calls and not via the regular sample
2609 * processing loop coming after that the function, otherwise
2610 * phony regular samples may be generated in the sampling buffer
2611 * not marked with the EXACT tag. Another possibility is to have
2612 * one PEBS event and at least one non-PEBS event whic hoverflows
2613 * while PEBS has armed. In this case, bit 62 of GLOBAL_STATUS will
2614 * not be set, yet the overflow status bit for the PEBS counter will
2615 * be on Skylake.
2616 *
2617 * To avoid this problem, we systematically ignore the PEBS-enabled
2618 * counters from the GLOBAL_STATUS mask and we always process PEBS
2619 * events via drain_pebs().
2620 */
2621 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
2622 status &= ~cpuc->pebs_enabled;
2623 else
2624 status &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
2625
2626 /*
2627 * PEBS overflow sets bit 62 in the global status register
2628 */
2629 if (__test_and_clear_bit(GLOBAL_STATUS_BUFFER_OVF_BIT, (unsigned long *)&status)) {
2630 u64 pebs_enabled = cpuc->pebs_enabled;
2631
2632 handled++;
2633 x86_pmu.drain_pebs(regs, &data);
2634 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
2635
2636 /*
2637 * PMI throttle may be triggered, which stops the PEBS event.
2638 * Although cpuc->pebs_enabled is updated accordingly, the
2639 * MSR_IA32_PEBS_ENABLE is not updated. Because the
2640 * cpuc->enabled has been forced to 0 in PMI.
2641 * Update the MSR if pebs_enabled is changed.
2642 */
2643 if (pebs_enabled != cpuc->pebs_enabled)
2644 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
2645 }
2646
2647 /*
2648 * Intel PT
2649 */
2650 if (__test_and_clear_bit(GLOBAL_STATUS_TRACE_TOPAPMI_BIT, (unsigned long *)&status)) {
2651 handled++;
2652 if (unlikely(perf_guest_cbs && perf_guest_cbs->is_in_guest() &&
2653 perf_guest_cbs->handle_intel_pt_intr))
2654 perf_guest_cbs->handle_intel_pt_intr();
2655 else
2656 intel_pt_interrupt();
2657 }
2658
2659 /*
2660 * Intel Perf mertrics
2661 */
2662 if (__test_and_clear_bit(GLOBAL_STATUS_PERF_METRICS_OVF_BIT, (unsigned long *)&status)) {
2663 handled++;
2664 if (x86_pmu.update_topdown_event)
2665 x86_pmu.update_topdown_event(NULL);
2666 }
2667
2668 /*
2669 * Checkpointed counters can lead to 'spurious' PMIs because the
2670 * rollback caused by the PMI will have cleared the overflow status
2671 * bit. Therefore always force probe these counters.
2672 */
2673 status |= cpuc->intel_cp_status;
2674
2675 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
2676 struct perf_event *event = cpuc->events[bit];
2677
2678 handled++;
2679
2680 if (!test_bit(bit, cpuc->active_mask))
2681 continue;
2682
2683 if (!intel_pmu_save_and_restart(event))
2684 continue;
2685
2686 perf_sample_data_init(&data, 0, event->hw.last_period);
2687
2688 if (has_branch_stack(event))
2689 data.br_stack = &cpuc->lbr_stack;
2690
2691 if (perf_event_overflow(event, &data, regs))
2692 x86_pmu_stop(event, 0);
2693 }
2694
2695 return handled;
2696 }
2697
2698 static bool disable_counter_freezing = true;
intel_perf_counter_freezing_setup(char * s)2699 static int __init intel_perf_counter_freezing_setup(char *s)
2700 {
2701 bool res;
2702
2703 if (kstrtobool(s, &res))
2704 return -EINVAL;
2705
2706 disable_counter_freezing = !res;
2707 return 1;
2708 }
2709 __setup("perf_v4_pmi=", intel_perf_counter_freezing_setup);
2710
2711 /*
2712 * Simplified handler for Arch Perfmon v4:
2713 * - We rely on counter freezing/unfreezing to enable/disable the PMU.
2714 * This is done automatically on PMU ack.
2715 * - Ack the PMU only after the APIC.
2716 */
2717
intel_pmu_handle_irq_v4(struct pt_regs * regs)2718 static int intel_pmu_handle_irq_v4(struct pt_regs *regs)
2719 {
2720 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2721 int handled = 0;
2722 bool bts = false;
2723 u64 status;
2724 int pmu_enabled = cpuc->enabled;
2725 int loops = 0;
2726
2727 /* PMU has been disabled because of counter freezing */
2728 cpuc->enabled = 0;
2729 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
2730 bts = true;
2731 intel_bts_disable_local();
2732 handled = intel_pmu_drain_bts_buffer();
2733 handled += intel_bts_interrupt();
2734 }
2735 status = intel_pmu_get_status();
2736 if (!status)
2737 goto done;
2738 again:
2739 intel_pmu_lbr_read();
2740 if (++loops > 100) {
2741 static bool warned;
2742
2743 if (!warned) {
2744 WARN(1, "perfevents: irq loop stuck!\n");
2745 perf_event_print_debug();
2746 warned = true;
2747 }
2748 intel_pmu_reset();
2749 goto done;
2750 }
2751
2752
2753 handled += handle_pmi_common(regs, status);
2754 done:
2755 /* Ack the PMI in the APIC */
2756 apic_write(APIC_LVTPC, APIC_DM_NMI);
2757
2758 /*
2759 * The counters start counting immediately while ack the status.
2760 * Make it as close as possible to IRET. This avoids bogus
2761 * freezing on Skylake CPUs.
2762 */
2763 if (status) {
2764 intel_pmu_ack_status(status);
2765 } else {
2766 /*
2767 * CPU may issues two PMIs very close to each other.
2768 * When the PMI handler services the first one, the
2769 * GLOBAL_STATUS is already updated to reflect both.
2770 * When it IRETs, the second PMI is immediately
2771 * handled and it sees clear status. At the meantime,
2772 * there may be a third PMI, because the freezing bit
2773 * isn't set since the ack in first PMI handlers.
2774 * Double check if there is more work to be done.
2775 */
2776 status = intel_pmu_get_status();
2777 if (status)
2778 goto again;
2779 }
2780
2781 if (bts)
2782 intel_bts_enable_local();
2783 cpuc->enabled = pmu_enabled;
2784 return handled;
2785 }
2786
2787 /*
2788 * This handler is triggered by the local APIC, so the APIC IRQ handling
2789 * rules apply:
2790 */
intel_pmu_handle_irq(struct pt_regs * regs)2791 static int intel_pmu_handle_irq(struct pt_regs *regs)
2792 {
2793 struct cpu_hw_events *cpuc;
2794 int loops;
2795 u64 status;
2796 int handled;
2797 int pmu_enabled;
2798
2799 cpuc = this_cpu_ptr(&cpu_hw_events);
2800
2801 /*
2802 * Save the PMU state.
2803 * It needs to be restored when leaving the handler.
2804 */
2805 pmu_enabled = cpuc->enabled;
2806 /*
2807 * No known reason to not always do late ACK,
2808 * but just in case do it opt-in.
2809 */
2810 if (!x86_pmu.late_ack)
2811 apic_write(APIC_LVTPC, APIC_DM_NMI);
2812 intel_bts_disable_local();
2813 cpuc->enabled = 0;
2814 __intel_pmu_disable_all();
2815 handled = intel_pmu_drain_bts_buffer();
2816 handled += intel_bts_interrupt();
2817 status = intel_pmu_get_status();
2818 if (!status)
2819 goto done;
2820
2821 loops = 0;
2822 again:
2823 intel_pmu_lbr_read();
2824 intel_pmu_ack_status(status);
2825 if (++loops > 100) {
2826 static bool warned;
2827
2828 if (!warned) {
2829 WARN(1, "perfevents: irq loop stuck!\n");
2830 perf_event_print_debug();
2831 warned = true;
2832 }
2833 intel_pmu_reset();
2834 goto done;
2835 }
2836
2837 handled += handle_pmi_common(regs, status);
2838
2839 /*
2840 * Repeat if there is more work to be done:
2841 */
2842 status = intel_pmu_get_status();
2843 if (status)
2844 goto again;
2845
2846 done:
2847 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2848 cpuc->enabled = pmu_enabled;
2849 if (pmu_enabled)
2850 __intel_pmu_enable_all(0, true);
2851 intel_bts_enable_local();
2852
2853 /*
2854 * Only unmask the NMI after the overflow counters
2855 * have been reset. This avoids spurious NMIs on
2856 * Haswell CPUs.
2857 */
2858 if (x86_pmu.late_ack)
2859 apic_write(APIC_LVTPC, APIC_DM_NMI);
2860 return handled;
2861 }
2862
2863 static struct event_constraint *
intel_bts_constraints(struct perf_event * event)2864 intel_bts_constraints(struct perf_event *event)
2865 {
2866 if (unlikely(intel_pmu_has_bts(event)))
2867 return &bts_constraint;
2868
2869 return NULL;
2870 }
2871
2872 /*
2873 * Note: matches a fake event, like Fixed2.
2874 */
2875 static struct event_constraint *
intel_vlbr_constraints(struct perf_event * event)2876 intel_vlbr_constraints(struct perf_event *event)
2877 {
2878 struct event_constraint *c = &vlbr_constraint;
2879
2880 if (unlikely(constraint_match(c, event->hw.config)))
2881 return c;
2882
2883 return NULL;
2884 }
2885
intel_alt_er(int idx,u64 config)2886 static int intel_alt_er(int idx, u64 config)
2887 {
2888 int alt_idx = idx;
2889
2890 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
2891 return idx;
2892
2893 if (idx == EXTRA_REG_RSP_0)
2894 alt_idx = EXTRA_REG_RSP_1;
2895
2896 if (idx == EXTRA_REG_RSP_1)
2897 alt_idx = EXTRA_REG_RSP_0;
2898
2899 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2900 return idx;
2901
2902 return alt_idx;
2903 }
2904
intel_fixup_er(struct perf_event * event,int idx)2905 static void intel_fixup_er(struct perf_event *event, int idx)
2906 {
2907 event->hw.extra_reg.idx = idx;
2908
2909 if (idx == EXTRA_REG_RSP_0) {
2910 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2911 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
2912 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
2913 } else if (idx == EXTRA_REG_RSP_1) {
2914 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
2915 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
2916 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
2917 }
2918 }
2919
2920 /*
2921 * manage allocation of shared extra msr for certain events
2922 *
2923 * sharing can be:
2924 * per-cpu: to be shared between the various events on a single PMU
2925 * per-core: per-cpu + shared by HT threads
2926 */
2927 static struct event_constraint *
__intel_shared_reg_get_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,struct hw_perf_event_extra * reg)2928 __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
2929 struct perf_event *event,
2930 struct hw_perf_event_extra *reg)
2931 {
2932 struct event_constraint *c = &emptyconstraint;
2933 struct er_account *era;
2934 unsigned long flags;
2935 int idx = reg->idx;
2936
2937 /*
2938 * reg->alloc can be set due to existing state, so for fake cpuc we
2939 * need to ignore this, otherwise we might fail to allocate proper fake
2940 * state for this extra reg constraint. Also see the comment below.
2941 */
2942 if (reg->alloc && !cpuc->is_fake)
2943 return NULL; /* call x86_get_event_constraint() */
2944
2945 again:
2946 era = &cpuc->shared_regs->regs[idx];
2947 /*
2948 * we use spin_lock_irqsave() to avoid lockdep issues when
2949 * passing a fake cpuc
2950 */
2951 raw_spin_lock_irqsave(&era->lock, flags);
2952
2953 if (!atomic_read(&era->ref) || era->config == reg->config) {
2954
2955 /*
2956 * If its a fake cpuc -- as per validate_{group,event}() we
2957 * shouldn't touch event state and we can avoid doing so
2958 * since both will only call get_event_constraints() once
2959 * on each event, this avoids the need for reg->alloc.
2960 *
2961 * Not doing the ER fixup will only result in era->reg being
2962 * wrong, but since we won't actually try and program hardware
2963 * this isn't a problem either.
2964 */
2965 if (!cpuc->is_fake) {
2966 if (idx != reg->idx)
2967 intel_fixup_er(event, idx);
2968
2969 /*
2970 * x86_schedule_events() can call get_event_constraints()
2971 * multiple times on events in the case of incremental
2972 * scheduling(). reg->alloc ensures we only do the ER
2973 * allocation once.
2974 */
2975 reg->alloc = 1;
2976 }
2977
2978 /* lock in msr value */
2979 era->config = reg->config;
2980 era->reg = reg->reg;
2981
2982 /* one more user */
2983 atomic_inc(&era->ref);
2984
2985 /*
2986 * need to call x86_get_event_constraint()
2987 * to check if associated event has constraints
2988 */
2989 c = NULL;
2990 } else {
2991 idx = intel_alt_er(idx, reg->config);
2992 if (idx != reg->idx) {
2993 raw_spin_unlock_irqrestore(&era->lock, flags);
2994 goto again;
2995 }
2996 }
2997 raw_spin_unlock_irqrestore(&era->lock, flags);
2998
2999 return c;
3000 }
3001
3002 static void
__intel_shared_reg_put_constraints(struct cpu_hw_events * cpuc,struct hw_perf_event_extra * reg)3003 __intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
3004 struct hw_perf_event_extra *reg)
3005 {
3006 struct er_account *era;
3007
3008 /*
3009 * Only put constraint if extra reg was actually allocated. Also takes
3010 * care of event which do not use an extra shared reg.
3011 *
3012 * Also, if this is a fake cpuc we shouldn't touch any event state
3013 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
3014 * either since it'll be thrown out.
3015 */
3016 if (!reg->alloc || cpuc->is_fake)
3017 return;
3018
3019 era = &cpuc->shared_regs->regs[reg->idx];
3020
3021 /* one fewer user */
3022 atomic_dec(&era->ref);
3023
3024 /* allocate again next time */
3025 reg->alloc = 0;
3026 }
3027
3028 static struct event_constraint *
intel_shared_regs_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3029 intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
3030 struct perf_event *event)
3031 {
3032 struct event_constraint *c = NULL, *d;
3033 struct hw_perf_event_extra *xreg, *breg;
3034
3035 xreg = &event->hw.extra_reg;
3036 if (xreg->idx != EXTRA_REG_NONE) {
3037 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
3038 if (c == &emptyconstraint)
3039 return c;
3040 }
3041 breg = &event->hw.branch_reg;
3042 if (breg->idx != EXTRA_REG_NONE) {
3043 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
3044 if (d == &emptyconstraint) {
3045 __intel_shared_reg_put_constraints(cpuc, xreg);
3046 c = d;
3047 }
3048 }
3049 return c;
3050 }
3051
3052 struct event_constraint *
x86_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3053 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3054 struct perf_event *event)
3055 {
3056 struct event_constraint *c;
3057
3058 if (x86_pmu.event_constraints) {
3059 for_each_event_constraint(c, x86_pmu.event_constraints) {
3060 if (constraint_match(c, event->hw.config)) {
3061 event->hw.flags |= c->flags;
3062 return c;
3063 }
3064 }
3065 }
3066
3067 return &unconstrained;
3068 }
3069
3070 static struct event_constraint *
__intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3071 __intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3072 struct perf_event *event)
3073 {
3074 struct event_constraint *c;
3075
3076 c = intel_vlbr_constraints(event);
3077 if (c)
3078 return c;
3079
3080 c = intel_bts_constraints(event);
3081 if (c)
3082 return c;
3083
3084 c = intel_shared_regs_constraints(cpuc, event);
3085 if (c)
3086 return c;
3087
3088 c = intel_pebs_constraints(event);
3089 if (c)
3090 return c;
3091
3092 return x86_get_event_constraints(cpuc, idx, event);
3093 }
3094
3095 static void
intel_start_scheduling(struct cpu_hw_events * cpuc)3096 intel_start_scheduling(struct cpu_hw_events *cpuc)
3097 {
3098 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3099 struct intel_excl_states *xl;
3100 int tid = cpuc->excl_thread_id;
3101
3102 /*
3103 * nothing needed if in group validation mode
3104 */
3105 if (cpuc->is_fake || !is_ht_workaround_enabled())
3106 return;
3107
3108 /*
3109 * no exclusion needed
3110 */
3111 if (WARN_ON_ONCE(!excl_cntrs))
3112 return;
3113
3114 xl = &excl_cntrs->states[tid];
3115
3116 xl->sched_started = true;
3117 /*
3118 * lock shared state until we are done scheduling
3119 * in stop_event_scheduling()
3120 * makes scheduling appear as a transaction
3121 */
3122 raw_spin_lock(&excl_cntrs->lock);
3123 }
3124
intel_commit_scheduling(struct cpu_hw_events * cpuc,int idx,int cntr)3125 static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
3126 {
3127 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3128 struct event_constraint *c = cpuc->event_constraint[idx];
3129 struct intel_excl_states *xl;
3130 int tid = cpuc->excl_thread_id;
3131
3132 if (cpuc->is_fake || !is_ht_workaround_enabled())
3133 return;
3134
3135 if (WARN_ON_ONCE(!excl_cntrs))
3136 return;
3137
3138 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
3139 return;
3140
3141 xl = &excl_cntrs->states[tid];
3142
3143 lockdep_assert_held(&excl_cntrs->lock);
3144
3145 if (c->flags & PERF_X86_EVENT_EXCL)
3146 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
3147 else
3148 xl->state[cntr] = INTEL_EXCL_SHARED;
3149 }
3150
3151 static void
intel_stop_scheduling(struct cpu_hw_events * cpuc)3152 intel_stop_scheduling(struct cpu_hw_events *cpuc)
3153 {
3154 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3155 struct intel_excl_states *xl;
3156 int tid = cpuc->excl_thread_id;
3157
3158 /*
3159 * nothing needed if in group validation mode
3160 */
3161 if (cpuc->is_fake || !is_ht_workaround_enabled())
3162 return;
3163 /*
3164 * no exclusion needed
3165 */
3166 if (WARN_ON_ONCE(!excl_cntrs))
3167 return;
3168
3169 xl = &excl_cntrs->states[tid];
3170
3171 xl->sched_started = false;
3172 /*
3173 * release shared state lock (acquired in intel_start_scheduling())
3174 */
3175 raw_spin_unlock(&excl_cntrs->lock);
3176 }
3177
3178 static struct event_constraint *
dyn_constraint(struct cpu_hw_events * cpuc,struct event_constraint * c,int idx)3179 dyn_constraint(struct cpu_hw_events *cpuc, struct event_constraint *c, int idx)
3180 {
3181 WARN_ON_ONCE(!cpuc->constraint_list);
3182
3183 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
3184 struct event_constraint *cx;
3185
3186 /*
3187 * grab pre-allocated constraint entry
3188 */
3189 cx = &cpuc->constraint_list[idx];
3190
3191 /*
3192 * initialize dynamic constraint
3193 * with static constraint
3194 */
3195 *cx = *c;
3196
3197 /*
3198 * mark constraint as dynamic
3199 */
3200 cx->flags |= PERF_X86_EVENT_DYNAMIC;
3201 c = cx;
3202 }
3203
3204 return c;
3205 }
3206
3207 static struct event_constraint *
intel_get_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event,int idx,struct event_constraint * c)3208 intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
3209 int idx, struct event_constraint *c)
3210 {
3211 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3212 struct intel_excl_states *xlo;
3213 int tid = cpuc->excl_thread_id;
3214 int is_excl, i, w;
3215
3216 /*
3217 * validating a group does not require
3218 * enforcing cross-thread exclusion
3219 */
3220 if (cpuc->is_fake || !is_ht_workaround_enabled())
3221 return c;
3222
3223 /*
3224 * no exclusion needed
3225 */
3226 if (WARN_ON_ONCE(!excl_cntrs))
3227 return c;
3228
3229 /*
3230 * because we modify the constraint, we need
3231 * to make a copy. Static constraints come
3232 * from static const tables.
3233 *
3234 * only needed when constraint has not yet
3235 * been cloned (marked dynamic)
3236 */
3237 c = dyn_constraint(cpuc, c, idx);
3238
3239 /*
3240 * From here on, the constraint is dynamic.
3241 * Either it was just allocated above, or it
3242 * was allocated during a earlier invocation
3243 * of this function
3244 */
3245
3246 /*
3247 * state of sibling HT
3248 */
3249 xlo = &excl_cntrs->states[tid ^ 1];
3250
3251 /*
3252 * event requires exclusive counter access
3253 * across HT threads
3254 */
3255 is_excl = c->flags & PERF_X86_EVENT_EXCL;
3256 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
3257 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
3258 if (!cpuc->n_excl++)
3259 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
3260 }
3261
3262 /*
3263 * Modify static constraint with current dynamic
3264 * state of thread
3265 *
3266 * EXCLUSIVE: sibling counter measuring exclusive event
3267 * SHARED : sibling counter measuring non-exclusive event
3268 * UNUSED : sibling counter unused
3269 */
3270 w = c->weight;
3271 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
3272 /*
3273 * exclusive event in sibling counter
3274 * our corresponding counter cannot be used
3275 * regardless of our event
3276 */
3277 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE) {
3278 __clear_bit(i, c->idxmsk);
3279 w--;
3280 continue;
3281 }
3282 /*
3283 * if measuring an exclusive event, sibling
3284 * measuring non-exclusive, then counter cannot
3285 * be used
3286 */
3287 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED) {
3288 __clear_bit(i, c->idxmsk);
3289 w--;
3290 continue;
3291 }
3292 }
3293
3294 /*
3295 * if we return an empty mask, then switch
3296 * back to static empty constraint to avoid
3297 * the cost of freeing later on
3298 */
3299 if (!w)
3300 c = &emptyconstraint;
3301
3302 c->weight = w;
3303
3304 return c;
3305 }
3306
3307 static struct event_constraint *
intel_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3308 intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3309 struct perf_event *event)
3310 {
3311 struct event_constraint *c1, *c2;
3312
3313 c1 = cpuc->event_constraint[idx];
3314
3315 /*
3316 * first time only
3317 * - static constraint: no change across incremental scheduling calls
3318 * - dynamic constraint: handled by intel_get_excl_constraints()
3319 */
3320 c2 = __intel_get_event_constraints(cpuc, idx, event);
3321 if (c1) {
3322 WARN_ON_ONCE(!(c1->flags & PERF_X86_EVENT_DYNAMIC));
3323 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
3324 c1->weight = c2->weight;
3325 c2 = c1;
3326 }
3327
3328 if (cpuc->excl_cntrs)
3329 return intel_get_excl_constraints(cpuc, event, idx, c2);
3330
3331 return c2;
3332 }
3333
intel_put_excl_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3334 static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
3335 struct perf_event *event)
3336 {
3337 struct hw_perf_event *hwc = &event->hw;
3338 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
3339 int tid = cpuc->excl_thread_id;
3340 struct intel_excl_states *xl;
3341
3342 /*
3343 * nothing needed if in group validation mode
3344 */
3345 if (cpuc->is_fake)
3346 return;
3347
3348 if (WARN_ON_ONCE(!excl_cntrs))
3349 return;
3350
3351 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
3352 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
3353 if (!--cpuc->n_excl)
3354 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
3355 }
3356
3357 /*
3358 * If event was actually assigned, then mark the counter state as
3359 * unused now.
3360 */
3361 if (hwc->idx >= 0) {
3362 xl = &excl_cntrs->states[tid];
3363
3364 /*
3365 * put_constraint may be called from x86_schedule_events()
3366 * which already has the lock held so here make locking
3367 * conditional.
3368 */
3369 if (!xl->sched_started)
3370 raw_spin_lock(&excl_cntrs->lock);
3371
3372 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
3373
3374 if (!xl->sched_started)
3375 raw_spin_unlock(&excl_cntrs->lock);
3376 }
3377 }
3378
3379 static void
intel_put_shared_regs_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3380 intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
3381 struct perf_event *event)
3382 {
3383 struct hw_perf_event_extra *reg;
3384
3385 reg = &event->hw.extra_reg;
3386 if (reg->idx != EXTRA_REG_NONE)
3387 __intel_shared_reg_put_constraints(cpuc, reg);
3388
3389 reg = &event->hw.branch_reg;
3390 if (reg->idx != EXTRA_REG_NONE)
3391 __intel_shared_reg_put_constraints(cpuc, reg);
3392 }
3393
intel_put_event_constraints(struct cpu_hw_events * cpuc,struct perf_event * event)3394 static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
3395 struct perf_event *event)
3396 {
3397 intel_put_shared_regs_event_constraints(cpuc, event);
3398
3399 /*
3400 * is PMU has exclusive counter restrictions, then
3401 * all events are subject to and must call the
3402 * put_excl_constraints() routine
3403 */
3404 if (cpuc->excl_cntrs)
3405 intel_put_excl_constraints(cpuc, event);
3406 }
3407
intel_pebs_aliases_core2(struct perf_event * event)3408 static void intel_pebs_aliases_core2(struct perf_event *event)
3409 {
3410 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3411 /*
3412 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3413 * (0x003c) so that we can use it with PEBS.
3414 *
3415 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3416 * PEBS capable. However we can use INST_RETIRED.ANY_P
3417 * (0x00c0), which is a PEBS capable event, to get the same
3418 * count.
3419 *
3420 * INST_RETIRED.ANY_P counts the number of cycles that retires
3421 * CNTMASK instructions. By setting CNTMASK to a value (16)
3422 * larger than the maximum number of instructions that can be
3423 * retired per cycle (4) and then inverting the condition, we
3424 * count all cycles that retire 16 or less instructions, which
3425 * is every cycle.
3426 *
3427 * Thereby we gain a PEBS capable cycle counter.
3428 */
3429 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
3430
3431 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3432 event->hw.config = alt_config;
3433 }
3434 }
3435
intel_pebs_aliases_snb(struct perf_event * event)3436 static void intel_pebs_aliases_snb(struct perf_event *event)
3437 {
3438 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3439 /*
3440 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3441 * (0x003c) so that we can use it with PEBS.
3442 *
3443 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3444 * PEBS capable. However we can use UOPS_RETIRED.ALL
3445 * (0x01c2), which is a PEBS capable event, to get the same
3446 * count.
3447 *
3448 * UOPS_RETIRED.ALL counts the number of cycles that retires
3449 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
3450 * larger than the maximum number of micro-ops that can be
3451 * retired per cycle (4) and then inverting the condition, we
3452 * count all cycles that retire 16 or less micro-ops, which
3453 * is every cycle.
3454 *
3455 * Thereby we gain a PEBS capable cycle counter.
3456 */
3457 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
3458
3459 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3460 event->hw.config = alt_config;
3461 }
3462 }
3463
intel_pebs_aliases_precdist(struct perf_event * event)3464 static void intel_pebs_aliases_precdist(struct perf_event *event)
3465 {
3466 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
3467 /*
3468 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
3469 * (0x003c) so that we can use it with PEBS.
3470 *
3471 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
3472 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
3473 * (0x01c0), which is a PEBS capable event, to get the same
3474 * count.
3475 *
3476 * The PREC_DIST event has special support to minimize sample
3477 * shadowing effects. One drawback is that it can be
3478 * only programmed on counter 1, but that seems like an
3479 * acceptable trade off.
3480 */
3481 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
3482
3483 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
3484 event->hw.config = alt_config;
3485 }
3486 }
3487
intel_pebs_aliases_ivb(struct perf_event * event)3488 static void intel_pebs_aliases_ivb(struct perf_event *event)
3489 {
3490 if (event->attr.precise_ip < 3)
3491 return intel_pebs_aliases_snb(event);
3492 return intel_pebs_aliases_precdist(event);
3493 }
3494
intel_pebs_aliases_skl(struct perf_event * event)3495 static void intel_pebs_aliases_skl(struct perf_event *event)
3496 {
3497 if (event->attr.precise_ip < 3)
3498 return intel_pebs_aliases_core2(event);
3499 return intel_pebs_aliases_precdist(event);
3500 }
3501
intel_pmu_large_pebs_flags(struct perf_event * event)3502 static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
3503 {
3504 unsigned long flags = x86_pmu.large_pebs_flags;
3505
3506 if (event->attr.use_clockid)
3507 flags &= ~PERF_SAMPLE_TIME;
3508 if (!event->attr.exclude_kernel)
3509 flags &= ~PERF_SAMPLE_REGS_USER;
3510 if (event->attr.sample_regs_user & ~PEBS_GP_REGS)
3511 flags &= ~(PERF_SAMPLE_REGS_USER | PERF_SAMPLE_REGS_INTR);
3512 return flags;
3513 }
3514
intel_pmu_bts_config(struct perf_event * event)3515 static int intel_pmu_bts_config(struct perf_event *event)
3516 {
3517 struct perf_event_attr *attr = &event->attr;
3518
3519 if (unlikely(intel_pmu_has_bts(event))) {
3520 /* BTS is not supported by this architecture. */
3521 if (!x86_pmu.bts_active)
3522 return -EOPNOTSUPP;
3523
3524 /* BTS is currently only allowed for user-mode. */
3525 if (!attr->exclude_kernel)
3526 return -EOPNOTSUPP;
3527
3528 /* BTS is not allowed for precise events. */
3529 if (attr->precise_ip)
3530 return -EOPNOTSUPP;
3531
3532 /* disallow bts if conflicting events are present */
3533 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3534 return -EBUSY;
3535
3536 event->destroy = hw_perf_lbr_event_destroy;
3537 }
3538
3539 return 0;
3540 }
3541
core_pmu_hw_config(struct perf_event * event)3542 static int core_pmu_hw_config(struct perf_event *event)
3543 {
3544 int ret = x86_pmu_hw_config(event);
3545
3546 if (ret)
3547 return ret;
3548
3549 return intel_pmu_bts_config(event);
3550 }
3551
intel_pmu_hw_config(struct perf_event * event)3552 static int intel_pmu_hw_config(struct perf_event *event)
3553 {
3554 int ret = x86_pmu_hw_config(event);
3555
3556 if (ret)
3557 return ret;
3558
3559 ret = intel_pmu_bts_config(event);
3560 if (ret)
3561 return ret;
3562
3563 if (event->attr.precise_ip) {
3564 if (!(event->attr.freq || (event->attr.wakeup_events && !event->attr.watermark))) {
3565 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
3566 if (!(event->attr.sample_type &
3567 ~intel_pmu_large_pebs_flags(event)))
3568 event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
3569 }
3570 if (x86_pmu.pebs_aliases)
3571 x86_pmu.pebs_aliases(event);
3572
3573 if (event->attr.sample_type & PERF_SAMPLE_CALLCHAIN)
3574 event->attr.sample_type |= __PERF_SAMPLE_CALLCHAIN_EARLY;
3575 }
3576
3577 if (needs_branch_stack(event)) {
3578 ret = intel_pmu_setup_lbr_filter(event);
3579 if (ret)
3580 return ret;
3581
3582 /*
3583 * BTS is set up earlier in this path, so don't account twice
3584 */
3585 if (!unlikely(intel_pmu_has_bts(event))) {
3586 /* disallow lbr if conflicting events are present */
3587 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
3588 return -EBUSY;
3589
3590 event->destroy = hw_perf_lbr_event_destroy;
3591 }
3592 }
3593
3594 if (event->attr.aux_output) {
3595 if (!event->attr.precise_ip)
3596 return -EINVAL;
3597
3598 event->hw.flags |= PERF_X86_EVENT_PEBS_VIA_PT;
3599 }
3600
3601 if (event->attr.type != PERF_TYPE_RAW)
3602 return 0;
3603
3604 /*
3605 * Config Topdown slots and metric events
3606 *
3607 * The slots event on Fixed Counter 3 can support sampling,
3608 * which will be handled normally in x86_perf_event_update().
3609 *
3610 * Metric events don't support sampling and require being paired
3611 * with a slots event as group leader. When the slots event
3612 * is used in a metrics group, it too cannot support sampling.
3613 */
3614 if (x86_pmu.intel_cap.perf_metrics && is_topdown_event(event)) {
3615 if (event->attr.config1 || event->attr.config2)
3616 return -EINVAL;
3617
3618 /*
3619 * The TopDown metrics events and slots event don't
3620 * support any filters.
3621 */
3622 if (event->attr.config & X86_ALL_EVENT_FLAGS)
3623 return -EINVAL;
3624
3625 if (is_metric_event(event)) {
3626 struct perf_event *leader = event->group_leader;
3627
3628 /* The metric events don't support sampling. */
3629 if (is_sampling_event(event))
3630 return -EINVAL;
3631
3632 /* The metric events require a slots group leader. */
3633 if (!is_slots_event(leader))
3634 return -EINVAL;
3635
3636 /*
3637 * The leader/SLOTS must not be a sampling event for
3638 * metric use; hardware requires it starts at 0 when used
3639 * in conjunction with MSR_PERF_METRICS.
3640 */
3641 if (is_sampling_event(leader))
3642 return -EINVAL;
3643
3644 event->event_caps |= PERF_EV_CAP_SIBLING;
3645 /*
3646 * Only once we have a METRICs sibling do we
3647 * need TopDown magic.
3648 */
3649 leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3650 event->hw.flags |= PERF_X86_EVENT_TOPDOWN;
3651 }
3652 }
3653
3654 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
3655 return 0;
3656
3657 if (x86_pmu.version < 3)
3658 return -EINVAL;
3659
3660 ret = perf_allow_cpu(&event->attr);
3661 if (ret)
3662 return ret;
3663
3664 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
3665
3666 return 0;
3667 }
3668
3669 #ifdef CONFIG_RETPOLINE
3670 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr);
3671 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr);
3672 #endif
3673
perf_guest_get_msrs(int * nr)3674 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
3675 {
3676 #ifdef CONFIG_RETPOLINE
3677 if (x86_pmu.guest_get_msrs == intel_guest_get_msrs)
3678 return intel_guest_get_msrs(nr);
3679 else if (x86_pmu.guest_get_msrs == core_guest_get_msrs)
3680 return core_guest_get_msrs(nr);
3681 #endif
3682 if (x86_pmu.guest_get_msrs)
3683 return x86_pmu.guest_get_msrs(nr);
3684 *nr = 0;
3685 return NULL;
3686 }
3687 EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
3688
intel_guest_get_msrs(int * nr)3689 static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
3690 {
3691 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3692 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3693
3694 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
3695 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
3696 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
3697 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
3698 arr[0].guest &= ~cpuc->pebs_enabled;
3699 else
3700 arr[0].guest &= ~(cpuc->pebs_enabled & PEBS_COUNTER_MASK);
3701 *nr = 1;
3702
3703 if (x86_pmu.pebs && x86_pmu.pebs_no_isolation) {
3704 /*
3705 * If PMU counter has PEBS enabled it is not enough to
3706 * disable counter on a guest entry since PEBS memory
3707 * write can overshoot guest entry and corrupt guest
3708 * memory. Disabling PEBS solves the problem.
3709 *
3710 * Don't do this if the CPU already enforces it.
3711 */
3712 arr[1].msr = MSR_IA32_PEBS_ENABLE;
3713 arr[1].host = cpuc->pebs_enabled;
3714 arr[1].guest = 0;
3715 *nr = 2;
3716 }
3717
3718 return arr;
3719 }
3720
core_guest_get_msrs(int * nr)3721 static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
3722 {
3723 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3724 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
3725 int idx;
3726
3727 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3728 struct perf_event *event = cpuc->events[idx];
3729
3730 arr[idx].msr = x86_pmu_config_addr(idx);
3731 arr[idx].host = arr[idx].guest = 0;
3732
3733 if (!test_bit(idx, cpuc->active_mask))
3734 continue;
3735
3736 arr[idx].host = arr[idx].guest =
3737 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
3738
3739 if (event->attr.exclude_host)
3740 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3741 else if (event->attr.exclude_guest)
3742 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
3743 }
3744
3745 *nr = x86_pmu.num_counters;
3746 return arr;
3747 }
3748
core_pmu_enable_event(struct perf_event * event)3749 static void core_pmu_enable_event(struct perf_event *event)
3750 {
3751 if (!event->attr.exclude_host)
3752 x86_pmu_enable_event(event);
3753 }
3754
core_pmu_enable_all(int added)3755 static void core_pmu_enable_all(int added)
3756 {
3757 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
3758 int idx;
3759
3760 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
3761 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
3762
3763 if (!test_bit(idx, cpuc->active_mask) ||
3764 cpuc->events[idx]->attr.exclude_host)
3765 continue;
3766
3767 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
3768 }
3769 }
3770
hsw_hw_config(struct perf_event * event)3771 static int hsw_hw_config(struct perf_event *event)
3772 {
3773 int ret = intel_pmu_hw_config(event);
3774
3775 if (ret)
3776 return ret;
3777 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
3778 return 0;
3779 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
3780
3781 /*
3782 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
3783 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
3784 * this combination.
3785 */
3786 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
3787 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
3788 event->attr.precise_ip > 0))
3789 return -EOPNOTSUPP;
3790
3791 if (event_is_checkpointed(event)) {
3792 /*
3793 * Sampling of checkpointed events can cause situations where
3794 * the CPU constantly aborts because of a overflow, which is
3795 * then checkpointed back and ignored. Forbid checkpointing
3796 * for sampling.
3797 *
3798 * But still allow a long sampling period, so that perf stat
3799 * from KVM works.
3800 */
3801 if (event->attr.sample_period > 0 &&
3802 event->attr.sample_period < 0x7fffffff)
3803 return -EOPNOTSUPP;
3804 }
3805 return 0;
3806 }
3807
3808 static struct event_constraint counter0_constraint =
3809 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1);
3810
3811 static struct event_constraint counter2_constraint =
3812 EVENT_CONSTRAINT(0, 0x4, 0);
3813
3814 static struct event_constraint fixed0_constraint =
3815 FIXED_EVENT_CONSTRAINT(0x00c0, 0);
3816
3817 static struct event_constraint fixed0_counter0_constraint =
3818 INTEL_ALL_EVENT_CONSTRAINT(0, 0x100000001ULL);
3819
3820 static struct event_constraint *
hsw_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3821 hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3822 struct perf_event *event)
3823 {
3824 struct event_constraint *c;
3825
3826 c = intel_get_event_constraints(cpuc, idx, event);
3827
3828 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
3829 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
3830 if (c->idxmsk64 & (1U << 2))
3831 return &counter2_constraint;
3832 return &emptyconstraint;
3833 }
3834
3835 return c;
3836 }
3837
3838 static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3839 icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3840 struct perf_event *event)
3841 {
3842 /*
3843 * Fixed counter 0 has less skid.
3844 * Force instruction:ppp in Fixed counter 0
3845 */
3846 if ((event->attr.precise_ip == 3) &&
3847 constraint_match(&fixed0_constraint, event->hw.config))
3848 return &fixed0_constraint;
3849
3850 return hsw_get_event_constraints(cpuc, idx, event);
3851 }
3852
3853 static struct event_constraint *
glp_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3854 glp_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3855 struct perf_event *event)
3856 {
3857 struct event_constraint *c;
3858
3859 /* :ppp means to do reduced skid PEBS which is PMC0 only. */
3860 if (event->attr.precise_ip == 3)
3861 return &counter0_constraint;
3862
3863 c = intel_get_event_constraints(cpuc, idx, event);
3864
3865 return c;
3866 }
3867
3868 static struct event_constraint *
tnt_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3869 tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3870 struct perf_event *event)
3871 {
3872 struct event_constraint *c;
3873
3874 /*
3875 * :ppp means to do reduced skid PEBS,
3876 * which is available on PMC0 and fixed counter 0.
3877 */
3878 if (event->attr.precise_ip == 3) {
3879 /* Force instruction:ppp on PMC0 and Fixed counter 0 */
3880 if (constraint_match(&fixed0_constraint, event->hw.config))
3881 return &fixed0_counter0_constraint;
3882
3883 return &counter0_constraint;
3884 }
3885
3886 c = intel_get_event_constraints(cpuc, idx, event);
3887
3888 return c;
3889 }
3890
3891 static bool allow_tsx_force_abort = true;
3892
3893 static struct event_constraint *
tfa_get_event_constraints(struct cpu_hw_events * cpuc,int idx,struct perf_event * event)3894 tfa_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
3895 struct perf_event *event)
3896 {
3897 struct event_constraint *c = hsw_get_event_constraints(cpuc, idx, event);
3898
3899 /*
3900 * Without TFA we must not use PMC3.
3901 */
3902 if (!allow_tsx_force_abort && test_bit(3, c->idxmsk)) {
3903 c = dyn_constraint(cpuc, c, idx);
3904 c->idxmsk64 &= ~(1ULL << 3);
3905 c->weight--;
3906 }
3907
3908 return c;
3909 }
3910
3911 /*
3912 * Broadwell:
3913 *
3914 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3915 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3916 * the two to enforce a minimum period of 128 (the smallest value that has bits
3917 * 0-5 cleared and >= 100).
3918 *
3919 * Because of how the code in x86_perf_event_set_period() works, the truncation
3920 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3921 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3922 *
3923 * Therefore the effective (average) period matches the requested period,
3924 * despite coarser hardware granularity.
3925 */
bdw_limit_period(struct perf_event * event,u64 left)3926 static u64 bdw_limit_period(struct perf_event *event, u64 left)
3927 {
3928 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3929 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3930 if (left < 128)
3931 left = 128;
3932 left &= ~0x3fULL;
3933 }
3934 return left;
3935 }
3936
nhm_limit_period(struct perf_event * event,u64 left)3937 static u64 nhm_limit_period(struct perf_event *event, u64 left)
3938 {
3939 return max(left, 32ULL);
3940 }
3941
3942 PMU_FORMAT_ATTR(event, "config:0-7" );
3943 PMU_FORMAT_ATTR(umask, "config:8-15" );
3944 PMU_FORMAT_ATTR(edge, "config:18" );
3945 PMU_FORMAT_ATTR(pc, "config:19" );
3946 PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3947 PMU_FORMAT_ATTR(inv, "config:23" );
3948 PMU_FORMAT_ATTR(cmask, "config:24-31" );
3949 PMU_FORMAT_ATTR(in_tx, "config:32");
3950 PMU_FORMAT_ATTR(in_tx_cp, "config:33");
3951
3952 static struct attribute *intel_arch_formats_attr[] = {
3953 &format_attr_event.attr,
3954 &format_attr_umask.attr,
3955 &format_attr_edge.attr,
3956 &format_attr_pc.attr,
3957 &format_attr_inv.attr,
3958 &format_attr_cmask.attr,
3959 NULL,
3960 };
3961
intel_event_sysfs_show(char * page,u64 config)3962 ssize_t intel_event_sysfs_show(char *page, u64 config)
3963 {
3964 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3965
3966 return x86_event_sysfs_show(page, config, event);
3967 }
3968
allocate_shared_regs(int cpu)3969 static struct intel_shared_regs *allocate_shared_regs(int cpu)
3970 {
3971 struct intel_shared_regs *regs;
3972 int i;
3973
3974 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3975 GFP_KERNEL, cpu_to_node(cpu));
3976 if (regs) {
3977 /*
3978 * initialize the locks to keep lockdep happy
3979 */
3980 for (i = 0; i < EXTRA_REG_MAX; i++)
3981 raw_spin_lock_init(®s->regs[i].lock);
3982
3983 regs->core_id = -1;
3984 }
3985 return regs;
3986 }
3987
allocate_excl_cntrs(int cpu)3988 static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3989 {
3990 struct intel_excl_cntrs *c;
3991
3992 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3993 GFP_KERNEL, cpu_to_node(cpu));
3994 if (c) {
3995 raw_spin_lock_init(&c->lock);
3996 c->core_id = -1;
3997 }
3998 return c;
3999 }
4000
4001
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)4002 int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
4003 {
4004 cpuc->pebs_record_size = x86_pmu.pebs_record_size;
4005
4006 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
4007 cpuc->shared_regs = allocate_shared_regs(cpu);
4008 if (!cpuc->shared_regs)
4009 goto err;
4010 }
4011
4012 if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) {
4013 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
4014
4015 cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu));
4016 if (!cpuc->constraint_list)
4017 goto err_shared_regs;
4018 }
4019
4020 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4021 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
4022 if (!cpuc->excl_cntrs)
4023 goto err_constraint_list;
4024
4025 cpuc->excl_thread_id = 0;
4026 }
4027
4028 return 0;
4029
4030 err_constraint_list:
4031 kfree(cpuc->constraint_list);
4032 cpuc->constraint_list = NULL;
4033
4034 err_shared_regs:
4035 kfree(cpuc->shared_regs);
4036 cpuc->shared_regs = NULL;
4037
4038 err:
4039 return -ENOMEM;
4040 }
4041
intel_pmu_cpu_prepare(int cpu)4042 static int intel_pmu_cpu_prepare(int cpu)
4043 {
4044 return intel_cpuc_prepare(&per_cpu(cpu_hw_events, cpu), cpu);
4045 }
4046
flip_smm_bit(void * data)4047 static void flip_smm_bit(void *data)
4048 {
4049 unsigned long set = *(unsigned long *)data;
4050
4051 if (set > 0) {
4052 msr_set_bit(MSR_IA32_DEBUGCTLMSR,
4053 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4054 } else {
4055 msr_clear_bit(MSR_IA32_DEBUGCTLMSR,
4056 DEBUGCTLMSR_FREEZE_IN_SMM_BIT);
4057 }
4058 }
4059
intel_pmu_cpu_starting(int cpu)4060 static void intel_pmu_cpu_starting(int cpu)
4061 {
4062 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
4063 int core_id = topology_core_id(cpu);
4064 int i;
4065
4066 init_debug_store_on_cpu(cpu);
4067 /*
4068 * Deal with CPUs that don't clear their LBRs on power-up.
4069 */
4070 intel_pmu_lbr_reset();
4071
4072 cpuc->lbr_sel = NULL;
4073
4074 if (x86_pmu.flags & PMU_FL_TFA) {
4075 WARN_ON_ONCE(cpuc->tfa_shadow);
4076 cpuc->tfa_shadow = ~0ULL;
4077 intel_set_tfa(cpuc, false);
4078 }
4079
4080 if (x86_pmu.version > 1)
4081 flip_smm_bit(&x86_pmu.attr_freeze_on_smi);
4082
4083 if (x86_pmu.counter_freezing)
4084 enable_counter_freeze();
4085
4086 /* Disable perf metrics if any added CPU doesn't support it. */
4087 if (x86_pmu.intel_cap.perf_metrics) {
4088 union perf_capabilities perf_cap;
4089
4090 rdmsrl(MSR_IA32_PERF_CAPABILITIES, perf_cap.capabilities);
4091 if (!perf_cap.perf_metrics) {
4092 x86_pmu.intel_cap.perf_metrics = 0;
4093 x86_pmu.intel_ctrl &= ~(1ULL << GLOBAL_CTRL_EN_PERF_METRICS);
4094 }
4095 }
4096
4097 if (!cpuc->shared_regs)
4098 return;
4099
4100 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
4101 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4102 struct intel_shared_regs *pc;
4103
4104 pc = per_cpu(cpu_hw_events, i).shared_regs;
4105 if (pc && pc->core_id == core_id) {
4106 cpuc->kfree_on_online[0] = cpuc->shared_regs;
4107 cpuc->shared_regs = pc;
4108 break;
4109 }
4110 }
4111 cpuc->shared_regs->core_id = core_id;
4112 cpuc->shared_regs->refcnt++;
4113 }
4114
4115 if (x86_pmu.lbr_sel_map)
4116 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
4117
4118 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
4119 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
4120 struct cpu_hw_events *sibling;
4121 struct intel_excl_cntrs *c;
4122
4123 sibling = &per_cpu(cpu_hw_events, i);
4124 c = sibling->excl_cntrs;
4125 if (c && c->core_id == core_id) {
4126 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
4127 cpuc->excl_cntrs = c;
4128 if (!sibling->excl_thread_id)
4129 cpuc->excl_thread_id = 1;
4130 break;
4131 }
4132 }
4133 cpuc->excl_cntrs->core_id = core_id;
4134 cpuc->excl_cntrs->refcnt++;
4135 }
4136 }
4137
free_excl_cntrs(struct cpu_hw_events * cpuc)4138 static void free_excl_cntrs(struct cpu_hw_events *cpuc)
4139 {
4140 struct intel_excl_cntrs *c;
4141
4142 c = cpuc->excl_cntrs;
4143 if (c) {
4144 if (c->core_id == -1 || --c->refcnt == 0)
4145 kfree(c);
4146 cpuc->excl_cntrs = NULL;
4147 }
4148
4149 kfree(cpuc->constraint_list);
4150 cpuc->constraint_list = NULL;
4151 }
4152
intel_pmu_cpu_dying(int cpu)4153 static void intel_pmu_cpu_dying(int cpu)
4154 {
4155 fini_debug_store_on_cpu(cpu);
4156
4157 if (x86_pmu.counter_freezing)
4158 disable_counter_freeze();
4159 }
4160
intel_cpuc_finish(struct cpu_hw_events * cpuc)4161 void intel_cpuc_finish(struct cpu_hw_events *cpuc)
4162 {
4163 struct intel_shared_regs *pc;
4164
4165 pc = cpuc->shared_regs;
4166 if (pc) {
4167 if (pc->core_id == -1 || --pc->refcnt == 0)
4168 kfree(pc);
4169 cpuc->shared_regs = NULL;
4170 }
4171
4172 free_excl_cntrs(cpuc);
4173 }
4174
intel_pmu_cpu_dead(int cpu)4175 static void intel_pmu_cpu_dead(int cpu)
4176 {
4177 intel_cpuc_finish(&per_cpu(cpu_hw_events, cpu));
4178 }
4179
intel_pmu_sched_task(struct perf_event_context * ctx,bool sched_in)4180 static void intel_pmu_sched_task(struct perf_event_context *ctx,
4181 bool sched_in)
4182 {
4183 intel_pmu_pebs_sched_task(ctx, sched_in);
4184 intel_pmu_lbr_sched_task(ctx, sched_in);
4185 }
4186
intel_pmu_swap_task_ctx(struct perf_event_context * prev,struct perf_event_context * next)4187 static void intel_pmu_swap_task_ctx(struct perf_event_context *prev,
4188 struct perf_event_context *next)
4189 {
4190 intel_pmu_lbr_swap_task_ctx(prev, next);
4191 }
4192
intel_pmu_check_period(struct perf_event * event,u64 value)4193 static int intel_pmu_check_period(struct perf_event *event, u64 value)
4194 {
4195 return intel_pmu_has_bts_period(event, value) ? -EINVAL : 0;
4196 }
4197
intel_pmu_aux_output_match(struct perf_event * event)4198 static int intel_pmu_aux_output_match(struct perf_event *event)
4199 {
4200 if (!x86_pmu.intel_cap.pebs_output_pt_available)
4201 return 0;
4202
4203 return is_intel_pt_event(event);
4204 }
4205
4206 PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
4207
4208 PMU_FORMAT_ATTR(ldlat, "config1:0-15");
4209
4210 PMU_FORMAT_ATTR(frontend, "config1:0-23");
4211
4212 static struct attribute *intel_arch3_formats_attr[] = {
4213 &format_attr_event.attr,
4214 &format_attr_umask.attr,
4215 &format_attr_edge.attr,
4216 &format_attr_pc.attr,
4217 &format_attr_any.attr,
4218 &format_attr_inv.attr,
4219 &format_attr_cmask.attr,
4220 NULL,
4221 };
4222
4223 static struct attribute *hsw_format_attr[] = {
4224 &format_attr_in_tx.attr,
4225 &format_attr_in_tx_cp.attr,
4226 &format_attr_offcore_rsp.attr,
4227 &format_attr_ldlat.attr,
4228 NULL
4229 };
4230
4231 static struct attribute *nhm_format_attr[] = {
4232 &format_attr_offcore_rsp.attr,
4233 &format_attr_ldlat.attr,
4234 NULL
4235 };
4236
4237 static struct attribute *slm_format_attr[] = {
4238 &format_attr_offcore_rsp.attr,
4239 NULL
4240 };
4241
4242 static struct attribute *skl_format_attr[] = {
4243 &format_attr_frontend.attr,
4244 NULL,
4245 };
4246
4247 static __initconst const struct x86_pmu core_pmu = {
4248 .name = "core",
4249 .handle_irq = x86_pmu_handle_irq,
4250 .disable_all = x86_pmu_disable_all,
4251 .enable_all = core_pmu_enable_all,
4252 .enable = core_pmu_enable_event,
4253 .disable = x86_pmu_disable_event,
4254 .hw_config = core_pmu_hw_config,
4255 .schedule_events = x86_schedule_events,
4256 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4257 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4258 .event_map = intel_pmu_event_map,
4259 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4260 .apic = 1,
4261 .large_pebs_flags = LARGE_PEBS_FLAGS,
4262
4263 /*
4264 * Intel PMCs cannot be accessed sanely above 32-bit width,
4265 * so we install an artificial 1<<31 period regardless of
4266 * the generic event period:
4267 */
4268 .max_period = (1ULL<<31) - 1,
4269 .get_event_constraints = intel_get_event_constraints,
4270 .put_event_constraints = intel_put_event_constraints,
4271 .event_constraints = intel_core_event_constraints,
4272 .guest_get_msrs = core_guest_get_msrs,
4273 .format_attrs = intel_arch_formats_attr,
4274 .events_sysfs_show = intel_event_sysfs_show,
4275
4276 /*
4277 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
4278 * together with PMU version 1 and thus be using core_pmu with
4279 * shared_regs. We need following callbacks here to allocate
4280 * it properly.
4281 */
4282 .cpu_prepare = intel_pmu_cpu_prepare,
4283 .cpu_starting = intel_pmu_cpu_starting,
4284 .cpu_dying = intel_pmu_cpu_dying,
4285 .cpu_dead = intel_pmu_cpu_dead,
4286
4287 .check_period = intel_pmu_check_period,
4288
4289 .lbr_reset = intel_pmu_lbr_reset_64,
4290 .lbr_read = intel_pmu_lbr_read_64,
4291 .lbr_save = intel_pmu_lbr_save,
4292 .lbr_restore = intel_pmu_lbr_restore,
4293 };
4294
4295 static __initconst const struct x86_pmu intel_pmu = {
4296 .name = "Intel",
4297 .handle_irq = intel_pmu_handle_irq,
4298 .disable_all = intel_pmu_disable_all,
4299 .enable_all = intel_pmu_enable_all,
4300 .enable = intel_pmu_enable_event,
4301 .disable = intel_pmu_disable_event,
4302 .add = intel_pmu_add_event,
4303 .del = intel_pmu_del_event,
4304 .read = intel_pmu_read_event,
4305 .hw_config = intel_pmu_hw_config,
4306 .schedule_events = x86_schedule_events,
4307 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
4308 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
4309 .event_map = intel_pmu_event_map,
4310 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
4311 .apic = 1,
4312 .large_pebs_flags = LARGE_PEBS_FLAGS,
4313 /*
4314 * Intel PMCs cannot be accessed sanely above 32 bit width,
4315 * so we install an artificial 1<<31 period regardless of
4316 * the generic event period:
4317 */
4318 .max_period = (1ULL << 31) - 1,
4319 .get_event_constraints = intel_get_event_constraints,
4320 .put_event_constraints = intel_put_event_constraints,
4321 .pebs_aliases = intel_pebs_aliases_core2,
4322
4323 .format_attrs = intel_arch3_formats_attr,
4324 .events_sysfs_show = intel_event_sysfs_show,
4325
4326 .cpu_prepare = intel_pmu_cpu_prepare,
4327 .cpu_starting = intel_pmu_cpu_starting,
4328 .cpu_dying = intel_pmu_cpu_dying,
4329 .cpu_dead = intel_pmu_cpu_dead,
4330
4331 .guest_get_msrs = intel_guest_get_msrs,
4332 .sched_task = intel_pmu_sched_task,
4333 .swap_task_ctx = intel_pmu_swap_task_ctx,
4334
4335 .check_period = intel_pmu_check_period,
4336
4337 .aux_output_match = intel_pmu_aux_output_match,
4338
4339 .lbr_reset = intel_pmu_lbr_reset_64,
4340 .lbr_read = intel_pmu_lbr_read_64,
4341 .lbr_save = intel_pmu_lbr_save,
4342 .lbr_restore = intel_pmu_lbr_restore,
4343 };
4344
intel_clovertown_quirk(void)4345 static __init void intel_clovertown_quirk(void)
4346 {
4347 /*
4348 * PEBS is unreliable due to:
4349 *
4350 * AJ67 - PEBS may experience CPL leaks
4351 * AJ68 - PEBS PMI may be delayed by one event
4352 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
4353 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
4354 *
4355 * AJ67 could be worked around by restricting the OS/USR flags.
4356 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
4357 *
4358 * AJ106 could possibly be worked around by not allowing LBR
4359 * usage from PEBS, including the fixup.
4360 * AJ68 could possibly be worked around by always programming
4361 * a pebs_event_reset[0] value and coping with the lost events.
4362 *
4363 * But taken together it might just make sense to not enable PEBS on
4364 * these chips.
4365 */
4366 pr_warn("PEBS disabled due to CPU errata\n");
4367 x86_pmu.pebs = 0;
4368 x86_pmu.pebs_constraints = NULL;
4369 }
4370
4371 static const struct x86_cpu_desc isolation_ucodes[] = {
4372 INTEL_CPU_DESC(INTEL_FAM6_HASWELL, 3, 0x0000001f),
4373 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_L, 1, 0x0000001e),
4374 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_G, 1, 0x00000015),
4375 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 2, 0x00000037),
4376 INTEL_CPU_DESC(INTEL_FAM6_HASWELL_X, 4, 0x0000000a),
4377 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL, 4, 0x00000023),
4378 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_G, 1, 0x00000014),
4379 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 2, 0x00000010),
4380 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 3, 0x07000009),
4381 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 4, 0x0f000009),
4382 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_D, 5, 0x0e000002),
4383 INTEL_CPU_DESC(INTEL_FAM6_BROADWELL_X, 2, 0x0b000014),
4384 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 3, 0x00000021),
4385 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_X, 4, 0x00000000),
4386 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE_L, 3, 0x0000007c),
4387 INTEL_CPU_DESC(INTEL_FAM6_SKYLAKE, 3, 0x0000007c),
4388 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 9, 0x0000004e),
4389 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 9, 0x0000004e),
4390 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 10, 0x0000004e),
4391 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 11, 0x0000004e),
4392 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE_L, 12, 0x0000004e),
4393 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 10, 0x0000004e),
4394 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 11, 0x0000004e),
4395 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 12, 0x0000004e),
4396 INTEL_CPU_DESC(INTEL_FAM6_KABYLAKE, 13, 0x0000004e),
4397 {}
4398 };
4399
intel_check_pebs_isolation(void)4400 static void intel_check_pebs_isolation(void)
4401 {
4402 x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);
4403 }
4404
intel_pebs_isolation_quirk(void)4405 static __init void intel_pebs_isolation_quirk(void)
4406 {
4407 WARN_ON_ONCE(x86_pmu.check_microcode);
4408 x86_pmu.check_microcode = intel_check_pebs_isolation;
4409 intel_check_pebs_isolation();
4410 }
4411
4412 static const struct x86_cpu_desc pebs_ucodes[] = {
4413 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE, 7, 0x00000028),
4414 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 6, 0x00000618),
4415 INTEL_CPU_DESC(INTEL_FAM6_SANDYBRIDGE_X, 7, 0x0000070c),
4416 {}
4417 };
4418
intel_snb_pebs_broken(void)4419 static bool intel_snb_pebs_broken(void)
4420 {
4421 return !x86_cpu_has_min_microcode_rev(pebs_ucodes);
4422 }
4423
intel_snb_check_microcode(void)4424 static void intel_snb_check_microcode(void)
4425 {
4426 if (intel_snb_pebs_broken() == x86_pmu.pebs_broken)
4427 return;
4428
4429 /*
4430 * Serialized by the microcode lock..
4431 */
4432 if (x86_pmu.pebs_broken) {
4433 pr_info("PEBS enabled due to microcode update\n");
4434 x86_pmu.pebs_broken = 0;
4435 } else {
4436 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
4437 x86_pmu.pebs_broken = 1;
4438 }
4439 }
4440
is_lbr_from(unsigned long msr)4441 static bool is_lbr_from(unsigned long msr)
4442 {
4443 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
4444
4445 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
4446 }
4447
4448 /*
4449 * Under certain circumstances, access certain MSR may cause #GP.
4450 * The function tests if the input MSR can be safely accessed.
4451 */
check_msr(unsigned long msr,u64 mask)4452 static bool check_msr(unsigned long msr, u64 mask)
4453 {
4454 u64 val_old, val_new, val_tmp;
4455
4456 /*
4457 * Disable the check for real HW, so we don't
4458 * mess with potentionaly enabled registers:
4459 */
4460 if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
4461 return true;
4462
4463 /*
4464 * Read the current value, change it and read it back to see if it
4465 * matches, this is needed to detect certain hardware emulators
4466 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
4467 */
4468 if (rdmsrl_safe(msr, &val_old))
4469 return false;
4470
4471 /*
4472 * Only change the bits which can be updated by wrmsrl.
4473 */
4474 val_tmp = val_old ^ mask;
4475
4476 if (is_lbr_from(msr))
4477 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
4478
4479 if (wrmsrl_safe(msr, val_tmp) ||
4480 rdmsrl_safe(msr, &val_new))
4481 return false;
4482
4483 /*
4484 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
4485 * should equal rdmsrl()'s even with the quirk.
4486 */
4487 if (val_new != val_tmp)
4488 return false;
4489
4490 if (is_lbr_from(msr))
4491 val_old = lbr_from_signext_quirk_wr(val_old);
4492
4493 /* Here it's sure that the MSR can be safely accessed.
4494 * Restore the old value and return.
4495 */
4496 wrmsrl(msr, val_old);
4497
4498 return true;
4499 }
4500
intel_sandybridge_quirk(void)4501 static __init void intel_sandybridge_quirk(void)
4502 {
4503 x86_pmu.check_microcode = intel_snb_check_microcode;
4504 cpus_read_lock();
4505 intel_snb_check_microcode();
4506 cpus_read_unlock();
4507 }
4508
4509 static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
4510 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
4511 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
4512 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
4513 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
4514 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
4515 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
4516 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
4517 };
4518
intel_arch_events_quirk(void)4519 static __init void intel_arch_events_quirk(void)
4520 {
4521 int bit;
4522
4523 /* disable event that reported as not presend by cpuid */
4524 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
4525 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
4526 pr_warn("CPUID marked event: \'%s\' unavailable\n",
4527 intel_arch_events_map[bit].name);
4528 }
4529 }
4530
intel_nehalem_quirk(void)4531 static __init void intel_nehalem_quirk(void)
4532 {
4533 union cpuid10_ebx ebx;
4534
4535 ebx.full = x86_pmu.events_maskl;
4536 if (ebx.split.no_branch_misses_retired) {
4537 /*
4538 * Erratum AAJ80 detected, we work it around by using
4539 * the BR_MISP_EXEC.ANY event. This will over-count
4540 * branch-misses, but it's still much better than the
4541 * architectural event which is often completely bogus:
4542 */
4543 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
4544 ebx.split.no_branch_misses_retired = 0;
4545 x86_pmu.events_maskl = ebx.full;
4546 pr_info("CPU erratum AAJ80 worked around\n");
4547 }
4548 }
4549
4550 static const struct x86_cpu_desc counter_freezing_ucodes[] = {
4551 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
4552 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
4553 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
4554 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_D, 1, 0x00000028),
4555 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
4556 INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
4557 {}
4558 };
4559
intel_counter_freezing_broken(void)4560 static bool intel_counter_freezing_broken(void)
4561 {
4562 return !x86_cpu_has_min_microcode_rev(counter_freezing_ucodes);
4563 }
4564
intel_counter_freezing_quirk(void)4565 static __init void intel_counter_freezing_quirk(void)
4566 {
4567 /* Check if it's already disabled */
4568 if (disable_counter_freezing)
4569 return;
4570
4571 /*
4572 * If the system starts with the wrong ucode, leave the
4573 * counter-freezing feature permanently disabled.
4574 */
4575 if (intel_counter_freezing_broken()) {
4576 pr_info("PMU counter freezing disabled due to CPU errata,"
4577 "please upgrade microcode\n");
4578 x86_pmu.counter_freezing = false;
4579 x86_pmu.handle_irq = intel_pmu_handle_irq;
4580 }
4581 }
4582
4583 /*
4584 * enable software workaround for errata:
4585 * SNB: BJ122
4586 * IVB: BV98
4587 * HSW: HSD29
4588 *
4589 * Only needed when HT is enabled. However detecting
4590 * if HT is enabled is difficult (model specific). So instead,
4591 * we enable the workaround in the early boot, and verify if
4592 * it is needed in a later initcall phase once we have valid
4593 * topology information to check if HT is actually enabled
4594 */
intel_ht_bug(void)4595 static __init void intel_ht_bug(void)
4596 {
4597 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
4598
4599 x86_pmu.start_scheduling = intel_start_scheduling;
4600 x86_pmu.commit_scheduling = intel_commit_scheduling;
4601 x86_pmu.stop_scheduling = intel_stop_scheduling;
4602 }
4603
4604 EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
4605 EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
4606
4607 /* Haswell special events */
4608 EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
4609 EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
4610 EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
4611 EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
4612 EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
4613 EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
4614 EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
4615 EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
4616 EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
4617 EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
4618 EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
4619 EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4620
4621 static struct attribute *hsw_events_attrs[] = {
4622 EVENT_PTR(td_slots_issued),
4623 EVENT_PTR(td_slots_retired),
4624 EVENT_PTR(td_fetch_bubbles),
4625 EVENT_PTR(td_total_slots),
4626 EVENT_PTR(td_total_slots_scale),
4627 EVENT_PTR(td_recovery_bubbles),
4628 EVENT_PTR(td_recovery_bubbles_scale),
4629 NULL
4630 };
4631
4632 static struct attribute *hsw_mem_events_attrs[] = {
4633 EVENT_PTR(mem_ld_hsw),
4634 EVENT_PTR(mem_st_hsw),
4635 NULL,
4636 };
4637
4638 static struct attribute *hsw_tsx_events_attrs[] = {
4639 EVENT_PTR(tx_start),
4640 EVENT_PTR(tx_commit),
4641 EVENT_PTR(tx_abort),
4642 EVENT_PTR(tx_capacity),
4643 EVENT_PTR(tx_conflict),
4644 EVENT_PTR(el_start),
4645 EVENT_PTR(el_commit),
4646 EVENT_PTR(el_abort),
4647 EVENT_PTR(el_capacity),
4648 EVENT_PTR(el_conflict),
4649 EVENT_PTR(cycles_t),
4650 EVENT_PTR(cycles_ct),
4651 NULL
4652 };
4653
4654 EVENT_ATTR_STR(tx-capacity-read, tx_capacity_read, "event=0x54,umask=0x80");
4655 EVENT_ATTR_STR(tx-capacity-write, tx_capacity_write, "event=0x54,umask=0x2");
4656 EVENT_ATTR_STR(el-capacity-read, el_capacity_read, "event=0x54,umask=0x80");
4657 EVENT_ATTR_STR(el-capacity-write, el_capacity_write, "event=0x54,umask=0x2");
4658
4659 static struct attribute *icl_events_attrs[] = {
4660 EVENT_PTR(mem_ld_hsw),
4661 EVENT_PTR(mem_st_hsw),
4662 NULL,
4663 };
4664
4665 static struct attribute *icl_td_events_attrs[] = {
4666 EVENT_PTR(slots),
4667 EVENT_PTR(td_retiring),
4668 EVENT_PTR(td_bad_spec),
4669 EVENT_PTR(td_fe_bound),
4670 EVENT_PTR(td_be_bound),
4671 NULL,
4672 };
4673
4674 static struct attribute *icl_tsx_events_attrs[] = {
4675 EVENT_PTR(tx_start),
4676 EVENT_PTR(tx_abort),
4677 EVENT_PTR(tx_commit),
4678 EVENT_PTR(tx_capacity_read),
4679 EVENT_PTR(tx_capacity_write),
4680 EVENT_PTR(tx_conflict),
4681 EVENT_PTR(el_start),
4682 EVENT_PTR(el_abort),
4683 EVENT_PTR(el_commit),
4684 EVENT_PTR(el_capacity_read),
4685 EVENT_PTR(el_capacity_write),
4686 EVENT_PTR(el_conflict),
4687 EVENT_PTR(cycles_t),
4688 EVENT_PTR(cycles_ct),
4689 NULL,
4690 };
4691
freeze_on_smi_show(struct device * cdev,struct device_attribute * attr,char * buf)4692 static ssize_t freeze_on_smi_show(struct device *cdev,
4693 struct device_attribute *attr,
4694 char *buf)
4695 {
4696 return sprintf(buf, "%lu\n", x86_pmu.attr_freeze_on_smi);
4697 }
4698
4699 static DEFINE_MUTEX(freeze_on_smi_mutex);
4700
freeze_on_smi_store(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)4701 static ssize_t freeze_on_smi_store(struct device *cdev,
4702 struct device_attribute *attr,
4703 const char *buf, size_t count)
4704 {
4705 unsigned long val;
4706 ssize_t ret;
4707
4708 ret = kstrtoul(buf, 0, &val);
4709 if (ret)
4710 return ret;
4711
4712 if (val > 1)
4713 return -EINVAL;
4714
4715 mutex_lock(&freeze_on_smi_mutex);
4716
4717 if (x86_pmu.attr_freeze_on_smi == val)
4718 goto done;
4719
4720 x86_pmu.attr_freeze_on_smi = val;
4721
4722 get_online_cpus();
4723 on_each_cpu(flip_smm_bit, &val, 1);
4724 put_online_cpus();
4725 done:
4726 mutex_unlock(&freeze_on_smi_mutex);
4727
4728 return count;
4729 }
4730
update_tfa_sched(void * ignored)4731 static void update_tfa_sched(void *ignored)
4732 {
4733 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
4734
4735 /*
4736 * check if PMC3 is used
4737 * and if so force schedule out for all event types all contexts
4738 */
4739 if (test_bit(3, cpuc->active_mask))
4740 perf_pmu_resched(x86_get_pmu());
4741 }
4742
show_sysctl_tfa(struct device * cdev,struct device_attribute * attr,char * buf)4743 static ssize_t show_sysctl_tfa(struct device *cdev,
4744 struct device_attribute *attr,
4745 char *buf)
4746 {
4747 return snprintf(buf, 40, "%d\n", allow_tsx_force_abort);
4748 }
4749
set_sysctl_tfa(struct device * cdev,struct device_attribute * attr,const char * buf,size_t count)4750 static ssize_t set_sysctl_tfa(struct device *cdev,
4751 struct device_attribute *attr,
4752 const char *buf, size_t count)
4753 {
4754 bool val;
4755 ssize_t ret;
4756
4757 ret = kstrtobool(buf, &val);
4758 if (ret)
4759 return ret;
4760
4761 /* no change */
4762 if (val == allow_tsx_force_abort)
4763 return count;
4764
4765 allow_tsx_force_abort = val;
4766
4767 get_online_cpus();
4768 on_each_cpu(update_tfa_sched, NULL, 1);
4769 put_online_cpus();
4770
4771 return count;
4772 }
4773
4774
4775 static DEVICE_ATTR_RW(freeze_on_smi);
4776
branches_show(struct device * cdev,struct device_attribute * attr,char * buf)4777 static ssize_t branches_show(struct device *cdev,
4778 struct device_attribute *attr,
4779 char *buf)
4780 {
4781 return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu.lbr_nr);
4782 }
4783
4784 static DEVICE_ATTR_RO(branches);
4785
4786 static struct attribute *lbr_attrs[] = {
4787 &dev_attr_branches.attr,
4788 NULL
4789 };
4790
4791 static char pmu_name_str[30];
4792
pmu_name_show(struct device * cdev,struct device_attribute * attr,char * buf)4793 static ssize_t pmu_name_show(struct device *cdev,
4794 struct device_attribute *attr,
4795 char *buf)
4796 {
4797 return snprintf(buf, PAGE_SIZE, "%s\n", pmu_name_str);
4798 }
4799
4800 static DEVICE_ATTR_RO(pmu_name);
4801
4802 static struct attribute *intel_pmu_caps_attrs[] = {
4803 &dev_attr_pmu_name.attr,
4804 NULL
4805 };
4806
4807 static DEVICE_ATTR(allow_tsx_force_abort, 0644,
4808 show_sysctl_tfa,
4809 set_sysctl_tfa);
4810
4811 static struct attribute *intel_pmu_attrs[] = {
4812 &dev_attr_freeze_on_smi.attr,
4813 &dev_attr_allow_tsx_force_abort.attr,
4814 NULL,
4815 };
4816
4817 static umode_t
tsx_is_visible(struct kobject * kobj,struct attribute * attr,int i)4818 tsx_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4819 {
4820 return boot_cpu_has(X86_FEATURE_RTM) ? attr->mode : 0;
4821 }
4822
4823 static umode_t
pebs_is_visible(struct kobject * kobj,struct attribute * attr,int i)4824 pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4825 {
4826 return x86_pmu.pebs ? attr->mode : 0;
4827 }
4828
4829 static umode_t
lbr_is_visible(struct kobject * kobj,struct attribute * attr,int i)4830 lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4831 {
4832 return x86_pmu.lbr_nr ? attr->mode : 0;
4833 }
4834
4835 static umode_t
exra_is_visible(struct kobject * kobj,struct attribute * attr,int i)4836 exra_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4837 {
4838 return x86_pmu.version >= 2 ? attr->mode : 0;
4839 }
4840
4841 static umode_t
default_is_visible(struct kobject * kobj,struct attribute * attr,int i)4842 default_is_visible(struct kobject *kobj, struct attribute *attr, int i)
4843 {
4844 if (attr == &dev_attr_allow_tsx_force_abort.attr)
4845 return x86_pmu.flags & PMU_FL_TFA ? attr->mode : 0;
4846
4847 return attr->mode;
4848 }
4849
4850 static struct attribute_group group_events_td = {
4851 .name = "events",
4852 };
4853
4854 static struct attribute_group group_events_mem = {
4855 .name = "events",
4856 .is_visible = pebs_is_visible,
4857 };
4858
4859 static struct attribute_group group_events_tsx = {
4860 .name = "events",
4861 .is_visible = tsx_is_visible,
4862 };
4863
4864 static struct attribute_group group_caps_gen = {
4865 .name = "caps",
4866 .attrs = intel_pmu_caps_attrs,
4867 };
4868
4869 static struct attribute_group group_caps_lbr = {
4870 .name = "caps",
4871 .attrs = lbr_attrs,
4872 .is_visible = lbr_is_visible,
4873 };
4874
4875 static struct attribute_group group_format_extra = {
4876 .name = "format",
4877 .is_visible = exra_is_visible,
4878 };
4879
4880 static struct attribute_group group_format_extra_skl = {
4881 .name = "format",
4882 .is_visible = exra_is_visible,
4883 };
4884
4885 static struct attribute_group group_default = {
4886 .attrs = intel_pmu_attrs,
4887 .is_visible = default_is_visible,
4888 };
4889
4890 static const struct attribute_group *attr_update[] = {
4891 &group_events_td,
4892 &group_events_mem,
4893 &group_events_tsx,
4894 &group_caps_gen,
4895 &group_caps_lbr,
4896 &group_format_extra,
4897 &group_format_extra_skl,
4898 &group_default,
4899 NULL,
4900 };
4901
4902 static struct attribute *empty_attrs;
4903
intel_pmu_init(void)4904 __init int intel_pmu_init(void)
4905 {
4906 struct attribute **extra_skl_attr = &empty_attrs;
4907 struct attribute **extra_attr = &empty_attrs;
4908 struct attribute **td_attr = &empty_attrs;
4909 struct attribute **mem_attr = &empty_attrs;
4910 struct attribute **tsx_attr = &empty_attrs;
4911 union cpuid10_edx edx;
4912 union cpuid10_eax eax;
4913 union cpuid10_ebx ebx;
4914 struct event_constraint *c;
4915 unsigned int unused;
4916 struct extra_reg *er;
4917 bool pmem = false;
4918 int version, i;
4919 char *name;
4920
4921 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
4922 switch (boot_cpu_data.x86) {
4923 case 0x6:
4924 return p6_pmu_init();
4925 case 0xb:
4926 return knc_pmu_init();
4927 case 0xf:
4928 return p4_pmu_init();
4929 }
4930 return -ENODEV;
4931 }
4932
4933 /*
4934 * Check whether the Architectural PerfMon supports
4935 * Branch Misses Retired hw_event or not.
4936 */
4937 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
4938 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
4939 return -ENODEV;
4940
4941 version = eax.split.version_id;
4942 if (version < 2)
4943 x86_pmu = core_pmu;
4944 else
4945 x86_pmu = intel_pmu;
4946
4947 x86_pmu.version = version;
4948 x86_pmu.num_counters = eax.split.num_counters;
4949 x86_pmu.cntval_bits = eax.split.bit_width;
4950 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
4951
4952 x86_pmu.events_maskl = ebx.full;
4953 x86_pmu.events_mask_len = eax.split.mask_length;
4954
4955 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
4956
4957 /*
4958 * Quirk: v2 perfmon does not report fixed-purpose events, so
4959 * assume at least 3 events, when not running in a hypervisor:
4960 */
4961 if (version > 1) {
4962 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
4963
4964 x86_pmu.num_counters_fixed =
4965 max((int)edx.split.num_counters_fixed, assume);
4966 }
4967
4968 if (version >= 4)
4969 x86_pmu.counter_freezing = !disable_counter_freezing;
4970
4971 if (boot_cpu_has(X86_FEATURE_PDCM)) {
4972 u64 capabilities;
4973
4974 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
4975 x86_pmu.intel_cap.capabilities = capabilities;
4976 }
4977
4978 if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32) {
4979 x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
4980 x86_pmu.lbr_read = intel_pmu_lbr_read_32;
4981 }
4982
4983 if (boot_cpu_has(X86_FEATURE_ARCH_LBR))
4984 intel_pmu_arch_lbr_init();
4985
4986 intel_ds_init();
4987
4988 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
4989
4990 if (version >= 5) {
4991 x86_pmu.intel_cap.anythread_deprecated = edx.split.anythread_deprecated;
4992 if (x86_pmu.intel_cap.anythread_deprecated)
4993 pr_cont(" AnyThread deprecated, ");
4994 }
4995
4996 /*
4997 * Install the hw-cache-events table:
4998 */
4999 switch (boot_cpu_data.x86_model) {
5000 case INTEL_FAM6_CORE_YONAH:
5001 pr_cont("Core events, ");
5002 name = "core";
5003 break;
5004
5005 case INTEL_FAM6_CORE2_MEROM:
5006 x86_add_quirk(intel_clovertown_quirk);
5007 fallthrough;
5008
5009 case INTEL_FAM6_CORE2_MEROM_L:
5010 case INTEL_FAM6_CORE2_PENRYN:
5011 case INTEL_FAM6_CORE2_DUNNINGTON:
5012 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
5013 sizeof(hw_cache_event_ids));
5014
5015 intel_pmu_lbr_init_core();
5016
5017 x86_pmu.event_constraints = intel_core2_event_constraints;
5018 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
5019 pr_cont("Core2 events, ");
5020 name = "core2";
5021 break;
5022
5023 case INTEL_FAM6_NEHALEM:
5024 case INTEL_FAM6_NEHALEM_EP:
5025 case INTEL_FAM6_NEHALEM_EX:
5026 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
5027 sizeof(hw_cache_event_ids));
5028 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5029 sizeof(hw_cache_extra_regs));
5030
5031 intel_pmu_lbr_init_nhm();
5032
5033 x86_pmu.event_constraints = intel_nehalem_event_constraints;
5034 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
5035 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5036 x86_pmu.extra_regs = intel_nehalem_extra_regs;
5037 x86_pmu.limit_period = nhm_limit_period;
5038
5039 mem_attr = nhm_mem_events_attrs;
5040
5041 /* UOPS_ISSUED.STALLED_CYCLES */
5042 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5043 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5044 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5045 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5046 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5047
5048 intel_pmu_pebs_data_source_nhm();
5049 x86_add_quirk(intel_nehalem_quirk);
5050 x86_pmu.pebs_no_tlb = 1;
5051 extra_attr = nhm_format_attr;
5052
5053 pr_cont("Nehalem events, ");
5054 name = "nehalem";
5055 break;
5056
5057 case INTEL_FAM6_ATOM_BONNELL:
5058 case INTEL_FAM6_ATOM_BONNELL_MID:
5059 case INTEL_FAM6_ATOM_SALTWELL:
5060 case INTEL_FAM6_ATOM_SALTWELL_MID:
5061 case INTEL_FAM6_ATOM_SALTWELL_TABLET:
5062 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
5063 sizeof(hw_cache_event_ids));
5064
5065 intel_pmu_lbr_init_atom();
5066
5067 x86_pmu.event_constraints = intel_gen_event_constraints;
5068 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
5069 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
5070 pr_cont("Atom events, ");
5071 name = "bonnell";
5072 break;
5073
5074 case INTEL_FAM6_ATOM_SILVERMONT:
5075 case INTEL_FAM6_ATOM_SILVERMONT_D:
5076 case INTEL_FAM6_ATOM_SILVERMONT_MID:
5077 case INTEL_FAM6_ATOM_AIRMONT:
5078 case INTEL_FAM6_ATOM_AIRMONT_MID:
5079 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
5080 sizeof(hw_cache_event_ids));
5081 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
5082 sizeof(hw_cache_extra_regs));
5083
5084 intel_pmu_lbr_init_slm();
5085
5086 x86_pmu.event_constraints = intel_slm_event_constraints;
5087 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5088 x86_pmu.extra_regs = intel_slm_extra_regs;
5089 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5090 td_attr = slm_events_attrs;
5091 extra_attr = slm_format_attr;
5092 pr_cont("Silvermont events, ");
5093 name = "silvermont";
5094 break;
5095
5096 case INTEL_FAM6_ATOM_GOLDMONT:
5097 case INTEL_FAM6_ATOM_GOLDMONT_D:
5098 x86_add_quirk(intel_counter_freezing_quirk);
5099 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
5100 sizeof(hw_cache_event_ids));
5101 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
5102 sizeof(hw_cache_extra_regs));
5103
5104 intel_pmu_lbr_init_skl();
5105
5106 x86_pmu.event_constraints = intel_slm_event_constraints;
5107 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
5108 x86_pmu.extra_regs = intel_glm_extra_regs;
5109 /*
5110 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5111 * for precise cycles.
5112 * :pp is identical to :ppp
5113 */
5114 x86_pmu.pebs_aliases = NULL;
5115 x86_pmu.pebs_prec_dist = true;
5116 x86_pmu.lbr_pt_coexist = true;
5117 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5118 td_attr = glm_events_attrs;
5119 extra_attr = slm_format_attr;
5120 pr_cont("Goldmont events, ");
5121 name = "goldmont";
5122 break;
5123
5124 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5125 x86_add_quirk(intel_counter_freezing_quirk);
5126 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5127 sizeof(hw_cache_event_ids));
5128 memcpy(hw_cache_extra_regs, glp_hw_cache_extra_regs,
5129 sizeof(hw_cache_extra_regs));
5130
5131 intel_pmu_lbr_init_skl();
5132
5133 x86_pmu.event_constraints = intel_slm_event_constraints;
5134 x86_pmu.extra_regs = intel_glm_extra_regs;
5135 /*
5136 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5137 * for precise cycles.
5138 */
5139 x86_pmu.pebs_aliases = NULL;
5140 x86_pmu.pebs_prec_dist = true;
5141 x86_pmu.lbr_pt_coexist = true;
5142 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5143 x86_pmu.flags |= PMU_FL_PEBS_ALL;
5144 x86_pmu.get_event_constraints = glp_get_event_constraints;
5145 td_attr = glm_events_attrs;
5146 /* Goldmont Plus has 4-wide pipeline */
5147 event_attr_td_total_slots_scale_glm.event_str = "4";
5148 extra_attr = slm_format_attr;
5149 pr_cont("Goldmont plus events, ");
5150 name = "goldmont_plus";
5151 break;
5152
5153 case INTEL_FAM6_ATOM_TREMONT_D:
5154 case INTEL_FAM6_ATOM_TREMONT:
5155 case INTEL_FAM6_ATOM_TREMONT_L:
5156 x86_pmu.late_ack = true;
5157 memcpy(hw_cache_event_ids, glp_hw_cache_event_ids,
5158 sizeof(hw_cache_event_ids));
5159 memcpy(hw_cache_extra_regs, tnt_hw_cache_extra_regs,
5160 sizeof(hw_cache_extra_regs));
5161 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5162
5163 intel_pmu_lbr_init_skl();
5164
5165 x86_pmu.event_constraints = intel_slm_event_constraints;
5166 x86_pmu.extra_regs = intel_tnt_extra_regs;
5167 /*
5168 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
5169 * for precise cycles.
5170 */
5171 x86_pmu.pebs_aliases = NULL;
5172 x86_pmu.pebs_prec_dist = true;
5173 x86_pmu.lbr_pt_coexist = true;
5174 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5175 x86_pmu.get_event_constraints = tnt_get_event_constraints;
5176 extra_attr = slm_format_attr;
5177 pr_cont("Tremont events, ");
5178 name = "Tremont";
5179 break;
5180
5181 case INTEL_FAM6_WESTMERE:
5182 case INTEL_FAM6_WESTMERE_EP:
5183 case INTEL_FAM6_WESTMERE_EX:
5184 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
5185 sizeof(hw_cache_event_ids));
5186 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
5187 sizeof(hw_cache_extra_regs));
5188
5189 intel_pmu_lbr_init_nhm();
5190
5191 x86_pmu.event_constraints = intel_westmere_event_constraints;
5192 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
5193 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
5194 x86_pmu.extra_regs = intel_westmere_extra_regs;
5195 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5196
5197 mem_attr = nhm_mem_events_attrs;
5198
5199 /* UOPS_ISSUED.STALLED_CYCLES */
5200 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5201 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5202 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
5203 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5204 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
5205
5206 intel_pmu_pebs_data_source_nhm();
5207 extra_attr = nhm_format_attr;
5208 pr_cont("Westmere events, ");
5209 name = "westmere";
5210 break;
5211
5212 case INTEL_FAM6_SANDYBRIDGE:
5213 case INTEL_FAM6_SANDYBRIDGE_X:
5214 x86_add_quirk(intel_sandybridge_quirk);
5215 x86_add_quirk(intel_ht_bug);
5216 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5217 sizeof(hw_cache_event_ids));
5218 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5219 sizeof(hw_cache_extra_regs));
5220
5221 intel_pmu_lbr_init_snb();
5222
5223 x86_pmu.event_constraints = intel_snb_event_constraints;
5224 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
5225 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
5226 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
5227 x86_pmu.extra_regs = intel_snbep_extra_regs;
5228 else
5229 x86_pmu.extra_regs = intel_snb_extra_regs;
5230
5231
5232 /* all extra regs are per-cpu when HT is on */
5233 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5234 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5235
5236 td_attr = snb_events_attrs;
5237 mem_attr = snb_mem_events_attrs;
5238
5239 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5240 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5241 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5242 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
5243 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
5244 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
5245
5246 extra_attr = nhm_format_attr;
5247
5248 pr_cont("SandyBridge events, ");
5249 name = "sandybridge";
5250 break;
5251
5252 case INTEL_FAM6_IVYBRIDGE:
5253 case INTEL_FAM6_IVYBRIDGE_X:
5254 x86_add_quirk(intel_ht_bug);
5255 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
5256 sizeof(hw_cache_event_ids));
5257 /* dTLB-load-misses on IVB is different than SNB */
5258 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
5259
5260 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
5261 sizeof(hw_cache_extra_regs));
5262
5263 intel_pmu_lbr_init_snb();
5264
5265 x86_pmu.event_constraints = intel_ivb_event_constraints;
5266 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
5267 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5268 x86_pmu.pebs_prec_dist = true;
5269 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
5270 x86_pmu.extra_regs = intel_snbep_extra_regs;
5271 else
5272 x86_pmu.extra_regs = intel_snb_extra_regs;
5273 /* all extra regs are per-cpu when HT is on */
5274 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5275 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5276
5277 td_attr = snb_events_attrs;
5278 mem_attr = snb_mem_events_attrs;
5279
5280 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
5281 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
5282 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
5283
5284 extra_attr = nhm_format_attr;
5285
5286 pr_cont("IvyBridge events, ");
5287 name = "ivybridge";
5288 break;
5289
5290
5291 case INTEL_FAM6_HASWELL:
5292 case INTEL_FAM6_HASWELL_X:
5293 case INTEL_FAM6_HASWELL_L:
5294 case INTEL_FAM6_HASWELL_G:
5295 x86_add_quirk(intel_ht_bug);
5296 x86_add_quirk(intel_pebs_isolation_quirk);
5297 x86_pmu.late_ack = true;
5298 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5299 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5300
5301 intel_pmu_lbr_init_hsw();
5302
5303 x86_pmu.event_constraints = intel_hsw_event_constraints;
5304 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
5305 x86_pmu.extra_regs = intel_snbep_extra_regs;
5306 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5307 x86_pmu.pebs_prec_dist = true;
5308 /* all extra regs are per-cpu when HT is on */
5309 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5310 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5311
5312 x86_pmu.hw_config = hsw_hw_config;
5313 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5314 x86_pmu.lbr_double_abort = true;
5315 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5316 hsw_format_attr : nhm_format_attr;
5317 td_attr = hsw_events_attrs;
5318 mem_attr = hsw_mem_events_attrs;
5319 tsx_attr = hsw_tsx_events_attrs;
5320 pr_cont("Haswell events, ");
5321 name = "haswell";
5322 break;
5323
5324 case INTEL_FAM6_BROADWELL:
5325 case INTEL_FAM6_BROADWELL_D:
5326 case INTEL_FAM6_BROADWELL_G:
5327 case INTEL_FAM6_BROADWELL_X:
5328 x86_add_quirk(intel_pebs_isolation_quirk);
5329 x86_pmu.late_ack = true;
5330 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5331 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5332
5333 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
5334 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
5335 BDW_L3_MISS|HSW_SNOOP_DRAM;
5336 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
5337 HSW_SNOOP_DRAM;
5338 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
5339 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5340 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
5341 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
5342
5343 intel_pmu_lbr_init_hsw();
5344
5345 x86_pmu.event_constraints = intel_bdw_event_constraints;
5346 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
5347 x86_pmu.extra_regs = intel_snbep_extra_regs;
5348 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
5349 x86_pmu.pebs_prec_dist = true;
5350 /* all extra regs are per-cpu when HT is on */
5351 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5352 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5353
5354 x86_pmu.hw_config = hsw_hw_config;
5355 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5356 x86_pmu.limit_period = bdw_limit_period;
5357 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5358 hsw_format_attr : nhm_format_attr;
5359 td_attr = hsw_events_attrs;
5360 mem_attr = hsw_mem_events_attrs;
5361 tsx_attr = hsw_tsx_events_attrs;
5362 pr_cont("Broadwell events, ");
5363 name = "broadwell";
5364 break;
5365
5366 case INTEL_FAM6_XEON_PHI_KNL:
5367 case INTEL_FAM6_XEON_PHI_KNM:
5368 memcpy(hw_cache_event_ids,
5369 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5370 memcpy(hw_cache_extra_regs,
5371 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5372 intel_pmu_lbr_init_knl();
5373
5374 x86_pmu.event_constraints = intel_slm_event_constraints;
5375 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
5376 x86_pmu.extra_regs = intel_knl_extra_regs;
5377
5378 /* all extra regs are per-cpu when HT is on */
5379 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5380 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5381 extra_attr = slm_format_attr;
5382 pr_cont("Knights Landing/Mill events, ");
5383 name = "knights-landing";
5384 break;
5385
5386 case INTEL_FAM6_SKYLAKE_X:
5387 pmem = true;
5388 fallthrough;
5389 case INTEL_FAM6_SKYLAKE_L:
5390 case INTEL_FAM6_SKYLAKE:
5391 case INTEL_FAM6_KABYLAKE_L:
5392 case INTEL_FAM6_KABYLAKE:
5393 case INTEL_FAM6_COMETLAKE_L:
5394 case INTEL_FAM6_COMETLAKE:
5395 x86_add_quirk(intel_pebs_isolation_quirk);
5396 x86_pmu.late_ack = true;
5397 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5398 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5399 intel_pmu_lbr_init_skl();
5400
5401 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
5402 event_attr_td_recovery_bubbles.event_str_noht =
5403 "event=0xd,umask=0x1,cmask=1";
5404 event_attr_td_recovery_bubbles.event_str_ht =
5405 "event=0xd,umask=0x1,cmask=1,any=1";
5406
5407 x86_pmu.event_constraints = intel_skl_event_constraints;
5408 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
5409 x86_pmu.extra_regs = intel_skl_extra_regs;
5410 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
5411 x86_pmu.pebs_prec_dist = true;
5412 /* all extra regs are per-cpu when HT is on */
5413 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5414 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5415
5416 x86_pmu.hw_config = hsw_hw_config;
5417 x86_pmu.get_event_constraints = hsw_get_event_constraints;
5418 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5419 hsw_format_attr : nhm_format_attr;
5420 extra_skl_attr = skl_format_attr;
5421 td_attr = hsw_events_attrs;
5422 mem_attr = hsw_mem_events_attrs;
5423 tsx_attr = hsw_tsx_events_attrs;
5424 intel_pmu_pebs_data_source_skl(pmem);
5425
5426 if (boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
5427 x86_pmu.flags |= PMU_FL_TFA;
5428 x86_pmu.get_event_constraints = tfa_get_event_constraints;
5429 x86_pmu.enable_all = intel_tfa_pmu_enable_all;
5430 x86_pmu.commit_scheduling = intel_tfa_commit_scheduling;
5431 }
5432
5433 pr_cont("Skylake events, ");
5434 name = "skylake";
5435 break;
5436
5437 case INTEL_FAM6_ICELAKE_X:
5438 case INTEL_FAM6_ICELAKE_D:
5439 pmem = true;
5440 fallthrough;
5441 case INTEL_FAM6_ICELAKE_L:
5442 case INTEL_FAM6_ICELAKE:
5443 case INTEL_FAM6_TIGERLAKE_L:
5444 case INTEL_FAM6_TIGERLAKE:
5445 x86_pmu.late_ack = true;
5446 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
5447 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
5448 hw_cache_event_ids[C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = -1;
5449 intel_pmu_lbr_init_skl();
5450
5451 x86_pmu.event_constraints = intel_icl_event_constraints;
5452 x86_pmu.pebs_constraints = intel_icl_pebs_event_constraints;
5453 x86_pmu.extra_regs = intel_icl_extra_regs;
5454 x86_pmu.pebs_aliases = NULL;
5455 x86_pmu.pebs_prec_dist = true;
5456 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
5457 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
5458
5459 x86_pmu.hw_config = hsw_hw_config;
5460 x86_pmu.get_event_constraints = icl_get_event_constraints;
5461 extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
5462 hsw_format_attr : nhm_format_attr;
5463 extra_skl_attr = skl_format_attr;
5464 mem_attr = icl_events_attrs;
5465 td_attr = icl_td_events_attrs;
5466 tsx_attr = icl_tsx_events_attrs;
5467 x86_pmu.rtm_abort_event = X86_CONFIG(.event=0xca, .umask=0x02);
5468 x86_pmu.lbr_pt_coexist = true;
5469 intel_pmu_pebs_data_source_skl(pmem);
5470 x86_pmu.update_topdown_event = icl_update_topdown_event;
5471 x86_pmu.set_topdown_event_period = icl_set_topdown_event_period;
5472 pr_cont("Icelake events, ");
5473 name = "icelake";
5474 break;
5475
5476 default:
5477 switch (x86_pmu.version) {
5478 case 1:
5479 x86_pmu.event_constraints = intel_v1_event_constraints;
5480 pr_cont("generic architected perfmon v1, ");
5481 name = "generic_arch_v1";
5482 break;
5483 default:
5484 /*
5485 * default constraints for v2 and up
5486 */
5487 x86_pmu.event_constraints = intel_gen_event_constraints;
5488 pr_cont("generic architected perfmon, ");
5489 name = "generic_arch_v2+";
5490 break;
5491 }
5492 }
5493
5494 snprintf(pmu_name_str, sizeof(pmu_name_str), "%s", name);
5495
5496
5497 group_events_td.attrs = td_attr;
5498 group_events_mem.attrs = mem_attr;
5499 group_events_tsx.attrs = tsx_attr;
5500 group_format_extra.attrs = extra_attr;
5501 group_format_extra_skl.attrs = extra_skl_attr;
5502
5503 x86_pmu.attr_update = attr_update;
5504
5505 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
5506 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
5507 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
5508 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
5509 }
5510 x86_pmu.intel_ctrl = (1ULL << x86_pmu.num_counters) - 1;
5511
5512 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
5513 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
5514 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
5515 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
5516 }
5517
5518 x86_pmu.intel_ctrl |=
5519 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
5520
5521 /* AnyThread may be deprecated on arch perfmon v5 or later */
5522 if (x86_pmu.intel_cap.anythread_deprecated)
5523 x86_pmu.format_attrs = intel_arch_formats_attr;
5524
5525 if (x86_pmu.event_constraints) {
5526 /*
5527 * event on fixed counter2 (REF_CYCLES) only works on this
5528 * counter, so do not extend mask to generic counters
5529 */
5530 for_each_event_constraint(c, x86_pmu.event_constraints) {
5531 /*
5532 * Don't extend the topdown slots and metrics
5533 * events to the generic counters.
5534 */
5535 if (c->idxmsk64 & INTEL_PMC_MSK_TOPDOWN) {
5536 c->weight = hweight64(c->idxmsk64);
5537 continue;
5538 }
5539
5540 if (c->cmask == FIXED_EVENT_FLAGS
5541 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
5542 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
5543 }
5544 c->idxmsk64 &=
5545 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
5546 c->weight = hweight64(c->idxmsk64);
5547 }
5548 }
5549
5550 /*
5551 * Access LBR MSR may cause #GP under certain circumstances.
5552 * E.g. KVM doesn't support LBR MSR
5553 * Check all LBT MSR here.
5554 * Disable LBR access if any LBR MSRs can not be accessed.
5555 */
5556 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
5557 x86_pmu.lbr_nr = 0;
5558 for (i = 0; i < x86_pmu.lbr_nr; i++) {
5559 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
5560 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
5561 x86_pmu.lbr_nr = 0;
5562 }
5563
5564 if (x86_pmu.lbr_nr)
5565 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
5566
5567 /*
5568 * Access extra MSR may cause #GP under certain circumstances.
5569 * E.g. KVM doesn't support offcore event
5570 * Check all extra_regs here.
5571 */
5572 if (x86_pmu.extra_regs) {
5573 for (er = x86_pmu.extra_regs; er->msr; er++) {
5574 er->extra_msr_access = check_msr(er->msr, 0x11UL);
5575 /* Disable LBR select mapping */
5576 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
5577 x86_pmu.lbr_sel_map = NULL;
5578 }
5579 }
5580
5581 /* Support full width counters using alternative MSR range */
5582 if (x86_pmu.intel_cap.full_width_write) {
5583 x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
5584 x86_pmu.perfctr = MSR_IA32_PMC0;
5585 pr_cont("full-width counters, ");
5586 }
5587
5588 /*
5589 * For arch perfmon 4 use counter freezing to avoid
5590 * several MSR accesses in the PMI.
5591 */
5592 if (x86_pmu.counter_freezing)
5593 x86_pmu.handle_irq = intel_pmu_handle_irq_v4;
5594
5595 if (x86_pmu.intel_cap.perf_metrics)
5596 x86_pmu.intel_ctrl |= 1ULL << GLOBAL_CTRL_EN_PERF_METRICS;
5597
5598 return 0;
5599 }
5600
5601 /*
5602 * HT bug: phase 2 init
5603 * Called once we have valid topology information to check
5604 * whether or not HT is enabled
5605 * If HT is off, then we disable the workaround
5606 */
fixup_ht_bug(void)5607 static __init int fixup_ht_bug(void)
5608 {
5609 int c;
5610 /*
5611 * problem not present on this CPU model, nothing to do
5612 */
5613 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
5614 return 0;
5615
5616 if (topology_max_smt_threads() > 1) {
5617 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
5618 return 0;
5619 }
5620
5621 cpus_read_lock();
5622
5623 hardlockup_detector_perf_stop();
5624
5625 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
5626
5627 x86_pmu.start_scheduling = NULL;
5628 x86_pmu.commit_scheduling = NULL;
5629 x86_pmu.stop_scheduling = NULL;
5630
5631 hardlockup_detector_perf_restart();
5632
5633 for_each_online_cpu(c)
5634 free_excl_cntrs(&per_cpu(cpu_hw_events, c));
5635
5636 cpus_read_unlock();
5637 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
5638 return 0;
5639 }
5640 subsys_initcall(fixup_ht_bug)
5641
