1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28
29 #include <drm/drm_fourcc.h>
30
31 #include "gem/i915_gem_pm.h"
32 #include "gt/intel_gpu_commands.h"
33 #include "gt/intel_ring.h"
34
35 #include "i915_drv.h"
36 #include "i915_reg.h"
37 #include "intel_de.h"
38 #include "intel_display_types.h"
39 #include "intel_frontbuffer.h"
40 #include "intel_overlay.h"
41
42 /* Limits for overlay size. According to intel doc, the real limits are:
43 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
44 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
45 * the mininum of both. */
46 #define IMAGE_MAX_WIDTH 2048
47 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
48 /* on 830 and 845 these large limits result in the card hanging */
49 #define IMAGE_MAX_WIDTH_LEGACY 1024
50 #define IMAGE_MAX_HEIGHT_LEGACY 1088
51
52 /* overlay register definitions */
53 /* OCMD register */
54 #define OCMD_TILED_SURFACE (0x1<<19)
55 #define OCMD_MIRROR_MASK (0x3<<17)
56 #define OCMD_MIRROR_MODE (0x3<<17)
57 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
58 #define OCMD_MIRROR_VERTICAL (0x2<<17)
59 #define OCMD_MIRROR_BOTH (0x3<<17)
60 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
61 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
62 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
63 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
64 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
65 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
66 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
67 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
68 #define OCMD_YUV_422_PACKED (0x8<<10)
69 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
70 #define OCMD_YUV_420_PLANAR (0xc<<10)
71 #define OCMD_YUV_422_PLANAR (0xd<<10)
72 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
73 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
74 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
75 #define OCMD_BUF_TYPE_MASK (0x1<<5)
76 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
77 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
78 #define OCMD_TEST_MODE (0x1<<4)
79 #define OCMD_BUFFER_SELECT (0x3<<2)
80 #define OCMD_BUFFER0 (0x0<<2)
81 #define OCMD_BUFFER1 (0x1<<2)
82 #define OCMD_FIELD_SELECT (0x1<<2)
83 #define OCMD_FIELD0 (0x0<<1)
84 #define OCMD_FIELD1 (0x1<<1)
85 #define OCMD_ENABLE (0x1<<0)
86
87 /* OCONFIG register */
88 #define OCONF_PIPE_MASK (0x1<<18)
89 #define OCONF_PIPE_A (0x0<<18)
90 #define OCONF_PIPE_B (0x1<<18)
91 #define OCONF_GAMMA2_ENABLE (0x1<<16)
92 #define OCONF_CSC_MODE_BT601 (0x0<<5)
93 #define OCONF_CSC_MODE_BT709 (0x1<<5)
94 #define OCONF_CSC_BYPASS (0x1<<4)
95 #define OCONF_CC_OUT_8BIT (0x1<<3)
96 #define OCONF_TEST_MODE (0x1<<2)
97 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
98 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
99
100 /* DCLRKM (dst-key) register */
101 #define DST_KEY_ENABLE (0x1<<31)
102 #define CLK_RGB24_MASK 0x0
103 #define CLK_RGB16_MASK 0x070307
104 #define CLK_RGB15_MASK 0x070707
105
106 #define RGB30_TO_COLORKEY(c) \
107 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
108 #define RGB16_TO_COLORKEY(c) \
109 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
110 #define RGB15_TO_COLORKEY(c) \
111 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
112 #define RGB8I_TO_COLORKEY(c) \
113 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
114
115 /* overlay flip addr flag */
116 #define OFC_UPDATE 0x1
117
118 /* polyphase filter coefficients */
119 #define N_HORIZ_Y_TAPS 5
120 #define N_VERT_Y_TAPS 3
121 #define N_HORIZ_UV_TAPS 3
122 #define N_VERT_UV_TAPS 3
123 #define N_PHASES 17
124 #define MAX_TAPS 5
125
126 /* memory bufferd overlay registers */
127 struct overlay_registers {
128 u32 OBUF_0Y;
129 u32 OBUF_1Y;
130 u32 OBUF_0U;
131 u32 OBUF_0V;
132 u32 OBUF_1U;
133 u32 OBUF_1V;
134 u32 OSTRIDE;
135 u32 YRGB_VPH;
136 u32 UV_VPH;
137 u32 HORZ_PH;
138 u32 INIT_PHS;
139 u32 DWINPOS;
140 u32 DWINSZ;
141 u32 SWIDTH;
142 u32 SWIDTHSW;
143 u32 SHEIGHT;
144 u32 YRGBSCALE;
145 u32 UVSCALE;
146 u32 OCLRC0;
147 u32 OCLRC1;
148 u32 DCLRKV;
149 u32 DCLRKM;
150 u32 SCLRKVH;
151 u32 SCLRKVL;
152 u32 SCLRKEN;
153 u32 OCONFIG;
154 u32 OCMD;
155 u32 RESERVED1; /* 0x6C */
156 u32 OSTART_0Y;
157 u32 OSTART_1Y;
158 u32 OSTART_0U;
159 u32 OSTART_0V;
160 u32 OSTART_1U;
161 u32 OSTART_1V;
162 u32 OTILEOFF_0Y;
163 u32 OTILEOFF_1Y;
164 u32 OTILEOFF_0U;
165 u32 OTILEOFF_0V;
166 u32 OTILEOFF_1U;
167 u32 OTILEOFF_1V;
168 u32 FASTHSCALE; /* 0xA0 */
169 u32 UVSCALEV; /* 0xA4 */
170 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
171 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
172 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
173 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
174 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
175 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
176 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
177 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
178 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
179 };
180
181 struct intel_overlay {
182 struct drm_i915_private *i915;
183 struct intel_context *context;
184 struct intel_crtc *crtc;
185 struct i915_vma *vma;
186 struct i915_vma *old_vma;
187 struct intel_frontbuffer *frontbuffer;
188 bool active;
189 bool pfit_active;
190 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
191 u32 color_key:24;
192 u32 color_key_enabled:1;
193 u32 brightness, contrast, saturation;
194 u32 old_xscale, old_yscale;
195 /* register access */
196 struct drm_i915_gem_object *reg_bo;
197 struct overlay_registers __iomem *regs;
198 u32 flip_addr;
199 /* flip handling */
200 struct i915_active last_flip;
201 void (*flip_complete)(struct intel_overlay *ovl);
202 };
203
i830_overlay_clock_gating(struct drm_i915_private * dev_priv,bool enable)204 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
205 bool enable)
206 {
207 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
208 u8 val;
209
210 /* WA_OVERLAY_CLKGATE:alm */
211 if (enable)
212 intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
213 else
214 intel_de_write(dev_priv, DSPCLK_GATE_D,
215 OVRUNIT_CLOCK_GATE_DISABLE);
216
217 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
218 pci_bus_read_config_byte(pdev->bus,
219 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
220 if (enable)
221 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
222 else
223 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
224 pci_bus_write_config_byte(pdev->bus,
225 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
226 }
227
228 static struct i915_request *
alloc_request(struct intel_overlay * overlay,void (* fn)(struct intel_overlay *))229 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
230 {
231 struct i915_request *rq;
232 int err;
233
234 overlay->flip_complete = fn;
235
236 rq = i915_request_create(overlay->context);
237 if (IS_ERR(rq))
238 return rq;
239
240 err = i915_active_add_request(&overlay->last_flip, rq);
241 if (err) {
242 i915_request_add(rq);
243 return ERR_PTR(err);
244 }
245
246 return rq;
247 }
248
249 /* overlay needs to be disable in OCMD reg */
intel_overlay_on(struct intel_overlay * overlay)250 static int intel_overlay_on(struct intel_overlay *overlay)
251 {
252 struct drm_i915_private *dev_priv = overlay->i915;
253 struct i915_request *rq;
254 u32 *cs;
255
256 drm_WARN_ON(&dev_priv->drm, overlay->active);
257
258 rq = alloc_request(overlay, NULL);
259 if (IS_ERR(rq))
260 return PTR_ERR(rq);
261
262 cs = intel_ring_begin(rq, 4);
263 if (IS_ERR(cs)) {
264 i915_request_add(rq);
265 return PTR_ERR(cs);
266 }
267
268 overlay->active = true;
269
270 if (IS_I830(dev_priv))
271 i830_overlay_clock_gating(dev_priv, false);
272
273 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
274 *cs++ = overlay->flip_addr | OFC_UPDATE;
275 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
276 *cs++ = MI_NOOP;
277 intel_ring_advance(rq, cs);
278
279 i915_request_add(rq);
280
281 return i915_active_wait(&overlay->last_flip);
282 }
283
intel_overlay_flip_prepare(struct intel_overlay * overlay,struct i915_vma * vma)284 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
285 struct i915_vma *vma)
286 {
287 enum pipe pipe = overlay->crtc->pipe;
288 struct intel_frontbuffer *frontbuffer = NULL;
289
290 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
291
292 if (vma)
293 frontbuffer = intel_frontbuffer_get(vma->obj);
294
295 intel_frontbuffer_track(overlay->frontbuffer, frontbuffer,
296 INTEL_FRONTBUFFER_OVERLAY(pipe));
297
298 if (overlay->frontbuffer)
299 intel_frontbuffer_put(overlay->frontbuffer);
300 overlay->frontbuffer = frontbuffer;
301
302 intel_frontbuffer_flip_prepare(overlay->i915,
303 INTEL_FRONTBUFFER_OVERLAY(pipe));
304
305 overlay->old_vma = overlay->vma;
306 if (vma)
307 overlay->vma = i915_vma_get(vma);
308 else
309 overlay->vma = NULL;
310 }
311
312 /* overlay needs to be enabled in OCMD reg */
intel_overlay_continue(struct intel_overlay * overlay,struct i915_vma * vma,bool load_polyphase_filter)313 static int intel_overlay_continue(struct intel_overlay *overlay,
314 struct i915_vma *vma,
315 bool load_polyphase_filter)
316 {
317 struct drm_i915_private *dev_priv = overlay->i915;
318 struct i915_request *rq;
319 u32 flip_addr = overlay->flip_addr;
320 u32 tmp, *cs;
321
322 drm_WARN_ON(&dev_priv->drm, !overlay->active);
323
324 if (load_polyphase_filter)
325 flip_addr |= OFC_UPDATE;
326
327 /* check for underruns */
328 tmp = intel_de_read(dev_priv, DOVSTA);
329 if (tmp & (1 << 17))
330 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
331
332 rq = alloc_request(overlay, NULL);
333 if (IS_ERR(rq))
334 return PTR_ERR(rq);
335
336 cs = intel_ring_begin(rq, 2);
337 if (IS_ERR(cs)) {
338 i915_request_add(rq);
339 return PTR_ERR(cs);
340 }
341
342 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
343 *cs++ = flip_addr;
344 intel_ring_advance(rq, cs);
345
346 intel_overlay_flip_prepare(overlay, vma);
347 i915_request_add(rq);
348
349 return 0;
350 }
351
intel_overlay_release_old_vma(struct intel_overlay * overlay)352 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
353 {
354 struct i915_vma *vma;
355
356 vma = fetch_and_zero(&overlay->old_vma);
357 if (drm_WARN_ON(&overlay->i915->drm, !vma))
358 return;
359
360 intel_frontbuffer_flip_complete(overlay->i915,
361 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
362
363 i915_vma_unpin(vma);
364 i915_vma_put(vma);
365 }
366
367 static void
intel_overlay_release_old_vid_tail(struct intel_overlay * overlay)368 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
369 {
370 intel_overlay_release_old_vma(overlay);
371 }
372
intel_overlay_off_tail(struct intel_overlay * overlay)373 static void intel_overlay_off_tail(struct intel_overlay *overlay)
374 {
375 struct drm_i915_private *dev_priv = overlay->i915;
376
377 intel_overlay_release_old_vma(overlay);
378
379 overlay->crtc->overlay = NULL;
380 overlay->crtc = NULL;
381 overlay->active = false;
382
383 if (IS_I830(dev_priv))
384 i830_overlay_clock_gating(dev_priv, true);
385 }
386
intel_overlay_last_flip_retire(struct i915_active * active)387 static void intel_overlay_last_flip_retire(struct i915_active *active)
388 {
389 struct intel_overlay *overlay =
390 container_of(active, typeof(*overlay), last_flip);
391
392 if (overlay->flip_complete)
393 overlay->flip_complete(overlay);
394 }
395
396 /* overlay needs to be disabled in OCMD reg */
intel_overlay_off(struct intel_overlay * overlay)397 static int intel_overlay_off(struct intel_overlay *overlay)
398 {
399 struct i915_request *rq;
400 u32 *cs, flip_addr = overlay->flip_addr;
401
402 drm_WARN_ON(&overlay->i915->drm, !overlay->active);
403
404 /* According to intel docs the overlay hw may hang (when switching
405 * off) without loading the filter coeffs. It is however unclear whether
406 * this applies to the disabling of the overlay or to the switching off
407 * of the hw. Do it in both cases */
408 flip_addr |= OFC_UPDATE;
409
410 rq = alloc_request(overlay, intel_overlay_off_tail);
411 if (IS_ERR(rq))
412 return PTR_ERR(rq);
413
414 cs = intel_ring_begin(rq, 6);
415 if (IS_ERR(cs)) {
416 i915_request_add(rq);
417 return PTR_ERR(cs);
418 }
419
420 /* wait for overlay to go idle */
421 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
422 *cs++ = flip_addr;
423 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
424
425 /* turn overlay off */
426 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
427 *cs++ = flip_addr;
428 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
429
430 intel_ring_advance(rq, cs);
431
432 intel_overlay_flip_prepare(overlay, NULL);
433 i915_request_add(rq);
434
435 return i915_active_wait(&overlay->last_flip);
436 }
437
438 /* recover from an interruption due to a signal
439 * We have to be careful not to repeat work forever an make forward progess. */
intel_overlay_recover_from_interrupt(struct intel_overlay * overlay)440 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
441 {
442 return i915_active_wait(&overlay->last_flip);
443 }
444
445 /* Wait for pending overlay flip and release old frame.
446 * Needs to be called before the overlay register are changed
447 * via intel_overlay_(un)map_regs
448 */
intel_overlay_release_old_vid(struct intel_overlay * overlay)449 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
450 {
451 struct drm_i915_private *dev_priv = overlay->i915;
452 struct i915_request *rq;
453 u32 *cs;
454
455 /*
456 * Only wait if there is actually an old frame to release to
457 * guarantee forward progress.
458 */
459 if (!overlay->old_vma)
460 return 0;
461
462 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
463 intel_overlay_release_old_vid_tail(overlay);
464 return 0;
465 }
466
467 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
468 if (IS_ERR(rq))
469 return PTR_ERR(rq);
470
471 cs = intel_ring_begin(rq, 2);
472 if (IS_ERR(cs)) {
473 i915_request_add(rq);
474 return PTR_ERR(cs);
475 }
476
477 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
478 *cs++ = MI_NOOP;
479 intel_ring_advance(rq, cs);
480
481 i915_request_add(rq);
482
483 return i915_active_wait(&overlay->last_flip);
484 }
485
intel_overlay_reset(struct drm_i915_private * dev_priv)486 void intel_overlay_reset(struct drm_i915_private *dev_priv)
487 {
488 struct intel_overlay *overlay = dev_priv->overlay;
489
490 if (!overlay)
491 return;
492
493 overlay->old_xscale = 0;
494 overlay->old_yscale = 0;
495 overlay->crtc = NULL;
496 overlay->active = false;
497 }
498
packed_depth_bytes(u32 format)499 static int packed_depth_bytes(u32 format)
500 {
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
502 case I915_OVERLAY_YUV422:
503 return 4;
504 case I915_OVERLAY_YUV411:
505 /* return 6; not implemented */
506 default:
507 return -EINVAL;
508 }
509 }
510
packed_width_bytes(u32 format,short width)511 static int packed_width_bytes(u32 format, short width)
512 {
513 switch (format & I915_OVERLAY_DEPTH_MASK) {
514 case I915_OVERLAY_YUV422:
515 return width << 1;
516 default:
517 return -EINVAL;
518 }
519 }
520
uv_hsubsampling(u32 format)521 static int uv_hsubsampling(u32 format)
522 {
523 switch (format & I915_OVERLAY_DEPTH_MASK) {
524 case I915_OVERLAY_YUV422:
525 case I915_OVERLAY_YUV420:
526 return 2;
527 case I915_OVERLAY_YUV411:
528 case I915_OVERLAY_YUV410:
529 return 4;
530 default:
531 return -EINVAL;
532 }
533 }
534
uv_vsubsampling(u32 format)535 static int uv_vsubsampling(u32 format)
536 {
537 switch (format & I915_OVERLAY_DEPTH_MASK) {
538 case I915_OVERLAY_YUV420:
539 case I915_OVERLAY_YUV410:
540 return 2;
541 case I915_OVERLAY_YUV422:
542 case I915_OVERLAY_YUV411:
543 return 1;
544 default:
545 return -EINVAL;
546 }
547 }
548
calc_swidthsw(struct drm_i915_private * dev_priv,u32 offset,u32 width)549 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
550 {
551 u32 sw;
552
553 if (DISPLAY_VER(dev_priv) == 2)
554 sw = ALIGN((offset & 31) + width, 32);
555 else
556 sw = ALIGN((offset & 63) + width, 64);
557
558 if (sw == 0)
559 return 0;
560
561 return (sw - 32) >> 3;
562 }
563
564 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
565 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
566 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
567 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
568 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
569 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
570 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
571 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
572 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
573 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
574 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
575 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
576 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
577 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
578 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
579 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
580 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
581 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
582 };
583
584 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
585 [ 0] = { 0x3000, 0x1800, 0x1800, },
586 [ 1] = { 0xb000, 0x18d0, 0x2e60, },
587 [ 2] = { 0xb000, 0x1990, 0x2ce0, },
588 [ 3] = { 0xb020, 0x1a68, 0x2b40, },
589 [ 4] = { 0xb040, 0x1b20, 0x29e0, },
590 [ 5] = { 0xb060, 0x1bd8, 0x2880, },
591 [ 6] = { 0xb080, 0x1c88, 0x3e60, },
592 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
593 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
594 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
595 [10] = { 0xb100, 0x1eb8, 0x3620, },
596 [11] = { 0xb100, 0x1f18, 0x34a0, },
597 [12] = { 0xb100, 0x1f68, 0x3360, },
598 [13] = { 0xb0e0, 0x1fa8, 0x3240, },
599 [14] = { 0xb0c0, 0x1fe0, 0x3140, },
600 [15] = { 0xb060, 0x1ff0, 0x30a0, },
601 [16] = { 0x3000, 0x0800, 0x3000, },
602 };
603
update_polyphase_filter(struct overlay_registers __iomem * regs)604 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
605 {
606 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
607 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
608 sizeof(uv_static_hcoeffs));
609 }
610
update_scaling_factors(struct intel_overlay * overlay,struct overlay_registers __iomem * regs,struct drm_intel_overlay_put_image * params)611 static bool update_scaling_factors(struct intel_overlay *overlay,
612 struct overlay_registers __iomem *regs,
613 struct drm_intel_overlay_put_image *params)
614 {
615 /* fixed point with a 12 bit shift */
616 u32 xscale, yscale, xscale_UV, yscale_UV;
617 #define FP_SHIFT 12
618 #define FRACT_MASK 0xfff
619 bool scale_changed = false;
620 int uv_hscale = uv_hsubsampling(params->flags);
621 int uv_vscale = uv_vsubsampling(params->flags);
622
623 if (params->dst_width > 1)
624 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
625 params->dst_width;
626 else
627 xscale = 1 << FP_SHIFT;
628
629 if (params->dst_height > 1)
630 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
631 params->dst_height;
632 else
633 yscale = 1 << FP_SHIFT;
634
635 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
636 xscale_UV = xscale/uv_hscale;
637 yscale_UV = yscale/uv_vscale;
638 /* make the Y scale to UV scale ratio an exact multiply */
639 xscale = xscale_UV * uv_hscale;
640 yscale = yscale_UV * uv_vscale;
641 /*} else {
642 xscale_UV = 0;
643 yscale_UV = 0;
644 }*/
645
646 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
647 scale_changed = true;
648 overlay->old_xscale = xscale;
649 overlay->old_yscale = yscale;
650
651 iowrite32(((yscale & FRACT_MASK) << 20) |
652 ((xscale >> FP_SHIFT) << 16) |
653 ((xscale & FRACT_MASK) << 3),
654 ®s->YRGBSCALE);
655
656 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
657 ((xscale_UV >> FP_SHIFT) << 16) |
658 ((xscale_UV & FRACT_MASK) << 3),
659 ®s->UVSCALE);
660
661 iowrite32((((yscale >> FP_SHIFT) << 16) |
662 ((yscale_UV >> FP_SHIFT) << 0)),
663 ®s->UVSCALEV);
664
665 if (scale_changed)
666 update_polyphase_filter(regs);
667
668 return scale_changed;
669 }
670
update_colorkey(struct intel_overlay * overlay,struct overlay_registers __iomem * regs)671 static void update_colorkey(struct intel_overlay *overlay,
672 struct overlay_registers __iomem *regs)
673 {
674 const struct intel_plane_state *state =
675 to_intel_plane_state(overlay->crtc->base.primary->state);
676 u32 key = overlay->color_key;
677 u32 format = 0;
678 u32 flags = 0;
679
680 if (overlay->color_key_enabled)
681 flags |= DST_KEY_ENABLE;
682
683 if (state->uapi.visible)
684 format = state->hw.fb->format->format;
685
686 switch (format) {
687 case DRM_FORMAT_C8:
688 key = RGB8I_TO_COLORKEY(key);
689 flags |= CLK_RGB24_MASK;
690 break;
691 case DRM_FORMAT_XRGB1555:
692 key = RGB15_TO_COLORKEY(key);
693 flags |= CLK_RGB15_MASK;
694 break;
695 case DRM_FORMAT_RGB565:
696 key = RGB16_TO_COLORKEY(key);
697 flags |= CLK_RGB16_MASK;
698 break;
699 case DRM_FORMAT_XRGB2101010:
700 case DRM_FORMAT_XBGR2101010:
701 key = RGB30_TO_COLORKEY(key);
702 flags |= CLK_RGB24_MASK;
703 break;
704 default:
705 flags |= CLK_RGB24_MASK;
706 break;
707 }
708
709 iowrite32(key, ®s->DCLRKV);
710 iowrite32(flags, ®s->DCLRKM);
711 }
712
overlay_cmd_reg(struct drm_intel_overlay_put_image * params)713 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
714 {
715 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
716
717 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
718 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
719 case I915_OVERLAY_YUV422:
720 cmd |= OCMD_YUV_422_PLANAR;
721 break;
722 case I915_OVERLAY_YUV420:
723 cmd |= OCMD_YUV_420_PLANAR;
724 break;
725 case I915_OVERLAY_YUV411:
726 case I915_OVERLAY_YUV410:
727 cmd |= OCMD_YUV_410_PLANAR;
728 break;
729 }
730 } else { /* YUV packed */
731 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
732 case I915_OVERLAY_YUV422:
733 cmd |= OCMD_YUV_422_PACKED;
734 break;
735 case I915_OVERLAY_YUV411:
736 cmd |= OCMD_YUV_411_PACKED;
737 break;
738 }
739
740 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
741 case I915_OVERLAY_NO_SWAP:
742 break;
743 case I915_OVERLAY_UV_SWAP:
744 cmd |= OCMD_UV_SWAP;
745 break;
746 case I915_OVERLAY_Y_SWAP:
747 cmd |= OCMD_Y_SWAP;
748 break;
749 case I915_OVERLAY_Y_AND_UV_SWAP:
750 cmd |= OCMD_Y_AND_UV_SWAP;
751 break;
752 }
753 }
754
755 return cmd;
756 }
757
intel_overlay_pin_fb(struct drm_i915_gem_object * new_bo)758 static struct i915_vma *intel_overlay_pin_fb(struct drm_i915_gem_object *new_bo)
759 {
760 struct i915_gem_ww_ctx ww;
761 struct i915_vma *vma;
762 int ret;
763
764 i915_gem_ww_ctx_init(&ww, true);
765 retry:
766 ret = i915_gem_object_lock(new_bo, &ww);
767 if (!ret) {
768 vma = i915_gem_object_pin_to_display_plane(new_bo, &ww, 0,
769 NULL, PIN_MAPPABLE);
770 ret = PTR_ERR_OR_ZERO(vma);
771 }
772 if (ret == -EDEADLK) {
773 ret = i915_gem_ww_ctx_backoff(&ww);
774 if (!ret)
775 goto retry;
776 }
777 i915_gem_ww_ctx_fini(&ww);
778 if (ret)
779 return ERR_PTR(ret);
780
781 return vma;
782 }
783
intel_overlay_do_put_image(struct intel_overlay * overlay,struct drm_i915_gem_object * new_bo,struct drm_intel_overlay_put_image * params)784 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
785 struct drm_i915_gem_object *new_bo,
786 struct drm_intel_overlay_put_image *params)
787 {
788 struct overlay_registers __iomem *regs = overlay->regs;
789 struct drm_i915_private *dev_priv = overlay->i915;
790 u32 swidth, swidthsw, sheight, ostride;
791 enum pipe pipe = overlay->crtc->pipe;
792 bool scale_changed = false;
793 struct i915_vma *vma;
794 int ret, tmp_width;
795
796 drm_WARN_ON(&dev_priv->drm,
797 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
798
799 ret = intel_overlay_release_old_vid(overlay);
800 if (ret != 0)
801 return ret;
802
803 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
804
805 vma = intel_overlay_pin_fb(new_bo);
806 if (IS_ERR(vma)) {
807 ret = PTR_ERR(vma);
808 goto out_pin_section;
809 }
810
811 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
812
813 if (!overlay->active) {
814 const struct intel_crtc_state *crtc_state =
815 overlay->crtc->config;
816 u32 oconfig = 0;
817
818 if (crtc_state->gamma_enable &&
819 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
820 oconfig |= OCONF_CC_OUT_8BIT;
821 if (crtc_state->gamma_enable)
822 oconfig |= OCONF_GAMMA2_ENABLE;
823 if (DISPLAY_VER(dev_priv) == 4)
824 oconfig |= OCONF_CSC_MODE_BT709;
825 oconfig |= pipe == 0 ?
826 OCONF_PIPE_A : OCONF_PIPE_B;
827 iowrite32(oconfig, ®s->OCONFIG);
828
829 ret = intel_overlay_on(overlay);
830 if (ret != 0)
831 goto out_unpin;
832 }
833
834 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS);
835 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ);
836
837 if (params->flags & I915_OVERLAY_YUV_PACKED)
838 tmp_width = packed_width_bytes(params->flags,
839 params->src_width);
840 else
841 tmp_width = params->src_width;
842
843 swidth = params->src_width;
844 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
845 sheight = params->src_height;
846 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y);
847 ostride = params->stride_Y;
848
849 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
850 int uv_hscale = uv_hsubsampling(params->flags);
851 int uv_vscale = uv_vsubsampling(params->flags);
852 u32 tmp_U, tmp_V;
853
854 swidth |= (params->src_width / uv_hscale) << 16;
855 sheight |= (params->src_height / uv_vscale) << 16;
856
857 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
858 params->src_width / uv_hscale);
859 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
860 params->src_width / uv_hscale);
861 swidthsw |= max(tmp_U, tmp_V) << 16;
862
863 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
864 ®s->OBUF_0U);
865 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
866 ®s->OBUF_0V);
867
868 ostride |= params->stride_UV << 16;
869 }
870
871 iowrite32(swidth, ®s->SWIDTH);
872 iowrite32(swidthsw, ®s->SWIDTHSW);
873 iowrite32(sheight, ®s->SHEIGHT);
874 iowrite32(ostride, ®s->OSTRIDE);
875
876 scale_changed = update_scaling_factors(overlay, regs, params);
877
878 update_colorkey(overlay, regs);
879
880 iowrite32(overlay_cmd_reg(params), ®s->OCMD);
881
882 ret = intel_overlay_continue(overlay, vma, scale_changed);
883 if (ret)
884 goto out_unpin;
885
886 return 0;
887
888 out_unpin:
889 i915_vma_unpin(vma);
890 out_pin_section:
891 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
892
893 return ret;
894 }
895
intel_overlay_switch_off(struct intel_overlay * overlay)896 int intel_overlay_switch_off(struct intel_overlay *overlay)
897 {
898 struct drm_i915_private *dev_priv = overlay->i915;
899 int ret;
900
901 drm_WARN_ON(&dev_priv->drm,
902 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
903
904 ret = intel_overlay_recover_from_interrupt(overlay);
905 if (ret != 0)
906 return ret;
907
908 if (!overlay->active)
909 return 0;
910
911 ret = intel_overlay_release_old_vid(overlay);
912 if (ret != 0)
913 return ret;
914
915 iowrite32(0, &overlay->regs->OCMD);
916
917 return intel_overlay_off(overlay);
918 }
919
check_overlay_possible_on_crtc(struct intel_overlay * overlay,struct intel_crtc * crtc)920 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
921 struct intel_crtc *crtc)
922 {
923 if (!crtc->active)
924 return -EINVAL;
925
926 /* can't use the overlay with double wide pipe */
927 if (crtc->config->double_wide)
928 return -EINVAL;
929
930 return 0;
931 }
932
update_pfit_vscale_ratio(struct intel_overlay * overlay)933 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
934 {
935 struct drm_i915_private *dev_priv = overlay->i915;
936 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
937 u32 ratio;
938
939 /* XXX: This is not the same logic as in the xorg driver, but more in
940 * line with the intel documentation for the i965
941 */
942 if (DISPLAY_VER(dev_priv) >= 4) {
943 /* on i965 use the PGM reg to read out the autoscaler values */
944 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
945 } else {
946 if (pfit_control & VERT_AUTO_SCALE)
947 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
948 else
949 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
950 ratio >>= PFIT_VERT_SCALE_SHIFT;
951 }
952
953 overlay->pfit_vscale_ratio = ratio;
954 }
955
check_overlay_dst(struct intel_overlay * overlay,struct drm_intel_overlay_put_image * rec)956 static int check_overlay_dst(struct intel_overlay *overlay,
957 struct drm_intel_overlay_put_image *rec)
958 {
959 const struct intel_crtc_state *pipe_config =
960 overlay->crtc->config;
961
962 if (rec->dst_x < pipe_config->pipe_src_w &&
963 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
964 rec->dst_y < pipe_config->pipe_src_h &&
965 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
966 return 0;
967 else
968 return -EINVAL;
969 }
970
check_overlay_scaling(struct drm_intel_overlay_put_image * rec)971 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
972 {
973 u32 tmp;
974
975 /* downscaling limit is 8.0 */
976 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
977 if (tmp > 7)
978 return -EINVAL;
979
980 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
981 if (tmp > 7)
982 return -EINVAL;
983
984 return 0;
985 }
986
check_overlay_src(struct drm_i915_private * dev_priv,struct drm_intel_overlay_put_image * rec,struct drm_i915_gem_object * new_bo)987 static int check_overlay_src(struct drm_i915_private *dev_priv,
988 struct drm_intel_overlay_put_image *rec,
989 struct drm_i915_gem_object *new_bo)
990 {
991 int uv_hscale = uv_hsubsampling(rec->flags);
992 int uv_vscale = uv_vsubsampling(rec->flags);
993 u32 stride_mask;
994 int depth;
995 u32 tmp;
996
997 /* check src dimensions */
998 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
999 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
1000 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
1001 return -EINVAL;
1002 } else {
1003 if (rec->src_height > IMAGE_MAX_HEIGHT ||
1004 rec->src_width > IMAGE_MAX_WIDTH)
1005 return -EINVAL;
1006 }
1007
1008 /* better safe than sorry, use 4 as the maximal subsampling ratio */
1009 if (rec->src_height < N_VERT_Y_TAPS*4 ||
1010 rec->src_width < N_HORIZ_Y_TAPS*4)
1011 return -EINVAL;
1012
1013 /* check alignment constraints */
1014 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1015 case I915_OVERLAY_RGB:
1016 /* not implemented */
1017 return -EINVAL;
1018
1019 case I915_OVERLAY_YUV_PACKED:
1020 if (uv_vscale != 1)
1021 return -EINVAL;
1022
1023 depth = packed_depth_bytes(rec->flags);
1024 if (depth < 0)
1025 return depth;
1026
1027 /* ignore UV planes */
1028 rec->stride_UV = 0;
1029 rec->offset_U = 0;
1030 rec->offset_V = 0;
1031 /* check pixel alignment */
1032 if (rec->offset_Y % depth)
1033 return -EINVAL;
1034 break;
1035
1036 case I915_OVERLAY_YUV_PLANAR:
1037 if (uv_vscale < 0 || uv_hscale < 0)
1038 return -EINVAL;
1039 /* no offset restrictions for planar formats */
1040 break;
1041
1042 default:
1043 return -EINVAL;
1044 }
1045
1046 if (rec->src_width % uv_hscale)
1047 return -EINVAL;
1048
1049 /* stride checking */
1050 if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1051 stride_mask = 255;
1052 else
1053 stride_mask = 63;
1054
1055 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1056 return -EINVAL;
1057 if (DISPLAY_VER(dev_priv) == 4 && rec->stride_Y < 512)
1058 return -EINVAL;
1059
1060 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1061 4096 : 8192;
1062 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1063 return -EINVAL;
1064
1065 /* check buffer dimensions */
1066 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1067 case I915_OVERLAY_RGB:
1068 case I915_OVERLAY_YUV_PACKED:
1069 /* always 4 Y values per depth pixels */
1070 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1071 return -EINVAL;
1072
1073 tmp = rec->stride_Y*rec->src_height;
1074 if (rec->offset_Y + tmp > new_bo->base.size)
1075 return -EINVAL;
1076 break;
1077
1078 case I915_OVERLAY_YUV_PLANAR:
1079 if (rec->src_width > rec->stride_Y)
1080 return -EINVAL;
1081 if (rec->src_width/uv_hscale > rec->stride_UV)
1082 return -EINVAL;
1083
1084 tmp = rec->stride_Y * rec->src_height;
1085 if (rec->offset_Y + tmp > new_bo->base.size)
1086 return -EINVAL;
1087
1088 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1089 if (rec->offset_U + tmp > new_bo->base.size ||
1090 rec->offset_V + tmp > new_bo->base.size)
1091 return -EINVAL;
1092 break;
1093 }
1094
1095 return 0;
1096 }
1097
intel_overlay_put_image_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)1098 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv)
1100 {
1101 struct drm_intel_overlay_put_image *params = data;
1102 struct drm_i915_private *dev_priv = to_i915(dev);
1103 struct intel_overlay *overlay;
1104 struct drm_crtc *drmmode_crtc;
1105 struct intel_crtc *crtc;
1106 struct drm_i915_gem_object *new_bo;
1107 int ret;
1108
1109 overlay = dev_priv->overlay;
1110 if (!overlay) {
1111 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1112 return -ENODEV;
1113 }
1114
1115 if (!(params->flags & I915_OVERLAY_ENABLE)) {
1116 drm_modeset_lock_all(dev);
1117 ret = intel_overlay_switch_off(overlay);
1118 drm_modeset_unlock_all(dev);
1119
1120 return ret;
1121 }
1122
1123 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1124 if (!drmmode_crtc)
1125 return -ENOENT;
1126 crtc = to_intel_crtc(drmmode_crtc);
1127
1128 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1129 if (!new_bo)
1130 return -ENOENT;
1131
1132 drm_modeset_lock_all(dev);
1133
1134 if (i915_gem_object_is_tiled(new_bo)) {
1135 drm_dbg_kms(&dev_priv->drm,
1136 "buffer used for overlay image can not be tiled\n");
1137 ret = -EINVAL;
1138 goto out_unlock;
1139 }
1140
1141 ret = intel_overlay_recover_from_interrupt(overlay);
1142 if (ret != 0)
1143 goto out_unlock;
1144
1145 if (overlay->crtc != crtc) {
1146 ret = intel_overlay_switch_off(overlay);
1147 if (ret != 0)
1148 goto out_unlock;
1149
1150 ret = check_overlay_possible_on_crtc(overlay, crtc);
1151 if (ret != 0)
1152 goto out_unlock;
1153
1154 overlay->crtc = crtc;
1155 crtc->overlay = overlay;
1156
1157 /* line too wide, i.e. one-line-mode */
1158 if (crtc->config->pipe_src_w > 1024 &&
1159 crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1160 overlay->pfit_active = true;
1161 update_pfit_vscale_ratio(overlay);
1162 } else
1163 overlay->pfit_active = false;
1164 }
1165
1166 ret = check_overlay_dst(overlay, params);
1167 if (ret != 0)
1168 goto out_unlock;
1169
1170 if (overlay->pfit_active) {
1171 params->dst_y = (((u32)params->dst_y << 12) /
1172 overlay->pfit_vscale_ratio);
1173 /* shifting right rounds downwards, so add 1 */
1174 params->dst_height = (((u32)params->dst_height << 12) /
1175 overlay->pfit_vscale_ratio) + 1;
1176 }
1177
1178 if (params->src_scan_height > params->src_height ||
1179 params->src_scan_width > params->src_width) {
1180 ret = -EINVAL;
1181 goto out_unlock;
1182 }
1183
1184 ret = check_overlay_src(dev_priv, params, new_bo);
1185 if (ret != 0)
1186 goto out_unlock;
1187
1188 /* Check scaling after src size to prevent a divide-by-zero. */
1189 ret = check_overlay_scaling(params);
1190 if (ret != 0)
1191 goto out_unlock;
1192
1193 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1194 if (ret != 0)
1195 goto out_unlock;
1196
1197 drm_modeset_unlock_all(dev);
1198 i915_gem_object_put(new_bo);
1199
1200 return 0;
1201
1202 out_unlock:
1203 drm_modeset_unlock_all(dev);
1204 i915_gem_object_put(new_bo);
1205
1206 return ret;
1207 }
1208
update_reg_attrs(struct intel_overlay * overlay,struct overlay_registers __iomem * regs)1209 static void update_reg_attrs(struct intel_overlay *overlay,
1210 struct overlay_registers __iomem *regs)
1211 {
1212 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1213 ®s->OCLRC0);
1214 iowrite32(overlay->saturation, ®s->OCLRC1);
1215 }
1216
check_gamma_bounds(u32 gamma1,u32 gamma2)1217 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1218 {
1219 int i;
1220
1221 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1222 return false;
1223
1224 for (i = 0; i < 3; i++) {
1225 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1226 return false;
1227 }
1228
1229 return true;
1230 }
1231
check_gamma5_errata(u32 gamma5)1232 static bool check_gamma5_errata(u32 gamma5)
1233 {
1234 int i;
1235
1236 for (i = 0; i < 3; i++) {
1237 if (((gamma5 >> i*8) & 0xff) == 0x80)
1238 return false;
1239 }
1240
1241 return true;
1242 }
1243
check_gamma(struct drm_intel_overlay_attrs * attrs)1244 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1245 {
1246 if (!check_gamma_bounds(0, attrs->gamma0) ||
1247 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1248 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1249 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1250 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1251 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1252 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1253 return -EINVAL;
1254
1255 if (!check_gamma5_errata(attrs->gamma5))
1256 return -EINVAL;
1257
1258 return 0;
1259 }
1260
intel_overlay_attrs_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)1261 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1262 struct drm_file *file_priv)
1263 {
1264 struct drm_intel_overlay_attrs *attrs = data;
1265 struct drm_i915_private *dev_priv = to_i915(dev);
1266 struct intel_overlay *overlay;
1267 int ret;
1268
1269 overlay = dev_priv->overlay;
1270 if (!overlay) {
1271 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1272 return -ENODEV;
1273 }
1274
1275 drm_modeset_lock_all(dev);
1276
1277 ret = -EINVAL;
1278 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1279 attrs->color_key = overlay->color_key;
1280 attrs->brightness = overlay->brightness;
1281 attrs->contrast = overlay->contrast;
1282 attrs->saturation = overlay->saturation;
1283
1284 if (DISPLAY_VER(dev_priv) != 2) {
1285 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1286 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1287 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1288 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1289 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1290 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1291 }
1292 } else {
1293 if (attrs->brightness < -128 || attrs->brightness > 127)
1294 goto out_unlock;
1295 if (attrs->contrast > 255)
1296 goto out_unlock;
1297 if (attrs->saturation > 1023)
1298 goto out_unlock;
1299
1300 overlay->color_key = attrs->color_key;
1301 overlay->brightness = attrs->brightness;
1302 overlay->contrast = attrs->contrast;
1303 overlay->saturation = attrs->saturation;
1304
1305 update_reg_attrs(overlay, overlay->regs);
1306
1307 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1308 if (DISPLAY_VER(dev_priv) == 2)
1309 goto out_unlock;
1310
1311 if (overlay->active) {
1312 ret = -EBUSY;
1313 goto out_unlock;
1314 }
1315
1316 ret = check_gamma(attrs);
1317 if (ret)
1318 goto out_unlock;
1319
1320 intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1321 intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1322 intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1323 intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1324 intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1325 intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1326 }
1327 }
1328 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1329
1330 ret = 0;
1331 out_unlock:
1332 drm_modeset_unlock_all(dev);
1333
1334 return ret;
1335 }
1336
get_registers(struct intel_overlay * overlay,bool use_phys)1337 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1338 {
1339 struct drm_i915_private *i915 = overlay->i915;
1340 struct drm_i915_gem_object *obj;
1341 struct i915_vma *vma;
1342 int err;
1343
1344 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1345 if (IS_ERR(obj))
1346 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1347 if (IS_ERR(obj))
1348 return PTR_ERR(obj);
1349
1350 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1351 if (IS_ERR(vma)) {
1352 err = PTR_ERR(vma);
1353 goto err_put_bo;
1354 }
1355
1356 if (use_phys)
1357 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1358 else
1359 overlay->flip_addr = i915_ggtt_offset(vma);
1360 overlay->regs = i915_vma_pin_iomap(vma);
1361 i915_vma_unpin(vma);
1362
1363 if (IS_ERR(overlay->regs)) {
1364 err = PTR_ERR(overlay->regs);
1365 goto err_put_bo;
1366 }
1367
1368 overlay->reg_bo = obj;
1369 return 0;
1370
1371 err_put_bo:
1372 i915_gem_object_put(obj);
1373 return err;
1374 }
1375
intel_overlay_setup(struct drm_i915_private * dev_priv)1376 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1377 {
1378 struct intel_overlay *overlay;
1379 struct intel_engine_cs *engine;
1380 int ret;
1381
1382 if (!HAS_OVERLAY(dev_priv))
1383 return;
1384
1385 engine = dev_priv->gt.engine[RCS0];
1386 if (!engine || !engine->kernel_context)
1387 return;
1388
1389 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1390 if (!overlay)
1391 return;
1392
1393 overlay->i915 = dev_priv;
1394 overlay->context = engine->kernel_context;
1395 GEM_BUG_ON(!overlay->context);
1396
1397 overlay->color_key = 0x0101fe;
1398 overlay->color_key_enabled = true;
1399 overlay->brightness = -19;
1400 overlay->contrast = 75;
1401 overlay->saturation = 146;
1402
1403 i915_active_init(&overlay->last_flip,
1404 NULL, intel_overlay_last_flip_retire, 0);
1405
1406 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1407 if (ret)
1408 goto out_free;
1409
1410 memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1411 update_polyphase_filter(overlay->regs);
1412 update_reg_attrs(overlay, overlay->regs);
1413
1414 dev_priv->overlay = overlay;
1415 drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1416 return;
1417
1418 out_free:
1419 kfree(overlay);
1420 }
1421
intel_overlay_cleanup(struct drm_i915_private * dev_priv)1422 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1423 {
1424 struct intel_overlay *overlay;
1425
1426 overlay = fetch_and_zero(&dev_priv->overlay);
1427 if (!overlay)
1428 return;
1429
1430 /*
1431 * The bo's should be free'd by the generic code already.
1432 * Furthermore modesetting teardown happens beforehand so the
1433 * hardware should be off already.
1434 */
1435 drm_WARN_ON(&dev_priv->drm, overlay->active);
1436
1437 i915_gem_object_put(overlay->reg_bo);
1438 i915_active_fini(&overlay->last_flip);
1439
1440 kfree(overlay);
1441 }
1442
1443 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1444
1445 struct intel_overlay_error_state {
1446 struct overlay_registers regs;
1447 unsigned long base;
1448 u32 dovsta;
1449 u32 isr;
1450 };
1451
1452 struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private * dev_priv)1453 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1454 {
1455 struct intel_overlay *overlay = dev_priv->overlay;
1456 struct intel_overlay_error_state *error;
1457
1458 if (!overlay || !overlay->active)
1459 return NULL;
1460
1461 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1462 if (error == NULL)
1463 return NULL;
1464
1465 error->dovsta = intel_de_read(dev_priv, DOVSTA);
1466 error->isr = intel_de_read(dev_priv, GEN2_ISR);
1467 error->base = overlay->flip_addr;
1468
1469 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1470
1471 return error;
1472 }
1473
1474 void
intel_overlay_print_error_state(struct drm_i915_error_state_buf * m,struct intel_overlay_error_state * error)1475 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1476 struct intel_overlay_error_state *error)
1477 {
1478 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1479 error->dovsta, error->isr);
1480 i915_error_printf(m, " Register file at 0x%08lx:\n",
1481 error->base);
1482
1483 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1484 P(OBUF_0Y);
1485 P(OBUF_1Y);
1486 P(OBUF_0U);
1487 P(OBUF_0V);
1488 P(OBUF_1U);
1489 P(OBUF_1V);
1490 P(OSTRIDE);
1491 P(YRGB_VPH);
1492 P(UV_VPH);
1493 P(HORZ_PH);
1494 P(INIT_PHS);
1495 P(DWINPOS);
1496 P(DWINSZ);
1497 P(SWIDTH);
1498 P(SWIDTHSW);
1499 P(SHEIGHT);
1500 P(YRGBSCALE);
1501 P(UVSCALE);
1502 P(OCLRC0);
1503 P(OCLRC1);
1504 P(DCLRKV);
1505 P(DCLRKM);
1506 P(SCLRKVH);
1507 P(SCLRKVL);
1508 P(SCLRKEN);
1509 P(OCONFIG);
1510 P(OCMD);
1511 P(OSTART_0Y);
1512 P(OSTART_1Y);
1513 P(OSTART_0U);
1514 P(OSTART_0V);
1515 P(OSTART_1U);
1516 P(OSTART_1V);
1517 P(OTILEOFF_0Y);
1518 P(OTILEOFF_1Y);
1519 P(OTILEOFF_0U);
1520 P(OTILEOFF_0V);
1521 P(OTILEOFF_1U);
1522 P(OTILEOFF_1V);
1523 P(FASTHSCALE);
1524 P(UVSCALEV);
1525 #undef P
1526 }
1527
1528 #endif
1529
