1 /*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
28
29 #include <drm/drm_fourcc.h>
30
31 #include "gem/i915_gem_pm.h"
32 #include "gt/intel_ring.h"
33
34 #include "i915_drv.h"
35 #include "i915_reg.h"
36 #include "intel_display_types.h"
37 #include "intel_frontbuffer.h"
38 #include "intel_overlay.h"
39
40 /* Limits for overlay size. According to intel doc, the real limits are:
41 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
42 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
43 * the mininum of both. */
44 #define IMAGE_MAX_WIDTH 2048
45 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
46 /* on 830 and 845 these large limits result in the card hanging */
47 #define IMAGE_MAX_WIDTH_LEGACY 1024
48 #define IMAGE_MAX_HEIGHT_LEGACY 1088
49
50 /* overlay register definitions */
51 /* OCMD register */
52 #define OCMD_TILED_SURFACE (0x1<<19)
53 #define OCMD_MIRROR_MASK (0x3<<17)
54 #define OCMD_MIRROR_MODE (0x3<<17)
55 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
56 #define OCMD_MIRROR_VERTICAL (0x2<<17)
57 #define OCMD_MIRROR_BOTH (0x3<<17)
58 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
59 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
60 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
61 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
62 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
63 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
64 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
65 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
66 #define OCMD_YUV_422_PACKED (0x8<<10)
67 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
68 #define OCMD_YUV_420_PLANAR (0xc<<10)
69 #define OCMD_YUV_422_PLANAR (0xd<<10)
70 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
71 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
72 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
73 #define OCMD_BUF_TYPE_MASK (0x1<<5)
74 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
75 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
76 #define OCMD_TEST_MODE (0x1<<4)
77 #define OCMD_BUFFER_SELECT (0x3<<2)
78 #define OCMD_BUFFER0 (0x0<<2)
79 #define OCMD_BUFFER1 (0x1<<2)
80 #define OCMD_FIELD_SELECT (0x1<<2)
81 #define OCMD_FIELD0 (0x0<<1)
82 #define OCMD_FIELD1 (0x1<<1)
83 #define OCMD_ENABLE (0x1<<0)
84
85 /* OCONFIG register */
86 #define OCONF_PIPE_MASK (0x1<<18)
87 #define OCONF_PIPE_A (0x0<<18)
88 #define OCONF_PIPE_B (0x1<<18)
89 #define OCONF_GAMMA2_ENABLE (0x1<<16)
90 #define OCONF_CSC_MODE_BT601 (0x0<<5)
91 #define OCONF_CSC_MODE_BT709 (0x1<<5)
92 #define OCONF_CSC_BYPASS (0x1<<4)
93 #define OCONF_CC_OUT_8BIT (0x1<<3)
94 #define OCONF_TEST_MODE (0x1<<2)
95 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
96 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
97
98 /* DCLRKM (dst-key) register */
99 #define DST_KEY_ENABLE (0x1<<31)
100 #define CLK_RGB24_MASK 0x0
101 #define CLK_RGB16_MASK 0x070307
102 #define CLK_RGB15_MASK 0x070707
103
104 #define RGB30_TO_COLORKEY(c) \
105 ((((c) & 0x3fc00000) >> 6) | (((c) & 0x000ff000) >> 4) | (((c) & 0x000003fc) >> 2))
106 #define RGB16_TO_COLORKEY(c) \
107 ((((c) & 0xf800) << 8) | (((c) & 0x07e0) << 5) | (((c) & 0x001f) << 3))
108 #define RGB15_TO_COLORKEY(c) \
109 ((((c) & 0x7c00) << 9) | (((c) & 0x03e0) << 6) | (((c) & 0x001f) << 3))
110 #define RGB8I_TO_COLORKEY(c) \
111 ((((c) & 0xff) << 16) | (((c) & 0xff) << 8) | (((c) & 0xff) << 0))
112
113 /* overlay flip addr flag */
114 #define OFC_UPDATE 0x1
115
116 /* polyphase filter coefficients */
117 #define N_HORIZ_Y_TAPS 5
118 #define N_VERT_Y_TAPS 3
119 #define N_HORIZ_UV_TAPS 3
120 #define N_VERT_UV_TAPS 3
121 #define N_PHASES 17
122 #define MAX_TAPS 5
123
124 /* memory bufferd overlay registers */
125 struct overlay_registers {
126 u32 OBUF_0Y;
127 u32 OBUF_1Y;
128 u32 OBUF_0U;
129 u32 OBUF_0V;
130 u32 OBUF_1U;
131 u32 OBUF_1V;
132 u32 OSTRIDE;
133 u32 YRGB_VPH;
134 u32 UV_VPH;
135 u32 HORZ_PH;
136 u32 INIT_PHS;
137 u32 DWINPOS;
138 u32 DWINSZ;
139 u32 SWIDTH;
140 u32 SWIDTHSW;
141 u32 SHEIGHT;
142 u32 YRGBSCALE;
143 u32 UVSCALE;
144 u32 OCLRC0;
145 u32 OCLRC1;
146 u32 DCLRKV;
147 u32 DCLRKM;
148 u32 SCLRKVH;
149 u32 SCLRKVL;
150 u32 SCLRKEN;
151 u32 OCONFIG;
152 u32 OCMD;
153 u32 RESERVED1; /* 0x6C */
154 u32 OSTART_0Y;
155 u32 OSTART_1Y;
156 u32 OSTART_0U;
157 u32 OSTART_0V;
158 u32 OSTART_1U;
159 u32 OSTART_1V;
160 u32 OTILEOFF_0Y;
161 u32 OTILEOFF_1Y;
162 u32 OTILEOFF_0U;
163 u32 OTILEOFF_0V;
164 u32 OTILEOFF_1U;
165 u32 OTILEOFF_1V;
166 u32 FASTHSCALE; /* 0xA0 */
167 u32 UVSCALEV; /* 0xA4 */
168 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
169 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
170 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
171 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
172 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
173 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
174 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
175 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
176 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
177 };
178
179 struct intel_overlay {
180 struct drm_i915_private *i915;
181 struct intel_context *context;
182 struct intel_crtc *crtc;
183 struct i915_vma *vma;
184 struct i915_vma *old_vma;
185 bool active;
186 bool pfit_active;
187 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
188 u32 color_key:24;
189 u32 color_key_enabled:1;
190 u32 brightness, contrast, saturation;
191 u32 old_xscale, old_yscale;
192 /* register access */
193 struct drm_i915_gem_object *reg_bo;
194 struct overlay_registers __iomem *regs;
195 u32 flip_addr;
196 /* flip handling */
197 struct i915_active last_flip;
198 void (*flip_complete)(struct intel_overlay *ovl);
199 };
200
i830_overlay_clock_gating(struct drm_i915_private * dev_priv,bool enable)201 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
202 bool enable)
203 {
204 struct pci_dev *pdev = dev_priv->drm.pdev;
205 u8 val;
206
207 /* WA_OVERLAY_CLKGATE:alm */
208 if (enable)
209 intel_de_write(dev_priv, DSPCLK_GATE_D, 0);
210 else
211 intel_de_write(dev_priv, DSPCLK_GATE_D,
212 OVRUNIT_CLOCK_GATE_DISABLE);
213
214 /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
215 pci_bus_read_config_byte(pdev->bus,
216 PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
217 if (enable)
218 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
219 else
220 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
221 pci_bus_write_config_byte(pdev->bus,
222 PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
223 }
224
225 static struct i915_request *
alloc_request(struct intel_overlay * overlay,void (* fn)(struct intel_overlay *))226 alloc_request(struct intel_overlay *overlay, void (*fn)(struct intel_overlay *))
227 {
228 struct i915_request *rq;
229 int err;
230
231 overlay->flip_complete = fn;
232
233 rq = i915_request_create(overlay->context);
234 if (IS_ERR(rq))
235 return rq;
236
237 err = i915_active_add_request(&overlay->last_flip, rq);
238 if (err) {
239 i915_request_add(rq);
240 return ERR_PTR(err);
241 }
242
243 return rq;
244 }
245
246 /* overlay needs to be disable in OCMD reg */
intel_overlay_on(struct intel_overlay * overlay)247 static int intel_overlay_on(struct intel_overlay *overlay)
248 {
249 struct drm_i915_private *dev_priv = overlay->i915;
250 struct i915_request *rq;
251 u32 *cs;
252
253 drm_WARN_ON(&dev_priv->drm, overlay->active);
254
255 rq = alloc_request(overlay, NULL);
256 if (IS_ERR(rq))
257 return PTR_ERR(rq);
258
259 cs = intel_ring_begin(rq, 4);
260 if (IS_ERR(cs)) {
261 i915_request_add(rq);
262 return PTR_ERR(cs);
263 }
264
265 overlay->active = true;
266
267 if (IS_I830(dev_priv))
268 i830_overlay_clock_gating(dev_priv, false);
269
270 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
271 *cs++ = overlay->flip_addr | OFC_UPDATE;
272 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
273 *cs++ = MI_NOOP;
274 intel_ring_advance(rq, cs);
275
276 i915_request_add(rq);
277
278 return i915_active_wait(&overlay->last_flip);
279 }
280
intel_overlay_flip_prepare(struct intel_overlay * overlay,struct i915_vma * vma)281 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
282 struct i915_vma *vma)
283 {
284 enum pipe pipe = overlay->crtc->pipe;
285 struct intel_frontbuffer *from = NULL, *to = NULL;
286
287 drm_WARN_ON(&overlay->i915->drm, overlay->old_vma);
288
289 if (overlay->vma)
290 from = intel_frontbuffer_get(overlay->vma->obj);
291 if (vma)
292 to = intel_frontbuffer_get(vma->obj);
293
294 intel_frontbuffer_track(from, to, INTEL_FRONTBUFFER_OVERLAY(pipe));
295
296 if (to)
297 intel_frontbuffer_put(to);
298 if (from)
299 intel_frontbuffer_put(from);
300
301 intel_frontbuffer_flip_prepare(overlay->i915,
302 INTEL_FRONTBUFFER_OVERLAY(pipe));
303
304 overlay->old_vma = overlay->vma;
305 if (vma)
306 overlay->vma = i915_vma_get(vma);
307 else
308 overlay->vma = NULL;
309 }
310
311 /* overlay needs to be enabled in OCMD reg */
intel_overlay_continue(struct intel_overlay * overlay,struct i915_vma * vma,bool load_polyphase_filter)312 static int intel_overlay_continue(struct intel_overlay *overlay,
313 struct i915_vma *vma,
314 bool load_polyphase_filter)
315 {
316 struct drm_i915_private *dev_priv = overlay->i915;
317 struct i915_request *rq;
318 u32 flip_addr = overlay->flip_addr;
319 u32 tmp, *cs;
320
321 drm_WARN_ON(&dev_priv->drm, !overlay->active);
322
323 if (load_polyphase_filter)
324 flip_addr |= OFC_UPDATE;
325
326 /* check for underruns */
327 tmp = intel_de_read(dev_priv, DOVSTA);
328 if (tmp & (1 << 17))
329 drm_dbg(&dev_priv->drm, "overlay underrun, DOVSTA: %x\n", tmp);
330
331 rq = alloc_request(overlay, NULL);
332 if (IS_ERR(rq))
333 return PTR_ERR(rq);
334
335 cs = intel_ring_begin(rq, 2);
336 if (IS_ERR(cs)) {
337 i915_request_add(rq);
338 return PTR_ERR(cs);
339 }
340
341 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
342 *cs++ = flip_addr;
343 intel_ring_advance(rq, cs);
344
345 intel_overlay_flip_prepare(overlay, vma);
346 i915_request_add(rq);
347
348 return 0;
349 }
350
intel_overlay_release_old_vma(struct intel_overlay * overlay)351 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
352 {
353 struct i915_vma *vma;
354
355 vma = fetch_and_zero(&overlay->old_vma);
356 if (drm_WARN_ON(&overlay->i915->drm, !vma))
357 return;
358
359 intel_frontbuffer_flip_complete(overlay->i915,
360 INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
361
362 i915_gem_object_unpin_from_display_plane(vma);
363 i915_vma_put(vma);
364 }
365
366 static void
intel_overlay_release_old_vid_tail(struct intel_overlay * overlay)367 intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
368 {
369 intel_overlay_release_old_vma(overlay);
370 }
371
intel_overlay_off_tail(struct intel_overlay * overlay)372 static void intel_overlay_off_tail(struct intel_overlay *overlay)
373 {
374 struct drm_i915_private *dev_priv = overlay->i915;
375
376 intel_overlay_release_old_vma(overlay);
377
378 overlay->crtc->overlay = NULL;
379 overlay->crtc = NULL;
380 overlay->active = false;
381
382 if (IS_I830(dev_priv))
383 i830_overlay_clock_gating(dev_priv, true);
384 }
385
386 static void
intel_overlay_last_flip_retire(struct i915_active * active)387 intel_overlay_last_flip_retire(struct i915_active *active)
388 {
389 struct intel_overlay *overlay =
390 container_of(active, typeof(*overlay), last_flip);
391
392 if (overlay->flip_complete)
393 overlay->flip_complete(overlay);
394 }
395
396 /* overlay needs to be disabled in OCMD reg */
intel_overlay_off(struct intel_overlay * overlay)397 static int intel_overlay_off(struct intel_overlay *overlay)
398 {
399 struct i915_request *rq;
400 u32 *cs, flip_addr = overlay->flip_addr;
401
402 drm_WARN_ON(&overlay->i915->drm, !overlay->active);
403
404 /* According to intel docs the overlay hw may hang (when switching
405 * off) without loading the filter coeffs. It is however unclear whether
406 * this applies to the disabling of the overlay or to the switching off
407 * of the hw. Do it in both cases */
408 flip_addr |= OFC_UPDATE;
409
410 rq = alloc_request(overlay, intel_overlay_off_tail);
411 if (IS_ERR(rq))
412 return PTR_ERR(rq);
413
414 cs = intel_ring_begin(rq, 6);
415 if (IS_ERR(cs)) {
416 i915_request_add(rq);
417 return PTR_ERR(cs);
418 }
419
420 /* wait for overlay to go idle */
421 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
422 *cs++ = flip_addr;
423 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
424
425 /* turn overlay off */
426 *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
427 *cs++ = flip_addr;
428 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
429
430 intel_ring_advance(rq, cs);
431
432 intel_overlay_flip_prepare(overlay, NULL);
433 i915_request_add(rq);
434
435 return i915_active_wait(&overlay->last_flip);
436 }
437
438 /* recover from an interruption due to a signal
439 * We have to be careful not to repeat work forever an make forward progess. */
intel_overlay_recover_from_interrupt(struct intel_overlay * overlay)440 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
441 {
442 return i915_active_wait(&overlay->last_flip);
443 }
444
445 /* Wait for pending overlay flip and release old frame.
446 * Needs to be called before the overlay register are changed
447 * via intel_overlay_(un)map_regs
448 */
intel_overlay_release_old_vid(struct intel_overlay * overlay)449 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
450 {
451 struct drm_i915_private *dev_priv = overlay->i915;
452 struct i915_request *rq;
453 u32 *cs;
454
455 /*
456 * Only wait if there is actually an old frame to release to
457 * guarantee forward progress.
458 */
459 if (!overlay->old_vma)
460 return 0;
461
462 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) {
463 intel_overlay_release_old_vid_tail(overlay);
464 return 0;
465 }
466
467 rq = alloc_request(overlay, intel_overlay_release_old_vid_tail);
468 if (IS_ERR(rq))
469 return PTR_ERR(rq);
470
471 cs = intel_ring_begin(rq, 2);
472 if (IS_ERR(cs)) {
473 i915_request_add(rq);
474 return PTR_ERR(cs);
475 }
476
477 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
478 *cs++ = MI_NOOP;
479 intel_ring_advance(rq, cs);
480
481 i915_request_add(rq);
482
483 return i915_active_wait(&overlay->last_flip);
484 }
485
intel_overlay_reset(struct drm_i915_private * dev_priv)486 void intel_overlay_reset(struct drm_i915_private *dev_priv)
487 {
488 struct intel_overlay *overlay = dev_priv->overlay;
489
490 if (!overlay)
491 return;
492
493 overlay->old_xscale = 0;
494 overlay->old_yscale = 0;
495 overlay->crtc = NULL;
496 overlay->active = false;
497 }
498
packed_depth_bytes(u32 format)499 static int packed_depth_bytes(u32 format)
500 {
501 switch (format & I915_OVERLAY_DEPTH_MASK) {
502 case I915_OVERLAY_YUV422:
503 return 4;
504 case I915_OVERLAY_YUV411:
505 /* return 6; not implemented */
506 default:
507 return -EINVAL;
508 }
509 }
510
packed_width_bytes(u32 format,short width)511 static int packed_width_bytes(u32 format, short width)
512 {
513 switch (format & I915_OVERLAY_DEPTH_MASK) {
514 case I915_OVERLAY_YUV422:
515 return width << 1;
516 default:
517 return -EINVAL;
518 }
519 }
520
uv_hsubsampling(u32 format)521 static int uv_hsubsampling(u32 format)
522 {
523 switch (format & I915_OVERLAY_DEPTH_MASK) {
524 case I915_OVERLAY_YUV422:
525 case I915_OVERLAY_YUV420:
526 return 2;
527 case I915_OVERLAY_YUV411:
528 case I915_OVERLAY_YUV410:
529 return 4;
530 default:
531 return -EINVAL;
532 }
533 }
534
uv_vsubsampling(u32 format)535 static int uv_vsubsampling(u32 format)
536 {
537 switch (format & I915_OVERLAY_DEPTH_MASK) {
538 case I915_OVERLAY_YUV420:
539 case I915_OVERLAY_YUV410:
540 return 2;
541 case I915_OVERLAY_YUV422:
542 case I915_OVERLAY_YUV411:
543 return 1;
544 default:
545 return -EINVAL;
546 }
547 }
548
calc_swidthsw(struct drm_i915_private * dev_priv,u32 offset,u32 width)549 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
550 {
551 u32 sw;
552
553 if (IS_GEN(dev_priv, 2))
554 sw = ALIGN((offset & 31) + width, 32);
555 else
556 sw = ALIGN((offset & 63) + width, 64);
557
558 if (sw == 0)
559 return 0;
560
561 return (sw - 32) >> 3;
562 }
563
564 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
565 [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
566 [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
567 [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
568 [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
569 [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
570 [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
571 [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
572 [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
573 [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
574 [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
575 [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
576 [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
577 [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
578 [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
579 [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
580 [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
581 [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
582 };
583
584 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
585 [ 0] = { 0x3000, 0x1800, 0x1800, },
586 [ 1] = { 0xb000, 0x18d0, 0x2e60, },
587 [ 2] = { 0xb000, 0x1990, 0x2ce0, },
588 [ 3] = { 0xb020, 0x1a68, 0x2b40, },
589 [ 4] = { 0xb040, 0x1b20, 0x29e0, },
590 [ 5] = { 0xb060, 0x1bd8, 0x2880, },
591 [ 6] = { 0xb080, 0x1c88, 0x3e60, },
592 [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
593 [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
594 [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
595 [10] = { 0xb100, 0x1eb8, 0x3620, },
596 [11] = { 0xb100, 0x1f18, 0x34a0, },
597 [12] = { 0xb100, 0x1f68, 0x3360, },
598 [13] = { 0xb0e0, 0x1fa8, 0x3240, },
599 [14] = { 0xb0c0, 0x1fe0, 0x3140, },
600 [15] = { 0xb060, 0x1ff0, 0x30a0, },
601 [16] = { 0x3000, 0x0800, 0x3000, },
602 };
603
update_polyphase_filter(struct overlay_registers __iomem * regs)604 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
605 {
606 memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
607 memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
608 sizeof(uv_static_hcoeffs));
609 }
610
update_scaling_factors(struct intel_overlay * overlay,struct overlay_registers __iomem * regs,struct drm_intel_overlay_put_image * params)611 static bool update_scaling_factors(struct intel_overlay *overlay,
612 struct overlay_registers __iomem *regs,
613 struct drm_intel_overlay_put_image *params)
614 {
615 /* fixed point with a 12 bit shift */
616 u32 xscale, yscale, xscale_UV, yscale_UV;
617 #define FP_SHIFT 12
618 #define FRACT_MASK 0xfff
619 bool scale_changed = false;
620 int uv_hscale = uv_hsubsampling(params->flags);
621 int uv_vscale = uv_vsubsampling(params->flags);
622
623 if (params->dst_width > 1)
624 xscale = ((params->src_scan_width - 1) << FP_SHIFT) /
625 params->dst_width;
626 else
627 xscale = 1 << FP_SHIFT;
628
629 if (params->dst_height > 1)
630 yscale = ((params->src_scan_height - 1) << FP_SHIFT) /
631 params->dst_height;
632 else
633 yscale = 1 << FP_SHIFT;
634
635 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
636 xscale_UV = xscale/uv_hscale;
637 yscale_UV = yscale/uv_vscale;
638 /* make the Y scale to UV scale ratio an exact multiply */
639 xscale = xscale_UV * uv_hscale;
640 yscale = yscale_UV * uv_vscale;
641 /*} else {
642 xscale_UV = 0;
643 yscale_UV = 0;
644 }*/
645
646 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
647 scale_changed = true;
648 overlay->old_xscale = xscale;
649 overlay->old_yscale = yscale;
650
651 iowrite32(((yscale & FRACT_MASK) << 20) |
652 ((xscale >> FP_SHIFT) << 16) |
653 ((xscale & FRACT_MASK) << 3),
654 ®s->YRGBSCALE);
655
656 iowrite32(((yscale_UV & FRACT_MASK) << 20) |
657 ((xscale_UV >> FP_SHIFT) << 16) |
658 ((xscale_UV & FRACT_MASK) << 3),
659 ®s->UVSCALE);
660
661 iowrite32((((yscale >> FP_SHIFT) << 16) |
662 ((yscale_UV >> FP_SHIFT) << 0)),
663 ®s->UVSCALEV);
664
665 if (scale_changed)
666 update_polyphase_filter(regs);
667
668 return scale_changed;
669 }
670
update_colorkey(struct intel_overlay * overlay,struct overlay_registers __iomem * regs)671 static void update_colorkey(struct intel_overlay *overlay,
672 struct overlay_registers __iomem *regs)
673 {
674 const struct intel_plane_state *state =
675 to_intel_plane_state(overlay->crtc->base.primary->state);
676 u32 key = overlay->color_key;
677 u32 format = 0;
678 u32 flags = 0;
679
680 if (overlay->color_key_enabled)
681 flags |= DST_KEY_ENABLE;
682
683 if (state->uapi.visible)
684 format = state->hw.fb->format->format;
685
686 switch (format) {
687 case DRM_FORMAT_C8:
688 key = RGB8I_TO_COLORKEY(key);
689 flags |= CLK_RGB24_MASK;
690 break;
691 case DRM_FORMAT_XRGB1555:
692 key = RGB15_TO_COLORKEY(key);
693 flags |= CLK_RGB15_MASK;
694 break;
695 case DRM_FORMAT_RGB565:
696 key = RGB16_TO_COLORKEY(key);
697 flags |= CLK_RGB16_MASK;
698 break;
699 case DRM_FORMAT_XRGB2101010:
700 case DRM_FORMAT_XBGR2101010:
701 key = RGB30_TO_COLORKEY(key);
702 flags |= CLK_RGB24_MASK;
703 break;
704 default:
705 flags |= CLK_RGB24_MASK;
706 break;
707 }
708
709 iowrite32(key, ®s->DCLRKV);
710 iowrite32(flags, ®s->DCLRKM);
711 }
712
overlay_cmd_reg(struct drm_intel_overlay_put_image * params)713 static u32 overlay_cmd_reg(struct drm_intel_overlay_put_image *params)
714 {
715 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
716
717 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
718 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
719 case I915_OVERLAY_YUV422:
720 cmd |= OCMD_YUV_422_PLANAR;
721 break;
722 case I915_OVERLAY_YUV420:
723 cmd |= OCMD_YUV_420_PLANAR;
724 break;
725 case I915_OVERLAY_YUV411:
726 case I915_OVERLAY_YUV410:
727 cmd |= OCMD_YUV_410_PLANAR;
728 break;
729 }
730 } else { /* YUV packed */
731 switch (params->flags & I915_OVERLAY_DEPTH_MASK) {
732 case I915_OVERLAY_YUV422:
733 cmd |= OCMD_YUV_422_PACKED;
734 break;
735 case I915_OVERLAY_YUV411:
736 cmd |= OCMD_YUV_411_PACKED;
737 break;
738 }
739
740 switch (params->flags & I915_OVERLAY_SWAP_MASK) {
741 case I915_OVERLAY_NO_SWAP:
742 break;
743 case I915_OVERLAY_UV_SWAP:
744 cmd |= OCMD_UV_SWAP;
745 break;
746 case I915_OVERLAY_Y_SWAP:
747 cmd |= OCMD_Y_SWAP;
748 break;
749 case I915_OVERLAY_Y_AND_UV_SWAP:
750 cmd |= OCMD_Y_AND_UV_SWAP;
751 break;
752 }
753 }
754
755 return cmd;
756 }
757
intel_overlay_do_put_image(struct intel_overlay * overlay,struct drm_i915_gem_object * new_bo,struct drm_intel_overlay_put_image * params)758 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
759 struct drm_i915_gem_object *new_bo,
760 struct drm_intel_overlay_put_image *params)
761 {
762 struct overlay_registers __iomem *regs = overlay->regs;
763 struct drm_i915_private *dev_priv = overlay->i915;
764 u32 swidth, swidthsw, sheight, ostride;
765 enum pipe pipe = overlay->crtc->pipe;
766 bool scale_changed = false;
767 struct i915_vma *vma;
768 int ret, tmp_width;
769
770 drm_WARN_ON(&dev_priv->drm,
771 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
772
773 ret = intel_overlay_release_old_vid(overlay);
774 if (ret != 0)
775 return ret;
776
777 atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
778
779 vma = i915_gem_object_pin_to_display_plane(new_bo,
780 0, NULL, PIN_MAPPABLE);
781 if (IS_ERR(vma)) {
782 ret = PTR_ERR(vma);
783 goto out_pin_section;
784 }
785 i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
786
787 if (!overlay->active) {
788 const struct intel_crtc_state *crtc_state =
789 overlay->crtc->config;
790 u32 oconfig = 0;
791
792 if (crtc_state->gamma_enable &&
793 crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
794 oconfig |= OCONF_CC_OUT_8BIT;
795 if (crtc_state->gamma_enable)
796 oconfig |= OCONF_GAMMA2_ENABLE;
797 if (IS_GEN(dev_priv, 4))
798 oconfig |= OCONF_CSC_MODE_BT709;
799 oconfig |= pipe == 0 ?
800 OCONF_PIPE_A : OCONF_PIPE_B;
801 iowrite32(oconfig, ®s->OCONFIG);
802
803 ret = intel_overlay_on(overlay);
804 if (ret != 0)
805 goto out_unpin;
806 }
807
808 iowrite32(params->dst_y << 16 | params->dst_x, ®s->DWINPOS);
809 iowrite32(params->dst_height << 16 | params->dst_width, ®s->DWINSZ);
810
811 if (params->flags & I915_OVERLAY_YUV_PACKED)
812 tmp_width = packed_width_bytes(params->flags,
813 params->src_width);
814 else
815 tmp_width = params->src_width;
816
817 swidth = params->src_width;
818 swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
819 sheight = params->src_height;
820 iowrite32(i915_ggtt_offset(vma) + params->offset_Y, ®s->OBUF_0Y);
821 ostride = params->stride_Y;
822
823 if (params->flags & I915_OVERLAY_YUV_PLANAR) {
824 int uv_hscale = uv_hsubsampling(params->flags);
825 int uv_vscale = uv_vsubsampling(params->flags);
826 u32 tmp_U, tmp_V;
827
828 swidth |= (params->src_width / uv_hscale) << 16;
829 sheight |= (params->src_height / uv_vscale) << 16;
830
831 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
832 params->src_width / uv_hscale);
833 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
834 params->src_width / uv_hscale);
835 swidthsw |= max(tmp_U, tmp_V) << 16;
836
837 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
838 ®s->OBUF_0U);
839 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
840 ®s->OBUF_0V);
841
842 ostride |= params->stride_UV << 16;
843 }
844
845 iowrite32(swidth, ®s->SWIDTH);
846 iowrite32(swidthsw, ®s->SWIDTHSW);
847 iowrite32(sheight, ®s->SHEIGHT);
848 iowrite32(ostride, ®s->OSTRIDE);
849
850 scale_changed = update_scaling_factors(overlay, regs, params);
851
852 update_colorkey(overlay, regs);
853
854 iowrite32(overlay_cmd_reg(params), ®s->OCMD);
855
856 ret = intel_overlay_continue(overlay, vma, scale_changed);
857 if (ret)
858 goto out_unpin;
859
860 return 0;
861
862 out_unpin:
863 i915_gem_object_unpin_from_display_plane(vma);
864 out_pin_section:
865 atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
866
867 return ret;
868 }
869
intel_overlay_switch_off(struct intel_overlay * overlay)870 int intel_overlay_switch_off(struct intel_overlay *overlay)
871 {
872 struct drm_i915_private *dev_priv = overlay->i915;
873 int ret;
874
875 drm_WARN_ON(&dev_priv->drm,
876 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
877
878 ret = intel_overlay_recover_from_interrupt(overlay);
879 if (ret != 0)
880 return ret;
881
882 if (!overlay->active)
883 return 0;
884
885 ret = intel_overlay_release_old_vid(overlay);
886 if (ret != 0)
887 return ret;
888
889 iowrite32(0, &overlay->regs->OCMD);
890
891 return intel_overlay_off(overlay);
892 }
893
check_overlay_possible_on_crtc(struct intel_overlay * overlay,struct intel_crtc * crtc)894 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
895 struct intel_crtc *crtc)
896 {
897 if (!crtc->active)
898 return -EINVAL;
899
900 /* can't use the overlay with double wide pipe */
901 if (crtc->config->double_wide)
902 return -EINVAL;
903
904 return 0;
905 }
906
update_pfit_vscale_ratio(struct intel_overlay * overlay)907 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
908 {
909 struct drm_i915_private *dev_priv = overlay->i915;
910 u32 pfit_control = intel_de_read(dev_priv, PFIT_CONTROL);
911 u32 ratio;
912
913 /* XXX: This is not the same logic as in the xorg driver, but more in
914 * line with the intel documentation for the i965
915 */
916 if (INTEL_GEN(dev_priv) >= 4) {
917 /* on i965 use the PGM reg to read out the autoscaler values */
918 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
919 } else {
920 if (pfit_control & VERT_AUTO_SCALE)
921 ratio = intel_de_read(dev_priv, PFIT_AUTO_RATIOS);
922 else
923 ratio = intel_de_read(dev_priv, PFIT_PGM_RATIOS);
924 ratio >>= PFIT_VERT_SCALE_SHIFT;
925 }
926
927 overlay->pfit_vscale_ratio = ratio;
928 }
929
check_overlay_dst(struct intel_overlay * overlay,struct drm_intel_overlay_put_image * rec)930 static int check_overlay_dst(struct intel_overlay *overlay,
931 struct drm_intel_overlay_put_image *rec)
932 {
933 const struct intel_crtc_state *pipe_config =
934 overlay->crtc->config;
935
936 if (rec->dst_x < pipe_config->pipe_src_w &&
937 rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
938 rec->dst_y < pipe_config->pipe_src_h &&
939 rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
940 return 0;
941 else
942 return -EINVAL;
943 }
944
check_overlay_scaling(struct drm_intel_overlay_put_image * rec)945 static int check_overlay_scaling(struct drm_intel_overlay_put_image *rec)
946 {
947 u32 tmp;
948
949 /* downscaling limit is 8.0 */
950 tmp = ((rec->src_scan_height << 16) / rec->dst_height) >> 16;
951 if (tmp > 7)
952 return -EINVAL;
953
954 tmp = ((rec->src_scan_width << 16) / rec->dst_width) >> 16;
955 if (tmp > 7)
956 return -EINVAL;
957
958 return 0;
959 }
960
check_overlay_src(struct drm_i915_private * dev_priv,struct drm_intel_overlay_put_image * rec,struct drm_i915_gem_object * new_bo)961 static int check_overlay_src(struct drm_i915_private *dev_priv,
962 struct drm_intel_overlay_put_image *rec,
963 struct drm_i915_gem_object *new_bo)
964 {
965 int uv_hscale = uv_hsubsampling(rec->flags);
966 int uv_vscale = uv_vsubsampling(rec->flags);
967 u32 stride_mask;
968 int depth;
969 u32 tmp;
970
971 /* check src dimensions */
972 if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
973 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
974 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
975 return -EINVAL;
976 } else {
977 if (rec->src_height > IMAGE_MAX_HEIGHT ||
978 rec->src_width > IMAGE_MAX_WIDTH)
979 return -EINVAL;
980 }
981
982 /* better safe than sorry, use 4 as the maximal subsampling ratio */
983 if (rec->src_height < N_VERT_Y_TAPS*4 ||
984 rec->src_width < N_HORIZ_Y_TAPS*4)
985 return -EINVAL;
986
987 /* check alignment constraints */
988 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
989 case I915_OVERLAY_RGB:
990 /* not implemented */
991 return -EINVAL;
992
993 case I915_OVERLAY_YUV_PACKED:
994 if (uv_vscale != 1)
995 return -EINVAL;
996
997 depth = packed_depth_bytes(rec->flags);
998 if (depth < 0)
999 return depth;
1000
1001 /* ignore UV planes */
1002 rec->stride_UV = 0;
1003 rec->offset_U = 0;
1004 rec->offset_V = 0;
1005 /* check pixel alignment */
1006 if (rec->offset_Y % depth)
1007 return -EINVAL;
1008 break;
1009
1010 case I915_OVERLAY_YUV_PLANAR:
1011 if (uv_vscale < 0 || uv_hscale < 0)
1012 return -EINVAL;
1013 /* no offset restrictions for planar formats */
1014 break;
1015
1016 default:
1017 return -EINVAL;
1018 }
1019
1020 if (rec->src_width % uv_hscale)
1021 return -EINVAL;
1022
1023 /* stride checking */
1024 if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1025 stride_mask = 255;
1026 else
1027 stride_mask = 63;
1028
1029 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1030 return -EINVAL;
1031 if (IS_GEN(dev_priv, 4) && rec->stride_Y < 512)
1032 return -EINVAL;
1033
1034 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1035 4096 : 8192;
1036 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1037 return -EINVAL;
1038
1039 /* check buffer dimensions */
1040 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1041 case I915_OVERLAY_RGB:
1042 case I915_OVERLAY_YUV_PACKED:
1043 /* always 4 Y values per depth pixels */
1044 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1045 return -EINVAL;
1046
1047 tmp = rec->stride_Y*rec->src_height;
1048 if (rec->offset_Y + tmp > new_bo->base.size)
1049 return -EINVAL;
1050 break;
1051
1052 case I915_OVERLAY_YUV_PLANAR:
1053 if (rec->src_width > rec->stride_Y)
1054 return -EINVAL;
1055 if (rec->src_width/uv_hscale > rec->stride_UV)
1056 return -EINVAL;
1057
1058 tmp = rec->stride_Y * rec->src_height;
1059 if (rec->offset_Y + tmp > new_bo->base.size)
1060 return -EINVAL;
1061
1062 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1063 if (rec->offset_U + tmp > new_bo->base.size ||
1064 rec->offset_V + tmp > new_bo->base.size)
1065 return -EINVAL;
1066 break;
1067 }
1068
1069 return 0;
1070 }
1071
intel_overlay_put_image_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)1072 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1073 struct drm_file *file_priv)
1074 {
1075 struct drm_intel_overlay_put_image *params = data;
1076 struct drm_i915_private *dev_priv = to_i915(dev);
1077 struct intel_overlay *overlay;
1078 struct drm_crtc *drmmode_crtc;
1079 struct intel_crtc *crtc;
1080 struct drm_i915_gem_object *new_bo;
1081 int ret;
1082
1083 overlay = dev_priv->overlay;
1084 if (!overlay) {
1085 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1086 return -ENODEV;
1087 }
1088
1089 if (!(params->flags & I915_OVERLAY_ENABLE)) {
1090 drm_modeset_lock_all(dev);
1091 ret = intel_overlay_switch_off(overlay);
1092 drm_modeset_unlock_all(dev);
1093
1094 return ret;
1095 }
1096
1097 drmmode_crtc = drm_crtc_find(dev, file_priv, params->crtc_id);
1098 if (!drmmode_crtc)
1099 return -ENOENT;
1100 crtc = to_intel_crtc(drmmode_crtc);
1101
1102 new_bo = i915_gem_object_lookup(file_priv, params->bo_handle);
1103 if (!new_bo)
1104 return -ENOENT;
1105
1106 drm_modeset_lock_all(dev);
1107
1108 if (i915_gem_object_is_tiled(new_bo)) {
1109 drm_dbg_kms(&dev_priv->drm,
1110 "buffer used for overlay image can not be tiled\n");
1111 ret = -EINVAL;
1112 goto out_unlock;
1113 }
1114
1115 ret = intel_overlay_recover_from_interrupt(overlay);
1116 if (ret != 0)
1117 goto out_unlock;
1118
1119 if (overlay->crtc != crtc) {
1120 ret = intel_overlay_switch_off(overlay);
1121 if (ret != 0)
1122 goto out_unlock;
1123
1124 ret = check_overlay_possible_on_crtc(overlay, crtc);
1125 if (ret != 0)
1126 goto out_unlock;
1127
1128 overlay->crtc = crtc;
1129 crtc->overlay = overlay;
1130
1131 /* line too wide, i.e. one-line-mode */
1132 if (crtc->config->pipe_src_w > 1024 &&
1133 crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1134 overlay->pfit_active = true;
1135 update_pfit_vscale_ratio(overlay);
1136 } else
1137 overlay->pfit_active = false;
1138 }
1139
1140 ret = check_overlay_dst(overlay, params);
1141 if (ret != 0)
1142 goto out_unlock;
1143
1144 if (overlay->pfit_active) {
1145 params->dst_y = (((u32)params->dst_y << 12) /
1146 overlay->pfit_vscale_ratio);
1147 /* shifting right rounds downwards, so add 1 */
1148 params->dst_height = (((u32)params->dst_height << 12) /
1149 overlay->pfit_vscale_ratio) + 1;
1150 }
1151
1152 if (params->src_scan_height > params->src_height ||
1153 params->src_scan_width > params->src_width) {
1154 ret = -EINVAL;
1155 goto out_unlock;
1156 }
1157
1158 ret = check_overlay_src(dev_priv, params, new_bo);
1159 if (ret != 0)
1160 goto out_unlock;
1161
1162 /* Check scaling after src size to prevent a divide-by-zero. */
1163 ret = check_overlay_scaling(params);
1164 if (ret != 0)
1165 goto out_unlock;
1166
1167 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1168 if (ret != 0)
1169 goto out_unlock;
1170
1171 drm_modeset_unlock_all(dev);
1172 i915_gem_object_put(new_bo);
1173
1174 return 0;
1175
1176 out_unlock:
1177 drm_modeset_unlock_all(dev);
1178 i915_gem_object_put(new_bo);
1179
1180 return ret;
1181 }
1182
update_reg_attrs(struct intel_overlay * overlay,struct overlay_registers __iomem * regs)1183 static void update_reg_attrs(struct intel_overlay *overlay,
1184 struct overlay_registers __iomem *regs)
1185 {
1186 iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1187 ®s->OCLRC0);
1188 iowrite32(overlay->saturation, ®s->OCLRC1);
1189 }
1190
check_gamma_bounds(u32 gamma1,u32 gamma2)1191 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1192 {
1193 int i;
1194
1195 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1196 return false;
1197
1198 for (i = 0; i < 3; i++) {
1199 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1200 return false;
1201 }
1202
1203 return true;
1204 }
1205
check_gamma5_errata(u32 gamma5)1206 static bool check_gamma5_errata(u32 gamma5)
1207 {
1208 int i;
1209
1210 for (i = 0; i < 3; i++) {
1211 if (((gamma5 >> i*8) & 0xff) == 0x80)
1212 return false;
1213 }
1214
1215 return true;
1216 }
1217
check_gamma(struct drm_intel_overlay_attrs * attrs)1218 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1219 {
1220 if (!check_gamma_bounds(0, attrs->gamma0) ||
1221 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1222 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1223 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1224 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1225 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1226 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1227 return -EINVAL;
1228
1229 if (!check_gamma5_errata(attrs->gamma5))
1230 return -EINVAL;
1231
1232 return 0;
1233 }
1234
intel_overlay_attrs_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)1235 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1236 struct drm_file *file_priv)
1237 {
1238 struct drm_intel_overlay_attrs *attrs = data;
1239 struct drm_i915_private *dev_priv = to_i915(dev);
1240 struct intel_overlay *overlay;
1241 int ret;
1242
1243 overlay = dev_priv->overlay;
1244 if (!overlay) {
1245 drm_dbg(&dev_priv->drm, "userspace bug: no overlay\n");
1246 return -ENODEV;
1247 }
1248
1249 drm_modeset_lock_all(dev);
1250
1251 ret = -EINVAL;
1252 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1253 attrs->color_key = overlay->color_key;
1254 attrs->brightness = overlay->brightness;
1255 attrs->contrast = overlay->contrast;
1256 attrs->saturation = overlay->saturation;
1257
1258 if (!IS_GEN(dev_priv, 2)) {
1259 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0);
1260 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1);
1261 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2);
1262 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3);
1263 attrs->gamma4 = intel_de_read(dev_priv, OGAMC4);
1264 attrs->gamma5 = intel_de_read(dev_priv, OGAMC5);
1265 }
1266 } else {
1267 if (attrs->brightness < -128 || attrs->brightness > 127)
1268 goto out_unlock;
1269 if (attrs->contrast > 255)
1270 goto out_unlock;
1271 if (attrs->saturation > 1023)
1272 goto out_unlock;
1273
1274 overlay->color_key = attrs->color_key;
1275 overlay->brightness = attrs->brightness;
1276 overlay->contrast = attrs->contrast;
1277 overlay->saturation = attrs->saturation;
1278
1279 update_reg_attrs(overlay, overlay->regs);
1280
1281 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1282 if (IS_GEN(dev_priv, 2))
1283 goto out_unlock;
1284
1285 if (overlay->active) {
1286 ret = -EBUSY;
1287 goto out_unlock;
1288 }
1289
1290 ret = check_gamma(attrs);
1291 if (ret)
1292 goto out_unlock;
1293
1294 intel_de_write(dev_priv, OGAMC0, attrs->gamma0);
1295 intel_de_write(dev_priv, OGAMC1, attrs->gamma1);
1296 intel_de_write(dev_priv, OGAMC2, attrs->gamma2);
1297 intel_de_write(dev_priv, OGAMC3, attrs->gamma3);
1298 intel_de_write(dev_priv, OGAMC4, attrs->gamma4);
1299 intel_de_write(dev_priv, OGAMC5, attrs->gamma5);
1300 }
1301 }
1302 overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1303
1304 ret = 0;
1305 out_unlock:
1306 drm_modeset_unlock_all(dev);
1307
1308 return ret;
1309 }
1310
get_registers(struct intel_overlay * overlay,bool use_phys)1311 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1312 {
1313 struct drm_i915_private *i915 = overlay->i915;
1314 struct drm_i915_gem_object *obj;
1315 struct i915_vma *vma;
1316 int err;
1317
1318 obj = i915_gem_object_create_stolen(i915, PAGE_SIZE);
1319 if (IS_ERR(obj))
1320 obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
1321 if (IS_ERR(obj))
1322 return PTR_ERR(obj);
1323
1324 vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1325 if (IS_ERR(vma)) {
1326 err = PTR_ERR(vma);
1327 goto err_put_bo;
1328 }
1329
1330 if (use_phys)
1331 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1332 else
1333 overlay->flip_addr = i915_ggtt_offset(vma);
1334 overlay->regs = i915_vma_pin_iomap(vma);
1335 i915_vma_unpin(vma);
1336
1337 if (IS_ERR(overlay->regs)) {
1338 err = PTR_ERR(overlay->regs);
1339 goto err_put_bo;
1340 }
1341
1342 overlay->reg_bo = obj;
1343 return 0;
1344
1345 err_put_bo:
1346 i915_gem_object_put(obj);
1347 return err;
1348 }
1349
intel_overlay_setup(struct drm_i915_private * dev_priv)1350 void intel_overlay_setup(struct drm_i915_private *dev_priv)
1351 {
1352 struct intel_overlay *overlay;
1353 struct intel_engine_cs *engine;
1354 int ret;
1355
1356 if (!HAS_OVERLAY(dev_priv))
1357 return;
1358
1359 engine = dev_priv->gt.engine[RCS0];
1360 if (!engine || !engine->kernel_context)
1361 return;
1362
1363 overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1364 if (!overlay)
1365 return;
1366
1367 overlay->i915 = dev_priv;
1368 overlay->context = engine->kernel_context;
1369 GEM_BUG_ON(!overlay->context);
1370
1371 overlay->color_key = 0x0101fe;
1372 overlay->color_key_enabled = true;
1373 overlay->brightness = -19;
1374 overlay->contrast = 75;
1375 overlay->saturation = 146;
1376
1377 i915_active_init(&overlay->last_flip,
1378 NULL, intel_overlay_last_flip_retire);
1379
1380 ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1381 if (ret)
1382 goto out_free;
1383
1384 memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1385 update_polyphase_filter(overlay->regs);
1386 update_reg_attrs(overlay, overlay->regs);
1387
1388 dev_priv->overlay = overlay;
1389 drm_info(&dev_priv->drm, "Initialized overlay support.\n");
1390 return;
1391
1392 out_free:
1393 kfree(overlay);
1394 }
1395
intel_overlay_cleanup(struct drm_i915_private * dev_priv)1396 void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
1397 {
1398 struct intel_overlay *overlay;
1399
1400 overlay = fetch_and_zero(&dev_priv->overlay);
1401 if (!overlay)
1402 return;
1403
1404 /*
1405 * The bo's should be free'd by the generic code already.
1406 * Furthermore modesetting teardown happens beforehand so the
1407 * hardware should be off already.
1408 */
1409 drm_WARN_ON(&dev_priv->drm, overlay->active);
1410
1411 i915_gem_object_put(overlay->reg_bo);
1412 i915_active_fini(&overlay->last_flip);
1413
1414 kfree(overlay);
1415 }
1416
1417 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1418
1419 struct intel_overlay_error_state {
1420 struct overlay_registers regs;
1421 unsigned long base;
1422 u32 dovsta;
1423 u32 isr;
1424 };
1425
1426 struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private * dev_priv)1427 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1428 {
1429 struct intel_overlay *overlay = dev_priv->overlay;
1430 struct intel_overlay_error_state *error;
1431
1432 if (!overlay || !overlay->active)
1433 return NULL;
1434
1435 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1436 if (error == NULL)
1437 return NULL;
1438
1439 error->dovsta = intel_de_read(dev_priv, DOVSTA);
1440 error->isr = intel_de_read(dev_priv, GEN2_ISR);
1441 error->base = overlay->flip_addr;
1442
1443 memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1444
1445 return error;
1446 }
1447
1448 void
intel_overlay_print_error_state(struct drm_i915_error_state_buf * m,struct intel_overlay_error_state * error)1449 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1450 struct intel_overlay_error_state *error)
1451 {
1452 i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1453 error->dovsta, error->isr);
1454 i915_error_printf(m, " Register file at 0x%08lx:\n",
1455 error->base);
1456
1457 #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1458 P(OBUF_0Y);
1459 P(OBUF_1Y);
1460 P(OBUF_0U);
1461 P(OBUF_0V);
1462 P(OBUF_1U);
1463 P(OBUF_1V);
1464 P(OSTRIDE);
1465 P(YRGB_VPH);
1466 P(UV_VPH);
1467 P(HORZ_PH);
1468 P(INIT_PHS);
1469 P(DWINPOS);
1470 P(DWINSZ);
1471 P(SWIDTH);
1472 P(SWIDTHSW);
1473 P(SHEIGHT);
1474 P(YRGBSCALE);
1475 P(UVSCALE);
1476 P(OCLRC0);
1477 P(OCLRC1);
1478 P(DCLRKV);
1479 P(DCLRKM);
1480 P(SCLRKVH);
1481 P(SCLRKVL);
1482 P(SCLRKEN);
1483 P(OCONFIG);
1484 P(OCMD);
1485 P(OSTART_0Y);
1486 P(OSTART_1Y);
1487 P(OSTART_0U);
1488 P(OSTART_0V);
1489 P(OSTART_1U);
1490 P(OSTART_1V);
1491 P(OTILEOFF_0Y);
1492 P(OTILEOFF_1Y);
1493 P(OTILEOFF_0U);
1494 P(OTILEOFF_0V);
1495 P(OTILEOFF_1U);
1496 P(OTILEOFF_1V);
1497 P(FASTHSCALE);
1498 P(UVSCALEV);
1499 #undef P
1500 }
1501
1502 #endif
1503
