1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2019 Intel Corporation
4 */
5
6 #include <linux/util_macros.h>
7
8 #include "intel_de.h"
9 #include "intel_display_types.h"
10 #include "intel_snps_phy.h"
11
12 /**
13 * DOC: Synopsis PHY support
14 *
15 * Synopsis PHYs are primarily programmed by looking up magic register values
16 * in tables rather than calculating the necessary values at runtime.
17 *
18 * Of special note is that the SNPS PHYs include a dedicated port PLL, known as
19 * an "MPLLB." The MPLLB replaces the shared DPLL functionality used on other
20 * platforms and must be programming directly during the modeset sequence
21 * since it is not handled by the shared DPLL framework as on other platforms.
22 */
23
intel_snps_phy_wait_for_calibration(struct drm_i915_private * dev_priv)24 void intel_snps_phy_wait_for_calibration(struct drm_i915_private *dev_priv)
25 {
26 enum phy phy;
27
28 for_each_phy_masked(phy, ~0) {
29 if (!intel_phy_is_snps(dev_priv, phy))
30 continue;
31
32 if (intel_de_wait_for_clear(dev_priv, ICL_PHY_MISC(phy),
33 DG2_PHY_DP_TX_ACK_MASK, 25))
34 DRM_ERROR("SNPS PHY %c failed to calibrate after 25ms.\n",
35 phy);
36 }
37 }
38
intel_snps_phy_update_psr_power_state(struct drm_i915_private * dev_priv,enum phy phy,bool enable)39 void intel_snps_phy_update_psr_power_state(struct drm_i915_private *dev_priv,
40 enum phy phy, bool enable)
41 {
42 u32 val;
43
44 if (!intel_phy_is_snps(dev_priv, phy))
45 return;
46
47 val = REG_FIELD_PREP(SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR,
48 enable ? 2 : 3);
49 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_TX_REQ(phy),
50 SNPS_PHY_TX_REQ_LN_DIS_PWR_STATE_PSR, val);
51 }
52
53 static const u32 dg2_ddi_translations[] = {
54 /* VS 0, pre-emph 0 */
55 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 26),
56
57 /* VS 0, pre-emph 1 */
58 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 33) |
59 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 6),
60
61 /* VS 0, pre-emph 2 */
62 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 38) |
63 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 12),
64
65 /* VS 0, pre-emph 3 */
66 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 43) |
67 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 19),
68
69 /* VS 1, pre-emph 0 */
70 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 39),
71
72 /* VS 1, pre-emph 1 */
73 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 44) |
74 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 8),
75
76 /* VS 1, pre-emph 2 */
77 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 47) |
78 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 15),
79
80 /* VS 2, pre-emph 0 */
81 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 52),
82
83 /* VS 2, pre-emph 1 */
84 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 51) |
85 REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, 10),
86
87 /* VS 3, pre-emph 0 */
88 REG_FIELD_PREP(SNPS_PHY_TX_EQ_MAIN, 62),
89 };
90
intel_snps_phy_ddi_vswing_sequence(struct intel_encoder * encoder,u32 level)91 void intel_snps_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
92 u32 level)
93 {
94 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
95 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
96 int n_entries, ln;
97
98 n_entries = ARRAY_SIZE(dg2_ddi_translations);
99 if (level >= n_entries)
100 level = n_entries - 1;
101
102 for (ln = 0; ln < 4; ln++)
103 intel_de_write(dev_priv, SNPS_PHY_TX_EQ(ln, phy),
104 dg2_ddi_translations[level]);
105 }
106
107 /*
108 * Basic DP link rates with 100 MHz reference clock.
109 */
110
111 static const struct intel_mpllb_state dg2_dp_rbr_100 = {
112 .clock = 162000,
113 .ref_control =
114 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
115 .mpllb_cp =
116 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
117 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
118 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
119 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
120 .mpllb_div =
121 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
122 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
123 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
124 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
125 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
126 .mpllb_div2 =
127 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
128 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
129 .mpllb_fracn1 =
130 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
131 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
132 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
133 .mpllb_fracn2 =
134 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
135 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
136 };
137
138 static const struct intel_mpllb_state dg2_dp_hbr1_100 = {
139 .clock = 270000,
140 .ref_control =
141 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
142 .mpllb_cp =
143 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
144 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
145 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
146 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
147 .mpllb_div =
148 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
149 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
150 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
151 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
152 .mpllb_div2 =
153 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
154 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
155 .mpllb_fracn1 =
156 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
157 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
158 };
159
160 static const struct intel_mpllb_state dg2_dp_hbr2_100 = {
161 .clock = 540000,
162 .ref_control =
163 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
164 .mpllb_cp =
165 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
166 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
167 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
168 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
169 .mpllb_div =
170 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
171 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
172 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
173 .mpllb_div2 =
174 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
175 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 184),
176 .mpllb_fracn1 =
177 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
178 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
179 };
180
181 static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
182 .clock = 810000,
183 .ref_control =
184 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
185 .mpllb_cp =
186 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
187 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
188 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
189 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
190 .mpllb_div =
191 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
192 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
193 .mpllb_div2 =
194 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
195 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 292),
196 .mpllb_fracn1 =
197 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
198 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
199 };
200
201 static const struct intel_mpllb_state *dg2_dp_100_tables[] = {
202 &dg2_dp_rbr_100,
203 &dg2_dp_hbr1_100,
204 &dg2_dp_hbr2_100,
205 &dg2_dp_hbr3_100,
206 NULL,
207 };
208
209 /*
210 * Basic DP link rates with 38.4 MHz reference clock.
211 */
212
213 static const struct intel_mpllb_state dg2_dp_rbr_38_4 = {
214 .clock = 162000,
215 .ref_control =
216 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
217 .mpllb_cp =
218 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
219 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
220 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
221 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
222 .mpllb_div =
223 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
224 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
225 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
226 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
227 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
228 .mpllb_div2 =
229 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
230 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 304),
231 .mpllb_fracn1 =
232 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
233 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
234 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
235 .mpllb_fracn2 =
236 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 49152),
237 };
238
239 static const struct intel_mpllb_state dg2_dp_hbr1_38_4 = {
240 .clock = 270000,
241 .ref_control =
242 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
243 .mpllb_cp =
244 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
245 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
246 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
247 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
248 .mpllb_div =
249 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
250 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
251 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
252 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
253 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
254 .mpllb_div2 =
255 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
256 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
257 .mpllb_fracn1 =
258 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
259 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
260 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
261 .mpllb_fracn2 =
262 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
263 };
264
265 static const struct intel_mpllb_state dg2_dp_hbr2_38_4 = {
266 .clock = 540000,
267 .ref_control =
268 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
269 .mpllb_cp =
270 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
271 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 25) |
272 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
273 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
274 .mpllb_div =
275 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
276 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
277 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
278 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
279 .mpllb_div2 =
280 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
281 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 248),
282 .mpllb_fracn1 =
283 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
284 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
285 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
286 .mpllb_fracn2 =
287 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40960),
288 };
289
290 static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
291 .clock = 810000,
292 .ref_control =
293 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
294 .mpllb_cp =
295 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
296 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
297 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
298 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
299 .mpllb_div =
300 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
301 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
302 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
303 .mpllb_div2 =
304 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
305 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 388),
306 .mpllb_fracn1 =
307 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
308 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
309 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
310 .mpllb_fracn2 =
311 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
312 };
313
314 static const struct intel_mpllb_state *dg2_dp_38_4_tables[] = {
315 &dg2_dp_rbr_38_4,
316 &dg2_dp_hbr1_38_4,
317 &dg2_dp_hbr2_38_4,
318 &dg2_dp_hbr3_38_4,
319 NULL,
320 };
321
322 /*
323 * eDP link rates with 100 MHz reference clock.
324 */
325
326 static const struct intel_mpllb_state dg2_edp_r216 = {
327 .clock = 216000,
328 .ref_control =
329 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
330 .mpllb_cp =
331 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
332 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
333 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
334 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
335 .mpllb_div =
336 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
337 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
338 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
339 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
340 .mpllb_div2 =
341 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
342 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
343 .mpllb_fracn1 =
344 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
345 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
346 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
347 .mpllb_fracn2 =
348 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
349 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
350 .mpllb_sscen =
351 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
352 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
353 .mpllb_sscstep =
354 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
355 };
356
357 static const struct intel_mpllb_state dg2_edp_r243 = {
358 .clock = 243000,
359 .ref_control =
360 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
361 .mpllb_cp =
362 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
363 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
364 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
365 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
366 .mpllb_div =
367 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
368 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
369 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
370 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
371 .mpllb_div2 =
372 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
373 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 356),
374 .mpllb_fracn1 =
375 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
376 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
377 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
378 .mpllb_fracn2 =
379 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
380 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
381 .mpllb_sscen =
382 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
383 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 57331),
384 .mpllb_sscstep =
385 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 73971),
386 };
387
388 static const struct intel_mpllb_state dg2_edp_r324 = {
389 .clock = 324000,
390 .ref_control =
391 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
392 .mpllb_cp =
393 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
394 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 20) |
395 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
396 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
397 .mpllb_div =
398 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
399 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
400 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
401 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
402 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
403 .mpllb_div2 =
404 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
405 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 226),
406 .mpllb_fracn1 =
407 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
408 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
409 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
410 .mpllb_fracn2 =
411 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
412 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 3),
413 .mpllb_sscen =
414 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
415 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 38221),
416 .mpllb_sscstep =
417 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 49314),
418 };
419
420 static const struct intel_mpllb_state dg2_edp_r432 = {
421 .clock = 432000,
422 .ref_control =
423 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
424 .mpllb_cp =
425 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
426 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 19) |
427 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
428 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
429 .mpllb_div =
430 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
431 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
432 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
433 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
434 .mpllb_div2 =
435 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
436 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 312),
437 .mpllb_fracn1 =
438 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
439 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
440 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
441 .mpllb_fracn2 =
442 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
443 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 4),
444 .mpllb_sscen =
445 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
446 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 50961),
447 .mpllb_sscstep =
448 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 65752),
449 };
450
451 static const struct intel_mpllb_state *dg2_edp_tables[] = {
452 &dg2_dp_rbr_100,
453 &dg2_edp_r216,
454 &dg2_edp_r243,
455 &dg2_dp_hbr1_100,
456 &dg2_edp_r324,
457 &dg2_edp_r432,
458 &dg2_dp_hbr2_100,
459 &dg2_dp_hbr3_100,
460 NULL,
461 };
462
463 /*
464 * HDMI link rates with 100 MHz reference clock.
465 */
466
467 static const struct intel_mpllb_state dg2_hdmi_25_175 = {
468 .clock = 25175,
469 .ref_control =
470 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
471 .mpllb_cp =
472 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
473 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
474 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
475 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
476 .mpllb_div =
477 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
478 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
479 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
480 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
481 .mpllb_div2 =
482 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
483 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
484 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
485 .mpllb_fracn1 =
486 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
487 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
488 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 143),
489 .mpllb_fracn2 =
490 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36663) |
491 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 71),
492 .mpllb_sscen =
493 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
494 };
495
496 static const struct intel_mpllb_state dg2_hdmi_27_0 = {
497 .clock = 27000,
498 .ref_control =
499 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
500 .mpllb_cp =
501 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
502 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
503 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
504 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
505 .mpllb_div =
506 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
507 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
508 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
509 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
510 .mpllb_div2 =
511 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
512 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
513 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
514 .mpllb_fracn1 =
515 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
516 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
517 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
518 .mpllb_fracn2 =
519 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
520 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
521 .mpllb_sscen =
522 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
523 };
524
525 static const struct intel_mpllb_state dg2_hdmi_74_25 = {
526 .clock = 74250,
527 .ref_control =
528 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
529 .mpllb_cp =
530 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
531 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
532 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
533 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
534 .mpllb_div =
535 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
536 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
537 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
538 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
539 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
540 .mpllb_div2 =
541 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
542 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
543 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
544 .mpllb_fracn1 =
545 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
546 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
547 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
548 .mpllb_fracn2 =
549 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
550 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
551 .mpllb_sscen =
552 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
553 };
554
555 static const struct intel_mpllb_state dg2_hdmi_148_5 = {
556 .clock = 148500,
557 .ref_control =
558 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
559 .mpllb_cp =
560 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
561 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
562 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
563 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
564 .mpllb_div =
565 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
566 REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
567 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
568 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
569 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
570 .mpllb_div2 =
571 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
572 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
573 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
574 .mpllb_fracn1 =
575 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
576 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
577 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
578 .mpllb_fracn2 =
579 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
580 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
581 .mpllb_sscen =
582 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
583 };
584
585 static const struct intel_mpllb_state dg2_hdmi_594 = {
586 .clock = 594000,
587 .ref_control =
588 REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
589 .mpllb_cp =
590 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
591 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
592 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
593 REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
594 .mpllb_div =
595 REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
596 REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
597 REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
598 REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
599 .mpllb_div2 =
600 REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
601 REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
602 REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
603 .mpllb_fracn1 =
604 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
605 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
606 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 5),
607 .mpllb_fracn2 =
608 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
609 REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2),
610 .mpllb_sscen =
611 REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
612 };
613
614 static const struct intel_mpllb_state *dg2_hdmi_tables[] = {
615 &dg2_hdmi_25_175,
616 &dg2_hdmi_27_0,
617 &dg2_hdmi_74_25,
618 &dg2_hdmi_148_5,
619 &dg2_hdmi_594,
620 NULL,
621 };
622
623 static const struct intel_mpllb_state **
intel_mpllb_tables_get(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)624 intel_mpllb_tables_get(struct intel_crtc_state *crtc_state,
625 struct intel_encoder *encoder)
626 {
627 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
628 return dg2_edp_tables;
629 } else if (intel_crtc_has_dp_encoder(crtc_state)) {
630 /*
631 * FIXME: Initially we're just enabling the "combo" outputs on
632 * port A-D. The MPLLB for those ports takes an input from the
633 * "Display Filter PLL" which always has an output frequency
634 * of 100 MHz, hence the use of the _100 tables below.
635 *
636 * Once we enable port TC1 it will either use the same 100 MHz
637 * "Display Filter PLL" (when strapped to support a native
638 * display connection) or different 38.4 MHz "Filter PLL" when
639 * strapped to support a USB connection, so we'll need to check
640 * that to determine which table to use.
641 */
642 if (0)
643 return dg2_dp_38_4_tables;
644 else
645 return dg2_dp_100_tables;
646 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
647 return dg2_hdmi_tables;
648 }
649
650 MISSING_CASE(encoder->type);
651 return NULL;
652 }
653
intel_mpllb_calc_state(struct intel_crtc_state * crtc_state,struct intel_encoder * encoder)654 int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state,
655 struct intel_encoder *encoder)
656 {
657 const struct intel_mpllb_state **tables;
658 int i;
659
660 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
661 if (intel_snps_phy_check_hdmi_link_rate(crtc_state->port_clock)
662 != MODE_OK) {
663 /*
664 * FIXME: Can only support fixed HDMI frequencies
665 * until we have a proper algorithm under a valid
666 * license.
667 */
668 DRM_DEBUG_KMS("Can't support HDMI link rate %d\n",
669 crtc_state->port_clock);
670 return -EINVAL;
671 }
672 }
673
674 tables = intel_mpllb_tables_get(crtc_state, encoder);
675 if (!tables)
676 return -EINVAL;
677
678 for (i = 0; tables[i]; i++) {
679 if (crtc_state->port_clock <= tables[i]->clock) {
680 crtc_state->mpllb_state = *tables[i];
681 return 0;
682 }
683 }
684
685 return -EINVAL;
686 }
687
intel_mpllb_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)688 void intel_mpllb_enable(struct intel_encoder *encoder,
689 const struct intel_crtc_state *crtc_state)
690 {
691 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
692 const struct intel_mpllb_state *pll_state = &crtc_state->mpllb_state;
693 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
694 i915_reg_t enable_reg = (phy <= PHY_D ?
695 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
696
697 /*
698 * 3. Software programs the following PLL registers for the desired
699 * frequency.
700 */
701 intel_de_write(dev_priv, SNPS_PHY_MPLLB_CP(phy), pll_state->mpllb_cp);
702 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy), pll_state->mpllb_div);
703 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV2(phy), pll_state->mpllb_div2);
704 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy), pll_state->mpllb_sscen);
705 intel_de_write(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy), pll_state->mpllb_sscstep);
706 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy), pll_state->mpllb_fracn1);
707 intel_de_write(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy), pll_state->mpllb_fracn2);
708
709 /*
710 * 4. If the frequency will result in a change to the voltage
711 * requirement, follow the Display Voltage Frequency Switching -
712 * Sequence Before Frequency Change.
713 *
714 * We handle this step in bxt_set_cdclk().
715 */
716
717 /* 5. Software sets DPLL_ENABLE [PLL Enable] to "1". */
718 intel_uncore_rmw(&dev_priv->uncore, enable_reg, 0, PLL_ENABLE);
719
720 /*
721 * 9. Software sets SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "1". This
722 * will keep the PLL running during the DDI lane programming and any
723 * typeC DP cable disconnect. Do not set the force before enabling the
724 * PLL because that will start the PLL before it has sampled the
725 * divider values.
726 */
727 intel_de_write(dev_priv, SNPS_PHY_MPLLB_DIV(phy),
728 pll_state->mpllb_div | SNPS_PHY_MPLLB_FORCE_EN);
729
730 /*
731 * 10. Software polls on register DPLL_ENABLE [PLL Lock] to confirm PLL
732 * is locked at new settings. This register bit is sampling PHY
733 * dp_mpllb_state interface signal.
734 */
735 if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 5))
736 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
737
738 /*
739 * 11. If the frequency will result in a change to the voltage
740 * requirement, follow the Display Voltage Frequency Switching -
741 * Sequence After Frequency Change.
742 *
743 * We handle this step in bxt_set_cdclk().
744 */
745 }
746
intel_mpllb_disable(struct intel_encoder * encoder)747 void intel_mpllb_disable(struct intel_encoder *encoder)
748 {
749 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
750 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
751 i915_reg_t enable_reg = (phy <= PHY_D ?
752 DG2_PLL_ENABLE(phy) : MG_PLL_ENABLE(0));
753
754 /*
755 * 1. If the frequency will result in a change to the voltage
756 * requirement, follow the Display Voltage Frequency Switching -
757 * Sequence Before Frequency Change.
758 *
759 * We handle this step in bxt_set_cdclk().
760 */
761
762 /* 2. Software programs DPLL_ENABLE [PLL Enable] to "0" */
763 intel_uncore_rmw(&dev_priv->uncore, enable_reg, PLL_ENABLE, 0);
764
765 /*
766 * 4. Software programs SNPS_PHY_MPLLB_DIV dp_mpllb_force_en to "0".
767 * This will allow the PLL to stop running.
768 */
769 intel_uncore_rmw(&dev_priv->uncore, SNPS_PHY_MPLLB_DIV(phy),
770 SNPS_PHY_MPLLB_FORCE_EN, 0);
771
772 /*
773 * 5. Software polls DPLL_ENABLE [PLL Lock] for PHY acknowledgment
774 * (dp_txX_ack) that the new transmitter setting request is completed.
775 */
776 if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 5))
777 DRM_ERROR("Port %c PLL not locked\n", phy_name(phy));
778
779 /*
780 * 6. If the frequency will result in a change to the voltage
781 * requirement, follow the Display Voltage Frequency Switching -
782 * Sequence After Frequency Change.
783 *
784 * We handle this step in bxt_set_cdclk().
785 */
786 }
787
intel_mpllb_calc_port_clock(struct intel_encoder * encoder,const struct intel_mpllb_state * pll_state)788 int intel_mpllb_calc_port_clock(struct intel_encoder *encoder,
789 const struct intel_mpllb_state *pll_state)
790 {
791 unsigned int frac_quot = 0, frac_rem = 0, frac_den = 1;
792 unsigned int multiplier, tx_clk_div, refclk;
793 bool frac_en;
794
795 if (0)
796 refclk = 38400;
797 else
798 refclk = 100000;
799
800 refclk >>= REG_FIELD_GET(SNPS_PHY_MPLLB_REF_CLK_DIV, pll_state->mpllb_div2) - 1;
801
802 frac_en = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_EN, pll_state->mpllb_fracn1);
803
804 if (frac_en) {
805 frac_quot = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_QUOT, pll_state->mpllb_fracn2);
806 frac_rem = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_REM, pll_state->mpllb_fracn2);
807 frac_den = REG_FIELD_GET(SNPS_PHY_MPLLB_FRACN_DEN, pll_state->mpllb_fracn1);
808 }
809
810 multiplier = REG_FIELD_GET(SNPS_PHY_MPLLB_MULTIPLIER, pll_state->mpllb_div2) / 2 + 16;
811
812 tx_clk_div = REG_FIELD_GET(SNPS_PHY_MPLLB_TX_CLK_DIV, pll_state->mpllb_div);
813
814 return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, (multiplier << 16) + frac_quot) +
815 DIV_ROUND_CLOSEST(refclk * frac_rem, frac_den),
816 10 << (tx_clk_div + 16));
817 }
818
intel_mpllb_readout_hw_state(struct intel_encoder * encoder,struct intel_mpllb_state * pll_state)819 void intel_mpllb_readout_hw_state(struct intel_encoder *encoder,
820 struct intel_mpllb_state *pll_state)
821 {
822 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
823 enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
824
825 pll_state->mpllb_cp = intel_de_read(dev_priv, SNPS_PHY_MPLLB_CP(phy));
826 pll_state->mpllb_div = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV(phy));
827 pll_state->mpllb_div2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_DIV2(phy));
828 pll_state->mpllb_sscen = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCEN(phy));
829 pll_state->mpllb_sscstep = intel_de_read(dev_priv, SNPS_PHY_MPLLB_SSCSTEP(phy));
830 pll_state->mpllb_fracn1 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN1(phy));
831 pll_state->mpllb_fracn2 = intel_de_read(dev_priv, SNPS_PHY_MPLLB_FRACN2(phy));
832
833 /*
834 * REF_CONTROL is under firmware control and never programmed by the
835 * driver; we read it only for sanity checking purposes. The bspec
836 * only tells us the expected value for one field in this register,
837 * so we'll only read out those specific bits here.
838 */
839 pll_state->ref_control = intel_de_read(dev_priv, SNPS_PHY_REF_CONTROL(phy)) &
840 SNPS_PHY_REF_CONTROL_REF_RANGE;
841
842 /*
843 * MPLLB_DIV is programmed twice, once with the software-computed
844 * state, then again with the MPLLB_FORCE_EN bit added. Drop that
845 * extra bit during readout so that we return the actual expected
846 * software state.
847 */
848 pll_state->mpllb_div &= ~SNPS_PHY_MPLLB_FORCE_EN;
849 }
850
intel_snps_phy_check_hdmi_link_rate(int clock)851 int intel_snps_phy_check_hdmi_link_rate(int clock)
852 {
853 const struct intel_mpllb_state **tables = dg2_hdmi_tables;
854 int i;
855
856 for (i = 0; tables[i]; i++) {
857 if (clock == tables[i]->clock)
858 return MODE_OK;
859 }
860
861 return MODE_CLOCK_RANGE;
862 }
863
