1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2014-2019 Intel Corporation
4 */
5
6 #ifndef _INTEL_GUC_H_
7 #define _INTEL_GUC_H_
8
9 #include "intel_uncore.h"
10 #include "intel_guc_fw.h"
11 #include "intel_guc_fwif.h"
12 #include "intel_guc_ct.h"
13 #include "intel_guc_log.h"
14 #include "intel_guc_reg.h"
15 #include "intel_uc_fw.h"
16 #include "i915_utils.h"
17 #include "i915_vma.h"
18
19 struct __guc_ads_blob;
20
21 /*
22 * Top level structure of GuC. It handles firmware loading and manages client
23 * pool. intel_guc owns a intel_guc_client to replace the legacy ExecList
24 * submission.
25 */
26 struct intel_guc {
27 struct intel_uc_fw fw;
28 struct intel_guc_log log;
29 struct intel_guc_ct ct;
30
31 /* intel_guc_recv interrupt related state */
32 spinlock_t irq_lock;
33 unsigned int msg_enabled_mask;
34
35 struct {
36 bool enabled;
37 void (*reset)(struct intel_guc *guc);
38 void (*enable)(struct intel_guc *guc);
39 void (*disable)(struct intel_guc *guc);
40 } interrupts;
41
42 bool submission_selected;
43
44 struct i915_vma *ads_vma;
45 struct __guc_ads_blob *ads_blob;
46
47 struct i915_vma *stage_desc_pool;
48 void *stage_desc_pool_vaddr;
49
50 struct i915_vma *workqueue;
51 void *workqueue_vaddr;
52 spinlock_t wq_lock;
53
54 struct i915_vma *proc_desc;
55 void *proc_desc_vaddr;
56
57 /* Control params for fw initialization */
58 u32 params[GUC_CTL_MAX_DWORDS];
59
60 /* GuC's FW specific registers used in MMIO send */
61 struct {
62 u32 base;
63 unsigned int count;
64 enum forcewake_domains fw_domains;
65 } send_regs;
66
67 /* register used to send interrupts to the GuC FW */
68 i915_reg_t notify_reg;
69
70 /* Store msg (e.g. log flush) that we see while CTBs are disabled */
71 u32 mmio_msg;
72
73 /* To serialize the intel_guc_send actions */
74 struct mutex send_mutex;
75 };
76
log_to_guc(struct intel_guc_log * log)77 static inline struct intel_guc *log_to_guc(struct intel_guc_log *log)
78 {
79 return container_of(log, struct intel_guc, log);
80 }
81
82 static
intel_guc_send(struct intel_guc * guc,const u32 * action,u32 len)83 inline int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len)
84 {
85 return intel_guc_ct_send(&guc->ct, action, len, NULL, 0);
86 }
87
88 static inline int
intel_guc_send_and_receive(struct intel_guc * guc,const u32 * action,u32 len,u32 * response_buf,u32 response_buf_size)89 intel_guc_send_and_receive(struct intel_guc *guc, const u32 *action, u32 len,
90 u32 *response_buf, u32 response_buf_size)
91 {
92 return intel_guc_ct_send(&guc->ct, action, len,
93 response_buf, response_buf_size);
94 }
95
intel_guc_to_host_event_handler(struct intel_guc * guc)96 static inline void intel_guc_to_host_event_handler(struct intel_guc *guc)
97 {
98 intel_guc_ct_event_handler(&guc->ct);
99 }
100
101 /* GuC addresses above GUC_GGTT_TOP also don't map through the GTT */
102 #define GUC_GGTT_TOP 0xFEE00000
103
104 /**
105 * intel_guc_ggtt_offset() - Get and validate the GGTT offset of @vma
106 * @guc: intel_guc structure.
107 * @vma: i915 graphics virtual memory area.
108 *
109 * GuC does not allow any gfx GGTT address that falls into range
110 * [0, ggtt.pin_bias), which is reserved for Boot ROM, SRAM and WOPCM.
111 * Currently, in order to exclude [0, ggtt.pin_bias) address space from
112 * GGTT, all gfx objects used by GuC are allocated with intel_guc_allocate_vma()
113 * and pinned with PIN_OFFSET_BIAS along with the value of ggtt.pin_bias.
114 *
115 * Return: GGTT offset of the @vma.
116 */
intel_guc_ggtt_offset(struct intel_guc * guc,struct i915_vma * vma)117 static inline u32 intel_guc_ggtt_offset(struct intel_guc *guc,
118 struct i915_vma *vma)
119 {
120 u32 offset = i915_ggtt_offset(vma);
121
122 GEM_BUG_ON(offset < i915_ggtt_pin_bias(vma));
123 GEM_BUG_ON(range_overflows_t(u64, offset, vma->size, GUC_GGTT_TOP));
124
125 return offset;
126 }
127
128 void intel_guc_init_early(struct intel_guc *guc);
129 void intel_guc_init_send_regs(struct intel_guc *guc);
130 void intel_guc_write_params(struct intel_guc *guc);
131 int intel_guc_init(struct intel_guc *guc);
132 void intel_guc_fini(struct intel_guc *guc);
133 void intel_guc_notify(struct intel_guc *guc);
134 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
135 u32 *response_buf, u32 response_buf_size);
136 int intel_guc_to_host_process_recv_msg(struct intel_guc *guc,
137 const u32 *payload, u32 len);
138 int intel_guc_sample_forcewake(struct intel_guc *guc);
139 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset);
140 int intel_guc_suspend(struct intel_guc *guc);
141 int intel_guc_resume(struct intel_guc *guc);
142 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size);
143 int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
144 struct i915_vma **out_vma, void **out_vaddr);
145
intel_guc_is_supported(struct intel_guc * guc)146 static inline bool intel_guc_is_supported(struct intel_guc *guc)
147 {
148 return intel_uc_fw_is_supported(&guc->fw);
149 }
150
intel_guc_is_wanted(struct intel_guc * guc)151 static inline bool intel_guc_is_wanted(struct intel_guc *guc)
152 {
153 return intel_uc_fw_is_enabled(&guc->fw);
154 }
155
intel_guc_is_used(struct intel_guc * guc)156 static inline bool intel_guc_is_used(struct intel_guc *guc)
157 {
158 GEM_BUG_ON(__intel_uc_fw_status(&guc->fw) == INTEL_UC_FIRMWARE_SELECTED);
159 return intel_uc_fw_is_available(&guc->fw);
160 }
161
intel_guc_is_fw_running(struct intel_guc * guc)162 static inline bool intel_guc_is_fw_running(struct intel_guc *guc)
163 {
164 return intel_uc_fw_is_running(&guc->fw);
165 }
166
intel_guc_is_ready(struct intel_guc * guc)167 static inline bool intel_guc_is_ready(struct intel_guc *guc)
168 {
169 return intel_guc_is_fw_running(guc) && intel_guc_ct_enabled(&guc->ct);
170 }
171
intel_guc_sanitize(struct intel_guc * guc)172 static inline int intel_guc_sanitize(struct intel_guc *guc)
173 {
174 intel_uc_fw_sanitize(&guc->fw);
175 intel_guc_ct_sanitize(&guc->ct);
176 guc->mmio_msg = 0;
177
178 return 0;
179 }
180
intel_guc_enable_msg(struct intel_guc * guc,u32 mask)181 static inline void intel_guc_enable_msg(struct intel_guc *guc, u32 mask)
182 {
183 spin_lock_irq(&guc->irq_lock);
184 guc->msg_enabled_mask |= mask;
185 spin_unlock_irq(&guc->irq_lock);
186 }
187
intel_guc_disable_msg(struct intel_guc * guc,u32 mask)188 static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
189 {
190 spin_lock_irq(&guc->irq_lock);
191 guc->msg_enabled_mask &= ~mask;
192 spin_unlock_irq(&guc->irq_lock);
193 }
194
195 int intel_guc_reset_engine(struct intel_guc *guc,
196 struct intel_engine_cs *engine);
197
198 void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
199
200 #endif
201
