1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2016 Intel Corporation
4 */
5
6 #include <linux/string_helpers.h>
7
8 #include <drm/drm_print.h>
9
10 #include "gem/i915_gem_context.h"
11 #include "gem/i915_gem_internal.h"
12 #include "gt/intel_gt_regs.h"
13
14 #include "i915_cmd_parser.h"
15 #include "i915_drv.h"
16 #include "intel_breadcrumbs.h"
17 #include "intel_context.h"
18 #include "intel_engine.h"
19 #include "intel_engine_pm.h"
20 #include "intel_engine_regs.h"
21 #include "intel_engine_user.h"
22 #include "intel_execlists_submission.h"
23 #include "intel_gt.h"
24 #include "intel_gt_mcr.h"
25 #include "intel_gt_pm.h"
26 #include "intel_gt_requests.h"
27 #include "intel_lrc.h"
28 #include "intel_lrc_reg.h"
29 #include "intel_reset.h"
30 #include "intel_ring.h"
31 #include "uc/intel_guc_submission.h"
32
33 /* Haswell does have the CXT_SIZE register however it does not appear to be
34 * valid. Now, docs explain in dwords what is in the context object. The full
35 * size is 70720 bytes, however, the power context and execlist context will
36 * never be saved (power context is stored elsewhere, and execlists don't work
37 * on HSW) - so the final size, including the extra state required for the
38 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
39 */
40 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
41
42 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
43 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
44 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
45 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
46
47 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
48
49 #define MAX_MMIO_BASES 3
50 struct engine_info {
51 u8 class;
52 u8 instance;
53 /* mmio bases table *must* be sorted in reverse graphics_ver order */
54 struct engine_mmio_base {
55 u32 graphics_ver : 8;
56 u32 base : 24;
57 } mmio_bases[MAX_MMIO_BASES];
58 };
59
60 static const struct engine_info intel_engines[] = {
61 [RCS0] = {
62 .class = RENDER_CLASS,
63 .instance = 0,
64 .mmio_bases = {
65 { .graphics_ver = 1, .base = RENDER_RING_BASE }
66 },
67 },
68 [BCS0] = {
69 .class = COPY_ENGINE_CLASS,
70 .instance = 0,
71 .mmio_bases = {
72 { .graphics_ver = 6, .base = BLT_RING_BASE }
73 },
74 },
75 [BCS1] = {
76 .class = COPY_ENGINE_CLASS,
77 .instance = 1,
78 .mmio_bases = {
79 { .graphics_ver = 12, .base = XEHPC_BCS1_RING_BASE }
80 },
81 },
82 [BCS2] = {
83 .class = COPY_ENGINE_CLASS,
84 .instance = 2,
85 .mmio_bases = {
86 { .graphics_ver = 12, .base = XEHPC_BCS2_RING_BASE }
87 },
88 },
89 [BCS3] = {
90 .class = COPY_ENGINE_CLASS,
91 .instance = 3,
92 .mmio_bases = {
93 { .graphics_ver = 12, .base = XEHPC_BCS3_RING_BASE }
94 },
95 },
96 [BCS4] = {
97 .class = COPY_ENGINE_CLASS,
98 .instance = 4,
99 .mmio_bases = {
100 { .graphics_ver = 12, .base = XEHPC_BCS4_RING_BASE }
101 },
102 },
103 [BCS5] = {
104 .class = COPY_ENGINE_CLASS,
105 .instance = 5,
106 .mmio_bases = {
107 { .graphics_ver = 12, .base = XEHPC_BCS5_RING_BASE }
108 },
109 },
110 [BCS6] = {
111 .class = COPY_ENGINE_CLASS,
112 .instance = 6,
113 .mmio_bases = {
114 { .graphics_ver = 12, .base = XEHPC_BCS6_RING_BASE }
115 },
116 },
117 [BCS7] = {
118 .class = COPY_ENGINE_CLASS,
119 .instance = 7,
120 .mmio_bases = {
121 { .graphics_ver = 12, .base = XEHPC_BCS7_RING_BASE }
122 },
123 },
124 [BCS8] = {
125 .class = COPY_ENGINE_CLASS,
126 .instance = 8,
127 .mmio_bases = {
128 { .graphics_ver = 12, .base = XEHPC_BCS8_RING_BASE }
129 },
130 },
131 [VCS0] = {
132 .class = VIDEO_DECODE_CLASS,
133 .instance = 0,
134 .mmio_bases = {
135 { .graphics_ver = 11, .base = GEN11_BSD_RING_BASE },
136 { .graphics_ver = 6, .base = GEN6_BSD_RING_BASE },
137 { .graphics_ver = 4, .base = BSD_RING_BASE }
138 },
139 },
140 [VCS1] = {
141 .class = VIDEO_DECODE_CLASS,
142 .instance = 1,
143 .mmio_bases = {
144 { .graphics_ver = 11, .base = GEN11_BSD2_RING_BASE },
145 { .graphics_ver = 8, .base = GEN8_BSD2_RING_BASE }
146 },
147 },
148 [VCS2] = {
149 .class = VIDEO_DECODE_CLASS,
150 .instance = 2,
151 .mmio_bases = {
152 { .graphics_ver = 11, .base = GEN11_BSD3_RING_BASE }
153 },
154 },
155 [VCS3] = {
156 .class = VIDEO_DECODE_CLASS,
157 .instance = 3,
158 .mmio_bases = {
159 { .graphics_ver = 11, .base = GEN11_BSD4_RING_BASE }
160 },
161 },
162 [VCS4] = {
163 .class = VIDEO_DECODE_CLASS,
164 .instance = 4,
165 .mmio_bases = {
166 { .graphics_ver = 12, .base = XEHP_BSD5_RING_BASE }
167 },
168 },
169 [VCS5] = {
170 .class = VIDEO_DECODE_CLASS,
171 .instance = 5,
172 .mmio_bases = {
173 { .graphics_ver = 12, .base = XEHP_BSD6_RING_BASE }
174 },
175 },
176 [VCS6] = {
177 .class = VIDEO_DECODE_CLASS,
178 .instance = 6,
179 .mmio_bases = {
180 { .graphics_ver = 12, .base = XEHP_BSD7_RING_BASE }
181 },
182 },
183 [VCS7] = {
184 .class = VIDEO_DECODE_CLASS,
185 .instance = 7,
186 .mmio_bases = {
187 { .graphics_ver = 12, .base = XEHP_BSD8_RING_BASE }
188 },
189 },
190 [VECS0] = {
191 .class = VIDEO_ENHANCEMENT_CLASS,
192 .instance = 0,
193 .mmio_bases = {
194 { .graphics_ver = 11, .base = GEN11_VEBOX_RING_BASE },
195 { .graphics_ver = 7, .base = VEBOX_RING_BASE }
196 },
197 },
198 [VECS1] = {
199 .class = VIDEO_ENHANCEMENT_CLASS,
200 .instance = 1,
201 .mmio_bases = {
202 { .graphics_ver = 11, .base = GEN11_VEBOX2_RING_BASE }
203 },
204 },
205 [VECS2] = {
206 .class = VIDEO_ENHANCEMENT_CLASS,
207 .instance = 2,
208 .mmio_bases = {
209 { .graphics_ver = 12, .base = XEHP_VEBOX3_RING_BASE }
210 },
211 },
212 [VECS3] = {
213 .class = VIDEO_ENHANCEMENT_CLASS,
214 .instance = 3,
215 .mmio_bases = {
216 { .graphics_ver = 12, .base = XEHP_VEBOX4_RING_BASE }
217 },
218 },
219 [CCS0] = {
220 .class = COMPUTE_CLASS,
221 .instance = 0,
222 .mmio_bases = {
223 { .graphics_ver = 12, .base = GEN12_COMPUTE0_RING_BASE }
224 }
225 },
226 [CCS1] = {
227 .class = COMPUTE_CLASS,
228 .instance = 1,
229 .mmio_bases = {
230 { .graphics_ver = 12, .base = GEN12_COMPUTE1_RING_BASE }
231 }
232 },
233 [CCS2] = {
234 .class = COMPUTE_CLASS,
235 .instance = 2,
236 .mmio_bases = {
237 { .graphics_ver = 12, .base = GEN12_COMPUTE2_RING_BASE }
238 }
239 },
240 [CCS3] = {
241 .class = COMPUTE_CLASS,
242 .instance = 3,
243 .mmio_bases = {
244 { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
245 }
246 },
247 };
248
249 /**
250 * intel_engine_context_size() - return the size of the context for an engine
251 * @gt: the gt
252 * @class: engine class
253 *
254 * Each engine class may require a different amount of space for a context
255 * image.
256 *
257 * Return: size (in bytes) of an engine class specific context image
258 *
259 * Note: this size includes the HWSP, which is part of the context image
260 * in LRC mode, but does not include the "shared data page" used with
261 * GuC submission. The caller should account for this if using the GuC.
262 */
intel_engine_context_size(struct intel_gt * gt,u8 class)263 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
264 {
265 struct intel_uncore *uncore = gt->uncore;
266 u32 cxt_size;
267
268 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
269
270 switch (class) {
271 case COMPUTE_CLASS:
272 fallthrough;
273 case RENDER_CLASS:
274 switch (GRAPHICS_VER(gt->i915)) {
275 default:
276 MISSING_CASE(GRAPHICS_VER(gt->i915));
277 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
278 case 12:
279 case 11:
280 return GEN11_LR_CONTEXT_RENDER_SIZE;
281 case 9:
282 return GEN9_LR_CONTEXT_RENDER_SIZE;
283 case 8:
284 return GEN8_LR_CONTEXT_RENDER_SIZE;
285 case 7:
286 if (IS_HASWELL(gt->i915))
287 return HSW_CXT_TOTAL_SIZE;
288
289 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
290 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
291 PAGE_SIZE);
292 case 6:
293 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
294 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
295 PAGE_SIZE);
296 case 5:
297 case 4:
298 /*
299 * There is a discrepancy here between the size reported
300 * by the register and the size of the context layout
301 * in the docs. Both are described as authorative!
302 *
303 * The discrepancy is on the order of a few cachelines,
304 * but the total is under one page (4k), which is our
305 * minimum allocation anyway so it should all come
306 * out in the wash.
307 */
308 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
309 drm_dbg(>->i915->drm,
310 "graphics_ver = %d CXT_SIZE = %d bytes [0x%08x]\n",
311 GRAPHICS_VER(gt->i915), cxt_size * 64,
312 cxt_size - 1);
313 return round_up(cxt_size * 64, PAGE_SIZE);
314 case 3:
315 case 2:
316 /* For the special day when i810 gets merged. */
317 case 1:
318 return 0;
319 }
320 break;
321 default:
322 MISSING_CASE(class);
323 fallthrough;
324 case VIDEO_DECODE_CLASS:
325 case VIDEO_ENHANCEMENT_CLASS:
326 case COPY_ENGINE_CLASS:
327 if (GRAPHICS_VER(gt->i915) < 8)
328 return 0;
329 return GEN8_LR_CONTEXT_OTHER_SIZE;
330 }
331 }
332
__engine_mmio_base(struct drm_i915_private * i915,const struct engine_mmio_base * bases)333 static u32 __engine_mmio_base(struct drm_i915_private *i915,
334 const struct engine_mmio_base *bases)
335 {
336 int i;
337
338 for (i = 0; i < MAX_MMIO_BASES; i++)
339 if (GRAPHICS_VER(i915) >= bases[i].graphics_ver)
340 break;
341
342 GEM_BUG_ON(i == MAX_MMIO_BASES);
343 GEM_BUG_ON(!bases[i].base);
344
345 return bases[i].base;
346 }
347
__sprint_engine_name(struct intel_engine_cs * engine)348 static void __sprint_engine_name(struct intel_engine_cs *engine)
349 {
350 /*
351 * Before we know what the uABI name for this engine will be,
352 * we still would like to keep track of this engine in the debug logs.
353 * We throw in a ' here as a reminder that this isn't its final name.
354 */
355 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
356 intel_engine_class_repr(engine->class),
357 engine->instance) >= sizeof(engine->name));
358 }
359
intel_engine_set_hwsp_writemask(struct intel_engine_cs * engine,u32 mask)360 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
361 {
362 /*
363 * Though they added more rings on g4x/ilk, they did not add
364 * per-engine HWSTAM until gen6.
365 */
366 if (GRAPHICS_VER(engine->i915) < 6 && engine->class != RENDER_CLASS)
367 return;
368
369 if (GRAPHICS_VER(engine->i915) >= 3)
370 ENGINE_WRITE(engine, RING_HWSTAM, mask);
371 else
372 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
373 }
374
intel_engine_sanitize_mmio(struct intel_engine_cs * engine)375 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
376 {
377 /* Mask off all writes into the unknown HWSP */
378 intel_engine_set_hwsp_writemask(engine, ~0u);
379 }
380
nop_irq_handler(struct intel_engine_cs * engine,u16 iir)381 static void nop_irq_handler(struct intel_engine_cs *engine, u16 iir)
382 {
383 GEM_DEBUG_WARN_ON(iir);
384 }
385
get_reset_domain(u8 ver,enum intel_engine_id id)386 static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
387 {
388 u32 reset_domain;
389
390 if (ver >= 11) {
391 static const u32 engine_reset_domains[] = {
392 [RCS0] = GEN11_GRDOM_RENDER,
393 [BCS0] = GEN11_GRDOM_BLT,
394 [BCS1] = XEHPC_GRDOM_BLT1,
395 [BCS2] = XEHPC_GRDOM_BLT2,
396 [BCS3] = XEHPC_GRDOM_BLT3,
397 [BCS4] = XEHPC_GRDOM_BLT4,
398 [BCS5] = XEHPC_GRDOM_BLT5,
399 [BCS6] = XEHPC_GRDOM_BLT6,
400 [BCS7] = XEHPC_GRDOM_BLT7,
401 [BCS8] = XEHPC_GRDOM_BLT8,
402 [VCS0] = GEN11_GRDOM_MEDIA,
403 [VCS1] = GEN11_GRDOM_MEDIA2,
404 [VCS2] = GEN11_GRDOM_MEDIA3,
405 [VCS3] = GEN11_GRDOM_MEDIA4,
406 [VCS4] = GEN11_GRDOM_MEDIA5,
407 [VCS5] = GEN11_GRDOM_MEDIA6,
408 [VCS6] = GEN11_GRDOM_MEDIA7,
409 [VCS7] = GEN11_GRDOM_MEDIA8,
410 [VECS0] = GEN11_GRDOM_VECS,
411 [VECS1] = GEN11_GRDOM_VECS2,
412 [VECS2] = GEN11_GRDOM_VECS3,
413 [VECS3] = GEN11_GRDOM_VECS4,
414 [CCS0] = GEN11_GRDOM_RENDER,
415 [CCS1] = GEN11_GRDOM_RENDER,
416 [CCS2] = GEN11_GRDOM_RENDER,
417 [CCS3] = GEN11_GRDOM_RENDER,
418 };
419 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
420 !engine_reset_domains[id]);
421 reset_domain = engine_reset_domains[id];
422 } else {
423 static const u32 engine_reset_domains[] = {
424 [RCS0] = GEN6_GRDOM_RENDER,
425 [BCS0] = GEN6_GRDOM_BLT,
426 [VCS0] = GEN6_GRDOM_MEDIA,
427 [VCS1] = GEN8_GRDOM_MEDIA2,
428 [VECS0] = GEN6_GRDOM_VECS,
429 };
430 GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
431 !engine_reset_domains[id]);
432 reset_domain = engine_reset_domains[id];
433 }
434
435 return reset_domain;
436 }
437
intel_engine_setup(struct intel_gt * gt,enum intel_engine_id id,u8 logical_instance)438 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
439 u8 logical_instance)
440 {
441 const struct engine_info *info = &intel_engines[id];
442 struct drm_i915_private *i915 = gt->i915;
443 struct intel_engine_cs *engine;
444 u8 guc_class;
445
446 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
447 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
448 BUILD_BUG_ON(I915_MAX_VCS > (MAX_ENGINE_INSTANCE + 1));
449 BUILD_BUG_ON(I915_MAX_VECS > (MAX_ENGINE_INSTANCE + 1));
450
451 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
452 return -EINVAL;
453
454 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
455 return -EINVAL;
456
457 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
458 return -EINVAL;
459
460 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
461 return -EINVAL;
462
463 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
464 if (!engine)
465 return -ENOMEM;
466
467 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
468
469 INIT_LIST_HEAD(&engine->pinned_contexts_list);
470 engine->id = id;
471 engine->legacy_idx = INVALID_ENGINE;
472 engine->mask = BIT(id);
473 engine->reset_domain = get_reset_domain(GRAPHICS_VER(gt->i915),
474 id);
475 engine->i915 = i915;
476 engine->gt = gt;
477 engine->uncore = gt->uncore;
478 guc_class = engine_class_to_guc_class(info->class);
479 engine->guc_id = MAKE_GUC_ID(guc_class, info->instance);
480 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
481
482 engine->irq_handler = nop_irq_handler;
483
484 engine->class = info->class;
485 engine->instance = info->instance;
486 engine->logical_mask = BIT(logical_instance);
487 __sprint_engine_name(engine);
488
489 engine->props.heartbeat_interval_ms =
490 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
491 engine->props.max_busywait_duration_ns =
492 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
493 engine->props.preempt_timeout_ms =
494 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
495 engine->props.stop_timeout_ms =
496 CONFIG_DRM_I915_STOP_TIMEOUT;
497 engine->props.timeslice_duration_ms =
498 CONFIG_DRM_I915_TIMESLICE_DURATION;
499
500 /* Override to uninterruptible for OpenCL workloads. */
501 if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
502 engine->props.preempt_timeout_ms = 0;
503
504 if ((engine->class == COMPUTE_CLASS && !RCS_MASK(engine->gt) &&
505 __ffs(CCS_MASK(engine->gt)) == engine->instance) ||
506 engine->class == RENDER_CLASS)
507 engine->flags |= I915_ENGINE_FIRST_RENDER_COMPUTE;
508
509 /* features common between engines sharing EUs */
510 if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS) {
511 engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
512 engine->flags |= I915_ENGINE_HAS_EU_PRIORITY;
513 }
514
515 engine->defaults = engine->props; /* never to change again */
516
517 engine->context_size = intel_engine_context_size(gt, engine->class);
518 if (WARN_ON(engine->context_size > BIT(20)))
519 engine->context_size = 0;
520 if (engine->context_size)
521 DRIVER_CAPS(i915)->has_logical_contexts = true;
522
523 ewma__engine_latency_init(&engine->latency);
524 seqcount_init(&engine->stats.execlists.lock);
525
526 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
527
528 /* Scrub mmio state on takeover */
529 intel_engine_sanitize_mmio(engine);
530
531 gt->engine_class[info->class][info->instance] = engine;
532 gt->engine[id] = engine;
533
534 return 0;
535 }
536
__setup_engine_capabilities(struct intel_engine_cs * engine)537 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
538 {
539 struct drm_i915_private *i915 = engine->i915;
540
541 if (engine->class == VIDEO_DECODE_CLASS) {
542 /*
543 * HEVC support is present on first engine instance
544 * before Gen11 and on all instances afterwards.
545 */
546 if (GRAPHICS_VER(i915) >= 11 ||
547 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
548 engine->uabi_capabilities |=
549 I915_VIDEO_CLASS_CAPABILITY_HEVC;
550
551 /*
552 * SFC block is present only on even logical engine
553 * instances.
554 */
555 if ((GRAPHICS_VER(i915) >= 11 &&
556 (engine->gt->info.vdbox_sfc_access &
557 BIT(engine->instance))) ||
558 (GRAPHICS_VER(i915) >= 9 && engine->instance == 0))
559 engine->uabi_capabilities |=
560 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
561 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
562 if (GRAPHICS_VER(i915) >= 9 &&
563 engine->gt->info.sfc_mask & BIT(engine->instance))
564 engine->uabi_capabilities |=
565 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
566 }
567 }
568
intel_setup_engine_capabilities(struct intel_gt * gt)569 static void intel_setup_engine_capabilities(struct intel_gt *gt)
570 {
571 struct intel_engine_cs *engine;
572 enum intel_engine_id id;
573
574 for_each_engine(engine, gt, id)
575 __setup_engine_capabilities(engine);
576 }
577
578 /**
579 * intel_engines_release() - free the resources allocated for Command Streamers
580 * @gt: pointer to struct intel_gt
581 */
intel_engines_release(struct intel_gt * gt)582 void intel_engines_release(struct intel_gt *gt)
583 {
584 struct intel_engine_cs *engine;
585 enum intel_engine_id id;
586
587 /*
588 * Before we release the resources held by engine, we must be certain
589 * that the HW is no longer accessing them -- having the GPU scribble
590 * to or read from a page being used for something else causes no end
591 * of fun.
592 *
593 * The GPU should be reset by this point, but assume the worst just
594 * in case we aborted before completely initialising the engines.
595 */
596 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
597 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
598 __intel_gt_reset(gt, ALL_ENGINES);
599
600 /* Decouple the backend; but keep the layout for late GPU resets */
601 for_each_engine(engine, gt, id) {
602 if (!engine->release)
603 continue;
604
605 intel_wakeref_wait_for_idle(&engine->wakeref);
606 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
607
608 engine->release(engine);
609 engine->release = NULL;
610
611 memset(&engine->reset, 0, sizeof(engine->reset));
612 }
613 }
614
intel_engine_free_request_pool(struct intel_engine_cs * engine)615 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
616 {
617 if (!engine->request_pool)
618 return;
619
620 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
621 }
622
intel_engines_free(struct intel_gt * gt)623 void intel_engines_free(struct intel_gt *gt)
624 {
625 struct intel_engine_cs *engine;
626 enum intel_engine_id id;
627
628 /* Free the requests! dma-resv keeps fences around for an eternity */
629 rcu_barrier();
630
631 for_each_engine(engine, gt, id) {
632 intel_engine_free_request_pool(engine);
633 kfree(engine);
634 gt->engine[id] = NULL;
635 }
636 }
637
638 static
gen11_vdbox_has_sfc(struct intel_gt * gt,unsigned int physical_vdbox,unsigned int logical_vdbox,u16 vdbox_mask)639 bool gen11_vdbox_has_sfc(struct intel_gt *gt,
640 unsigned int physical_vdbox,
641 unsigned int logical_vdbox, u16 vdbox_mask)
642 {
643 struct drm_i915_private *i915 = gt->i915;
644
645 /*
646 * In Gen11, only even numbered logical VDBOXes are hooked
647 * up to an SFC (Scaler & Format Converter) unit.
648 * In Gen12, Even numbered physical instance always are connected
649 * to an SFC. Odd numbered physical instances have SFC only if
650 * previous even instance is fused off.
651 *
652 * Starting with Xe_HP, there's also a dedicated SFC_ENABLE field
653 * in the fuse register that tells us whether a specific SFC is present.
654 */
655 if ((gt->info.sfc_mask & BIT(physical_vdbox / 2)) == 0)
656 return false;
657 else if (MEDIA_VER(i915) >= 12)
658 return (physical_vdbox % 2 == 0) ||
659 !(BIT(physical_vdbox - 1) & vdbox_mask);
660 else if (MEDIA_VER(i915) == 11)
661 return logical_vdbox % 2 == 0;
662
663 return false;
664 }
665
engine_mask_apply_media_fuses(struct intel_gt * gt)666 static void engine_mask_apply_media_fuses(struct intel_gt *gt)
667 {
668 struct drm_i915_private *i915 = gt->i915;
669 unsigned int logical_vdbox = 0;
670 unsigned int i;
671 u32 media_fuse, fuse1;
672 u16 vdbox_mask;
673 u16 vebox_mask;
674
675 if (MEDIA_VER(gt->i915) < 11)
676 return;
677
678 /*
679 * On newer platforms the fusing register is called 'enable' and has
680 * enable semantics, while on older platforms it is called 'disable'
681 * and bits have disable semantices.
682 */
683 media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
684 if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))
685 media_fuse = ~media_fuse;
686
687 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
688 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
689 GEN11_GT_VEBOX_DISABLE_SHIFT;
690
691 if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {
692 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);
693 gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);
694 } else {
695 gt->info.sfc_mask = ~0;
696 }
697
698 for (i = 0; i < I915_MAX_VCS; i++) {
699 if (!HAS_ENGINE(gt, _VCS(i))) {
700 vdbox_mask &= ~BIT(i);
701 continue;
702 }
703
704 if (!(BIT(i) & vdbox_mask)) {
705 gt->info.engine_mask &= ~BIT(_VCS(i));
706 drm_dbg(&i915->drm, "vcs%u fused off\n", i);
707 continue;
708 }
709
710 if (gen11_vdbox_has_sfc(gt, i, logical_vdbox, vdbox_mask))
711 gt->info.vdbox_sfc_access |= BIT(i);
712 logical_vdbox++;
713 }
714 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
715 vdbox_mask, VDBOX_MASK(gt));
716 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
717
718 for (i = 0; i < I915_MAX_VECS; i++) {
719 if (!HAS_ENGINE(gt, _VECS(i))) {
720 vebox_mask &= ~BIT(i);
721 continue;
722 }
723
724 if (!(BIT(i) & vebox_mask)) {
725 gt->info.engine_mask &= ~BIT(_VECS(i));
726 drm_dbg(&i915->drm, "vecs%u fused off\n", i);
727 }
728 }
729 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
730 vebox_mask, VEBOX_MASK(gt));
731 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
732 }
733
engine_mask_apply_compute_fuses(struct intel_gt * gt)734 static void engine_mask_apply_compute_fuses(struct intel_gt *gt)
735 {
736 struct drm_i915_private *i915 = gt->i915;
737 struct intel_gt_info *info = >->info;
738 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS;
739 unsigned long ccs_mask;
740 unsigned int i;
741
742 if (GRAPHICS_VER(i915) < 11)
743 return;
744
745 if (hweight32(CCS_MASK(gt)) <= 1)
746 return;
747
748 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask,
749 ss_per_ccs);
750 /*
751 * If all DSS in a quadrant are fused off, the corresponding CCS
752 * engine is not available for use.
753 */
754 for_each_clear_bit(i, &ccs_mask, I915_MAX_CCS) {
755 info->engine_mask &= ~BIT(_CCS(i));
756 drm_dbg(&i915->drm, "ccs%u fused off\n", i);
757 }
758 }
759
engine_mask_apply_copy_fuses(struct intel_gt * gt)760 static void engine_mask_apply_copy_fuses(struct intel_gt *gt)
761 {
762 struct drm_i915_private *i915 = gt->i915;
763 struct intel_gt_info *info = >->info;
764 unsigned long meml3_mask;
765 unsigned long quad;
766
767 if (!(GRAPHICS_VER_FULL(i915) >= IP_VER(12, 60) &&
768 GRAPHICS_VER_FULL(i915) < IP_VER(12, 70)))
769 return;
770
771 meml3_mask = intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3);
772 meml3_mask = REG_FIELD_GET(GEN12_MEML3_EN_MASK, meml3_mask);
773
774 /*
775 * Link Copy engines may be fused off according to meml3_mask. Each
776 * bit is a quad that houses 2 Link Copy and two Sub Copy engines.
777 */
778 for_each_clear_bit(quad, &meml3_mask, GEN12_MAX_MSLICES) {
779 unsigned int instance = quad * 2 + 1;
780 intel_engine_mask_t mask = GENMASK(_BCS(instance + 1),
781 _BCS(instance));
782
783 if (mask & info->engine_mask) {
784 drm_dbg(&i915->drm, "bcs%u fused off\n", instance);
785 drm_dbg(&i915->drm, "bcs%u fused off\n", instance + 1);
786
787 info->engine_mask &= ~mask;
788 }
789 }
790 }
791
792 /*
793 * Determine which engines are fused off in our particular hardware.
794 * Note that we have a catch-22 situation where we need to be able to access
795 * the blitter forcewake domain to read the engine fuses, but at the same time
796 * we need to know which engines are available on the system to know which
797 * forcewake domains are present. We solve this by intializing the forcewake
798 * domains based on the full engine mask in the platform capabilities before
799 * calling this function and pruning the domains for fused-off engines
800 * afterwards.
801 */
init_engine_mask(struct intel_gt * gt)802 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
803 {
804 struct intel_gt_info *info = >->info;
805
806 GEM_BUG_ON(!info->engine_mask);
807
808 engine_mask_apply_media_fuses(gt);
809 engine_mask_apply_compute_fuses(gt);
810 engine_mask_apply_copy_fuses(gt);
811
812 return info->engine_mask;
813 }
814
populate_logical_ids(struct intel_gt * gt,u8 * logical_ids,u8 class,const u8 * map,u8 num_instances)815 static void populate_logical_ids(struct intel_gt *gt, u8 *logical_ids,
816 u8 class, const u8 *map, u8 num_instances)
817 {
818 int i, j;
819 u8 current_logical_id = 0;
820
821 for (j = 0; j < num_instances; ++j) {
822 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
823 if (!HAS_ENGINE(gt, i) ||
824 intel_engines[i].class != class)
825 continue;
826
827 if (intel_engines[i].instance == map[j]) {
828 logical_ids[intel_engines[i].instance] =
829 current_logical_id++;
830 break;
831 }
832 }
833 }
834 }
835
setup_logical_ids(struct intel_gt * gt,u8 * logical_ids,u8 class)836 static void setup_logical_ids(struct intel_gt *gt, u8 *logical_ids, u8 class)
837 {
838 /*
839 * Logical to physical mapping is needed for proper support
840 * to split-frame feature.
841 */
842 if (MEDIA_VER(gt->i915) >= 11 && class == VIDEO_DECODE_CLASS) {
843 const u8 map[] = { 0, 2, 4, 6, 1, 3, 5, 7 };
844
845 populate_logical_ids(gt, logical_ids, class,
846 map, ARRAY_SIZE(map));
847 } else {
848 int i;
849 u8 map[MAX_ENGINE_INSTANCE + 1];
850
851 for (i = 0; i < MAX_ENGINE_INSTANCE + 1; ++i)
852 map[i] = i;
853 populate_logical_ids(gt, logical_ids, class,
854 map, ARRAY_SIZE(map));
855 }
856 }
857
858 /**
859 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
860 * @gt: pointer to struct intel_gt
861 *
862 * Return: non-zero if the initialization failed.
863 */
intel_engines_init_mmio(struct intel_gt * gt)864 int intel_engines_init_mmio(struct intel_gt *gt)
865 {
866 struct drm_i915_private *i915 = gt->i915;
867 const unsigned int engine_mask = init_engine_mask(gt);
868 unsigned int mask = 0;
869 unsigned int i, class;
870 u8 logical_ids[MAX_ENGINE_INSTANCE + 1];
871 int err;
872
873 drm_WARN_ON(&i915->drm, engine_mask == 0);
874 drm_WARN_ON(&i915->drm, engine_mask &
875 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
876
877 if (i915_inject_probe_failure(i915))
878 return -ENODEV;
879
880 for (class = 0; class < MAX_ENGINE_CLASS + 1; ++class) {
881 setup_logical_ids(gt, logical_ids, class);
882
883 for (i = 0; i < ARRAY_SIZE(intel_engines); ++i) {
884 u8 instance = intel_engines[i].instance;
885
886 if (intel_engines[i].class != class ||
887 !HAS_ENGINE(gt, i))
888 continue;
889
890 err = intel_engine_setup(gt, i,
891 logical_ids[instance]);
892 if (err)
893 goto cleanup;
894
895 mask |= BIT(i);
896 }
897 }
898
899 /*
900 * Catch failures to update intel_engines table when the new engines
901 * are added to the driver by a warning and disabling the forgotten
902 * engines.
903 */
904 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
905 gt->info.engine_mask = mask;
906
907 gt->info.num_engines = hweight32(mask);
908
909 intel_gt_check_and_clear_faults(gt);
910
911 intel_setup_engine_capabilities(gt);
912
913 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
914
915 return 0;
916
917 cleanup:
918 intel_engines_free(gt);
919 return err;
920 }
921
intel_engine_init_execlists(struct intel_engine_cs * engine)922 void intel_engine_init_execlists(struct intel_engine_cs *engine)
923 {
924 struct intel_engine_execlists * const execlists = &engine->execlists;
925
926 execlists->port_mask = 1;
927 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
928 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
929
930 memset(execlists->pending, 0, sizeof(execlists->pending));
931 execlists->active =
932 memset(execlists->inflight, 0, sizeof(execlists->inflight));
933 }
934
cleanup_status_page(struct intel_engine_cs * engine)935 static void cleanup_status_page(struct intel_engine_cs *engine)
936 {
937 struct i915_vma *vma;
938
939 /* Prevent writes into HWSP after returning the page to the system */
940 intel_engine_set_hwsp_writemask(engine, ~0u);
941
942 vma = fetch_and_zero(&engine->status_page.vma);
943 if (!vma)
944 return;
945
946 if (!HWS_NEEDS_PHYSICAL(engine->i915))
947 i915_vma_unpin(vma);
948
949 i915_gem_object_unpin_map(vma->obj);
950 i915_gem_object_put(vma->obj);
951 }
952
pin_ggtt_status_page(struct intel_engine_cs * engine,struct i915_gem_ww_ctx * ww,struct i915_vma * vma)953 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
954 struct i915_gem_ww_ctx *ww,
955 struct i915_vma *vma)
956 {
957 unsigned int flags;
958
959 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
960 /*
961 * On g33, we cannot place HWS above 256MiB, so
962 * restrict its pinning to the low mappable arena.
963 * Though this restriction is not documented for
964 * gen4, gen5, or byt, they also behave similarly
965 * and hang if the HWS is placed at the top of the
966 * GTT. To generalise, it appears that all !llc
967 * platforms have issues with us placing the HWS
968 * above the mappable region (even though we never
969 * actually map it).
970 */
971 flags = PIN_MAPPABLE;
972 else
973 flags = PIN_HIGH;
974
975 return i915_ggtt_pin(vma, ww, 0, flags);
976 }
977
init_status_page(struct intel_engine_cs * engine)978 static int init_status_page(struct intel_engine_cs *engine)
979 {
980 struct drm_i915_gem_object *obj;
981 struct i915_gem_ww_ctx ww;
982 struct i915_vma *vma;
983 void *vaddr;
984 int ret;
985
986 INIT_LIST_HEAD(&engine->status_page.timelines);
987
988 /*
989 * Though the HWS register does support 36bit addresses, historically
990 * we have had hangs and corruption reported due to wild writes if
991 * the HWS is placed above 4G. We only allow objects to be allocated
992 * in GFP_DMA32 for i965, and no earlier physical address users had
993 * access to more than 4G.
994 */
995 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
996 if (IS_ERR(obj)) {
997 drm_err(&engine->i915->drm,
998 "Failed to allocate status page\n");
999 return PTR_ERR(obj);
1000 }
1001
1002 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
1003
1004 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1005 if (IS_ERR(vma)) {
1006 ret = PTR_ERR(vma);
1007 goto err_put;
1008 }
1009
1010 i915_gem_ww_ctx_init(&ww, true);
1011 retry:
1012 ret = i915_gem_object_lock(obj, &ww);
1013 if (!ret && !HWS_NEEDS_PHYSICAL(engine->i915))
1014 ret = pin_ggtt_status_page(engine, &ww, vma);
1015 if (ret)
1016 goto err;
1017
1018 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1019 if (IS_ERR(vaddr)) {
1020 ret = PTR_ERR(vaddr);
1021 goto err_unpin;
1022 }
1023
1024 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
1025 engine->status_page.vma = vma;
1026
1027 err_unpin:
1028 if (ret)
1029 i915_vma_unpin(vma);
1030 err:
1031 if (ret == -EDEADLK) {
1032 ret = i915_gem_ww_ctx_backoff(&ww);
1033 if (!ret)
1034 goto retry;
1035 }
1036 i915_gem_ww_ctx_fini(&ww);
1037 err_put:
1038 if (ret)
1039 i915_gem_object_put(obj);
1040 return ret;
1041 }
1042
engine_setup_common(struct intel_engine_cs * engine)1043 static int engine_setup_common(struct intel_engine_cs *engine)
1044 {
1045 int err;
1046
1047 init_llist_head(&engine->barrier_tasks);
1048
1049 err = init_status_page(engine);
1050 if (err)
1051 return err;
1052
1053 engine->breadcrumbs = intel_breadcrumbs_create(engine);
1054 if (!engine->breadcrumbs) {
1055 err = -ENOMEM;
1056 goto err_status;
1057 }
1058
1059 engine->sched_engine = i915_sched_engine_create(ENGINE_PHYSICAL);
1060 if (!engine->sched_engine) {
1061 err = -ENOMEM;
1062 goto err_sched_engine;
1063 }
1064 engine->sched_engine->private_data = engine;
1065
1066 err = intel_engine_init_cmd_parser(engine);
1067 if (err)
1068 goto err_cmd_parser;
1069
1070 intel_engine_init_execlists(engine);
1071 intel_engine_init__pm(engine);
1072 intel_engine_init_retire(engine);
1073
1074 /* Use the whole device by default */
1075 engine->sseu =
1076 intel_sseu_from_device_info(&engine->gt->info.sseu);
1077
1078 intel_engine_init_workarounds(engine);
1079 intel_engine_init_whitelist(engine);
1080 intel_engine_init_ctx_wa(engine);
1081
1082 if (GRAPHICS_VER(engine->i915) >= 12)
1083 engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
1084
1085 return 0;
1086
1087 err_cmd_parser:
1088 i915_sched_engine_put(engine->sched_engine);
1089 err_sched_engine:
1090 intel_breadcrumbs_put(engine->breadcrumbs);
1091 err_status:
1092 cleanup_status_page(engine);
1093 return err;
1094 }
1095
1096 struct measure_breadcrumb {
1097 struct i915_request rq;
1098 struct intel_ring ring;
1099 u32 cs[2048];
1100 };
1101
measure_breadcrumb_dw(struct intel_context * ce)1102 static int measure_breadcrumb_dw(struct intel_context *ce)
1103 {
1104 struct intel_engine_cs *engine = ce->engine;
1105 struct measure_breadcrumb *frame;
1106 int dw;
1107
1108 GEM_BUG_ON(!engine->gt->scratch);
1109
1110 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
1111 if (!frame)
1112 return -ENOMEM;
1113
1114 frame->rq.engine = engine;
1115 frame->rq.context = ce;
1116 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
1117 frame->rq.hwsp_seqno = ce->timeline->hwsp_seqno;
1118
1119 frame->ring.vaddr = frame->cs;
1120 frame->ring.size = sizeof(frame->cs);
1121 frame->ring.wrap =
1122 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
1123 frame->ring.effective_size = frame->ring.size;
1124 intel_ring_update_space(&frame->ring);
1125 frame->rq.ring = &frame->ring;
1126
1127 mutex_lock(&ce->timeline->mutex);
1128 spin_lock_irq(&engine->sched_engine->lock);
1129
1130 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
1131
1132 spin_unlock_irq(&engine->sched_engine->lock);
1133 mutex_unlock(&ce->timeline->mutex);
1134
1135 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
1136
1137 kfree(frame);
1138 return dw;
1139 }
1140
1141 struct intel_context *
intel_engine_create_pinned_context(struct intel_engine_cs * engine,struct i915_address_space * vm,unsigned int ring_size,unsigned int hwsp,struct lock_class_key * key,const char * name)1142 intel_engine_create_pinned_context(struct intel_engine_cs *engine,
1143 struct i915_address_space *vm,
1144 unsigned int ring_size,
1145 unsigned int hwsp,
1146 struct lock_class_key *key,
1147 const char *name)
1148 {
1149 struct intel_context *ce;
1150 int err;
1151
1152 ce = intel_context_create(engine);
1153 if (IS_ERR(ce))
1154 return ce;
1155
1156 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
1157 ce->timeline = page_pack_bits(NULL, hwsp);
1158 ce->ring = NULL;
1159 ce->ring_size = ring_size;
1160
1161 i915_vm_put(ce->vm);
1162 ce->vm = i915_vm_get(vm);
1163
1164 err = intel_context_pin(ce); /* perma-pin so it is always available */
1165 if (err) {
1166 intel_context_put(ce);
1167 return ERR_PTR(err);
1168 }
1169
1170 list_add_tail(&ce->pinned_contexts_link, &engine->pinned_contexts_list);
1171
1172 /*
1173 * Give our perma-pinned kernel timelines a separate lockdep class,
1174 * so that we can use them from within the normal user timelines
1175 * should we need to inject GPU operations during their request
1176 * construction.
1177 */
1178 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
1179
1180 return ce;
1181 }
1182
intel_engine_destroy_pinned_context(struct intel_context * ce)1183 void intel_engine_destroy_pinned_context(struct intel_context *ce)
1184 {
1185 struct intel_engine_cs *engine = ce->engine;
1186 struct i915_vma *hwsp = engine->status_page.vma;
1187
1188 GEM_BUG_ON(ce->timeline->hwsp_ggtt != hwsp);
1189
1190 mutex_lock(&hwsp->vm->mutex);
1191 list_del(&ce->timeline->engine_link);
1192 mutex_unlock(&hwsp->vm->mutex);
1193
1194 list_del(&ce->pinned_contexts_link);
1195 intel_context_unpin(ce);
1196 intel_context_put(ce);
1197 }
1198
1199 static struct intel_context *
create_kernel_context(struct intel_engine_cs * engine)1200 create_kernel_context(struct intel_engine_cs *engine)
1201 {
1202 static struct lock_class_key kernel;
1203
1204 return intel_engine_create_pinned_context(engine, engine->gt->vm, SZ_4K,
1205 I915_GEM_HWS_SEQNO_ADDR,
1206 &kernel, "kernel_context");
1207 }
1208
1209 /**
1210 * intel_engines_init_common - initialize cengine state which might require hw access
1211 * @engine: Engine to initialize.
1212 *
1213 * Initializes @engine@ structure members shared between legacy and execlists
1214 * submission modes which do require hardware access.
1215 *
1216 * Typcally done at later stages of submission mode specific engine setup.
1217 *
1218 * Returns zero on success or an error code on failure.
1219 */
engine_init_common(struct intel_engine_cs * engine)1220 static int engine_init_common(struct intel_engine_cs *engine)
1221 {
1222 struct intel_context *ce;
1223 int ret;
1224
1225 engine->set_default_submission(engine);
1226
1227 /*
1228 * We may need to do things with the shrinker which
1229 * require us to immediately switch back to the default
1230 * context. This can cause a problem as pinning the
1231 * default context also requires GTT space which may not
1232 * be available. To avoid this we always pin the default
1233 * context.
1234 */
1235 ce = create_kernel_context(engine);
1236 if (IS_ERR(ce))
1237 return PTR_ERR(ce);
1238
1239 ret = measure_breadcrumb_dw(ce);
1240 if (ret < 0)
1241 goto err_context;
1242
1243 engine->emit_fini_breadcrumb_dw = ret;
1244 engine->kernel_context = ce;
1245
1246 return 0;
1247
1248 err_context:
1249 intel_engine_destroy_pinned_context(ce);
1250 return ret;
1251 }
1252
intel_engines_init(struct intel_gt * gt)1253 int intel_engines_init(struct intel_gt *gt)
1254 {
1255 int (*setup)(struct intel_engine_cs *engine);
1256 struct intel_engine_cs *engine;
1257 enum intel_engine_id id;
1258 int err;
1259
1260 if (intel_uc_uses_guc_submission(>->uc)) {
1261 gt->submission_method = INTEL_SUBMISSION_GUC;
1262 setup = intel_guc_submission_setup;
1263 } else if (HAS_EXECLISTS(gt->i915)) {
1264 gt->submission_method = INTEL_SUBMISSION_ELSP;
1265 setup = intel_execlists_submission_setup;
1266 } else {
1267 gt->submission_method = INTEL_SUBMISSION_RING;
1268 setup = intel_ring_submission_setup;
1269 }
1270
1271 for_each_engine(engine, gt, id) {
1272 err = engine_setup_common(engine);
1273 if (err)
1274 return err;
1275
1276 err = setup(engine);
1277 if (err)
1278 return err;
1279
1280 err = engine_init_common(engine);
1281 if (err)
1282 return err;
1283
1284 intel_engine_add_user(engine);
1285 }
1286
1287 return 0;
1288 }
1289
1290 /**
1291 * intel_engines_cleanup_common - cleans up the engine state created by
1292 * the common initiailizers.
1293 * @engine: Engine to cleanup.
1294 *
1295 * This cleans up everything created by the common helpers.
1296 */
intel_engine_cleanup_common(struct intel_engine_cs * engine)1297 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
1298 {
1299 GEM_BUG_ON(!list_empty(&engine->sched_engine->requests));
1300
1301 i915_sched_engine_put(engine->sched_engine);
1302 intel_breadcrumbs_put(engine->breadcrumbs);
1303
1304 intel_engine_fini_retire(engine);
1305 intel_engine_cleanup_cmd_parser(engine);
1306
1307 if (engine->default_state)
1308 fput(engine->default_state);
1309
1310 if (engine->kernel_context)
1311 intel_engine_destroy_pinned_context(engine->kernel_context);
1312
1313 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
1314 cleanup_status_page(engine);
1315
1316 intel_wa_list_free(&engine->ctx_wa_list);
1317 intel_wa_list_free(&engine->wa_list);
1318 intel_wa_list_free(&engine->whitelist);
1319 }
1320
1321 /**
1322 * intel_engine_resume - re-initializes the HW state of the engine
1323 * @engine: Engine to resume.
1324 *
1325 * Returns zero on success or an error code on failure.
1326 */
intel_engine_resume(struct intel_engine_cs * engine)1327 int intel_engine_resume(struct intel_engine_cs *engine)
1328 {
1329 intel_engine_apply_workarounds(engine);
1330 intel_engine_apply_whitelist(engine);
1331
1332 return engine->resume(engine);
1333 }
1334
intel_engine_get_active_head(const struct intel_engine_cs * engine)1335 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
1336 {
1337 struct drm_i915_private *i915 = engine->i915;
1338
1339 u64 acthd;
1340
1341 if (GRAPHICS_VER(i915) >= 8)
1342 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
1343 else if (GRAPHICS_VER(i915) >= 4)
1344 acthd = ENGINE_READ(engine, RING_ACTHD);
1345 else
1346 acthd = ENGINE_READ(engine, ACTHD);
1347
1348 return acthd;
1349 }
1350
intel_engine_get_last_batch_head(const struct intel_engine_cs * engine)1351 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
1352 {
1353 u64 bbaddr;
1354
1355 if (GRAPHICS_VER(engine->i915) >= 8)
1356 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
1357 else
1358 bbaddr = ENGINE_READ(engine, RING_BBADDR);
1359
1360 return bbaddr;
1361 }
1362
stop_timeout(const struct intel_engine_cs * engine)1363 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
1364 {
1365 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1366 return 0;
1367
1368 /*
1369 * If we are doing a normal GPU reset, we can take our time and allow
1370 * the engine to quiesce. We've stopped submission to the engine, and
1371 * if we wait long enough an innocent context should complete and
1372 * leave the engine idle. So they should not be caught unaware by
1373 * the forthcoming GPU reset (which usually follows the stop_cs)!
1374 */
1375 return READ_ONCE(engine->props.stop_timeout_ms);
1376 }
1377
__intel_engine_stop_cs(struct intel_engine_cs * engine,int fast_timeout_us,int slow_timeout_ms)1378 static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
1379 int fast_timeout_us,
1380 int slow_timeout_ms)
1381 {
1382 struct intel_uncore *uncore = engine->uncore;
1383 const i915_reg_t mode = RING_MI_MODE(engine->mmio_base);
1384 int err;
1385
1386 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1387
1388 /*
1389 * Wa_22011802037 : gen11, gen12, Prior to doing a reset, ensure CS is
1390 * stopped, set ring stop bit and prefetch disable bit to halt CS
1391 */
1392 if (IS_GRAPHICS_VER(engine->i915, 11, 12))
1393 intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
1394 _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
1395
1396 err = __intel_wait_for_register_fw(engine->uncore, mode,
1397 MODE_IDLE, MODE_IDLE,
1398 fast_timeout_us,
1399 slow_timeout_ms,
1400 NULL);
1401
1402 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1403 intel_uncore_posting_read_fw(uncore, mode);
1404 return err;
1405 }
1406
intel_engine_stop_cs(struct intel_engine_cs * engine)1407 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1408 {
1409 int err = 0;
1410
1411 if (GRAPHICS_VER(engine->i915) < 3)
1412 return -ENODEV;
1413
1414 ENGINE_TRACE(engine, "\n");
1415 /*
1416 * TODO: Find out why occasionally stopping the CS times out. Seen
1417 * especially with gem_eio tests.
1418 *
1419 * Occasionally trying to stop the cs times out, but does not adversely
1420 * affect functionality. The timeout is set as a config parameter that
1421 * defaults to 100ms. In most cases the follow up operation is to wait
1422 * for pending MI_FORCE_WAKES. The assumption is that this timeout is
1423 * sufficient for any pending MI_FORCEWAKEs to complete. Once root
1424 * caused, the caller must check and handle the return from this
1425 * function.
1426 */
1427 if (__intel_engine_stop_cs(engine, 1000, stop_timeout(engine))) {
1428 ENGINE_TRACE(engine,
1429 "timed out on STOP_RING -> IDLE; HEAD:%04x, TAIL:%04x\n",
1430 ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR,
1431 ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR);
1432
1433 /*
1434 * Sometimes we observe that the idle flag is not
1435 * set even though the ring is empty. So double
1436 * check before giving up.
1437 */
1438 if ((ENGINE_READ_FW(engine, RING_HEAD) & HEAD_ADDR) !=
1439 (ENGINE_READ_FW(engine, RING_TAIL) & TAIL_ADDR))
1440 err = -ETIMEDOUT;
1441 }
1442
1443 return err;
1444 }
1445
intel_engine_cancel_stop_cs(struct intel_engine_cs * engine)1446 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1447 {
1448 ENGINE_TRACE(engine, "\n");
1449
1450 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1451 }
1452
__cs_pending_mi_force_wakes(struct intel_engine_cs * engine)1453 static u32 __cs_pending_mi_force_wakes(struct intel_engine_cs *engine)
1454 {
1455 static const i915_reg_t _reg[I915_NUM_ENGINES] = {
1456 [RCS0] = MSG_IDLE_CS,
1457 [BCS0] = MSG_IDLE_BCS,
1458 [VCS0] = MSG_IDLE_VCS0,
1459 [VCS1] = MSG_IDLE_VCS1,
1460 [VCS2] = MSG_IDLE_VCS2,
1461 [VCS3] = MSG_IDLE_VCS3,
1462 [VCS4] = MSG_IDLE_VCS4,
1463 [VCS5] = MSG_IDLE_VCS5,
1464 [VCS6] = MSG_IDLE_VCS6,
1465 [VCS7] = MSG_IDLE_VCS7,
1466 [VECS0] = MSG_IDLE_VECS0,
1467 [VECS1] = MSG_IDLE_VECS1,
1468 [VECS2] = MSG_IDLE_VECS2,
1469 [VECS3] = MSG_IDLE_VECS3,
1470 [CCS0] = MSG_IDLE_CS,
1471 [CCS1] = MSG_IDLE_CS,
1472 [CCS2] = MSG_IDLE_CS,
1473 [CCS3] = MSG_IDLE_CS,
1474 };
1475 u32 val;
1476
1477 if (!_reg[engine->id].reg) {
1478 drm_err(&engine->i915->drm,
1479 "MSG IDLE undefined for engine id %u\n", engine->id);
1480 return 0;
1481 }
1482
1483 val = intel_uncore_read(engine->uncore, _reg[engine->id]);
1484
1485 /* bits[29:25] & bits[13:9] >> shift */
1486 return (val & (val >> 16) & MSG_IDLE_FW_MASK) >> MSG_IDLE_FW_SHIFT;
1487 }
1488
__gpm_wait_for_fw_complete(struct intel_gt * gt,u32 fw_mask)1489 static void __gpm_wait_for_fw_complete(struct intel_gt *gt, u32 fw_mask)
1490 {
1491 int ret;
1492
1493 /* Ensure GPM receives fw up/down after CS is stopped */
1494 udelay(1);
1495
1496 /* Wait for forcewake request to complete in GPM */
1497 ret = __intel_wait_for_register_fw(gt->uncore,
1498 GEN9_PWRGT_DOMAIN_STATUS,
1499 fw_mask, fw_mask, 5000, 0, NULL);
1500
1501 /* Ensure CS receives fw ack from GPM */
1502 udelay(1);
1503
1504 if (ret)
1505 GT_TRACE(gt, "Failed to complete pending forcewake %d\n", ret);
1506 }
1507
1508 /*
1509 * Wa_22011802037:gen12: In addition to stopping the cs, we need to wait for any
1510 * pending MI_FORCE_WAKEUP requests that the CS has initiated to complete. The
1511 * pending status is indicated by bits[13:9] (masked by bits[29:25]) in the
1512 * MSG_IDLE register. There's one MSG_IDLE register per reset domain. Since we
1513 * are concerned only with the gt reset here, we use a logical OR of pending
1514 * forcewakeups from all reset domains and then wait for them to complete by
1515 * querying PWRGT_DOMAIN_STATUS.
1516 */
intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs * engine)1517 void intel_engine_wait_for_pending_mi_fw(struct intel_engine_cs *engine)
1518 {
1519 u32 fw_pending = __cs_pending_mi_force_wakes(engine);
1520
1521 if (fw_pending)
1522 __gpm_wait_for_fw_complete(engine->gt, fw_pending);
1523 }
1524
1525 /* NB: please notice the memset */
intel_engine_get_instdone(const struct intel_engine_cs * engine,struct intel_instdone * instdone)1526 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1527 struct intel_instdone *instdone)
1528 {
1529 struct drm_i915_private *i915 = engine->i915;
1530 struct intel_uncore *uncore = engine->uncore;
1531 u32 mmio_base = engine->mmio_base;
1532 int slice;
1533 int subslice;
1534 int iter;
1535
1536 memset(instdone, 0, sizeof(*instdone));
1537
1538 if (GRAPHICS_VER(i915) >= 8) {
1539 instdone->instdone =
1540 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1541
1542 if (engine->id != RCS0)
1543 return;
1544
1545 instdone->slice_common =
1546 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1547 if (GRAPHICS_VER(i915) >= 12) {
1548 instdone->slice_common_extra[0] =
1549 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1550 instdone->slice_common_extra[1] =
1551 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1552 }
1553
1554 for_each_ss_steering(iter, engine->gt, slice, subslice) {
1555 instdone->sampler[slice][subslice] =
1556 intel_gt_mcr_read(engine->gt,
1557 GEN7_SAMPLER_INSTDONE,
1558 slice, subslice);
1559 instdone->row[slice][subslice] =
1560 intel_gt_mcr_read(engine->gt,
1561 GEN7_ROW_INSTDONE,
1562 slice, subslice);
1563 }
1564
1565 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
1566 for_each_ss_steering(iter, engine->gt, slice, subslice)
1567 instdone->geom_svg[slice][subslice] =
1568 intel_gt_mcr_read(engine->gt,
1569 XEHPG_INSTDONE_GEOM_SVG,
1570 slice, subslice);
1571 }
1572 } else if (GRAPHICS_VER(i915) >= 7) {
1573 instdone->instdone =
1574 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1575
1576 if (engine->id != RCS0)
1577 return;
1578
1579 instdone->slice_common =
1580 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1581 instdone->sampler[0][0] =
1582 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1583 instdone->row[0][0] =
1584 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1585 } else if (GRAPHICS_VER(i915) >= 4) {
1586 instdone->instdone =
1587 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1588 if (engine->id == RCS0)
1589 /* HACK: Using the wrong struct member */
1590 instdone->slice_common =
1591 intel_uncore_read(uncore, GEN4_INSTDONE1);
1592 } else {
1593 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1594 }
1595 }
1596
ring_is_idle(struct intel_engine_cs * engine)1597 static bool ring_is_idle(struct intel_engine_cs *engine)
1598 {
1599 bool idle = true;
1600
1601 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1602 return true;
1603
1604 if (!intel_engine_pm_get_if_awake(engine))
1605 return true;
1606
1607 /* First check that no commands are left in the ring */
1608 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1609 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1610 idle = false;
1611
1612 /* No bit for gen2, so assume the CS parser is idle */
1613 if (GRAPHICS_VER(engine->i915) > 2 &&
1614 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1615 idle = false;
1616
1617 intel_engine_pm_put(engine);
1618
1619 return idle;
1620 }
1621
__intel_engine_flush_submission(struct intel_engine_cs * engine,bool sync)1622 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync)
1623 {
1624 struct tasklet_struct *t = &engine->sched_engine->tasklet;
1625
1626 if (!t->callback)
1627 return;
1628
1629 local_bh_disable();
1630 if (tasklet_trylock(t)) {
1631 /* Must wait for any GPU reset in progress. */
1632 if (__tasklet_is_enabled(t))
1633 t->callback(t);
1634 tasklet_unlock(t);
1635 }
1636 local_bh_enable();
1637
1638 /* Synchronise and wait for the tasklet on another CPU */
1639 if (sync)
1640 tasklet_unlock_wait(t);
1641 }
1642
1643 /**
1644 * intel_engine_is_idle() - Report if the engine has finished process all work
1645 * @engine: the intel_engine_cs
1646 *
1647 * Return true if there are no requests pending, nothing left to be submitted
1648 * to hardware, and that the engine is idle.
1649 */
intel_engine_is_idle(struct intel_engine_cs * engine)1650 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1651 {
1652 /* More white lies, if wedged, hw state is inconsistent */
1653 if (intel_gt_is_wedged(engine->gt))
1654 return true;
1655
1656 if (!intel_engine_pm_is_awake(engine))
1657 return true;
1658
1659 /* Waiting to drain ELSP? */
1660 intel_synchronize_hardirq(engine->i915);
1661 intel_engine_flush_submission(engine);
1662
1663 /* ELSP is empty, but there are ready requests? E.g. after reset */
1664 if (!i915_sched_engine_is_empty(engine->sched_engine))
1665 return false;
1666
1667 /* Ring stopped? */
1668 return ring_is_idle(engine);
1669 }
1670
intel_engines_are_idle(struct intel_gt * gt)1671 bool intel_engines_are_idle(struct intel_gt *gt)
1672 {
1673 struct intel_engine_cs *engine;
1674 enum intel_engine_id id;
1675
1676 /*
1677 * If the driver is wedged, HW state may be very inconsistent and
1678 * report that it is still busy, even though we have stopped using it.
1679 */
1680 if (intel_gt_is_wedged(gt))
1681 return true;
1682
1683 /* Already parked (and passed an idleness test); must still be idle */
1684 if (!READ_ONCE(gt->awake))
1685 return true;
1686
1687 for_each_engine(engine, gt, id) {
1688 if (!intel_engine_is_idle(engine))
1689 return false;
1690 }
1691
1692 return true;
1693 }
1694
intel_engine_irq_enable(struct intel_engine_cs * engine)1695 bool intel_engine_irq_enable(struct intel_engine_cs *engine)
1696 {
1697 if (!engine->irq_enable)
1698 return false;
1699
1700 /* Caller disables interrupts */
1701 spin_lock(engine->gt->irq_lock);
1702 engine->irq_enable(engine);
1703 spin_unlock(engine->gt->irq_lock);
1704
1705 return true;
1706 }
1707
intel_engine_irq_disable(struct intel_engine_cs * engine)1708 void intel_engine_irq_disable(struct intel_engine_cs *engine)
1709 {
1710 if (!engine->irq_disable)
1711 return;
1712
1713 /* Caller disables interrupts */
1714 spin_lock(engine->gt->irq_lock);
1715 engine->irq_disable(engine);
1716 spin_unlock(engine->gt->irq_lock);
1717 }
1718
intel_engines_reset_default_submission(struct intel_gt * gt)1719 void intel_engines_reset_default_submission(struct intel_gt *gt)
1720 {
1721 struct intel_engine_cs *engine;
1722 enum intel_engine_id id;
1723
1724 for_each_engine(engine, gt, id) {
1725 if (engine->sanitize)
1726 engine->sanitize(engine);
1727
1728 engine->set_default_submission(engine);
1729 }
1730 }
1731
intel_engine_can_store_dword(struct intel_engine_cs * engine)1732 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1733 {
1734 switch (GRAPHICS_VER(engine->i915)) {
1735 case 2:
1736 return false; /* uses physical not virtual addresses */
1737 case 3:
1738 /* maybe only uses physical not virtual addresses */
1739 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1740 case 4:
1741 return !IS_I965G(engine->i915); /* who knows! */
1742 case 6:
1743 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1744 default:
1745 return true;
1746 }
1747 }
1748
get_timeline(struct i915_request * rq)1749 static struct intel_timeline *get_timeline(struct i915_request *rq)
1750 {
1751 struct intel_timeline *tl;
1752
1753 /*
1754 * Even though we are holding the engine->sched_engine->lock here, there
1755 * is no control over the submission queue per-se and we are
1756 * inspecting the active state at a random point in time, with an
1757 * unknown queue. Play safe and make sure the timeline remains valid.
1758 * (Only being used for pretty printing, one extra kref shouldn't
1759 * cause a camel stampede!)
1760 */
1761 rcu_read_lock();
1762 tl = rcu_dereference(rq->timeline);
1763 if (!kref_get_unless_zero(&tl->kref))
1764 tl = NULL;
1765 rcu_read_unlock();
1766
1767 return tl;
1768 }
1769
print_ring(char * buf,int sz,struct i915_request * rq)1770 static int print_ring(char *buf, int sz, struct i915_request *rq)
1771 {
1772 int len = 0;
1773
1774 if (!i915_request_signaled(rq)) {
1775 struct intel_timeline *tl = get_timeline(rq);
1776
1777 len = scnprintf(buf, sz,
1778 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1779 i915_ggtt_offset(rq->ring->vma),
1780 tl ? tl->hwsp_offset : 0,
1781 hwsp_seqno(rq),
1782 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1783 1000 * 1000));
1784
1785 if (tl)
1786 intel_timeline_put(tl);
1787 }
1788
1789 return len;
1790 }
1791
hexdump(struct drm_printer * m,const void * buf,size_t len)1792 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1793 {
1794 const size_t rowsize = 8 * sizeof(u32);
1795 const void *prev = NULL;
1796 bool skip = false;
1797 size_t pos;
1798
1799 for (pos = 0; pos < len; pos += rowsize) {
1800 char line[128];
1801
1802 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1803 if (!skip) {
1804 drm_printf(m, "*\n");
1805 skip = true;
1806 }
1807 continue;
1808 }
1809
1810 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1811 rowsize, sizeof(u32),
1812 line, sizeof(line),
1813 false) >= sizeof(line));
1814 drm_printf(m, "[%04zx] %s\n", pos, line);
1815
1816 prev = buf + pos;
1817 skip = false;
1818 }
1819 }
1820
repr_timer(const struct timer_list * t)1821 static const char *repr_timer(const struct timer_list *t)
1822 {
1823 if (!READ_ONCE(t->expires))
1824 return "inactive";
1825
1826 if (timer_pending(t))
1827 return "active";
1828
1829 return "expired";
1830 }
1831
intel_engine_print_registers(struct intel_engine_cs * engine,struct drm_printer * m)1832 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1833 struct drm_printer *m)
1834 {
1835 struct drm_i915_private *dev_priv = engine->i915;
1836 struct intel_engine_execlists * const execlists = &engine->execlists;
1837 u64 addr;
1838
1839 if (engine->id == RENDER_CLASS && IS_GRAPHICS_VER(dev_priv, 4, 7))
1840 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1841 if (HAS_EXECLISTS(dev_priv)) {
1842 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1843 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1844 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1845 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1846 }
1847 drm_printf(m, "\tRING_START: 0x%08x\n",
1848 ENGINE_READ(engine, RING_START));
1849 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1850 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1851 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1852 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1853 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1854 ENGINE_READ(engine, RING_CTL),
1855 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1856 if (GRAPHICS_VER(engine->i915) > 2) {
1857 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1858 ENGINE_READ(engine, RING_MI_MODE),
1859 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1860 }
1861
1862 if (GRAPHICS_VER(dev_priv) >= 6) {
1863 drm_printf(m, "\tRING_IMR: 0x%08x\n",
1864 ENGINE_READ(engine, RING_IMR));
1865 drm_printf(m, "\tRING_ESR: 0x%08x\n",
1866 ENGINE_READ(engine, RING_ESR));
1867 drm_printf(m, "\tRING_EMR: 0x%08x\n",
1868 ENGINE_READ(engine, RING_EMR));
1869 drm_printf(m, "\tRING_EIR: 0x%08x\n",
1870 ENGINE_READ(engine, RING_EIR));
1871 }
1872
1873 addr = intel_engine_get_active_head(engine);
1874 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1875 upper_32_bits(addr), lower_32_bits(addr));
1876 addr = intel_engine_get_last_batch_head(engine);
1877 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1878 upper_32_bits(addr), lower_32_bits(addr));
1879 if (GRAPHICS_VER(dev_priv) >= 8)
1880 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1881 else if (GRAPHICS_VER(dev_priv) >= 4)
1882 addr = ENGINE_READ(engine, RING_DMA_FADD);
1883 else
1884 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1885 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1886 upper_32_bits(addr), lower_32_bits(addr));
1887 if (GRAPHICS_VER(dev_priv) >= 4) {
1888 drm_printf(m, "\tIPEIR: 0x%08x\n",
1889 ENGINE_READ(engine, RING_IPEIR));
1890 drm_printf(m, "\tIPEHR: 0x%08x\n",
1891 ENGINE_READ(engine, RING_IPEHR));
1892 } else {
1893 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1894 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1895 }
1896
1897 if (HAS_EXECLISTS(dev_priv) && !intel_engine_uses_guc(engine)) {
1898 struct i915_request * const *port, *rq;
1899 const u32 *hws =
1900 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1901 const u8 num_entries = execlists->csb_size;
1902 unsigned int idx;
1903 u8 read, write;
1904
1905 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1906 str_yes_no(test_bit(TASKLET_STATE_SCHED, &engine->sched_engine->tasklet.state)),
1907 str_enabled_disabled(!atomic_read(&engine->sched_engine->tasklet.count)),
1908 repr_timer(&engine->execlists.preempt),
1909 repr_timer(&engine->execlists.timer));
1910
1911 read = execlists->csb_head;
1912 write = READ_ONCE(*execlists->csb_write);
1913
1914 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1915 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1916 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1917 read, write, num_entries);
1918
1919 if (read >= num_entries)
1920 read = 0;
1921 if (write >= num_entries)
1922 write = 0;
1923 if (read > write)
1924 write += num_entries;
1925 while (read < write) {
1926 idx = ++read % num_entries;
1927 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1928 idx, hws[idx * 2], hws[idx * 2 + 1]);
1929 }
1930
1931 i915_sched_engine_active_lock_bh(engine->sched_engine);
1932 rcu_read_lock();
1933 for (port = execlists->active; (rq = *port); port++) {
1934 char hdr[160];
1935 int len;
1936
1937 len = scnprintf(hdr, sizeof(hdr),
1938 "\t\tActive[%d]: ccid:%08x%s%s, ",
1939 (int)(port - execlists->active),
1940 rq->context->lrc.ccid,
1941 intel_context_is_closed(rq->context) ? "!" : "",
1942 intel_context_is_banned(rq->context) ? "*" : "");
1943 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1944 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1945 i915_request_show(m, rq, hdr, 0);
1946 }
1947 for (port = execlists->pending; (rq = *port); port++) {
1948 char hdr[160];
1949 int len;
1950
1951 len = scnprintf(hdr, sizeof(hdr),
1952 "\t\tPending[%d]: ccid:%08x%s%s, ",
1953 (int)(port - execlists->pending),
1954 rq->context->lrc.ccid,
1955 intel_context_is_closed(rq->context) ? "!" : "",
1956 intel_context_is_banned(rq->context) ? "*" : "");
1957 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1958 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1959 i915_request_show(m, rq, hdr, 0);
1960 }
1961 rcu_read_unlock();
1962 i915_sched_engine_active_unlock_bh(engine->sched_engine);
1963 } else if (GRAPHICS_VER(dev_priv) > 6) {
1964 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1965 ENGINE_READ(engine, RING_PP_DIR_BASE));
1966 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1967 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1968 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1969 ENGINE_READ(engine, RING_PP_DIR_DCLV));
1970 }
1971 }
1972
print_request_ring(struct drm_printer * m,struct i915_request * rq)1973 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1974 {
1975 struct i915_vma_resource *vma_res = rq->batch_res;
1976 void *ring;
1977 int size;
1978
1979 drm_printf(m,
1980 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1981 rq->head, rq->postfix, rq->tail,
1982 vma_res ? upper_32_bits(vma_res->start) : ~0u,
1983 vma_res ? lower_32_bits(vma_res->start) : ~0u);
1984
1985 size = rq->tail - rq->head;
1986 if (rq->tail < rq->head)
1987 size += rq->ring->size;
1988
1989 ring = kmalloc(size, GFP_ATOMIC);
1990 if (ring) {
1991 const void *vaddr = rq->ring->vaddr;
1992 unsigned int head = rq->head;
1993 unsigned int len = 0;
1994
1995 if (rq->tail < head) {
1996 len = rq->ring->size - head;
1997 memcpy(ring, vaddr + head, len);
1998 head = 0;
1999 }
2000 memcpy(ring + len, vaddr + head, size - len);
2001
2002 hexdump(m, ring, size);
2003 kfree(ring);
2004 }
2005 }
2006
list_count(struct list_head * list)2007 static unsigned long list_count(struct list_head *list)
2008 {
2009 struct list_head *pos;
2010 unsigned long count = 0;
2011
2012 list_for_each(pos, list)
2013 count++;
2014
2015 return count;
2016 }
2017
read_ul(void * p,size_t x)2018 static unsigned long read_ul(void *p, size_t x)
2019 {
2020 return *(unsigned long *)(p + x);
2021 }
2022
print_properties(struct intel_engine_cs * engine,struct drm_printer * m)2023 static void print_properties(struct intel_engine_cs *engine,
2024 struct drm_printer *m)
2025 {
2026 static const struct pmap {
2027 size_t offset;
2028 const char *name;
2029 } props[] = {
2030 #define P(x) { \
2031 .offset = offsetof(typeof(engine->props), x), \
2032 .name = #x \
2033 }
2034 P(heartbeat_interval_ms),
2035 P(max_busywait_duration_ns),
2036 P(preempt_timeout_ms),
2037 P(stop_timeout_ms),
2038 P(timeslice_duration_ms),
2039
2040 {},
2041 #undef P
2042 };
2043 const struct pmap *p;
2044
2045 drm_printf(m, "\tProperties:\n");
2046 for (p = props; p->name; p++)
2047 drm_printf(m, "\t\t%s: %lu [default %lu]\n",
2048 p->name,
2049 read_ul(&engine->props, p->offset),
2050 read_ul(&engine->defaults, p->offset));
2051 }
2052
engine_dump_request(struct i915_request * rq,struct drm_printer * m,const char * msg)2053 static void engine_dump_request(struct i915_request *rq, struct drm_printer *m, const char *msg)
2054 {
2055 struct intel_timeline *tl = get_timeline(rq);
2056
2057 i915_request_show(m, rq, msg, 0);
2058
2059 drm_printf(m, "\t\tring->start: 0x%08x\n",
2060 i915_ggtt_offset(rq->ring->vma));
2061 drm_printf(m, "\t\tring->head: 0x%08x\n",
2062 rq->ring->head);
2063 drm_printf(m, "\t\tring->tail: 0x%08x\n",
2064 rq->ring->tail);
2065 drm_printf(m, "\t\tring->emit: 0x%08x\n",
2066 rq->ring->emit);
2067 drm_printf(m, "\t\tring->space: 0x%08x\n",
2068 rq->ring->space);
2069
2070 if (tl) {
2071 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
2072 tl->hwsp_offset);
2073 intel_timeline_put(tl);
2074 }
2075
2076 print_request_ring(m, rq);
2077
2078 if (rq->context->lrc_reg_state) {
2079 drm_printf(m, "Logical Ring Context:\n");
2080 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
2081 }
2082 }
2083
intel_engine_dump_active_requests(struct list_head * requests,struct i915_request * hung_rq,struct drm_printer * m)2084 void intel_engine_dump_active_requests(struct list_head *requests,
2085 struct i915_request *hung_rq,
2086 struct drm_printer *m)
2087 {
2088 struct i915_request *rq;
2089 const char *msg;
2090 enum i915_request_state state;
2091
2092 list_for_each_entry(rq, requests, sched.link) {
2093 if (rq == hung_rq)
2094 continue;
2095
2096 state = i915_test_request_state(rq);
2097 if (state < I915_REQUEST_QUEUED)
2098 continue;
2099
2100 if (state == I915_REQUEST_ACTIVE)
2101 msg = "\t\tactive on engine";
2102 else
2103 msg = "\t\tactive in queue";
2104
2105 engine_dump_request(rq, m, msg);
2106 }
2107 }
2108
engine_dump_active_requests(struct intel_engine_cs * engine,struct drm_printer * m)2109 static void engine_dump_active_requests(struct intel_engine_cs *engine, struct drm_printer *m)
2110 {
2111 struct i915_request *hung_rq = NULL;
2112 struct intel_context *ce;
2113 bool guc;
2114
2115 /*
2116 * No need for an engine->irq_seqno_barrier() before the seqno reads.
2117 * The GPU is still running so requests are still executing and any
2118 * hardware reads will be out of date by the time they are reported.
2119 * But the intention here is just to report an instantaneous snapshot
2120 * so that's fine.
2121 */
2122 lockdep_assert_held(&engine->sched_engine->lock);
2123
2124 drm_printf(m, "\tRequests:\n");
2125
2126 guc = intel_uc_uses_guc_submission(&engine->gt->uc);
2127 if (guc) {
2128 ce = intel_engine_get_hung_context(engine);
2129 if (ce)
2130 hung_rq = intel_context_find_active_request(ce);
2131 } else {
2132 hung_rq = intel_engine_execlist_find_hung_request(engine);
2133 }
2134
2135 if (hung_rq)
2136 engine_dump_request(hung_rq, m, "\t\thung");
2137
2138 if (guc)
2139 intel_guc_dump_active_requests(engine, hung_rq, m);
2140 else
2141 intel_engine_dump_active_requests(&engine->sched_engine->requests,
2142 hung_rq, m);
2143 }
2144
intel_engine_dump(struct intel_engine_cs * engine,struct drm_printer * m,const char * header,...)2145 void intel_engine_dump(struct intel_engine_cs *engine,
2146 struct drm_printer *m,
2147 const char *header, ...)
2148 {
2149 struct i915_gpu_error * const error = &engine->i915->gpu_error;
2150 struct i915_request *rq;
2151 intel_wakeref_t wakeref;
2152 unsigned long flags;
2153 ktime_t dummy;
2154
2155 if (header) {
2156 va_list ap;
2157
2158 va_start(ap, header);
2159 drm_vprintf(m, header, &ap);
2160 va_end(ap);
2161 }
2162
2163 if (intel_gt_is_wedged(engine->gt))
2164 drm_printf(m, "*** WEDGED ***\n");
2165
2166 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
2167 drm_printf(m, "\tBarriers?: %s\n",
2168 str_yes_no(!llist_empty(&engine->barrier_tasks)));
2169 drm_printf(m, "\tLatency: %luus\n",
2170 ewma__engine_latency_read(&engine->latency));
2171 if (intel_engine_supports_stats(engine))
2172 drm_printf(m, "\tRuntime: %llums\n",
2173 ktime_to_ms(intel_engine_get_busy_time(engine,
2174 &dummy)));
2175 drm_printf(m, "\tForcewake: %x domains, %d active\n",
2176 engine->fw_domain, READ_ONCE(engine->fw_active));
2177
2178 rcu_read_lock();
2179 rq = READ_ONCE(engine->heartbeat.systole);
2180 if (rq)
2181 drm_printf(m, "\tHeartbeat: %d ms ago\n",
2182 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
2183 rcu_read_unlock();
2184 drm_printf(m, "\tReset count: %d (global %d)\n",
2185 i915_reset_engine_count(error, engine),
2186 i915_reset_count(error));
2187 print_properties(engine, m);
2188
2189 spin_lock_irqsave(&engine->sched_engine->lock, flags);
2190 engine_dump_active_requests(engine, m);
2191
2192 drm_printf(m, "\tOn hold?: %lu\n",
2193 list_count(&engine->sched_engine->hold));
2194 spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
2195
2196 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
2197 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
2198 if (wakeref) {
2199 intel_engine_print_registers(engine, m);
2200 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
2201 } else {
2202 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
2203 }
2204
2205 intel_execlists_show_requests(engine, m, i915_request_show, 8);
2206
2207 drm_printf(m, "HWSP:\n");
2208 hexdump(m, engine->status_page.addr, PAGE_SIZE);
2209
2210 drm_printf(m, "Idle? %s\n", str_yes_no(intel_engine_is_idle(engine)));
2211
2212 intel_engine_print_breadcrumbs(engine, m);
2213 }
2214
2215 /**
2216 * intel_engine_get_busy_time() - Return current accumulated engine busyness
2217 * @engine: engine to report on
2218 * @now: monotonic timestamp of sampling
2219 *
2220 * Returns accumulated time @engine was busy since engine stats were enabled.
2221 */
intel_engine_get_busy_time(struct intel_engine_cs * engine,ktime_t * now)2222 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
2223 {
2224 return engine->busyness(engine, now);
2225 }
2226
2227 struct intel_context *
intel_engine_create_virtual(struct intel_engine_cs ** siblings,unsigned int count,unsigned long flags)2228 intel_engine_create_virtual(struct intel_engine_cs **siblings,
2229 unsigned int count, unsigned long flags)
2230 {
2231 if (count == 0)
2232 return ERR_PTR(-EINVAL);
2233
2234 if (count == 1 && !(flags & FORCE_VIRTUAL))
2235 return intel_context_create(siblings[0]);
2236
2237 GEM_BUG_ON(!siblings[0]->cops->create_virtual);
2238 return siblings[0]->cops->create_virtual(siblings, count, flags);
2239 }
2240
2241 struct i915_request *
intel_engine_execlist_find_hung_request(struct intel_engine_cs * engine)2242 intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine)
2243 {
2244 struct i915_request *request, *active = NULL;
2245
2246 /*
2247 * This search does not work in GuC submission mode. However, the GuC
2248 * will report the hanging context directly to the driver itself. So
2249 * the driver should never get here when in GuC mode.
2250 */
2251 GEM_BUG_ON(intel_uc_uses_guc_submission(&engine->gt->uc));
2252
2253 /*
2254 * We are called by the error capture, reset and to dump engine
2255 * state at random points in time. In particular, note that neither is
2256 * crucially ordered with an interrupt. After a hang, the GPU is dead
2257 * and we assume that no more writes can happen (we waited long enough
2258 * for all writes that were in transaction to be flushed) - adding an
2259 * extra delay for a recent interrupt is pointless. Hence, we do
2260 * not need an engine->irq_seqno_barrier() before the seqno reads.
2261 * At all other times, we must assume the GPU is still running, but
2262 * we only care about the snapshot of this moment.
2263 */
2264 lockdep_assert_held(&engine->sched_engine->lock);
2265
2266 rcu_read_lock();
2267 request = execlists_active(&engine->execlists);
2268 if (request) {
2269 struct intel_timeline *tl = request->context->timeline;
2270
2271 list_for_each_entry_from_reverse(request, &tl->requests, link) {
2272 if (__i915_request_is_complete(request))
2273 break;
2274
2275 active = request;
2276 }
2277 }
2278 rcu_read_unlock();
2279 if (active)
2280 return active;
2281
2282 list_for_each_entry(request, &engine->sched_engine->requests,
2283 sched.link) {
2284 if (i915_test_request_state(request) != I915_REQUEST_ACTIVE)
2285 continue;
2286
2287 active = request;
2288 break;
2289 }
2290
2291 return active;
2292 }
2293
xehp_enable_ccs_engines(struct intel_engine_cs * engine)2294 void xehp_enable_ccs_engines(struct intel_engine_cs *engine)
2295 {
2296 /*
2297 * If there are any non-fused-off CCS engines, we need to enable CCS
2298 * support in the RCU_MODE register. This only needs to be done once,
2299 * so for simplicity we'll take care of this in the RCS engine's
2300 * resume handler; since the RCS and all CCS engines belong to the
2301 * same reset domain and are reset together, this will also take care
2302 * of re-applying the setting after i915-triggered resets.
2303 */
2304 if (!CCS_MASK(engine->gt))
2305 return;
2306
2307 intel_uncore_write(engine->uncore, GEN12_RCU_MODE,
2308 _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));
2309 }
2310
2311 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2312 #include "mock_engine.c"
2313 #include "selftest_engine.c"
2314 #include "selftest_engine_cs.c"
2315 #endif
2316
