1 /*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "intel_drv.h"
25
26 static void
intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])27 intel_dp_dump_link_status(const uint8_t link_status[DP_LINK_STATUS_SIZE])
28 {
29
30 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x",
31 link_status[0], link_status[1], link_status[2],
32 link_status[3], link_status[4], link_status[5]);
33 }
34
35 static void
intel_get_adjust_train(struct intel_dp * intel_dp,const uint8_t link_status[DP_LINK_STATUS_SIZE])36 intel_get_adjust_train(struct intel_dp *intel_dp,
37 const uint8_t link_status[DP_LINK_STATUS_SIZE])
38 {
39 uint8_t v = 0;
40 uint8_t p = 0;
41 int lane;
42 uint8_t voltage_max;
43 uint8_t preemph_max;
44
45 for (lane = 0; lane < intel_dp->lane_count; lane++) {
46 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
47 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
48
49 if (this_v > v)
50 v = this_v;
51 if (this_p > p)
52 p = this_p;
53 }
54
55 voltage_max = intel_dp_voltage_max(intel_dp);
56 if (v >= voltage_max)
57 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
58
59 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
60 if (p >= preemph_max)
61 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
62
63 for (lane = 0; lane < 4; lane++)
64 intel_dp->train_set[lane] = v | p;
65 }
66
67 static bool
intel_dp_set_link_train(struct intel_dp * intel_dp,uint8_t dp_train_pat)68 intel_dp_set_link_train(struct intel_dp *intel_dp,
69 uint8_t dp_train_pat)
70 {
71 uint8_t buf[sizeof(intel_dp->train_set) + 1];
72 int ret, len;
73
74 intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
75
76 buf[0] = dp_train_pat;
77 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
78 DP_TRAINING_PATTERN_DISABLE) {
79 /* don't write DP_TRAINING_LANEx_SET on disable */
80 len = 1;
81 } else {
82 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
83 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
84 len = intel_dp->lane_count + 1;
85 }
86
87 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
88 buf, len);
89
90 return ret == len;
91 }
92
93 static bool
intel_dp_reset_link_train(struct intel_dp * intel_dp,uint8_t dp_train_pat)94 intel_dp_reset_link_train(struct intel_dp *intel_dp,
95 uint8_t dp_train_pat)
96 {
97 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
98 intel_dp_set_signal_levels(intel_dp);
99 return intel_dp_set_link_train(intel_dp, dp_train_pat);
100 }
101
102 static bool
intel_dp_update_link_train(struct intel_dp * intel_dp)103 intel_dp_update_link_train(struct intel_dp *intel_dp)
104 {
105 int ret;
106
107 intel_dp_set_signal_levels(intel_dp);
108
109 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
110 intel_dp->train_set, intel_dp->lane_count);
111
112 return ret == intel_dp->lane_count;
113 }
114
intel_dp_link_max_vswing_reached(struct intel_dp * intel_dp)115 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp)
116 {
117 int lane;
118
119 for (lane = 0; lane < intel_dp->lane_count; lane++)
120 if ((intel_dp->train_set[lane] &
121 DP_TRAIN_MAX_SWING_REACHED) == 0)
122 return false;
123
124 return true;
125 }
126
127 /* Enable corresponding port and start training pattern 1 */
128 static bool
intel_dp_link_training_clock_recovery(struct intel_dp * intel_dp)129 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
130 {
131 uint8_t voltage;
132 int voltage_tries, max_vswing_tries;
133 uint8_t link_config[2];
134 uint8_t link_bw, rate_select;
135
136 if (intel_dp->prepare_link_retrain)
137 intel_dp->prepare_link_retrain(intel_dp);
138
139 intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
140 &link_bw, &rate_select);
141
142 if (link_bw)
143 DRM_DEBUG_KMS("Using LINK_BW_SET value %02x\n", link_bw);
144 else
145 DRM_DEBUG_KMS("Using LINK_RATE_SET value %02x\n", rate_select);
146
147 /* Write the link configuration data */
148 link_config[0] = link_bw;
149 link_config[1] = intel_dp->lane_count;
150 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
151 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
152 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
153
154 /* eDP 1.4 rate select method. */
155 if (!link_bw)
156 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
157 &rate_select, 1);
158
159 link_config[0] = 0;
160 link_config[1] = DP_SET_ANSI_8B10B;
161 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
162
163 intel_dp->DP |= DP_PORT_EN;
164
165 /* clock recovery */
166 if (!intel_dp_reset_link_train(intel_dp,
167 DP_TRAINING_PATTERN_1 |
168 DP_LINK_SCRAMBLING_DISABLE)) {
169 DRM_ERROR("failed to enable link training\n");
170 return false;
171 }
172
173 voltage_tries = 1;
174 max_vswing_tries = 0;
175 for (;;) {
176 uint8_t link_status[DP_LINK_STATUS_SIZE];
177
178 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
179
180 if (!intel_dp_get_link_status(intel_dp, link_status)) {
181 DRM_ERROR("failed to get link status\n");
182 return false;
183 }
184
185 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
186 DRM_DEBUG_KMS("clock recovery OK\n");
187 return true;
188 }
189
190 if (voltage_tries == 5) {
191 DRM_DEBUG_KMS("Same voltage tried 5 times\n");
192 return false;
193 }
194
195 if (max_vswing_tries == 1) {
196 DRM_DEBUG_KMS("Max Voltage Swing reached\n");
197 return false;
198 }
199
200 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
201
202 /* Update training set as requested by target */
203 intel_get_adjust_train(intel_dp, link_status);
204 if (!intel_dp_update_link_train(intel_dp)) {
205 DRM_ERROR("failed to update link training\n");
206 return false;
207 }
208
209 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
210 voltage)
211 ++voltage_tries;
212 else
213 voltage_tries = 1;
214
215 if (intel_dp_link_max_vswing_reached(intel_dp))
216 ++max_vswing_tries;
217
218 }
219 }
220
221 /*
222 * Pick training pattern for channel equalization. Training pattern 4 for HBR3
223 * or for 1.4 devices that support it, training Pattern 3 for HBR2
224 * or 1.2 devices that support it, Training Pattern 2 otherwise.
225 */
intel_dp_training_pattern(struct intel_dp * intel_dp)226 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
227 {
228 bool source_tps3, sink_tps3, source_tps4, sink_tps4;
229
230 /*
231 * Intel platforms that support HBR3 also support TPS4. It is mandatory
232 * for all downstream devices that support HBR3. There are no known eDP
233 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
234 * specification.
235 */
236 source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
237 sink_tps4 = drm_dp_tps4_supported(intel_dp->dpcd);
238 if (source_tps4 && sink_tps4) {
239 return DP_TRAINING_PATTERN_4;
240 } else if (intel_dp->link_rate == 810000) {
241 if (!source_tps4)
242 DRM_DEBUG_KMS("8.1 Gbps link rate without source HBR3/TPS4 support\n");
243 if (!sink_tps4)
244 DRM_DEBUG_KMS("8.1 Gbps link rate without sink TPS4 support\n");
245 }
246 /*
247 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
248 * also mandatory for downstream devices that support HBR2. However, not
249 * all sinks follow the spec.
250 */
251 source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
252 sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
253 if (source_tps3 && sink_tps3) {
254 return DP_TRAINING_PATTERN_3;
255 } else if (intel_dp->link_rate >= 540000) {
256 if (!source_tps3)
257 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
258 if (!sink_tps3)
259 DRM_DEBUG_KMS(">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
260 }
261
262 return DP_TRAINING_PATTERN_2;
263 }
264
265 static bool
intel_dp_link_training_channel_equalization(struct intel_dp * intel_dp)266 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
267 {
268 int tries;
269 u32 training_pattern;
270 uint8_t link_status[DP_LINK_STATUS_SIZE];
271 bool channel_eq = false;
272
273 training_pattern = intel_dp_training_pattern(intel_dp);
274 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
275 if (training_pattern != DP_TRAINING_PATTERN_4)
276 training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
277
278 /* channel equalization */
279 if (!intel_dp_set_link_train(intel_dp,
280 training_pattern)) {
281 DRM_ERROR("failed to start channel equalization\n");
282 return false;
283 }
284
285 for (tries = 0; tries < 5; tries++) {
286
287 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
288 if (!intel_dp_get_link_status(intel_dp, link_status)) {
289 DRM_ERROR("failed to get link status\n");
290 break;
291 }
292
293 /* Make sure clock is still ok */
294 if (!drm_dp_clock_recovery_ok(link_status,
295 intel_dp->lane_count)) {
296 intel_dp_dump_link_status(link_status);
297 DRM_DEBUG_KMS("Clock recovery check failed, cannot "
298 "continue channel equalization\n");
299 break;
300 }
301
302 if (drm_dp_channel_eq_ok(link_status,
303 intel_dp->lane_count)) {
304 channel_eq = true;
305 DRM_DEBUG_KMS("Channel EQ done. DP Training "
306 "successful\n");
307 break;
308 }
309
310 /* Update training set as requested by target */
311 intel_get_adjust_train(intel_dp, link_status);
312 if (!intel_dp_update_link_train(intel_dp)) {
313 DRM_ERROR("failed to update link training\n");
314 break;
315 }
316 }
317
318 /* Try 5 times, else fail and try at lower BW */
319 if (tries == 5) {
320 intel_dp_dump_link_status(link_status);
321 DRM_DEBUG_KMS("Channel equalization failed 5 times\n");
322 }
323
324 intel_dp_set_idle_link_train(intel_dp);
325
326 return channel_eq;
327
328 }
329
intel_dp_stop_link_train(struct intel_dp * intel_dp)330 void intel_dp_stop_link_train(struct intel_dp *intel_dp)
331 {
332 intel_dp->link_trained = true;
333
334 intel_dp_set_link_train(intel_dp,
335 DP_TRAINING_PATTERN_DISABLE);
336 }
337
338 void
intel_dp_start_link_train(struct intel_dp * intel_dp)339 intel_dp_start_link_train(struct intel_dp *intel_dp)
340 {
341 struct intel_connector *intel_connector = intel_dp->attached_connector;
342
343 if (!intel_dp_link_training_clock_recovery(intel_dp))
344 goto failure_handling;
345 if (!intel_dp_link_training_channel_equalization(intel_dp))
346 goto failure_handling;
347
348 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training Passed at Link Rate = %d, Lane count = %d",
349 intel_connector->base.base.id,
350 intel_connector->base.name,
351 intel_dp->link_rate, intel_dp->lane_count);
352 return;
353
354 failure_handling:
355 /* Dont fallback and prune modes if its eDP */
356 if (!intel_dp_is_edp(intel_dp)) {
357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
358 intel_connector->base.base.id,
359 intel_connector->base.name,
360 intel_dp->link_rate, intel_dp->lane_count);
361 if (!intel_dp_get_link_train_fallback_values(intel_dp,
362 intel_dp->link_rate,
363 intel_dp->lane_count))
364 /* Schedule a Hotplug Uevent to userspace to start modeset */
365 schedule_work(&intel_connector->modeset_retry_work);
366 } else {
367 DRM_ERROR("[CONNECTOR:%d:%s] Link Training failed at link rate = %d, lane count = %d",
368 intel_connector->base.base.id,
369 intel_connector->base.name,
370 intel_dp->link_rate, intel_dp->lane_count);
371 }
372 return;
373 }
374
