1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright (C) 2020 Google, Inc.
4 *
5 * Authors:
6 * Sean Paul <seanpaul@chromium.org>
7 */
8
9 #include <drm/drm_dp_helper.h>
10 #include <drm/drm_dp_mst_helper.h>
11 #include <drm/drm_hdcp.h>
12 #include <drm/drm_print.h>
13
14 #include "intel_ddi.h"
15 #include "intel_de.h"
16 #include "intel_display_types.h"
17 #include "intel_dp.h"
18 #include "intel_dp_hdcp.h"
19 #include "intel_hdcp.h"
20
transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)21 static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
22 {
23 u32 stream_enc_mask;
24
25 switch (cpu_transcoder) {
26 case TRANSCODER_A:
27 stream_enc_mask = HDCP_STATUS_STREAM_A_ENC;
28 break;
29 case TRANSCODER_B:
30 stream_enc_mask = HDCP_STATUS_STREAM_B_ENC;
31 break;
32 case TRANSCODER_C:
33 stream_enc_mask = HDCP_STATUS_STREAM_C_ENC;
34 break;
35 case TRANSCODER_D:
36 stream_enc_mask = HDCP_STATUS_STREAM_D_ENC;
37 break;
38 default:
39 stream_enc_mask = 0;
40 }
41
42 return stream_enc_mask;
43 }
44
intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp * hdcp,int timeout)45 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
46 {
47 long ret;
48
49 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
50 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
51 msecs_to_jiffies(timeout));
52
53 if (!ret)
54 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
55 }
56
57 static
intel_dp_hdcp_write_an_aksv(struct intel_digital_port * dig_port,u8 * an)58 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
59 u8 *an)
60 {
61 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
62 u8 aksv[DRM_HDCP_KSV_LEN] = {};
63 ssize_t dpcd_ret;
64
65 /* Output An first, that's easy */
66 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
67 an, DRM_HDCP_AN_LEN);
68 if (dpcd_ret != DRM_HDCP_AN_LEN) {
69 drm_dbg_kms(&i915->drm,
70 "Failed to write An over DP/AUX (%zd)\n",
71 dpcd_ret);
72 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
73 }
74
75 /*
76 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
77 * send an empty buffer of the correct length through the DP helpers. On
78 * the other side, in the transfer hook, we'll generate a flag based on
79 * the destination address which will tickle the hardware to output the
80 * Aksv on our behalf after the header is sent.
81 */
82 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
83 aksv, DRM_HDCP_KSV_LEN);
84 if (dpcd_ret != DRM_HDCP_KSV_LEN) {
85 drm_dbg_kms(&i915->drm,
86 "Failed to write Aksv over DP/AUX (%zd)\n",
87 dpcd_ret);
88 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
89 }
90 return 0;
91 }
92
intel_dp_hdcp_read_bksv(struct intel_digital_port * dig_port,u8 * bksv)93 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
94 u8 *bksv)
95 {
96 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
97 ssize_t ret;
98
99 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
100 DRM_HDCP_KSV_LEN);
101 if (ret != DRM_HDCP_KSV_LEN) {
102 drm_dbg_kms(&i915->drm,
103 "Read Bksv from DP/AUX failed (%zd)\n", ret);
104 return ret >= 0 ? -EIO : ret;
105 }
106 return 0;
107 }
108
intel_dp_hdcp_read_bstatus(struct intel_digital_port * dig_port,u8 * bstatus)109 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
110 u8 *bstatus)
111 {
112 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
113 ssize_t ret;
114
115 /*
116 * For some reason the HDMI and DP HDCP specs call this register
117 * definition by different names. In the HDMI spec, it's called BSTATUS,
118 * but in DP it's called BINFO.
119 */
120 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
121 bstatus, DRM_HDCP_BSTATUS_LEN);
122 if (ret != DRM_HDCP_BSTATUS_LEN) {
123 drm_dbg_kms(&i915->drm,
124 "Read bstatus from DP/AUX failed (%zd)\n", ret);
125 return ret >= 0 ? -EIO : ret;
126 }
127 return 0;
128 }
129
130 static
intel_dp_hdcp_read_bcaps(struct intel_digital_port * dig_port,u8 * bcaps)131 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
132 u8 *bcaps)
133 {
134 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
135 ssize_t ret;
136
137 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
138 bcaps, 1);
139 if (ret != 1) {
140 drm_dbg_kms(&i915->drm,
141 "Read bcaps from DP/AUX failed (%zd)\n", ret);
142 return ret >= 0 ? -EIO : ret;
143 }
144
145 return 0;
146 }
147
148 static
intel_dp_hdcp_repeater_present(struct intel_digital_port * dig_port,bool * repeater_present)149 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
150 bool *repeater_present)
151 {
152 ssize_t ret;
153 u8 bcaps;
154
155 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
156 if (ret)
157 return ret;
158
159 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
160 return 0;
161 }
162
163 static
intel_dp_hdcp_read_ri_prime(struct intel_digital_port * dig_port,u8 * ri_prime)164 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
165 u8 *ri_prime)
166 {
167 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
168 ssize_t ret;
169
170 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
171 ri_prime, DRM_HDCP_RI_LEN);
172 if (ret != DRM_HDCP_RI_LEN) {
173 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
174 ret);
175 return ret >= 0 ? -EIO : ret;
176 }
177 return 0;
178 }
179
180 static
intel_dp_hdcp_read_ksv_ready(struct intel_digital_port * dig_port,bool * ksv_ready)181 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
182 bool *ksv_ready)
183 {
184 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
185 ssize_t ret;
186 u8 bstatus;
187
188 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
189 &bstatus, 1);
190 if (ret != 1) {
191 drm_dbg_kms(&i915->drm,
192 "Read bstatus from DP/AUX failed (%zd)\n", ret);
193 return ret >= 0 ? -EIO : ret;
194 }
195 *ksv_ready = bstatus & DP_BSTATUS_READY;
196 return 0;
197 }
198
199 static
intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port * dig_port,int num_downstream,u8 * ksv_fifo)200 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
201 int num_downstream, u8 *ksv_fifo)
202 {
203 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
204 ssize_t ret;
205 int i;
206
207 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
208 for (i = 0; i < num_downstream; i += 3) {
209 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
210 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
211 DP_AUX_HDCP_KSV_FIFO,
212 ksv_fifo + i * DRM_HDCP_KSV_LEN,
213 len);
214 if (ret != len) {
215 drm_dbg_kms(&i915->drm,
216 "Read ksv[%d] from DP/AUX failed (%zd)\n",
217 i, ret);
218 return ret >= 0 ? -EIO : ret;
219 }
220 }
221 return 0;
222 }
223
224 static
intel_dp_hdcp_read_v_prime_part(struct intel_digital_port * dig_port,int i,u32 * part)225 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
226 int i, u32 *part)
227 {
228 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
229 ssize_t ret;
230
231 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
232 return -EINVAL;
233
234 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
235 DP_AUX_HDCP_V_PRIME(i), part,
236 DRM_HDCP_V_PRIME_PART_LEN);
237 if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
238 drm_dbg_kms(&i915->drm,
239 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
240 return ret >= 0 ? -EIO : ret;
241 }
242 return 0;
243 }
244
245 static
intel_dp_hdcp_toggle_signalling(struct intel_digital_port * dig_port,enum transcoder cpu_transcoder,bool enable)246 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
247 enum transcoder cpu_transcoder,
248 bool enable)
249 {
250 /* Not used for single stream DisplayPort setups */
251 return 0;
252 }
253
254 static
intel_dp_hdcp_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)255 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
256 struct intel_connector *connector)
257 {
258 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
259 ssize_t ret;
260 u8 bstatus;
261
262 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
263 &bstatus, 1);
264 if (ret != 1) {
265 drm_dbg_kms(&i915->drm,
266 "Read bstatus from DP/AUX failed (%zd)\n", ret);
267 return false;
268 }
269
270 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
271 }
272
273 static
intel_dp_hdcp_capable(struct intel_digital_port * dig_port,bool * hdcp_capable)274 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
275 bool *hdcp_capable)
276 {
277 ssize_t ret;
278 u8 bcaps;
279
280 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
281 if (ret)
282 return ret;
283
284 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
285 return 0;
286 }
287
288 struct hdcp2_dp_errata_stream_type {
289 u8 msg_id;
290 u8 stream_type;
291 } __packed;
292
293 struct hdcp2_dp_msg_data {
294 u8 msg_id;
295 u32 offset;
296 bool msg_detectable;
297 u32 timeout;
298 u32 timeout2; /* Added for non_paired situation */
299 /* Timeout to read entire msg */
300 u32 msg_read_timeout;
301 };
302
303 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
304 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
305 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
306 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
307 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
308 false, 0, 0, 0 },
309 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
310 false, 0, 0, 0 },
311 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
312 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
313 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
314 { HDCP_2_2_AKE_SEND_PAIRING_INFO,
315 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
316 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
317 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
318 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
319 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
320 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
321 0, 0, 0 },
322 { HDCP_2_2_REP_SEND_RECVID_LIST,
323 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
324 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
325 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
326 0, 0, 0 },
327 { HDCP_2_2_REP_STREAM_MANAGE,
328 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
329 0, 0, 0},
330 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
331 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
332 /* local define to shovel this through the write_2_2 interface */
333 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50
334 { HDCP_2_2_ERRATA_DP_STREAM_TYPE,
335 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
336 0, 0 },
337 };
338
339 static int
intel_dp_hdcp2_read_rx_status(struct intel_digital_port * dig_port,u8 * rx_status)340 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
341 u8 *rx_status)
342 {
343 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
344 ssize_t ret;
345
346 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
347 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
348 HDCP_2_2_DP_RXSTATUS_LEN);
349 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
350 drm_dbg_kms(&i915->drm,
351 "Read bstatus from DP/AUX failed (%zd)\n", ret);
352 return ret >= 0 ? -EIO : ret;
353 }
354
355 return 0;
356 }
357
358 static
hdcp2_detect_msg_availability(struct intel_digital_port * dig_port,u8 msg_id,bool * msg_ready)359 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
360 u8 msg_id, bool *msg_ready)
361 {
362 u8 rx_status;
363 int ret;
364
365 *msg_ready = false;
366 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
367 if (ret < 0)
368 return ret;
369
370 switch (msg_id) {
371 case HDCP_2_2_AKE_SEND_HPRIME:
372 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
373 *msg_ready = true;
374 break;
375 case HDCP_2_2_AKE_SEND_PAIRING_INFO:
376 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
377 *msg_ready = true;
378 break;
379 case HDCP_2_2_REP_SEND_RECVID_LIST:
380 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
381 *msg_ready = true;
382 break;
383 default:
384 DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
385 return -EINVAL;
386 }
387
388 return 0;
389 }
390
391 static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_digital_port * dig_port,const struct hdcp2_dp_msg_data * hdcp2_msg_data)392 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
393 const struct hdcp2_dp_msg_data *hdcp2_msg_data)
394 {
395 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
396 struct intel_dp *dp = &dig_port->dp;
397 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
398 u8 msg_id = hdcp2_msg_data->msg_id;
399 int ret, timeout;
400 bool msg_ready = false;
401
402 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
403 timeout = hdcp2_msg_data->timeout2;
404 else
405 timeout = hdcp2_msg_data->timeout;
406
407 /*
408 * There is no way to detect the CERT, LPRIME and STREAM_READY
409 * availability. So Wait for timeout and read the msg.
410 */
411 if (!hdcp2_msg_data->msg_detectable) {
412 mdelay(timeout);
413 ret = 0;
414 } else {
415 /*
416 * As we want to check the msg availability at timeout, Ignoring
417 * the timeout at wait for CP_IRQ.
418 */
419 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
420 ret = hdcp2_detect_msg_availability(dig_port,
421 msg_id, &msg_ready);
422 if (!msg_ready)
423 ret = -ETIMEDOUT;
424 }
425
426 if (ret)
427 drm_dbg_kms(&i915->drm,
428 "msg_id %d, ret %d, timeout(mSec): %d\n",
429 hdcp2_msg_data->msg_id, ret, timeout);
430
431 return ret;
432 }
433
get_hdcp2_dp_msg_data(u8 msg_id)434 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
435 {
436 int i;
437
438 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
439 if (hdcp2_dp_msg_data[i].msg_id == msg_id)
440 return &hdcp2_dp_msg_data[i];
441
442 return NULL;
443 }
444
445 static
intel_dp_hdcp2_write_msg(struct intel_digital_port * dig_port,void * buf,size_t size)446 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
447 void *buf, size_t size)
448 {
449 struct intel_dp *dp = &dig_port->dp;
450 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
451 unsigned int offset;
452 u8 *byte = buf;
453 ssize_t ret, bytes_to_write, len;
454 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
455
456 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
457 if (!hdcp2_msg_data)
458 return -EINVAL;
459
460 offset = hdcp2_msg_data->offset;
461
462 /* No msg_id in DP HDCP2.2 msgs */
463 bytes_to_write = size - 1;
464 byte++;
465
466 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
467
468 while (bytes_to_write) {
469 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
470 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
471
472 ret = drm_dp_dpcd_write(&dig_port->dp.aux,
473 offset, (void *)byte, len);
474 if (ret < 0)
475 return ret;
476
477 bytes_to_write -= ret;
478 byte += ret;
479 offset += ret;
480 }
481
482 return size;
483 }
484
485 static int
get_rxinfo_hdcp_1_dev_downstream(struct intel_digital_port * dig_port,bool * hdcp_1_x)486 get_rxinfo_hdcp_1_dev_downstream(struct intel_digital_port *dig_port, bool *hdcp_1_x)
487 {
488 u8 rx_info[HDCP_2_2_RXINFO_LEN];
489 int ret;
490
491 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
492 DP_HDCP_2_2_REG_RXINFO_OFFSET,
493 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
494
495 if (ret != HDCP_2_2_RXINFO_LEN)
496 return ret >= 0 ? -EIO : ret;
497
498 *hdcp_1_x = HDCP_2_2_HDCP1_DEVICE_CONNECTED(rx_info[1]) ? true : false;
499 return 0;
500 }
501
502 static
get_receiver_id_list_size(struct intel_digital_port * dig_port)503 ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port)
504 {
505 u8 rx_info[HDCP_2_2_RXINFO_LEN];
506 u32 dev_cnt;
507 ssize_t ret;
508
509 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
510 DP_HDCP_2_2_REG_RXINFO_OFFSET,
511 (void *)rx_info, HDCP_2_2_RXINFO_LEN);
512 if (ret != HDCP_2_2_RXINFO_LEN)
513 return ret >= 0 ? -EIO : ret;
514
515 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
516 HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
517
518 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
519 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
520
521 ret = sizeof(struct hdcp2_rep_send_receiverid_list) -
522 HDCP_2_2_RECEIVER_IDS_MAX_LEN +
523 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
524
525 return ret;
526 }
527
528 static
intel_dp_hdcp2_read_msg(struct intel_digital_port * dig_port,u8 msg_id,void * buf,size_t size)529 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
530 u8 msg_id, void *buf, size_t size)
531 {
532 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
533 unsigned int offset;
534 u8 *byte = buf;
535 ssize_t ret, bytes_to_recv, len;
536 const struct hdcp2_dp_msg_data *hdcp2_msg_data;
537 ktime_t msg_end = ktime_set(0, 0);
538 bool msg_expired;
539
540 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
541 if (!hdcp2_msg_data)
542 return -EINVAL;
543 offset = hdcp2_msg_data->offset;
544
545 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
546 if (ret < 0)
547 return ret;
548
549 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
550 ret = get_receiver_id_list_size(dig_port);
551 if (ret < 0)
552 return ret;
553
554 size = ret;
555 }
556 bytes_to_recv = size - 1;
557
558 /* DP adaptation msgs has no msg_id */
559 byte++;
560
561 while (bytes_to_recv) {
562 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
563 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
564
565 /* Entire msg read timeout since initiate of msg read */
566 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
567 msg_end = ktime_add_ms(ktime_get_raw(),
568 hdcp2_msg_data->msg_read_timeout);
569
570 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
571 (void *)byte, len);
572 if (ret < 0) {
573 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
574 msg_id, ret);
575 return ret;
576 }
577
578 bytes_to_recv -= ret;
579 byte += ret;
580 offset += ret;
581 }
582
583 if (hdcp2_msg_data->msg_read_timeout > 0) {
584 msg_expired = ktime_after(ktime_get_raw(), msg_end);
585 if (msg_expired) {
586 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
587 msg_id, hdcp2_msg_data->msg_read_timeout);
588 return -ETIMEDOUT;
589 }
590 }
591
592 byte = buf;
593 *byte = msg_id;
594
595 return size;
596 }
597
598 static
intel_dp_hdcp2_config_stream_type(struct intel_digital_port * dig_port,bool is_repeater,u8 content_type)599 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
600 bool is_repeater, u8 content_type)
601 {
602 int ret;
603 struct hdcp2_dp_errata_stream_type stream_type_msg;
604
605 if (is_repeater)
606 return 0;
607
608 /*
609 * Errata for DP: As Stream type is used for encryption, Receiver
610 * should be communicated with stream type for the decryption of the
611 * content.
612 * Repeater will be communicated with stream type as a part of it's
613 * auth later in time.
614 */
615 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
616 stream_type_msg.stream_type = content_type;
617
618 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
619 sizeof(stream_type_msg));
620
621 return ret < 0 ? ret : 0;
622
623 }
624
625 static
intel_dp_hdcp2_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)626 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
627 struct intel_connector *connector)
628 {
629 u8 rx_status;
630 int ret;
631
632 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
633 if (ret)
634 return ret;
635
636 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
637 ret = HDCP_REAUTH_REQUEST;
638 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
639 ret = HDCP_LINK_INTEGRITY_FAILURE;
640 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
641 ret = HDCP_TOPOLOGY_CHANGE;
642
643 return ret;
644 }
645
646 static
intel_dp_hdcp2_capable(struct intel_digital_port * dig_port,bool * capable)647 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
648 bool *capable)
649 {
650 u8 rx_caps[3];
651 int ret;
652
653 *capable = false;
654 ret = drm_dp_dpcd_read(&dig_port->dp.aux,
655 DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
656 rx_caps, HDCP_2_2_RXCAPS_LEN);
657 if (ret != HDCP_2_2_RXCAPS_LEN)
658 return ret >= 0 ? -EIO : ret;
659
660 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
661 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
662 *capable = true;
663
664 return 0;
665 }
666
667 static
intel_dp_mst_streams_type1_capable(struct intel_connector * connector,bool * capable)668 int intel_dp_mst_streams_type1_capable(struct intel_connector *connector,
669 bool *capable)
670 {
671 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
672 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
673 int ret;
674 bool hdcp_1_x;
675
676 ret = get_rxinfo_hdcp_1_dev_downstream(dig_port, &hdcp_1_x);
677 if (ret) {
678 drm_dbg_kms(&i915->drm,
679 "[%s:%d] failed to read RxInfo ret=%d\n",
680 connector->base.name, connector->base.base.id, ret);
681 return ret;
682 }
683
684 *capable = !hdcp_1_x;
685 return 0;
686 }
687
688 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
689 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
690 .read_bksv = intel_dp_hdcp_read_bksv,
691 .read_bstatus = intel_dp_hdcp_read_bstatus,
692 .repeater_present = intel_dp_hdcp_repeater_present,
693 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
694 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
695 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
696 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
697 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
698 .check_link = intel_dp_hdcp_check_link,
699 .hdcp_capable = intel_dp_hdcp_capable,
700 .write_2_2_msg = intel_dp_hdcp2_write_msg,
701 .read_2_2_msg = intel_dp_hdcp2_read_msg,
702 .config_stream_type = intel_dp_hdcp2_config_stream_type,
703 .check_2_2_link = intel_dp_hdcp2_check_link,
704 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
705 .protocol = HDCP_PROTOCOL_DP,
706 };
707
708 static int
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector * connector,bool enable)709 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
710 bool enable)
711 {
712 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
713 struct drm_i915_private *i915 = to_i915(connector->base.dev);
714 struct intel_hdcp *hdcp = &connector->hdcp;
715 int ret;
716
717 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
718 hdcp->stream_transcoder, enable,
719 TRANS_DDI_HDCP_SELECT);
720 if (ret)
721 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
722 enable ? "Enable" : "Disable", ret);
723 return ret;
724 }
725
726 static int
intel_dp_mst_hdcp_stream_encryption(struct intel_connector * connector,bool enable)727 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
728 bool enable)
729 {
730 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
731 struct drm_i915_private *i915 = to_i915(connector->base.dev);
732 struct intel_hdcp *hdcp = &connector->hdcp;
733 enum port port = dig_port->base.port;
734 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
735 u32 stream_enc_status;
736 int ret;
737
738 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
739 if (ret)
740 return ret;
741
742 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder);
743 if (!stream_enc_status)
744 return -EINVAL;
745
746 /* Wait for encryption confirmation */
747 if (intel_de_wait_for_register(i915,
748 HDCP_STATUS(i915, cpu_transcoder, port),
749 stream_enc_status,
750 enable ? stream_enc_status : 0,
751 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
752 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
753 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
754 return -ETIMEDOUT;
755 }
756
757 return 0;
758 }
759
760 static int
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector * connector,bool enable)761 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
762 bool enable)
763 {
764 struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
765 struct drm_i915_private *i915 = to_i915(connector->base.dev);
766 struct hdcp_port_data *data = &dig_port->hdcp_port_data;
767 struct intel_hdcp *hdcp = &connector->hdcp;
768 enum transcoder cpu_transcoder = hdcp->stream_transcoder;
769 enum pipe pipe = (enum pipe)cpu_transcoder;
770 enum port port = dig_port->base.port;
771 int ret;
772
773 drm_WARN_ON(&i915->drm, enable &&
774 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
775 & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
776
777 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
778 if (ret)
779 return ret;
780
781 /* Wait for encryption confirmation */
782 if (intel_de_wait_for_register(i915,
783 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
784 STREAM_ENCRYPTION_STATUS,
785 enable ? STREAM_ENCRYPTION_STATUS : 0,
786 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
787 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
788 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
789 return -ETIMEDOUT;
790 }
791
792 return 0;
793 }
794
795 static
intel_dp_mst_hdcp2_check_link(struct intel_digital_port * dig_port,struct intel_connector * connector)796 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
797 struct intel_connector *connector)
798 {
799 struct intel_hdcp *hdcp = &connector->hdcp;
800 int ret;
801
802 /*
803 * We do need to do the Link Check only for the connector involved with
804 * HDCP port authentication and encryption.
805 * We can re-use the hdcp->is_repeater flag to know that the connector
806 * involved with HDCP port authentication and encryption.
807 */
808 if (hdcp->is_repeater) {
809 ret = intel_dp_hdcp2_check_link(dig_port, connector);
810 if (ret)
811 return ret;
812 }
813
814 return 0;
815 }
816
817 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
818 .write_an_aksv = intel_dp_hdcp_write_an_aksv,
819 .read_bksv = intel_dp_hdcp_read_bksv,
820 .read_bstatus = intel_dp_hdcp_read_bstatus,
821 .repeater_present = intel_dp_hdcp_repeater_present,
822 .read_ri_prime = intel_dp_hdcp_read_ri_prime,
823 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
824 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
825 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
826 .toggle_signalling = intel_dp_hdcp_toggle_signalling,
827 .stream_encryption = intel_dp_mst_hdcp_stream_encryption,
828 .check_link = intel_dp_hdcp_check_link,
829 .hdcp_capable = intel_dp_hdcp_capable,
830 .write_2_2_msg = intel_dp_hdcp2_write_msg,
831 .read_2_2_msg = intel_dp_hdcp2_read_msg,
832 .config_stream_type = intel_dp_hdcp2_config_stream_type,
833 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
834 .check_2_2_link = intel_dp_mst_hdcp2_check_link,
835 .hdcp_2_2_capable = intel_dp_hdcp2_capable,
836 .streams_type1_capable = intel_dp_mst_streams_type1_capable,
837 .protocol = HDCP_PROTOCOL_DP,
838 };
839
intel_dp_hdcp_init(struct intel_digital_port * dig_port,struct intel_connector * intel_connector)840 int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
841 struct intel_connector *intel_connector)
842 {
843 struct drm_device *dev = intel_connector->base.dev;
844 struct drm_i915_private *dev_priv = to_i915(dev);
845 struct intel_encoder *intel_encoder = &dig_port->base;
846 enum port port = intel_encoder->port;
847 struct intel_dp *intel_dp = &dig_port->dp;
848
849 if (!is_hdcp_supported(dev_priv, port))
850 return 0;
851
852 if (intel_connector->mst_port)
853 return intel_hdcp_init(intel_connector, dig_port,
854 &intel_dp_mst_hdcp_shim);
855 else if (!intel_dp_is_edp(intel_dp))
856 return intel_hdcp_init(intel_connector, dig_port,
857 &intel_dp_hdcp_shim);
858
859 return 0;
860 }
861
