1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 */
7
8 #define pr_fmt(fmt) "CPU features: " fmt
9
10 #include <linux/bsearch.h>
11 #include <linux/cpumask.h>
12 #include <linux/crash_dump.h>
13 #include <linux/sort.h>
14 #include <linux/stop_machine.h>
15 #include <linux/types.h>
16 #include <linux/mm.h>
17 #include <linux/cpu.h>
18 #include <asm/cpu.h>
19 #include <asm/cpufeature.h>
20 #include <asm/cpu_ops.h>
21 #include <asm/fpsimd.h>
22 #include <asm/mmu_context.h>
23 #include <asm/processor.h>
24 #include <asm/sysreg.h>
25 #include <asm/traps.h>
26 #include <asm/virt.h>
27
28 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
29 static unsigned long elf_hwcap __read_mostly;
30
31 #ifdef CONFIG_COMPAT
32 #define COMPAT_ELF_HWCAP_DEFAULT \
33 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
34 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
35 COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
36 COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
37 COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
38 COMPAT_HWCAP_LPAE)
39 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
40 unsigned int compat_elf_hwcap2 __read_mostly;
41 #endif
42
43 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
44 EXPORT_SYMBOL(cpu_hwcaps);
45 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
46
47 /* Need also bit for ARM64_CB_PATCH */
48 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
49
50 /*
51 * Flag to indicate if we have computed the system wide
52 * capabilities based on the boot time active CPUs. This
53 * will be used to determine if a new booting CPU should
54 * go through the verification process to make sure that it
55 * supports the system capabilities, without using a hotplug
56 * notifier.
57 */
58 static bool sys_caps_initialised;
59
set_sys_caps_initialised(void)60 static inline void set_sys_caps_initialised(void)
61 {
62 sys_caps_initialised = true;
63 }
64
dump_cpu_hwcaps(struct notifier_block * self,unsigned long v,void * p)65 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
66 {
67 /* file-wide pr_fmt adds "CPU features: " prefix */
68 pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
69 return 0;
70 }
71
72 static struct notifier_block cpu_hwcaps_notifier = {
73 .notifier_call = dump_cpu_hwcaps
74 };
75
register_cpu_hwcaps_dumper(void)76 static int __init register_cpu_hwcaps_dumper(void)
77 {
78 atomic_notifier_chain_register(&panic_notifier_list,
79 &cpu_hwcaps_notifier);
80 return 0;
81 }
82 __initcall(register_cpu_hwcaps_dumper);
83
84 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
85 EXPORT_SYMBOL(cpu_hwcap_keys);
86
87 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
88 { \
89 .sign = SIGNED, \
90 .visible = VISIBLE, \
91 .strict = STRICT, \
92 .type = TYPE, \
93 .shift = SHIFT, \
94 .width = WIDTH, \
95 .safe_val = SAFE_VAL, \
96 }
97
98 /* Define a feature with unsigned values */
99 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
100 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
101
102 /* Define a feature with a signed value */
103 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
104 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
105
106 #define ARM64_FTR_END \
107 { \
108 .width = 0, \
109 }
110
111 /* meta feature for alternatives */
112 static bool __maybe_unused
113 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
114
115 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
116
117 /*
118 * NOTE: Any changes to the visibility of features should be kept in
119 * sync with the documentation of the CPU feature register ABI.
120 */
121 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
122 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
123 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
124 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
125 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
126 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
127 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
128 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
129 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
130 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
131 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
132 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
133 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
134 ARM64_FTR_END,
135 };
136
137 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
138 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
139 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FRINTTS_SHIFT, 4, 0),
140 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
141 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
142 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
143 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
144 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
145 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
146 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
147 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
148 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
149 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
150 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
151 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
152 ARM64_FTR_END,
153 };
154
155 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
156 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
157 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
158 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
159 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
160 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
161 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
162 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
163 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
164 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
165 /* Linux doesn't care about the EL3 */
166 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
167 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
168 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
169 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
170 ARM64_FTR_END,
171 };
172
173 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
174 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
175 ARM64_FTR_END,
176 };
177
178 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
179 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
180 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
181 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
182 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
183 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
184 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
185 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
186 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
187 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
188 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
189 ARM64_FTR_END,
190 };
191
192 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
193 /*
194 * We already refuse to boot CPUs that don't support our configured
195 * page size, so we can only detect mismatches for a page size other
196 * than the one we're currently using. Unfortunately, SoCs like this
197 * exist in the wild so, even though we don't like it, we'll have to go
198 * along with it and treat them as non-strict.
199 */
200 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
201 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
202 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
203
204 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
205 /* Linux shouldn't care about secure memory */
206 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
207 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
208 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
209 /*
210 * Differing PARange is fine as long as all peripherals and memory are mapped
211 * within the minimum PARange of all CPUs
212 */
213 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
214 ARM64_FTR_END,
215 };
216
217 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
218 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
219 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
220 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
221 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
222 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
223 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
224 ARM64_FTR_END,
225 };
226
227 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
230 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
231 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
232 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
233 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
234 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
235 ARM64_FTR_END,
236 };
237
238 static const struct arm64_ftr_bits ftr_ctr[] = {
239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
241 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
242 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_CWG_SHIFT, 4, 0),
243 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_ERG_SHIFT, 4, 0),
244 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
245 /*
246 * Linux can handle differing I-cache policies. Userspace JITs will
247 * make use of *minLine.
248 * If we have differing I-cache policies, report it as the weakest - VIPT.
249 */
250 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT), /* L1Ip */
251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
252 ARM64_FTR_END,
253 };
254
255 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
256 .name = "SYS_CTR_EL0",
257 .ftr_bits = ftr_ctr
258 };
259
260 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
261 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf), /* InnerShr */
262 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), /* FCSE */
263 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0), /* AuxReg */
264 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), /* TCM */
265 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* ShareLvl */
266 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf), /* OuterShr */
267 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* PMSA */
268 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* VMSA */
269 ARM64_FTR_END,
270 };
271
272 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
273 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
274 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
275 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
276 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
277 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
278 /*
279 * We can instantiate multiple PMU instances with different levels
280 * of support.
281 */
282 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
283 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
284 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
285 ARM64_FTR_END,
286 };
287
288 static const struct arm64_ftr_bits ftr_mvfr2[] = {
289 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* FPMisc */
290 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* SIMDMisc */
291 ARM64_FTR_END,
292 };
293
294 static const struct arm64_ftr_bits ftr_dczid[] = {
295 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1), /* DZP */
296 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* BS */
297 ARM64_FTR_END,
298 };
299
300
301 static const struct arm64_ftr_bits ftr_id_isar5[] = {
302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
303 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
304 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
308 ARM64_FTR_END,
309 };
310
311 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
312 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
313 ARM64_FTR_END,
314 };
315
316 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
317 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), /* State3 */
318 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), /* State2 */
319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* State1 */
320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), /* State0 */
321 ARM64_FTR_END,
322 };
323
324 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
325 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
326 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf), /* PerfMon */
327 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
328 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
329 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
330 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
332 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
333 ARM64_FTR_END,
334 };
335
336 static const struct arm64_ftr_bits ftr_zcr[] = {
337 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
338 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0), /* LEN */
339 ARM64_FTR_END,
340 };
341
342 /*
343 * Common ftr bits for a 32bit register with all hidden, strict
344 * attributes, with 4bit feature fields and a default safe value of
345 * 0. Covers the following 32bit registers:
346 * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
347 */
348 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
349 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
350 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
351 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
352 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
353 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
354 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
355 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
356 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
357 ARM64_FTR_END,
358 };
359
360 /* Table for a single 32bit feature value */
361 static const struct arm64_ftr_bits ftr_single32[] = {
362 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
363 ARM64_FTR_END,
364 };
365
366 static const struct arm64_ftr_bits ftr_raz[] = {
367 ARM64_FTR_END,
368 };
369
370 #define ARM64_FTR_REG(id, table) { \
371 .sys_id = id, \
372 .reg = &(struct arm64_ftr_reg){ \
373 .name = #id, \
374 .ftr_bits = &((table)[0]), \
375 }}
376
377 static const struct __ftr_reg_entry {
378 u32 sys_id;
379 struct arm64_ftr_reg *reg;
380 } arm64_ftr_regs[] = {
381
382 /* Op1 = 0, CRn = 0, CRm = 1 */
383 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
384 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
385 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
386 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
387 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
388 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
389 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
390
391 /* Op1 = 0, CRn = 0, CRm = 2 */
392 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
393 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
394 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
395 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
396 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
397 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
398 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
399
400 /* Op1 = 0, CRn = 0, CRm = 3 */
401 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
402 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
403 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
404
405 /* Op1 = 0, CRn = 0, CRm = 4 */
406 ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
407 ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
408 ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
409
410 /* Op1 = 0, CRn = 0, CRm = 5 */
411 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
412 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
413
414 /* Op1 = 0, CRn = 0, CRm = 6 */
415 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
416 ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
417
418 /* Op1 = 0, CRn = 0, CRm = 7 */
419 ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
420 ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
421 ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
422
423 /* Op1 = 0, CRn = 1, CRm = 2 */
424 ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
425
426 /* Op1 = 3, CRn = 0, CRm = 0 */
427 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
428 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
429
430 /* Op1 = 3, CRn = 14, CRm = 0 */
431 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
432 };
433
search_cmp_ftr_reg(const void * id,const void * regp)434 static int search_cmp_ftr_reg(const void *id, const void *regp)
435 {
436 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
437 }
438
439 /*
440 * get_arm64_ftr_reg - Lookup a feature register entry using its
441 * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
442 * ascending order of sys_id , we use binary search to find a matching
443 * entry.
444 *
445 * returns - Upon success, matching ftr_reg entry for id.
446 * - NULL on failure. It is upto the caller to decide
447 * the impact of a failure.
448 */
get_arm64_ftr_reg(u32 sys_id)449 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
450 {
451 const struct __ftr_reg_entry *ret;
452
453 ret = bsearch((const void *)(unsigned long)sys_id,
454 arm64_ftr_regs,
455 ARRAY_SIZE(arm64_ftr_regs),
456 sizeof(arm64_ftr_regs[0]),
457 search_cmp_ftr_reg);
458 if (ret)
459 return ret->reg;
460 return NULL;
461 }
462
arm64_ftr_set_value(const struct arm64_ftr_bits * ftrp,s64 reg,s64 ftr_val)463 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
464 s64 ftr_val)
465 {
466 u64 mask = arm64_ftr_mask(ftrp);
467
468 reg &= ~mask;
469 reg |= (ftr_val << ftrp->shift) & mask;
470 return reg;
471 }
472
arm64_ftr_safe_value(const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)473 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
474 s64 cur)
475 {
476 s64 ret = 0;
477
478 switch (ftrp->type) {
479 case FTR_EXACT:
480 ret = ftrp->safe_val;
481 break;
482 case FTR_LOWER_SAFE:
483 ret = new < cur ? new : cur;
484 break;
485 case FTR_HIGHER_OR_ZERO_SAFE:
486 if (!cur || !new)
487 break;
488 /* Fallthrough */
489 case FTR_HIGHER_SAFE:
490 ret = new > cur ? new : cur;
491 break;
492 default:
493 BUG();
494 }
495
496 return ret;
497 }
498
sort_ftr_regs(void)499 static void __init sort_ftr_regs(void)
500 {
501 int i;
502
503 /* Check that the array is sorted so that we can do the binary search */
504 for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
505 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
506 }
507
508 /*
509 * Initialise the CPU feature register from Boot CPU values.
510 * Also initiliases the strict_mask for the register.
511 * Any bits that are not covered by an arm64_ftr_bits entry are considered
512 * RES0 for the system-wide value, and must strictly match.
513 */
init_cpu_ftr_reg(u32 sys_reg,u64 new)514 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
515 {
516 u64 val = 0;
517 u64 strict_mask = ~0x0ULL;
518 u64 user_mask = 0;
519 u64 valid_mask = 0;
520
521 const struct arm64_ftr_bits *ftrp;
522 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
523
524 BUG_ON(!reg);
525
526 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
527 u64 ftr_mask = arm64_ftr_mask(ftrp);
528 s64 ftr_new = arm64_ftr_value(ftrp, new);
529
530 val = arm64_ftr_set_value(ftrp, val, ftr_new);
531
532 valid_mask |= ftr_mask;
533 if (!ftrp->strict)
534 strict_mask &= ~ftr_mask;
535 if (ftrp->visible)
536 user_mask |= ftr_mask;
537 else
538 reg->user_val = arm64_ftr_set_value(ftrp,
539 reg->user_val,
540 ftrp->safe_val);
541 }
542
543 val &= valid_mask;
544
545 reg->sys_val = val;
546 reg->strict_mask = strict_mask;
547 reg->user_mask = user_mask;
548 }
549
550 extern const struct arm64_cpu_capabilities arm64_errata[];
551 static const struct arm64_cpu_capabilities arm64_features[];
552
553 static void __init
init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities * caps)554 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
555 {
556 for (; caps->matches; caps++) {
557 if (WARN(caps->capability >= ARM64_NCAPS,
558 "Invalid capability %d\n", caps->capability))
559 continue;
560 if (WARN(cpu_hwcaps_ptrs[caps->capability],
561 "Duplicate entry for capability %d\n",
562 caps->capability))
563 continue;
564 cpu_hwcaps_ptrs[caps->capability] = caps;
565 }
566 }
567
init_cpu_hwcaps_indirect_list(void)568 static void __init init_cpu_hwcaps_indirect_list(void)
569 {
570 init_cpu_hwcaps_indirect_list_from_array(arm64_features);
571 init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
572 }
573
574 static void __init setup_boot_cpu_capabilities(void);
575
init_cpu_features(struct cpuinfo_arm64 * info)576 void __init init_cpu_features(struct cpuinfo_arm64 *info)
577 {
578 /* Before we start using the tables, make sure it is sorted */
579 sort_ftr_regs();
580
581 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
582 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
583 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
584 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
585 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
586 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
587 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
588 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
589 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
590 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
591 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
592 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
593 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
594
595 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
596 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
597 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
598 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
599 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
600 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
601 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
602 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
603 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
604 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
605 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
606 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
607 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
608 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
609 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
610 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
611 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
612 }
613
614 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
615 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
616 sve_init_vq_map();
617 }
618
619 /*
620 * Initialize the indirect array of CPU hwcaps capabilities pointers
621 * before we handle the boot CPU below.
622 */
623 init_cpu_hwcaps_indirect_list();
624
625 /*
626 * Detect and enable early CPU capabilities based on the boot CPU,
627 * after we have initialised the CPU feature infrastructure.
628 */
629 setup_boot_cpu_capabilities();
630 }
631
update_cpu_ftr_reg(struct arm64_ftr_reg * reg,u64 new)632 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
633 {
634 const struct arm64_ftr_bits *ftrp;
635
636 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
637 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
638 s64 ftr_new = arm64_ftr_value(ftrp, new);
639
640 if (ftr_cur == ftr_new)
641 continue;
642 /* Find a safe value */
643 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
644 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
645 }
646
647 }
648
check_update_ftr_reg(u32 sys_id,int cpu,u64 val,u64 boot)649 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
650 {
651 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
652
653 BUG_ON(!regp);
654 update_cpu_ftr_reg(regp, val);
655 if ((boot & regp->strict_mask) == (val & regp->strict_mask))
656 return 0;
657 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
658 regp->name, boot, cpu, val);
659 return 1;
660 }
661
662 /*
663 * Update system wide CPU feature registers with the values from a
664 * non-boot CPU. Also performs SANITY checks to make sure that there
665 * aren't any insane variations from that of the boot CPU.
666 */
update_cpu_features(int cpu,struct cpuinfo_arm64 * info,struct cpuinfo_arm64 * boot)667 void update_cpu_features(int cpu,
668 struct cpuinfo_arm64 *info,
669 struct cpuinfo_arm64 *boot)
670 {
671 int taint = 0;
672
673 /*
674 * The kernel can handle differing I-cache policies, but otherwise
675 * caches should look identical. Userspace JITs will make use of
676 * *minLine.
677 */
678 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
679 info->reg_ctr, boot->reg_ctr);
680
681 /*
682 * Userspace may perform DC ZVA instructions. Mismatched block sizes
683 * could result in too much or too little memory being zeroed if a
684 * process is preempted and migrated between CPUs.
685 */
686 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
687 info->reg_dczid, boot->reg_dczid);
688
689 /* If different, timekeeping will be broken (especially with KVM) */
690 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
691 info->reg_cntfrq, boot->reg_cntfrq);
692
693 /*
694 * The kernel uses self-hosted debug features and expects CPUs to
695 * support identical debug features. We presently need CTX_CMPs, WRPs,
696 * and BRPs to be identical.
697 * ID_AA64DFR1 is currently RES0.
698 */
699 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
700 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
701 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
702 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
703 /*
704 * Even in big.LITTLE, processors should be identical instruction-set
705 * wise.
706 */
707 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
708 info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
709 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
710 info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
711
712 /*
713 * Differing PARange support is fine as long as all peripherals and
714 * memory are mapped within the minimum PARange of all CPUs.
715 * Linux should not care about secure memory.
716 */
717 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
718 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
719 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
720 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
721 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
722 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
723
724 /*
725 * EL3 is not our concern.
726 */
727 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
728 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
729 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
730 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
731
732 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
733 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
734
735 /*
736 * If we have AArch32, we care about 32-bit features for compat.
737 * If the system doesn't support AArch32, don't update them.
738 */
739 if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
740 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
741
742 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
743 info->reg_id_dfr0, boot->reg_id_dfr0);
744 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
745 info->reg_id_isar0, boot->reg_id_isar0);
746 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
747 info->reg_id_isar1, boot->reg_id_isar1);
748 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
749 info->reg_id_isar2, boot->reg_id_isar2);
750 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
751 info->reg_id_isar3, boot->reg_id_isar3);
752 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
753 info->reg_id_isar4, boot->reg_id_isar4);
754 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
755 info->reg_id_isar5, boot->reg_id_isar5);
756
757 /*
758 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
759 * ACTLR formats could differ across CPUs and therefore would have to
760 * be trapped for virtualization anyway.
761 */
762 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
763 info->reg_id_mmfr0, boot->reg_id_mmfr0);
764 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
765 info->reg_id_mmfr1, boot->reg_id_mmfr1);
766 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
767 info->reg_id_mmfr2, boot->reg_id_mmfr2);
768 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
769 info->reg_id_mmfr3, boot->reg_id_mmfr3);
770 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
771 info->reg_id_pfr0, boot->reg_id_pfr0);
772 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
773 info->reg_id_pfr1, boot->reg_id_pfr1);
774 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
775 info->reg_mvfr0, boot->reg_mvfr0);
776 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
777 info->reg_mvfr1, boot->reg_mvfr1);
778 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
779 info->reg_mvfr2, boot->reg_mvfr2);
780 }
781
782 if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
783 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
784 info->reg_zcr, boot->reg_zcr);
785
786 /* Probe vector lengths, unless we already gave up on SVE */
787 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
788 !sys_caps_initialised)
789 sve_update_vq_map();
790 }
791
792 /*
793 * Mismatched CPU features are a recipe for disaster. Don't even
794 * pretend to support them.
795 */
796 if (taint) {
797 pr_warn_once("Unsupported CPU feature variation detected.\n");
798 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
799 }
800 }
801
read_sanitised_ftr_reg(u32 id)802 u64 read_sanitised_ftr_reg(u32 id)
803 {
804 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
805
806 /* We shouldn't get a request for an unsupported register */
807 BUG_ON(!regp);
808 return regp->sys_val;
809 }
810
811 #define read_sysreg_case(r) \
812 case r: return read_sysreg_s(r)
813
814 /*
815 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
816 * Read the system register on the current CPU
817 */
__read_sysreg_by_encoding(u32 sys_id)818 static u64 __read_sysreg_by_encoding(u32 sys_id)
819 {
820 switch (sys_id) {
821 read_sysreg_case(SYS_ID_PFR0_EL1);
822 read_sysreg_case(SYS_ID_PFR1_EL1);
823 read_sysreg_case(SYS_ID_DFR0_EL1);
824 read_sysreg_case(SYS_ID_MMFR0_EL1);
825 read_sysreg_case(SYS_ID_MMFR1_EL1);
826 read_sysreg_case(SYS_ID_MMFR2_EL1);
827 read_sysreg_case(SYS_ID_MMFR3_EL1);
828 read_sysreg_case(SYS_ID_ISAR0_EL1);
829 read_sysreg_case(SYS_ID_ISAR1_EL1);
830 read_sysreg_case(SYS_ID_ISAR2_EL1);
831 read_sysreg_case(SYS_ID_ISAR3_EL1);
832 read_sysreg_case(SYS_ID_ISAR4_EL1);
833 read_sysreg_case(SYS_ID_ISAR5_EL1);
834 read_sysreg_case(SYS_MVFR0_EL1);
835 read_sysreg_case(SYS_MVFR1_EL1);
836 read_sysreg_case(SYS_MVFR2_EL1);
837
838 read_sysreg_case(SYS_ID_AA64PFR0_EL1);
839 read_sysreg_case(SYS_ID_AA64PFR1_EL1);
840 read_sysreg_case(SYS_ID_AA64ZFR0_EL1);
841 read_sysreg_case(SYS_ID_AA64DFR0_EL1);
842 read_sysreg_case(SYS_ID_AA64DFR1_EL1);
843 read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
844 read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
845 read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
846 read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
847 read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
848
849 read_sysreg_case(SYS_CNTFRQ_EL0);
850 read_sysreg_case(SYS_CTR_EL0);
851 read_sysreg_case(SYS_DCZID_EL0);
852
853 default:
854 BUG();
855 return 0;
856 }
857 }
858
859 #include <linux/irqchip/arm-gic-v3.h>
860
861 static bool
feature_matches(u64 reg,const struct arm64_cpu_capabilities * entry)862 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
863 {
864 int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
865
866 return val >= entry->min_field_value;
867 }
868
869 static bool
has_cpuid_feature(const struct arm64_cpu_capabilities * entry,int scope)870 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
871 {
872 u64 val;
873
874 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
875 if (scope == SCOPE_SYSTEM)
876 val = read_sanitised_ftr_reg(entry->sys_reg);
877 else
878 val = __read_sysreg_by_encoding(entry->sys_reg);
879
880 return feature_matches(val, entry);
881 }
882
has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities * entry,int scope)883 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
884 {
885 bool has_sre;
886
887 if (!has_cpuid_feature(entry, scope))
888 return false;
889
890 has_sre = gic_enable_sre();
891 if (!has_sre)
892 pr_warn_once("%s present but disabled by higher exception level\n",
893 entry->desc);
894
895 return has_sre;
896 }
897
has_no_hw_prefetch(const struct arm64_cpu_capabilities * entry,int __unused)898 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
899 {
900 u32 midr = read_cpuid_id();
901
902 /* Cavium ThunderX pass 1.x and 2.x */
903 return midr_is_cpu_model_range(midr, MIDR_THUNDERX,
904 MIDR_CPU_VAR_REV(0, 0),
905 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
906 }
907
has_no_fpsimd(const struct arm64_cpu_capabilities * entry,int __unused)908 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
909 {
910 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
911
912 return cpuid_feature_extract_signed_field(pfr0,
913 ID_AA64PFR0_FP_SHIFT) < 0;
914 }
915
has_cache_idc(const struct arm64_cpu_capabilities * entry,int scope)916 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
917 int scope)
918 {
919 u64 ctr;
920
921 if (scope == SCOPE_SYSTEM)
922 ctr = arm64_ftr_reg_ctrel0.sys_val;
923 else
924 ctr = read_cpuid_effective_cachetype();
925
926 return ctr & BIT(CTR_IDC_SHIFT);
927 }
928
cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities * __unused)929 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
930 {
931 /*
932 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
933 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
934 * to the CTR_EL0 on this CPU and emulate it with the real/safe
935 * value.
936 */
937 if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
938 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
939 }
940
has_cache_dic(const struct arm64_cpu_capabilities * entry,int scope)941 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
942 int scope)
943 {
944 u64 ctr;
945
946 if (scope == SCOPE_SYSTEM)
947 ctr = arm64_ftr_reg_ctrel0.sys_val;
948 else
949 ctr = read_cpuid_cachetype();
950
951 return ctr & BIT(CTR_DIC_SHIFT);
952 }
953
954 static bool __maybe_unused
has_useable_cnp(const struct arm64_cpu_capabilities * entry,int scope)955 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
956 {
957 /*
958 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
959 * may share TLB entries with a CPU stuck in the crashed
960 * kernel.
961 */
962 if (is_kdump_kernel())
963 return false;
964
965 return has_cpuid_feature(entry, scope);
966 }
967
968 static bool __meltdown_safe = true;
969 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
970
unmap_kernel_at_el0(const struct arm64_cpu_capabilities * entry,int scope)971 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
972 int scope)
973 {
974 /* List of CPUs that are not vulnerable and don't need KPTI */
975 static const struct midr_range kpti_safe_list[] = {
976 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
977 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
978 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
979 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
980 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
981 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
982 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
983 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
984 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
985 { /* sentinel */ }
986 };
987 char const *str = "kpti command line option";
988 bool meltdown_safe;
989
990 meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
991
992 /* Defer to CPU feature registers */
993 if (has_cpuid_feature(entry, scope))
994 meltdown_safe = true;
995
996 if (!meltdown_safe)
997 __meltdown_safe = false;
998
999 /*
1000 * For reasons that aren't entirely clear, enabling KPTI on Cavium
1001 * ThunderX leads to apparent I-cache corruption of kernel text, which
1002 * ends as well as you might imagine. Don't even try.
1003 */
1004 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
1005 str = "ARM64_WORKAROUND_CAVIUM_27456";
1006 __kpti_forced = -1;
1007 }
1008
1009 /* Useful for KASLR robustness */
1010 if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1011 if (!__kpti_forced) {
1012 str = "KASLR";
1013 __kpti_forced = 1;
1014 }
1015 }
1016
1017 if (cpu_mitigations_off() && !__kpti_forced) {
1018 str = "mitigations=off";
1019 __kpti_forced = -1;
1020 }
1021
1022 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1023 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1024 return false;
1025 }
1026
1027 /* Forced? */
1028 if (__kpti_forced) {
1029 pr_info_once("kernel page table isolation forced %s by %s\n",
1030 __kpti_forced > 0 ? "ON" : "OFF", str);
1031 return __kpti_forced > 0;
1032 }
1033
1034 return !meltdown_safe;
1035 }
1036
1037 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1038 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1039 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1040 {
1041 typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1042 extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1043 kpti_remap_fn *remap_fn;
1044
1045 static bool kpti_applied = false;
1046 int cpu = smp_processor_id();
1047
1048 /*
1049 * We don't need to rewrite the page-tables if either we've done
1050 * it already or we have KASLR enabled and therefore have not
1051 * created any global mappings at all.
1052 */
1053 if (kpti_applied || kaslr_offset() > 0)
1054 return;
1055
1056 remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1057
1058 cpu_install_idmap();
1059 remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1060 cpu_uninstall_idmap();
1061
1062 if (!cpu)
1063 kpti_applied = true;
1064
1065 return;
1066 }
1067 #else
1068 static void
kpti_install_ng_mappings(const struct arm64_cpu_capabilities * __unused)1069 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1070 {
1071 }
1072 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1073
parse_kpti(char * str)1074 static int __init parse_kpti(char *str)
1075 {
1076 bool enabled;
1077 int ret = strtobool(str, &enabled);
1078
1079 if (ret)
1080 return ret;
1081
1082 __kpti_forced = enabled ? 1 : -1;
1083 return 0;
1084 }
1085 early_param("kpti", parse_kpti);
1086
1087 #ifdef CONFIG_ARM64_HW_AFDBM
__cpu_enable_hw_dbm(void)1088 static inline void __cpu_enable_hw_dbm(void)
1089 {
1090 u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1091
1092 write_sysreg(tcr, tcr_el1);
1093 isb();
1094 }
1095
cpu_has_broken_dbm(void)1096 static bool cpu_has_broken_dbm(void)
1097 {
1098 /* List of CPUs which have broken DBM support. */
1099 static const struct midr_range cpus[] = {
1100 #ifdef CONFIG_ARM64_ERRATUM_1024718
1101 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
1102 #endif
1103 {},
1104 };
1105
1106 return is_midr_in_range_list(read_cpuid_id(), cpus);
1107 }
1108
cpu_can_use_dbm(const struct arm64_cpu_capabilities * cap)1109 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1110 {
1111 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1112 !cpu_has_broken_dbm();
1113 }
1114
cpu_enable_hw_dbm(struct arm64_cpu_capabilities const * cap)1115 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1116 {
1117 if (cpu_can_use_dbm(cap))
1118 __cpu_enable_hw_dbm();
1119 }
1120
has_hw_dbm(const struct arm64_cpu_capabilities * cap,int __unused)1121 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1122 int __unused)
1123 {
1124 static bool detected = false;
1125 /*
1126 * DBM is a non-conflicting feature. i.e, the kernel can safely
1127 * run a mix of CPUs with and without the feature. So, we
1128 * unconditionally enable the capability to allow any late CPU
1129 * to use the feature. We only enable the control bits on the
1130 * CPU, if it actually supports.
1131 *
1132 * We have to make sure we print the "feature" detection only
1133 * when at least one CPU actually uses it. So check if this CPU
1134 * can actually use it and print the message exactly once.
1135 *
1136 * This is safe as all CPUs (including secondary CPUs - due to the
1137 * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1138 * goes through the "matches" check exactly once. Also if a CPU
1139 * matches the criteria, it is guaranteed that the CPU will turn
1140 * the DBM on, as the capability is unconditionally enabled.
1141 */
1142 if (!detected && cpu_can_use_dbm(cap)) {
1143 detected = true;
1144 pr_info("detected: Hardware dirty bit management\n");
1145 }
1146
1147 return true;
1148 }
1149
1150 #endif
1151
1152 #ifdef CONFIG_ARM64_VHE
runs_at_el2(const struct arm64_cpu_capabilities * entry,int __unused)1153 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1154 {
1155 return is_kernel_in_hyp_mode();
1156 }
1157
cpu_copy_el2regs(const struct arm64_cpu_capabilities * __unused)1158 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1159 {
1160 /*
1161 * Copy register values that aren't redirected by hardware.
1162 *
1163 * Before code patching, we only set tpidr_el1, all CPUs need to copy
1164 * this value to tpidr_el2 before we patch the code. Once we've done
1165 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1166 * do anything here.
1167 */
1168 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1169 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1170 }
1171 #endif
1172
cpu_has_fwb(const struct arm64_cpu_capabilities * __unused)1173 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1174 {
1175 u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1176
1177 /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1178 WARN_ON(val & (7 << 27 | 7 << 21));
1179 }
1180
1181 #ifdef CONFIG_ARM64_SSBD
ssbs_emulation_handler(struct pt_regs * regs,u32 instr)1182 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1183 {
1184 if (user_mode(regs))
1185 return 1;
1186
1187 if (instr & BIT(PSTATE_Imm_shift))
1188 regs->pstate |= PSR_SSBS_BIT;
1189 else
1190 regs->pstate &= ~PSR_SSBS_BIT;
1191
1192 arm64_skip_faulting_instruction(regs, 4);
1193 return 0;
1194 }
1195
1196 static struct undef_hook ssbs_emulation_hook = {
1197 .instr_mask = ~(1U << PSTATE_Imm_shift),
1198 .instr_val = 0xd500401f | PSTATE_SSBS,
1199 .fn = ssbs_emulation_handler,
1200 };
1201
cpu_enable_ssbs(const struct arm64_cpu_capabilities * __unused)1202 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1203 {
1204 static bool undef_hook_registered = false;
1205 static DEFINE_RAW_SPINLOCK(hook_lock);
1206
1207 raw_spin_lock(&hook_lock);
1208 if (!undef_hook_registered) {
1209 register_undef_hook(&ssbs_emulation_hook);
1210 undef_hook_registered = true;
1211 }
1212 raw_spin_unlock(&hook_lock);
1213
1214 if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1215 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1216 arm64_set_ssbd_mitigation(false);
1217 } else {
1218 arm64_set_ssbd_mitigation(true);
1219 }
1220 }
1221 #endif /* CONFIG_ARM64_SSBD */
1222
1223 #ifdef CONFIG_ARM64_PAN
cpu_enable_pan(const struct arm64_cpu_capabilities * __unused)1224 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1225 {
1226 /*
1227 * We modify PSTATE. This won't work from irq context as the PSTATE
1228 * is discarded once we return from the exception.
1229 */
1230 WARN_ON_ONCE(in_interrupt());
1231
1232 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1233 asm(SET_PSTATE_PAN(1));
1234 }
1235 #endif /* CONFIG_ARM64_PAN */
1236
1237 #ifdef CONFIG_ARM64_RAS_EXTN
cpu_clear_disr(const struct arm64_cpu_capabilities * __unused)1238 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1239 {
1240 /* Firmware may have left a deferred SError in this register. */
1241 write_sysreg_s(0, SYS_DISR_EL1);
1242 }
1243 #endif /* CONFIG_ARM64_RAS_EXTN */
1244
1245 #ifdef CONFIG_ARM64_PTR_AUTH
cpu_enable_address_auth(struct arm64_cpu_capabilities const * cap)1246 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1247 {
1248 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1249 SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1250 }
1251 #endif /* CONFIG_ARM64_PTR_AUTH */
1252
1253 #ifdef CONFIG_ARM64_PSEUDO_NMI
1254 static bool enable_pseudo_nmi;
1255
early_enable_pseudo_nmi(char * p)1256 static int __init early_enable_pseudo_nmi(char *p)
1257 {
1258 return strtobool(p, &enable_pseudo_nmi);
1259 }
1260 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1261
can_use_gic_priorities(const struct arm64_cpu_capabilities * entry,int scope)1262 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1263 int scope)
1264 {
1265 return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1266 }
1267 #endif
1268
1269 static const struct arm64_cpu_capabilities arm64_features[] = {
1270 {
1271 .desc = "GIC system register CPU interface",
1272 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1273 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1274 .matches = has_useable_gicv3_cpuif,
1275 .sys_reg = SYS_ID_AA64PFR0_EL1,
1276 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1277 .sign = FTR_UNSIGNED,
1278 .min_field_value = 1,
1279 },
1280 #ifdef CONFIG_ARM64_PAN
1281 {
1282 .desc = "Privileged Access Never",
1283 .capability = ARM64_HAS_PAN,
1284 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1285 .matches = has_cpuid_feature,
1286 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1287 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1288 .sign = FTR_UNSIGNED,
1289 .min_field_value = 1,
1290 .cpu_enable = cpu_enable_pan,
1291 },
1292 #endif /* CONFIG_ARM64_PAN */
1293 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1294 {
1295 .desc = "LSE atomic instructions",
1296 .capability = ARM64_HAS_LSE_ATOMICS,
1297 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1298 .matches = has_cpuid_feature,
1299 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1300 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1301 .sign = FTR_UNSIGNED,
1302 .min_field_value = 2,
1303 },
1304 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1305 {
1306 .desc = "Software prefetching using PRFM",
1307 .capability = ARM64_HAS_NO_HW_PREFETCH,
1308 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1309 .matches = has_no_hw_prefetch,
1310 },
1311 #ifdef CONFIG_ARM64_UAO
1312 {
1313 .desc = "User Access Override",
1314 .capability = ARM64_HAS_UAO,
1315 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1316 .matches = has_cpuid_feature,
1317 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1318 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1319 .min_field_value = 1,
1320 /*
1321 * We rely on stop_machine() calling uao_thread_switch() to set
1322 * UAO immediately after patching.
1323 */
1324 },
1325 #endif /* CONFIG_ARM64_UAO */
1326 #ifdef CONFIG_ARM64_PAN
1327 {
1328 .capability = ARM64_ALT_PAN_NOT_UAO,
1329 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1330 .matches = cpufeature_pan_not_uao,
1331 },
1332 #endif /* CONFIG_ARM64_PAN */
1333 #ifdef CONFIG_ARM64_VHE
1334 {
1335 .desc = "Virtualization Host Extensions",
1336 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1337 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1338 .matches = runs_at_el2,
1339 .cpu_enable = cpu_copy_el2regs,
1340 },
1341 #endif /* CONFIG_ARM64_VHE */
1342 {
1343 .desc = "32-bit EL0 Support",
1344 .capability = ARM64_HAS_32BIT_EL0,
1345 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1346 .matches = has_cpuid_feature,
1347 .sys_reg = SYS_ID_AA64PFR0_EL1,
1348 .sign = FTR_UNSIGNED,
1349 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1350 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1351 },
1352 {
1353 .desc = "Kernel page table isolation (KPTI)",
1354 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1355 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1356 /*
1357 * The ID feature fields below are used to indicate that
1358 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1359 * more details.
1360 */
1361 .sys_reg = SYS_ID_AA64PFR0_EL1,
1362 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1363 .min_field_value = 1,
1364 .matches = unmap_kernel_at_el0,
1365 .cpu_enable = kpti_install_ng_mappings,
1366 },
1367 {
1368 /* FP/SIMD is not implemented */
1369 .capability = ARM64_HAS_NO_FPSIMD,
1370 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1371 .min_field_value = 0,
1372 .matches = has_no_fpsimd,
1373 },
1374 #ifdef CONFIG_ARM64_PMEM
1375 {
1376 .desc = "Data cache clean to Point of Persistence",
1377 .capability = ARM64_HAS_DCPOP,
1378 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1379 .matches = has_cpuid_feature,
1380 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1381 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1382 .min_field_value = 1,
1383 },
1384 {
1385 .desc = "Data cache clean to Point of Deep Persistence",
1386 .capability = ARM64_HAS_DCPODP,
1387 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1388 .matches = has_cpuid_feature,
1389 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1390 .sign = FTR_UNSIGNED,
1391 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1392 .min_field_value = 2,
1393 },
1394 #endif
1395 #ifdef CONFIG_ARM64_SVE
1396 {
1397 .desc = "Scalable Vector Extension",
1398 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1399 .capability = ARM64_SVE,
1400 .sys_reg = SYS_ID_AA64PFR0_EL1,
1401 .sign = FTR_UNSIGNED,
1402 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1403 .min_field_value = ID_AA64PFR0_SVE,
1404 .matches = has_cpuid_feature,
1405 .cpu_enable = sve_kernel_enable,
1406 },
1407 #endif /* CONFIG_ARM64_SVE */
1408 #ifdef CONFIG_ARM64_RAS_EXTN
1409 {
1410 .desc = "RAS Extension Support",
1411 .capability = ARM64_HAS_RAS_EXTN,
1412 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1413 .matches = has_cpuid_feature,
1414 .sys_reg = SYS_ID_AA64PFR0_EL1,
1415 .sign = FTR_UNSIGNED,
1416 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1417 .min_field_value = ID_AA64PFR0_RAS_V1,
1418 .cpu_enable = cpu_clear_disr,
1419 },
1420 #endif /* CONFIG_ARM64_RAS_EXTN */
1421 {
1422 .desc = "Data cache clean to the PoU not required for I/D coherence",
1423 .capability = ARM64_HAS_CACHE_IDC,
1424 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1425 .matches = has_cache_idc,
1426 .cpu_enable = cpu_emulate_effective_ctr,
1427 },
1428 {
1429 .desc = "Instruction cache invalidation not required for I/D coherence",
1430 .capability = ARM64_HAS_CACHE_DIC,
1431 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1432 .matches = has_cache_dic,
1433 },
1434 {
1435 .desc = "Stage-2 Force Write-Back",
1436 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1437 .capability = ARM64_HAS_STAGE2_FWB,
1438 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1439 .sign = FTR_UNSIGNED,
1440 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1441 .min_field_value = 1,
1442 .matches = has_cpuid_feature,
1443 .cpu_enable = cpu_has_fwb,
1444 },
1445 #ifdef CONFIG_ARM64_HW_AFDBM
1446 {
1447 /*
1448 * Since we turn this on always, we don't want the user to
1449 * think that the feature is available when it may not be.
1450 * So hide the description.
1451 *
1452 * .desc = "Hardware pagetable Dirty Bit Management",
1453 *
1454 */
1455 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1456 .capability = ARM64_HW_DBM,
1457 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1458 .sign = FTR_UNSIGNED,
1459 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1460 .min_field_value = 2,
1461 .matches = has_hw_dbm,
1462 .cpu_enable = cpu_enable_hw_dbm,
1463 },
1464 #endif
1465 {
1466 .desc = "CRC32 instructions",
1467 .capability = ARM64_HAS_CRC32,
1468 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1469 .matches = has_cpuid_feature,
1470 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1471 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1472 .min_field_value = 1,
1473 },
1474 #ifdef CONFIG_ARM64_SSBD
1475 {
1476 .desc = "Speculative Store Bypassing Safe (SSBS)",
1477 .capability = ARM64_SSBS,
1478 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1479 .matches = has_cpuid_feature,
1480 .sys_reg = SYS_ID_AA64PFR1_EL1,
1481 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1482 .sign = FTR_UNSIGNED,
1483 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1484 .cpu_enable = cpu_enable_ssbs,
1485 },
1486 #endif
1487 #ifdef CONFIG_ARM64_CNP
1488 {
1489 .desc = "Common not Private translations",
1490 .capability = ARM64_HAS_CNP,
1491 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1492 .matches = has_useable_cnp,
1493 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1494 .sign = FTR_UNSIGNED,
1495 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1496 .min_field_value = 1,
1497 .cpu_enable = cpu_enable_cnp,
1498 },
1499 #endif
1500 {
1501 .desc = "Speculation barrier (SB)",
1502 .capability = ARM64_HAS_SB,
1503 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1504 .matches = has_cpuid_feature,
1505 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1506 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1507 .sign = FTR_UNSIGNED,
1508 .min_field_value = 1,
1509 },
1510 #ifdef CONFIG_ARM64_PTR_AUTH
1511 {
1512 .desc = "Address authentication (architected algorithm)",
1513 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1514 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1515 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1516 .sign = FTR_UNSIGNED,
1517 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1518 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1519 .matches = has_cpuid_feature,
1520 .cpu_enable = cpu_enable_address_auth,
1521 },
1522 {
1523 .desc = "Address authentication (IMP DEF algorithm)",
1524 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1525 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1526 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1527 .sign = FTR_UNSIGNED,
1528 .field_pos = ID_AA64ISAR1_API_SHIFT,
1529 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1530 .matches = has_cpuid_feature,
1531 .cpu_enable = cpu_enable_address_auth,
1532 },
1533 {
1534 .desc = "Generic authentication (architected algorithm)",
1535 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1536 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1537 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1538 .sign = FTR_UNSIGNED,
1539 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1540 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1541 .matches = has_cpuid_feature,
1542 },
1543 {
1544 .desc = "Generic authentication (IMP DEF algorithm)",
1545 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1546 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1547 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1548 .sign = FTR_UNSIGNED,
1549 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1550 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1551 .matches = has_cpuid_feature,
1552 },
1553 #endif /* CONFIG_ARM64_PTR_AUTH */
1554 #ifdef CONFIG_ARM64_PSEUDO_NMI
1555 {
1556 /*
1557 * Depends on having GICv3
1558 */
1559 .desc = "IRQ priority masking",
1560 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1561 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1562 .matches = can_use_gic_priorities,
1563 .sys_reg = SYS_ID_AA64PFR0_EL1,
1564 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1565 .sign = FTR_UNSIGNED,
1566 .min_field_value = 1,
1567 },
1568 #endif
1569 {},
1570 };
1571
1572 #define HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1573 .matches = has_cpuid_feature, \
1574 .sys_reg = reg, \
1575 .field_pos = field, \
1576 .sign = s, \
1577 .min_field_value = min_value,
1578
1579 #define __HWCAP_CAP(name, cap_type, cap) \
1580 .desc = name, \
1581 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \
1582 .hwcap_type = cap_type, \
1583 .hwcap = cap, \
1584
1585 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap) \
1586 { \
1587 __HWCAP_CAP(#cap, cap_type, cap) \
1588 HWCAP_CPUID_MATCH(reg, field, s, min_value) \
1589 }
1590
1591 #define HWCAP_MULTI_CAP(list, cap_type, cap) \
1592 { \
1593 __HWCAP_CAP(#cap, cap_type, cap) \
1594 .matches = cpucap_multi_entry_cap_matches, \
1595 .match_list = list, \
1596 }
1597
1598 #ifdef CONFIG_ARM64_PTR_AUTH
1599 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1600 {
1601 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1602 FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1603 },
1604 {
1605 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1606 FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1607 },
1608 {},
1609 };
1610
1611 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1612 {
1613 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1614 FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1615 },
1616 {
1617 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1618 FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1619 },
1620 {},
1621 };
1622 #endif
1623
1624 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1625 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1626 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1627 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1628 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1629 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1630 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1631 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1632 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1633 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1634 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1635 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1636 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1637 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1638 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1639 HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2),
1640 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1641 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1642 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1643 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1644 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1645 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1646 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1647 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1648 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1649 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1650 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1651 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FRINTTS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FRINT),
1652 HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1653 HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1654 #ifdef CONFIG_ARM64_SVE
1655 HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1656 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1657 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1658 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1659 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1660 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1661 HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1662 #endif
1663 HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1664 #ifdef CONFIG_ARM64_PTR_AUTH
1665 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1666 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1667 #endif
1668 {},
1669 };
1670
1671 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1672 #ifdef CONFIG_COMPAT
1673 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1674 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1675 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1676 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1677 HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1678 #endif
1679 {},
1680 };
1681
cap_set_elf_hwcap(const struct arm64_cpu_capabilities * cap)1682 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1683 {
1684 switch (cap->hwcap_type) {
1685 case CAP_HWCAP:
1686 cpu_set_feature(cap->hwcap);
1687 break;
1688 #ifdef CONFIG_COMPAT
1689 case CAP_COMPAT_HWCAP:
1690 compat_elf_hwcap |= (u32)cap->hwcap;
1691 break;
1692 case CAP_COMPAT_HWCAP2:
1693 compat_elf_hwcap2 |= (u32)cap->hwcap;
1694 break;
1695 #endif
1696 default:
1697 WARN_ON(1);
1698 break;
1699 }
1700 }
1701
1702 /* Check if we have a particular HWCAP enabled */
cpus_have_elf_hwcap(const struct arm64_cpu_capabilities * cap)1703 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1704 {
1705 bool rc;
1706
1707 switch (cap->hwcap_type) {
1708 case CAP_HWCAP:
1709 rc = cpu_have_feature(cap->hwcap);
1710 break;
1711 #ifdef CONFIG_COMPAT
1712 case CAP_COMPAT_HWCAP:
1713 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1714 break;
1715 case CAP_COMPAT_HWCAP2:
1716 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1717 break;
1718 #endif
1719 default:
1720 WARN_ON(1);
1721 rc = false;
1722 }
1723
1724 return rc;
1725 }
1726
setup_elf_hwcaps(const struct arm64_cpu_capabilities * hwcaps)1727 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1728 {
1729 /* We support emulation of accesses to CPU ID feature registers */
1730 cpu_set_named_feature(CPUID);
1731 for (; hwcaps->matches; hwcaps++)
1732 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1733 cap_set_elf_hwcap(hwcaps);
1734 }
1735
update_cpu_capabilities(u16 scope_mask)1736 static void update_cpu_capabilities(u16 scope_mask)
1737 {
1738 int i;
1739 const struct arm64_cpu_capabilities *caps;
1740
1741 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1742 for (i = 0; i < ARM64_NCAPS; i++) {
1743 caps = cpu_hwcaps_ptrs[i];
1744 if (!caps || !(caps->type & scope_mask) ||
1745 cpus_have_cap(caps->capability) ||
1746 !caps->matches(caps, cpucap_default_scope(caps)))
1747 continue;
1748
1749 if (caps->desc)
1750 pr_info("detected: %s\n", caps->desc);
1751 cpus_set_cap(caps->capability);
1752
1753 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1754 set_bit(caps->capability, boot_capabilities);
1755 }
1756 }
1757
1758 /*
1759 * Enable all the available capabilities on this CPU. The capabilities
1760 * with BOOT_CPU scope are handled separately and hence skipped here.
1761 */
cpu_enable_non_boot_scope_capabilities(void * __unused)1762 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1763 {
1764 int i;
1765 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1766
1767 for_each_available_cap(i) {
1768 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1769
1770 if (WARN_ON(!cap))
1771 continue;
1772
1773 if (!(cap->type & non_boot_scope))
1774 continue;
1775
1776 if (cap->cpu_enable)
1777 cap->cpu_enable(cap);
1778 }
1779 return 0;
1780 }
1781
1782 /*
1783 * Run through the enabled capabilities and enable() it on all active
1784 * CPUs
1785 */
enable_cpu_capabilities(u16 scope_mask)1786 static void __init enable_cpu_capabilities(u16 scope_mask)
1787 {
1788 int i;
1789 const struct arm64_cpu_capabilities *caps;
1790 bool boot_scope;
1791
1792 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1793 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1794
1795 for (i = 0; i < ARM64_NCAPS; i++) {
1796 unsigned int num;
1797
1798 caps = cpu_hwcaps_ptrs[i];
1799 if (!caps || !(caps->type & scope_mask))
1800 continue;
1801 num = caps->capability;
1802 if (!cpus_have_cap(num))
1803 continue;
1804
1805 /* Ensure cpus_have_const_cap(num) works */
1806 static_branch_enable(&cpu_hwcap_keys[num]);
1807
1808 if (boot_scope && caps->cpu_enable)
1809 /*
1810 * Capabilities with SCOPE_BOOT_CPU scope are finalised
1811 * before any secondary CPU boots. Thus, each secondary
1812 * will enable the capability as appropriate via
1813 * check_local_cpu_capabilities(). The only exception is
1814 * the boot CPU, for which the capability must be
1815 * enabled here. This approach avoids costly
1816 * stop_machine() calls for this case.
1817 */
1818 caps->cpu_enable(caps);
1819 }
1820
1821 /*
1822 * For all non-boot scope capabilities, use stop_machine()
1823 * as it schedules the work allowing us to modify PSTATE,
1824 * instead of on_each_cpu() which uses an IPI, giving us a
1825 * PSTATE that disappears when we return.
1826 */
1827 if (!boot_scope)
1828 stop_machine(cpu_enable_non_boot_scope_capabilities,
1829 NULL, cpu_online_mask);
1830 }
1831
1832 /*
1833 * Run through the list of capabilities to check for conflicts.
1834 * If the system has already detected a capability, take necessary
1835 * action on this CPU.
1836 *
1837 * Returns "false" on conflicts.
1838 */
verify_local_cpu_caps(u16 scope_mask)1839 static bool verify_local_cpu_caps(u16 scope_mask)
1840 {
1841 int i;
1842 bool cpu_has_cap, system_has_cap;
1843 const struct arm64_cpu_capabilities *caps;
1844
1845 scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1846
1847 for (i = 0; i < ARM64_NCAPS; i++) {
1848 caps = cpu_hwcaps_ptrs[i];
1849 if (!caps || !(caps->type & scope_mask))
1850 continue;
1851
1852 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1853 system_has_cap = cpus_have_cap(caps->capability);
1854
1855 if (system_has_cap) {
1856 /*
1857 * Check if the new CPU misses an advertised feature,
1858 * which is not safe to miss.
1859 */
1860 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1861 break;
1862 /*
1863 * We have to issue cpu_enable() irrespective of
1864 * whether the CPU has it or not, as it is enabeld
1865 * system wide. It is upto the call back to take
1866 * appropriate action on this CPU.
1867 */
1868 if (caps->cpu_enable)
1869 caps->cpu_enable(caps);
1870 } else {
1871 /*
1872 * Check if the CPU has this capability if it isn't
1873 * safe to have when the system doesn't.
1874 */
1875 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1876 break;
1877 }
1878 }
1879
1880 if (i < ARM64_NCAPS) {
1881 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1882 smp_processor_id(), caps->capability,
1883 caps->desc, system_has_cap, cpu_has_cap);
1884 return false;
1885 }
1886
1887 return true;
1888 }
1889
1890 /*
1891 * Check for CPU features that are used in early boot
1892 * based on the Boot CPU value.
1893 */
check_early_cpu_features(void)1894 static void check_early_cpu_features(void)
1895 {
1896 verify_cpu_asid_bits();
1897 /*
1898 * Early features are used by the kernel already. If there
1899 * is a conflict, we cannot proceed further.
1900 */
1901 if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1902 cpu_panic_kernel();
1903 }
1904
1905 static void
verify_local_elf_hwcaps(const struct arm64_cpu_capabilities * caps)1906 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1907 {
1908
1909 for (; caps->matches; caps++)
1910 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1911 pr_crit("CPU%d: missing HWCAP: %s\n",
1912 smp_processor_id(), caps->desc);
1913 cpu_die_early();
1914 }
1915 }
1916
verify_sve_features(void)1917 static void verify_sve_features(void)
1918 {
1919 u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1920 u64 zcr = read_zcr_features();
1921
1922 unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1923 unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1924
1925 if (len < safe_len || sve_verify_vq_map()) {
1926 pr_crit("CPU%d: SVE: vector length support mismatch\n",
1927 smp_processor_id());
1928 cpu_die_early();
1929 }
1930
1931 /* Add checks on other ZCR bits here if necessary */
1932 }
1933
1934
1935 /*
1936 * Run through the enabled system capabilities and enable() it on this CPU.
1937 * The capabilities were decided based on the available CPUs at the boot time.
1938 * Any new CPU should match the system wide status of the capability. If the
1939 * new CPU doesn't have a capability which the system now has enabled, we
1940 * cannot do anything to fix it up and could cause unexpected failures. So
1941 * we park the CPU.
1942 */
verify_local_cpu_capabilities(void)1943 static void verify_local_cpu_capabilities(void)
1944 {
1945 /*
1946 * The capabilities with SCOPE_BOOT_CPU are checked from
1947 * check_early_cpu_features(), as they need to be verified
1948 * on all secondary CPUs.
1949 */
1950 if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1951 cpu_die_early();
1952
1953 verify_local_elf_hwcaps(arm64_elf_hwcaps);
1954
1955 if (system_supports_32bit_el0())
1956 verify_local_elf_hwcaps(compat_elf_hwcaps);
1957
1958 if (system_supports_sve())
1959 verify_sve_features();
1960 }
1961
check_local_cpu_capabilities(void)1962 void check_local_cpu_capabilities(void)
1963 {
1964 /*
1965 * All secondary CPUs should conform to the early CPU features
1966 * in use by the kernel based on boot CPU.
1967 */
1968 check_early_cpu_features();
1969
1970 /*
1971 * If we haven't finalised the system capabilities, this CPU gets
1972 * a chance to update the errata work arounds and local features.
1973 * Otherwise, this CPU should verify that it has all the system
1974 * advertised capabilities.
1975 */
1976 if (!sys_caps_initialised)
1977 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1978 else
1979 verify_local_cpu_capabilities();
1980 }
1981
setup_boot_cpu_capabilities(void)1982 static void __init setup_boot_cpu_capabilities(void)
1983 {
1984 /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1985 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1986 /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1987 enable_cpu_capabilities(SCOPE_BOOT_CPU);
1988 }
1989
1990 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1991 EXPORT_SYMBOL(arm64_const_caps_ready);
1992
mark_const_caps_ready(void)1993 static void __init mark_const_caps_ready(void)
1994 {
1995 static_branch_enable(&arm64_const_caps_ready);
1996 }
1997
this_cpu_has_cap(unsigned int n)1998 bool this_cpu_has_cap(unsigned int n)
1999 {
2000 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
2001 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
2002
2003 if (cap)
2004 return cap->matches(cap, SCOPE_LOCAL_CPU);
2005 }
2006
2007 return false;
2008 }
2009
cpu_set_feature(unsigned int num)2010 void cpu_set_feature(unsigned int num)
2011 {
2012 WARN_ON(num >= MAX_CPU_FEATURES);
2013 elf_hwcap |= BIT(num);
2014 }
2015 EXPORT_SYMBOL_GPL(cpu_set_feature);
2016
cpu_have_feature(unsigned int num)2017 bool cpu_have_feature(unsigned int num)
2018 {
2019 WARN_ON(num >= MAX_CPU_FEATURES);
2020 return elf_hwcap & BIT(num);
2021 }
2022 EXPORT_SYMBOL_GPL(cpu_have_feature);
2023
cpu_get_elf_hwcap(void)2024 unsigned long cpu_get_elf_hwcap(void)
2025 {
2026 /*
2027 * We currently only populate the first 32 bits of AT_HWCAP. Please
2028 * note that for userspace compatibility we guarantee that bits 62
2029 * and 63 will always be returned as 0.
2030 */
2031 return lower_32_bits(elf_hwcap);
2032 }
2033
cpu_get_elf_hwcap2(void)2034 unsigned long cpu_get_elf_hwcap2(void)
2035 {
2036 return upper_32_bits(elf_hwcap);
2037 }
2038
setup_system_capabilities(void)2039 static void __init setup_system_capabilities(void)
2040 {
2041 /*
2042 * We have finalised the system-wide safe feature
2043 * registers, finalise the capabilities that depend
2044 * on it. Also enable all the available capabilities,
2045 * that are not enabled already.
2046 */
2047 update_cpu_capabilities(SCOPE_SYSTEM);
2048 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2049 }
2050
setup_cpu_features(void)2051 void __init setup_cpu_features(void)
2052 {
2053 u32 cwg;
2054
2055 setup_system_capabilities();
2056 mark_const_caps_ready();
2057 setup_elf_hwcaps(arm64_elf_hwcaps);
2058
2059 if (system_supports_32bit_el0())
2060 setup_elf_hwcaps(compat_elf_hwcaps);
2061
2062 if (system_uses_ttbr0_pan())
2063 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2064
2065 sve_setup();
2066 minsigstksz_setup();
2067
2068 /* Advertise that we have computed the system capabilities */
2069 set_sys_caps_initialised();
2070
2071 /*
2072 * Check for sane CTR_EL0.CWG value.
2073 */
2074 cwg = cache_type_cwg();
2075 if (!cwg)
2076 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2077 ARCH_DMA_MINALIGN);
2078 }
2079
2080 static bool __maybe_unused
cpufeature_pan_not_uao(const struct arm64_cpu_capabilities * entry,int __unused)2081 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2082 {
2083 return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2084 }
2085
cpu_enable_cnp(struct arm64_cpu_capabilities const * cap)2086 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2087 {
2088 cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2089 }
2090
2091 /*
2092 * We emulate only the following system register space.
2093 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2094 * See Table C5-6 System instruction encodings for System register accesses,
2095 * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2096 */
is_emulated(u32 id)2097 static inline bool __attribute_const__ is_emulated(u32 id)
2098 {
2099 return (sys_reg_Op0(id) == 0x3 &&
2100 sys_reg_CRn(id) == 0x0 &&
2101 sys_reg_Op1(id) == 0x0 &&
2102 (sys_reg_CRm(id) == 0 ||
2103 ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2104 }
2105
2106 /*
2107 * With CRm == 0, reg should be one of :
2108 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2109 */
emulate_id_reg(u32 id,u64 * valp)2110 static inline int emulate_id_reg(u32 id, u64 *valp)
2111 {
2112 switch (id) {
2113 case SYS_MIDR_EL1:
2114 *valp = read_cpuid_id();
2115 break;
2116 case SYS_MPIDR_EL1:
2117 *valp = SYS_MPIDR_SAFE_VAL;
2118 break;
2119 case SYS_REVIDR_EL1:
2120 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2121 *valp = 0;
2122 break;
2123 default:
2124 return -EINVAL;
2125 }
2126
2127 return 0;
2128 }
2129
emulate_sys_reg(u32 id,u64 * valp)2130 static int emulate_sys_reg(u32 id, u64 *valp)
2131 {
2132 struct arm64_ftr_reg *regp;
2133
2134 if (!is_emulated(id))
2135 return -EINVAL;
2136
2137 if (sys_reg_CRm(id) == 0)
2138 return emulate_id_reg(id, valp);
2139
2140 regp = get_arm64_ftr_reg(id);
2141 if (regp)
2142 *valp = arm64_ftr_reg_user_value(regp);
2143 else
2144 /*
2145 * The untracked registers are either IMPLEMENTATION DEFINED
2146 * (e.g, ID_AFR0_EL1) or reserved RAZ.
2147 */
2148 *valp = 0;
2149 return 0;
2150 }
2151
do_emulate_mrs(struct pt_regs * regs,u32 sys_reg,u32 rt)2152 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2153 {
2154 int rc;
2155 u64 val;
2156
2157 rc = emulate_sys_reg(sys_reg, &val);
2158 if (!rc) {
2159 pt_regs_write_reg(regs, rt, val);
2160 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2161 }
2162 return rc;
2163 }
2164
emulate_mrs(struct pt_regs * regs,u32 insn)2165 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2166 {
2167 u32 sys_reg, rt;
2168
2169 /*
2170 * sys_reg values are defined as used in mrs/msr instruction.
2171 * shift the imm value to get the encoding.
2172 */
2173 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2174 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2175 return do_emulate_mrs(regs, sys_reg, rt);
2176 }
2177
2178 static struct undef_hook mrs_hook = {
2179 .instr_mask = 0xfff00000,
2180 .instr_val = 0xd5300000,
2181 .pstate_mask = PSR_AA32_MODE_MASK,
2182 .pstate_val = PSR_MODE_EL0t,
2183 .fn = emulate_mrs,
2184 };
2185
enable_mrs_emulation(void)2186 static int __init enable_mrs_emulation(void)
2187 {
2188 register_undef_hook(&mrs_hook);
2189 return 0;
2190 }
2191
2192 core_initcall(enable_mrs_emulation);
2193
cpu_show_meltdown(struct device * dev,struct device_attribute * attr,char * buf)2194 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2195 char *buf)
2196 {
2197 if (__meltdown_safe)
2198 return sprintf(buf, "Not affected\n");
2199
2200 if (arm64_kernel_unmapped_at_el0())
2201 return sprintf(buf, "Mitigation: PTI\n");
2202
2203 return sprintf(buf, "Vulnerable\n");
2204 }
2205
