1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __MACH_IMX_CLK_H
3 #define __MACH_IMX_CLK_H
4
5 #include <linux/bits.h>
6 #include <linux/spinlock.h>
7 #include <linux/clk-provider.h>
8
9 #define IMX_CLK_GATE2_SINGLE_BIT 1
10
11 extern spinlock_t imx_ccm_lock;
12
13 void imx_check_clocks(struct clk *clks[], unsigned int count);
14 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count);
15 #ifndef MODULE
16 void imx_register_uart_clocks(struct clk ** const clks[]);
17 #else
imx_register_uart_clocks(struct clk ** const clks[])18 static inline void imx_register_uart_clocks(struct clk ** const clks[])
19 {
20 }
21 #endif
22 void imx_mmdc_mask_handshake(void __iomem *ccm_base, unsigned int chn);
23 void imx_unregister_clocks(struct clk *clks[], unsigned int count);
24 void imx_unregister_hw_clocks(struct clk_hw *hws[], unsigned int count);
25
26 extern void imx_cscmr1_fixup(u32 *val);
27
28 enum imx_pllv1_type {
29 IMX_PLLV1_IMX1,
30 IMX_PLLV1_IMX21,
31 IMX_PLLV1_IMX25,
32 IMX_PLLV1_IMX27,
33 IMX_PLLV1_IMX31,
34 IMX_PLLV1_IMX35,
35 };
36
37 enum imx_sscg_pll_type {
38 SCCG_PLL1,
39 SCCG_PLL2,
40 };
41
42 enum imx_pll14xx_type {
43 PLL_1416X,
44 PLL_1443X,
45 };
46
47 /* NOTE: Rate table should be kept sorted in descending order. */
48 struct imx_pll14xx_rate_table {
49 unsigned int rate;
50 unsigned int pdiv;
51 unsigned int mdiv;
52 unsigned int sdiv;
53 unsigned int kdiv;
54 };
55
56 struct imx_pll14xx_clk {
57 enum imx_pll14xx_type type;
58 const struct imx_pll14xx_rate_table *rate_table;
59 int rate_count;
60 int flags;
61 };
62
63 extern struct imx_pll14xx_clk imx_1416x_pll;
64 extern struct imx_pll14xx_clk imx_1443x_pll;
65 extern struct imx_pll14xx_clk imx_1443x_dram_pll;
66
67 #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
68 to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step))
69
70 #define clk_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
71 cgr_val, clk_gate_flags, lock, share_count) \
72 to_clk(clk_hw_register_gate2(dev, name, parent_name, flags, reg, bit_idx, \
73 cgr_val, clk_gate_flags, lock, share_count))
74
75 #define imx_clk_pllv3(type, name, parent_name, base, div_mask) \
76 to_clk(imx_clk_hw_pllv3(type, name, parent_name, base, div_mask))
77
78 #define imx_clk_pfd(name, parent_name, reg, idx) \
79 to_clk(imx_clk_hw_pfd(name, parent_name, reg, idx))
80
81 #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
82 to_clk(imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask))
83
84 #define imx_clk_fixed(name, rate) \
85 to_clk(imx_clk_hw_fixed(name, rate))
86
87 #define imx_clk_fixed_factor(name, parent, mult, div) \
88 to_clk(imx_clk_hw_fixed_factor(name, parent, mult, div))
89
90 #define imx_clk_divider(name, parent, reg, shift, width) \
91 to_clk(imx_clk_hw_divider(name, parent, reg, shift, width))
92
93 #define imx_clk_divider2(name, parent, reg, shift, width) \
94 to_clk(imx_clk_hw_divider2(name, parent, reg, shift, width))
95
96 #define imx_clk_divider_flags(name, parent, reg, shift, width, flags) \
97 to_clk(imx_clk_hw_divider_flags(name, parent, reg, shift, width, flags))
98
99 #define imx_clk_gate(name, parent, reg, shift) \
100 to_clk(imx_clk_hw_gate(name, parent, reg, shift))
101
102 #define imx_clk_gate_dis(name, parent, reg, shift) \
103 to_clk(imx_clk_hw_gate_dis(name, parent, reg, shift))
104
105 #define imx_clk_gate2(name, parent, reg, shift) \
106 to_clk(imx_clk_hw_gate2(name, parent, reg, shift))
107
108 #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
109 to_clk(imx_clk_hw_gate2_flags(name, parent, reg, shift, flags))
110
111 #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
112 to_clk(imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count))
113
114 #define imx_clk_gate3(name, parent, reg, shift) \
115 to_clk(imx_clk_hw_gate3(name, parent, reg, shift))
116
117 #define imx_clk_gate4(name, parent, reg, shift) \
118 to_clk(imx_clk_hw_gate4(name, parent, reg, shift))
119
120 #define imx_clk_mux(name, reg, shift, width, parents, num_parents) \
121 to_clk(imx_clk_hw_mux(name, reg, shift, width, parents, num_parents))
122
123 #define imx_clk_pllv1(type, name, parent, base) \
124 to_clk(imx_clk_hw_pllv1(type, name, parent, base))
125
126 #define imx_clk_pllv2(name, parent, base) \
127 to_clk(imx_clk_hw_pllv2(name, parent, base))
128
129 #define imx_clk_frac_pll(name, parent_name, base) \
130 to_clk(imx_clk_hw_frac_pll(name, parent_name, base))
131
132 #define imx_clk_sscg_pll(name, parent_names, num_parents, parent,\
133 bypass1, bypass2, base, flags) \
134 to_clk(imx_clk_hw_sscg_pll(name, parent_names, num_parents, parent,\
135 bypass1, bypass2, base, flags))
136
137 struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
138 void __iomem *base, const struct imx_pll14xx_clk *pll_clk);
139
140 #define imx_clk_pll14xx(name, parent_name, base, pll_clk) \
141 to_clk(imx_clk_hw_pll14xx(name, parent_name, base, pll_clk))
142
143 struct clk_hw *imx_dev_clk_hw_pll14xx(struct device *dev, const char *name,
144 const char *parent_name, void __iomem *base,
145 const struct imx_pll14xx_clk *pll_clk);
146
147 struct clk_hw *imx_clk_hw_pllv1(enum imx_pllv1_type type, const char *name,
148 const char *parent, void __iomem *base);
149
150 struct clk_hw *imx_clk_hw_pllv2(const char *name, const char *parent,
151 void __iomem *base);
152
153 struct clk_hw *imx_clk_hw_frac_pll(const char *name, const char *parent_name,
154 void __iomem *base);
155
156 struct clk_hw *imx_clk_hw_sscg_pll(const char *name,
157 const char * const *parent_names,
158 u8 num_parents,
159 u8 parent, u8 bypass1, u8 bypass2,
160 void __iomem *base,
161 unsigned long flags);
162
163 enum imx_pllv3_type {
164 IMX_PLLV3_GENERIC,
165 IMX_PLLV3_SYS,
166 IMX_PLLV3_USB,
167 IMX_PLLV3_USB_VF610,
168 IMX_PLLV3_AV,
169 IMX_PLLV3_ENET,
170 IMX_PLLV3_ENET_IMX7,
171 IMX_PLLV3_SYS_VF610,
172 IMX_PLLV3_DDR_IMX7,
173 IMX_PLLV3_AV_IMX7,
174 };
175
176 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
177 const char *parent_name, void __iomem *base, u32 div_mask);
178
179 #define PLL_1416X_RATE(_rate, _m, _p, _s) \
180 { \
181 .rate = (_rate), \
182 .mdiv = (_m), \
183 .pdiv = (_p), \
184 .sdiv = (_s), \
185 }
186
187 #define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
188 { \
189 .rate = (_rate), \
190 .mdiv = (_m), \
191 .pdiv = (_p), \
192 .sdiv = (_s), \
193 .kdiv = (_k), \
194 }
195
196 struct clk_hw *imx_clk_hw_pllv4(const char *name, const char *parent_name,
197 void __iomem *base);
198
199 struct clk_hw *clk_hw_register_gate2(struct device *dev, const char *name,
200 const char *parent_name, unsigned long flags,
201 void __iomem *reg, u8 bit_idx, u8 cgr_val,
202 u8 clk_gate_flags, spinlock_t *lock,
203 unsigned int *share_count);
204
205 struct clk * imx_obtain_fixed_clock(
206 const char *name, unsigned long rate);
207
208 struct clk_hw *imx_obtain_fixed_clock_hw(
209 const char *name, unsigned long rate);
210
211 struct clk_hw *imx_obtain_fixed_clk_hw(struct device_node *np,
212 const char *name);
213
214 struct clk_hw *imx_clk_hw_gate_exclusive(const char *name, const char *parent,
215 void __iomem *reg, u8 shift, u32 exclusive_mask);
216
217 struct clk_hw *imx_clk_hw_pfd(const char *name, const char *parent_name,
218 void __iomem *reg, u8 idx);
219
220 struct clk_hw *imx_clk_hw_pfdv2(const char *name, const char *parent_name,
221 void __iomem *reg, u8 idx);
222
223 struct clk_hw *imx_clk_hw_busy_divider(const char *name, const char *parent_name,
224 void __iomem *reg, u8 shift, u8 width,
225 void __iomem *busy_reg, u8 busy_shift);
226
227 struct clk_hw *imx_clk_hw_busy_mux(const char *name, void __iomem *reg, u8 shift,
228 u8 width, void __iomem *busy_reg, u8 busy_shift,
229 const char * const *parent_names, int num_parents);
230
231 struct clk_hw *imx7ulp_clk_hw_composite(const char *name,
232 const char * const *parent_names,
233 int num_parents, bool mux_present,
234 bool rate_present, bool gate_present,
235 void __iomem *reg);
236
237 struct clk_hw *imx_clk_hw_fixup_divider(const char *name, const char *parent,
238 void __iomem *reg, u8 shift, u8 width,
239 void (*fixup)(u32 *val));
240
241 struct clk_hw *imx_clk_hw_fixup_mux(const char *name, void __iomem *reg,
242 u8 shift, u8 width, const char * const *parents,
243 int num_parents, void (*fixup)(u32 *val));
244
to_clk(struct clk_hw * hw)245 static inline struct clk *to_clk(struct clk_hw *hw)
246 {
247 if (IS_ERR_OR_NULL(hw))
248 return ERR_CAST(hw);
249 return hw->clk;
250 }
251
imx_clk_hw_pll14xx(const char * name,const char * parent_name,void __iomem * base,const struct imx_pll14xx_clk * pll_clk)252 static inline struct clk_hw *imx_clk_hw_pll14xx(const char *name, const char *parent_name,
253 void __iomem *base,
254 const struct imx_pll14xx_clk *pll_clk)
255 {
256 return imx_dev_clk_hw_pll14xx(NULL, name, parent_name, base, pll_clk);
257 }
258
imx_clk_hw_fixed(const char * name,int rate)259 static inline struct clk_hw *imx_clk_hw_fixed(const char *name, int rate)
260 {
261 return clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
262 }
263
imx_clk_hw_mux_ldb(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)264 static inline struct clk_hw *imx_clk_hw_mux_ldb(const char *name, void __iomem *reg,
265 u8 shift, u8 width, const char * const *parents,
266 int num_parents)
267 {
268 return clk_hw_register_mux(NULL, name, parents, num_parents,
269 CLK_SET_RATE_NO_REPARENT | CLK_SET_RATE_PARENT, reg,
270 shift, width, CLK_MUX_READ_ONLY, &imx_ccm_lock);
271 }
272
imx_clk_hw_fixed_factor(const char * name,const char * parent,unsigned int mult,unsigned int div)273 static inline struct clk_hw *imx_clk_hw_fixed_factor(const char *name,
274 const char *parent, unsigned int mult, unsigned int div)
275 {
276 return clk_hw_register_fixed_factor(NULL, name, parent,
277 CLK_SET_RATE_PARENT, mult, div);
278 }
279
imx_clk_hw_divider(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)280 static inline struct clk_hw *imx_clk_hw_divider(const char *name,
281 const char *parent,
282 void __iomem *reg, u8 shift,
283 u8 width)
284 {
285 return clk_hw_register_divider(NULL, name, parent, CLK_SET_RATE_PARENT,
286 reg, shift, width, 0, &imx_ccm_lock);
287 }
288
imx_clk_hw_divider_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,unsigned long flags)289 static inline struct clk_hw *imx_clk_hw_divider_flags(const char *name,
290 const char *parent,
291 void __iomem *reg, u8 shift,
292 u8 width, unsigned long flags)
293 {
294 return clk_hw_register_divider(NULL, name, parent, flags,
295 reg, shift, width, 0, &imx_ccm_lock);
296 }
297
imx_clk_hw_divider2(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width)298 static inline struct clk_hw *imx_clk_hw_divider2(const char *name, const char *parent,
299 void __iomem *reg, u8 shift, u8 width)
300 {
301 return clk_hw_register_divider(NULL, name, parent,
302 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
303 reg, shift, width, 0, &imx_ccm_lock);
304 }
305
imx_clk_divider2_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 width,unsigned long flags)306 static inline struct clk *imx_clk_divider2_flags(const char *name,
307 const char *parent, void __iomem *reg, u8 shift, u8 width,
308 unsigned long flags)
309 {
310 return clk_register_divider(NULL, name, parent,
311 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
312 reg, shift, width, 0, &imx_ccm_lock);
313 }
314
imx_clk_hw_gate_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)315 static inline struct clk_hw *imx_clk_hw_gate_flags(const char *name, const char *parent,
316 void __iomem *reg, u8 shift, unsigned long flags)
317 {
318 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
319 shift, 0, &imx_ccm_lock);
320 }
321
imx_clk_hw_gate(const char * name,const char * parent,void __iomem * reg,u8 shift)322 static inline struct clk_hw *imx_clk_hw_gate(const char *name, const char *parent,
323 void __iomem *reg, u8 shift)
324 {
325 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
326 shift, 0, &imx_ccm_lock);
327 }
328
imx_dev_clk_hw_gate(struct device * dev,const char * name,const char * parent,void __iomem * reg,u8 shift)329 static inline struct clk_hw *imx_dev_clk_hw_gate(struct device *dev, const char *name,
330 const char *parent, void __iomem *reg, u8 shift)
331 {
332 return clk_hw_register_gate(dev, name, parent, CLK_SET_RATE_PARENT, reg,
333 shift, 0, &imx_ccm_lock);
334 }
335
imx_clk_hw_gate_dis(const char * name,const char * parent,void __iomem * reg,u8 shift)336 static inline struct clk_hw *imx_clk_hw_gate_dis(const char *name, const char *parent,
337 void __iomem *reg, u8 shift)
338 {
339 return clk_hw_register_gate(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
340 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
341 }
342
imx_clk_hw_gate_dis_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)343 static inline struct clk_hw *imx_clk_hw_gate_dis_flags(const char *name, const char *parent,
344 void __iomem *reg, u8 shift, unsigned long flags)
345 {
346 return clk_hw_register_gate(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
347 shift, CLK_GATE_SET_TO_DISABLE, &imx_ccm_lock);
348 }
349
imx_clk_hw_gate2(const char * name,const char * parent,void __iomem * reg,u8 shift)350 static inline struct clk_hw *imx_clk_hw_gate2(const char *name, const char *parent,
351 void __iomem *reg, u8 shift)
352 {
353 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
354 shift, 0x3, 0, &imx_ccm_lock, NULL);
355 }
356
imx_clk_hw_gate2_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)357 static inline struct clk_hw *imx_clk_hw_gate2_flags(const char *name, const char *parent,
358 void __iomem *reg, u8 shift, unsigned long flags)
359 {
360 return clk_hw_register_gate2(NULL, name, parent, flags | CLK_SET_RATE_PARENT, reg,
361 shift, 0x3, 0, &imx_ccm_lock, NULL);
362 }
363
imx_clk_hw_gate2_shared(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned int * share_count)364 static inline struct clk_hw *imx_clk_hw_gate2_shared(const char *name,
365 const char *parent, void __iomem *reg, u8 shift,
366 unsigned int *share_count)
367 {
368 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
369 shift, 0x3, 0, &imx_ccm_lock, share_count);
370 }
371
imx_clk_hw_gate2_shared2(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned int * share_count)372 static inline struct clk_hw *imx_clk_hw_gate2_shared2(const char *name,
373 const char *parent, void __iomem *reg, u8 shift,
374 unsigned int *share_count)
375 {
376 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
377 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3, 0,
378 &imx_ccm_lock, share_count);
379 }
380
imx_dev_clk_hw_gate_shared(struct device * dev,const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned int * share_count)381 static inline struct clk_hw *imx_dev_clk_hw_gate_shared(struct device *dev,
382 const char *name, const char *parent,
383 void __iomem *reg, u8 shift,
384 unsigned int *share_count)
385 {
386 return clk_hw_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT |
387 CLK_OPS_PARENT_ENABLE, reg, shift, 0x3,
388 IMX_CLK_GATE2_SINGLE_BIT,
389 &imx_ccm_lock, share_count);
390 }
391
imx_clk_gate2_cgr(const char * name,const char * parent,void __iomem * reg,u8 shift,u8 cgr_val)392 static inline struct clk *imx_clk_gate2_cgr(const char *name,
393 const char *parent, void __iomem *reg, u8 shift, u8 cgr_val)
394 {
395 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
396 shift, cgr_val, 0, &imx_ccm_lock, NULL);
397 }
398
imx_clk_hw_gate3(const char * name,const char * parent,void __iomem * reg,u8 shift)399 static inline struct clk_hw *imx_clk_hw_gate3(const char *name, const char *parent,
400 void __iomem *reg, u8 shift)
401 {
402 return clk_hw_register_gate(NULL, name, parent,
403 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
404 reg, shift, 0, &imx_ccm_lock);
405 }
406
imx_clk_hw_gate3_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)407 static inline struct clk_hw *imx_clk_hw_gate3_flags(const char *name,
408 const char *parent, void __iomem *reg, u8 shift,
409 unsigned long flags)
410 {
411 return clk_hw_register_gate(NULL, name, parent,
412 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
413 reg, shift, 0, &imx_ccm_lock);
414 }
415
416 #define imx_clk_gate3_flags(name, parent, reg, shift, flags) \
417 to_clk(imx_clk_hw_gate3_flags(name, parent, reg, shift, flags))
418
imx_clk_hw_gate4(const char * name,const char * parent,void __iomem * reg,u8 shift)419 static inline struct clk_hw *imx_clk_hw_gate4(const char *name, const char *parent,
420 void __iomem *reg, u8 shift)
421 {
422 return clk_hw_register_gate2(NULL, name, parent,
423 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
424 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
425 }
426
imx_clk_hw_gate4_flags(const char * name,const char * parent,void __iomem * reg,u8 shift,unsigned long flags)427 static inline struct clk_hw *imx_clk_hw_gate4_flags(const char *name,
428 const char *parent, void __iomem *reg, u8 shift,
429 unsigned long flags)
430 {
431 return clk_hw_register_gate2(NULL, name, parent,
432 flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
433 reg, shift, 0x3, 0, &imx_ccm_lock, NULL);
434 }
435
436 #define imx_clk_gate4_flags(name, parent, reg, shift, flags) \
437 to_clk(imx_clk_hw_gate4_flags(name, parent, reg, shift, flags))
438
imx_clk_hw_mux(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)439 static inline struct clk_hw *imx_clk_hw_mux(const char *name, void __iomem *reg,
440 u8 shift, u8 width, const char * const *parents,
441 int num_parents)
442 {
443 return clk_hw_register_mux(NULL, name, parents, num_parents,
444 CLK_SET_RATE_NO_REPARENT, reg, shift,
445 width, 0, &imx_ccm_lock);
446 }
447
imx_dev_clk_hw_mux(struct device * dev,const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)448 static inline struct clk_hw *imx_dev_clk_hw_mux(struct device *dev,
449 const char *name, void __iomem *reg, u8 shift,
450 u8 width, const char * const *parents, int num_parents)
451 {
452 return clk_hw_register_mux(dev, name, parents, num_parents,
453 CLK_SET_RATE_NO_REPARENT | CLK_SET_PARENT_GATE,
454 reg, shift, width, 0, &imx_ccm_lock);
455 }
456
imx_clk_mux2(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)457 static inline struct clk *imx_clk_mux2(const char *name, void __iomem *reg,
458 u8 shift, u8 width, const char * const *parents,
459 int num_parents)
460 {
461 return clk_register_mux(NULL, name, parents, num_parents,
462 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
463 reg, shift, width, 0, &imx_ccm_lock);
464 }
465
imx_clk_hw_mux2(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents)466 static inline struct clk_hw *imx_clk_hw_mux2(const char *name, void __iomem *reg,
467 u8 shift, u8 width,
468 const char * const *parents,
469 int num_parents)
470 {
471 return clk_hw_register_mux(NULL, name, parents, num_parents,
472 CLK_SET_RATE_NO_REPARENT |
473 CLK_OPS_PARENT_ENABLE,
474 reg, shift, width, 0, &imx_ccm_lock);
475 }
476
imx_clk_mux_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)477 static inline struct clk *imx_clk_mux_flags(const char *name,
478 void __iomem *reg, u8 shift, u8 width,
479 const char * const *parents, int num_parents,
480 unsigned long flags)
481 {
482 return clk_register_mux(NULL, name, parents, num_parents,
483 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
484 &imx_ccm_lock);
485 }
486
imx_clk_hw_mux2_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)487 static inline struct clk_hw *imx_clk_hw_mux2_flags(const char *name,
488 void __iomem *reg, u8 shift, u8 width,
489 const char * const *parents,
490 int num_parents, unsigned long flags)
491 {
492 return clk_hw_register_mux(NULL, name, parents, num_parents,
493 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
494 reg, shift, width, 0, &imx_ccm_lock);
495 }
496
imx_clk_mux2_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)497 static inline struct clk *imx_clk_mux2_flags(const char *name,
498 void __iomem *reg, u8 shift, u8 width,
499 const char * const *parents,
500 int num_parents, unsigned long flags)
501 {
502 return clk_register_mux(NULL, name, parents, num_parents,
503 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE,
504 reg, shift, width, 0, &imx_ccm_lock);
505 }
506
imx_clk_hw_mux_flags(const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)507 static inline struct clk_hw *imx_clk_hw_mux_flags(const char *name,
508 void __iomem *reg, u8 shift,
509 u8 width,
510 const char * const *parents,
511 int num_parents,
512 unsigned long flags)
513 {
514 return clk_hw_register_mux(NULL, name, parents, num_parents,
515 flags | CLK_SET_RATE_NO_REPARENT,
516 reg, shift, width, 0, &imx_ccm_lock);
517 }
518
imx_dev_clk_hw_mux_flags(struct device * dev,const char * name,void __iomem * reg,u8 shift,u8 width,const char * const * parents,int num_parents,unsigned long flags)519 static inline struct clk_hw *imx_dev_clk_hw_mux_flags(struct device *dev,
520 const char *name,
521 void __iomem *reg, u8 shift,
522 u8 width,
523 const char * const *parents,
524 int num_parents,
525 unsigned long flags)
526 {
527 return clk_hw_register_mux(dev, name, parents, num_parents,
528 flags | CLK_SET_RATE_NO_REPARENT,
529 reg, shift, width, 0, &imx_ccm_lock);
530 }
531
532 struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name,
533 struct clk *div, struct clk *mux, struct clk *pll,
534 struct clk *step);
535
536 #define IMX_COMPOSITE_CORE BIT(0)
537 #define IMX_COMPOSITE_BUS BIT(1)
538
539 struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,
540 const char * const *parent_names,
541 int num_parents,
542 void __iomem *reg,
543 u32 composite_flags,
544 unsigned long flags);
545
546 #define imx8m_clk_hw_composite_bus(name, parent_names, reg) \
547 imx8m_clk_hw_composite_flags(name, parent_names, \
548 ARRAY_SIZE(parent_names), reg, \
549 IMX_COMPOSITE_BUS, \
550 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
551
552 #define imx8m_clk_hw_composite_bus_critical(name, parent_names, reg) \
553 imx8m_clk_hw_composite_flags(name, parent_names, ARRAY_SIZE(parent_names), reg, \
554 IMX_COMPOSITE_BUS, \
555 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE | CLK_IS_CRITICAL)
556
557 #define imx8m_clk_hw_composite_core(name, parent_names, reg) \
558 imx8m_clk_hw_composite_flags(name, parent_names, \
559 ARRAY_SIZE(parent_names), reg, \
560 IMX_COMPOSITE_CORE, \
561 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
562
563 #define imx8m_clk_composite_flags(name, parent_names, num_parents, reg, \
564 flags) \
565 to_clk(imx8m_clk_hw_composite_flags(name, parent_names, \
566 num_parents, reg, 0, flags))
567
568 #define __imx8m_clk_hw_composite(name, parent_names, reg, flags) \
569 imx8m_clk_hw_composite_flags(name, parent_names, \
570 ARRAY_SIZE(parent_names), reg, 0, \
571 flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
572
573 #define __imx8m_clk_composite(name, parent_names, reg, flags) \
574 to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))
575
576 #define imx8m_clk_hw_composite(name, parent_names, reg) \
577 __imx8m_clk_hw_composite(name, parent_names, reg, 0)
578
579 #define imx8m_clk_composite(name, parent_names, reg) \
580 __imx8m_clk_composite(name, parent_names, reg, 0)
581
582 #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \
583 __imx8m_clk_hw_composite(name, parent_names, reg, CLK_IS_CRITICAL)
584
585 #define imx8m_clk_composite_critical(name, parent_names, reg) \
586 __imx8m_clk_composite(name, parent_names, reg, CLK_IS_CRITICAL)
587
588 struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,
589 unsigned long flags, void __iomem *reg, u8 shift, u8 width,
590 u8 clk_divider_flags, const struct clk_div_table *table,
591 spinlock_t *lock);
592 #endif
593
