1 /*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * This file contains the CPU initialization code.
12 */
13
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21
22 #include "hardware.h"
23 #include "common.h"
24
25 static int mx5_cpu_rev = -1;
26
27 #define IIM_SREV 0x24
28
imx5_read_srev_reg(const char * compat)29 static u32 imx5_read_srev_reg(const char *compat)
30 {
31 void __iomem *iim_base;
32 struct device_node *np;
33 u32 srev;
34
35 np = of_find_compatible_node(NULL, NULL, compat);
36 iim_base = of_iomap(np, 0);
37 WARN_ON(!iim_base);
38
39 srev = readl(iim_base + IIM_SREV) & 0xff;
40
41 iounmap(iim_base);
42
43 return srev;
44 }
45
get_mx51_srev(void)46 static int get_mx51_srev(void)
47 {
48 u32 rev = imx5_read_srev_reg("fsl,imx51-iim");
49
50 switch (rev) {
51 case 0x0:
52 return IMX_CHIP_REVISION_2_0;
53 case 0x10:
54 return IMX_CHIP_REVISION_3_0;
55 default:
56 return IMX_CHIP_REVISION_UNKNOWN;
57 }
58 }
59
60 /*
61 * Returns:
62 * the silicon revision of the cpu
63 */
mx51_revision(void)64 int mx51_revision(void)
65 {
66 if (mx5_cpu_rev == -1)
67 mx5_cpu_rev = get_mx51_srev();
68
69 return mx5_cpu_rev;
70 }
71 EXPORT_SYMBOL(mx51_revision);
72
73 #ifdef CONFIG_NEON
74
75 /*
76 * All versions of the silicon before Rev. 3 have broken NEON implementations.
77 * Dependent on link order - so the assumption is that vfp_init is called
78 * before us.
79 */
mx51_neon_fixup(void)80 int __init mx51_neon_fixup(void)
81 {
82 if (mx51_revision() < IMX_CHIP_REVISION_3_0 &&
83 (elf_hwcap & HWCAP_NEON)) {
84 elf_hwcap &= ~HWCAP_NEON;
85 pr_info("Turning off NEON support, detected broken NEON implementation\n");
86 }
87 return 0;
88 }
89
90 #endif
91
get_mx53_srev(void)92 static int get_mx53_srev(void)
93 {
94 u32 rev = imx5_read_srev_reg("fsl,imx53-iim");
95
96 switch (rev) {
97 case 0x0:
98 return IMX_CHIP_REVISION_1_0;
99 case 0x2:
100 return IMX_CHIP_REVISION_2_0;
101 case 0x3:
102 return IMX_CHIP_REVISION_2_1;
103 default:
104 return IMX_CHIP_REVISION_UNKNOWN;
105 }
106 }
107
108 /*
109 * Returns:
110 * the silicon revision of the cpu
111 */
mx53_revision(void)112 int mx53_revision(void)
113 {
114 if (mx5_cpu_rev == -1)
115 mx5_cpu_rev = get_mx53_srev();
116
117 return mx5_cpu_rev;
118 }
119 EXPORT_SYMBOL(mx53_revision);
120
121 #define ARM_GPC 0x4
122 #define DBGEN BIT(16)
123
124 /*
125 * This enables the DBGEN bit in ARM_GPC register, which is
126 * required for accessing some performance counter features.
127 * Technically it is only required while perf is used, but to
128 * keep the source code simple we just enable it all the time
129 * when the kernel configuration allows using the feature.
130 */
imx5_pmu_init(void)131 void __init imx5_pmu_init(void)
132 {
133 void __iomem *tigerp_base;
134 struct device_node *np;
135 u32 gpc;
136
137 if (!IS_ENABLED(CONFIG_ARM_PMU))
138 return;
139
140 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
141 if (!np)
142 return;
143
144 if (!of_property_read_bool(np, "secure-reg-access"))
145 goto exit;
146
147 of_node_put(np);
148
149 np = of_find_compatible_node(NULL, NULL, "fsl,imx51-tigerp");
150 if (!np)
151 return;
152
153 tigerp_base = of_iomap(np, 0);
154 if (!tigerp_base)
155 goto exit;
156
157 gpc = readl_relaxed(tigerp_base + ARM_GPC);
158 gpc |= DBGEN;
159 writel_relaxed(gpc, tigerp_base + ARM_GPC);
160 iounmap(tigerp_base);
161 exit:
162 of_node_put(np);
163
164 }
165
