1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * arch/arm/mach-imx/mm-imx21.c
4 *
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 */
7
8 #include <linux/mm.h>
9 #include <linux/init.h>
10 #include <linux/pinctrl/machine.h>
11 #include <asm/pgtable.h>
12 #include <asm/mach/map.h>
13
14 #include "common.h"
15 #include "devices/devices-common.h"
16 #include "hardware.h"
17 #include "iomux-v1.h"
18
19 /* MX21 memory map definition */
20 static struct map_desc imx21_io_desc[] __initdata = {
21 /*
22 * this fixed mapping covers:
23 * - AIPI1
24 * - AIPI2
25 * - AITC
26 * - ROM Patch
27 * - and some reserved space
28 */
29 imx_map_entry(MX21, AIPI, MT_DEVICE),
30 /*
31 * this fixed mapping covers:
32 * - CSI
33 * - ATA
34 */
35 imx_map_entry(MX21, SAHB1, MT_DEVICE),
36 /*
37 * this fixed mapping covers:
38 * - EMI
39 */
40 imx_map_entry(MX21, X_MEMC, MT_DEVICE),
41 };
42
43 /*
44 * Initialize the memory map. It is called during the
45 * system startup to create static physical to virtual
46 * memory map for the IO modules.
47 */
mx21_map_io(void)48 void __init mx21_map_io(void)
49 {
50 iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
51 }
52
imx21_init_early(void)53 void __init imx21_init_early(void)
54 {
55 mxc_set_cpu_type(MXC_CPU_MX21);
56 imx_iomuxv1_init(MX21_IO_ADDRESS(MX21_GPIO_BASE_ADDR),
57 MX21_NUM_GPIO_PORT);
58 }
59
mx21_init_irq(void)60 void __init mx21_init_irq(void)
61 {
62 mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
63 }
64
65 static const struct resource imx21_audmux_res[] __initconst = {
66 DEFINE_RES_MEM(MX21_AUDMUX_BASE_ADDR, SZ_4K),
67 };
68
imx21_soc_init(void)69 void __init imx21_soc_init(void)
70 {
71 mxc_arch_reset_init(MX21_IO_ADDRESS(MX21_WDOG_BASE_ADDR));
72 mxc_device_init();
73
74 mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
75 mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
76 mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
77 mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
78 mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
79 mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
80
81 pinctrl_provide_dummies();
82 imx_add_imx_dma("imx21-dma", MX21_DMA_BASE_ADDR,
83 MX21_INT_DMACH0, 0); /* No ERR irq */
84 platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
85 ARRAY_SIZE(imx21_audmux_res));
86 }
87
