1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Cell Internal Interrupt Controller
4 *
5 * Copyright (C) 2006 Benjamin Herrenschmidt (benh@kernel.crashing.org)
6 * IBM, Corp.
7 *
8 * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
9 *
10 * Author: Arnd Bergmann <arndb@de.ibm.com>
11 *
12 * TODO:
13 * - Fix various assumptions related to HW CPU numbers vs. linux CPU numbers
14 * vs node numbers in the setup code
15 * - Implement proper handling of maxcpus=1/2 (that is, routing of irqs from
16 * a non-active node to the active node)
17 */
18
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/export.h>
22 #include <linux/percpu.h>
23 #include <linux/types.h>
24 #include <linux/ioport.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/pgtable.h>
27
28 #include <asm/io.h>
29 #include <asm/prom.h>
30 #include <asm/ptrace.h>
31 #include <asm/machdep.h>
32 #include <asm/cell-regs.h>
33
34 #include "interrupt.h"
35
36 struct iic {
37 struct cbe_iic_thread_regs __iomem *regs;
38 u8 target_id;
39 u8 eoi_stack[16];
40 int eoi_ptr;
41 struct device_node *node;
42 };
43
44 static DEFINE_PER_CPU(struct iic, cpu_iic);
45 #define IIC_NODE_COUNT 2
46 static struct irq_domain *iic_host;
47
48 /* Convert between "pending" bits and hw irq number */
iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)49 static irq_hw_number_t iic_pending_to_hwnum(struct cbe_iic_pending_bits bits)
50 {
51 unsigned char unit = bits.source & 0xf;
52 unsigned char node = bits.source >> 4;
53 unsigned char class = bits.class & 3;
54
55 /* Decode IPIs */
56 if (bits.flags & CBE_IIC_IRQ_IPI)
57 return IIC_IRQ_TYPE_IPI | (bits.prio >> 4);
58 else
59 return (node << IIC_IRQ_NODE_SHIFT) | (class << 4) | unit;
60 }
61
iic_mask(struct irq_data * d)62 static void iic_mask(struct irq_data *d)
63 {
64 }
65
iic_unmask(struct irq_data * d)66 static void iic_unmask(struct irq_data *d)
67 {
68 }
69
iic_eoi(struct irq_data * d)70 static void iic_eoi(struct irq_data *d)
71 {
72 struct iic *iic = this_cpu_ptr(&cpu_iic);
73 out_be64(&iic->regs->prio, iic->eoi_stack[--iic->eoi_ptr]);
74 BUG_ON(iic->eoi_ptr < 0);
75 }
76
77 static struct irq_chip iic_chip = {
78 .name = "CELL-IIC",
79 .irq_mask = iic_mask,
80 .irq_unmask = iic_unmask,
81 .irq_eoi = iic_eoi,
82 };
83
84
iic_ioexc_eoi(struct irq_data * d)85 static void iic_ioexc_eoi(struct irq_data *d)
86 {
87 }
88
iic_ioexc_cascade(struct irq_desc * desc)89 static void iic_ioexc_cascade(struct irq_desc *desc)
90 {
91 struct irq_chip *chip = irq_desc_get_chip(desc);
92 struct cbe_iic_regs __iomem *node_iic =
93 (void __iomem *)irq_desc_get_handler_data(desc);
94 unsigned int irq = irq_desc_get_irq(desc);
95 unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
96 unsigned long bits, ack;
97 int cascade;
98
99 for (;;) {
100 bits = in_be64(&node_iic->iic_is);
101 if (bits == 0)
102 break;
103 /* pre-ack edge interrupts */
104 ack = bits & IIC_ISR_EDGE_MASK;
105 if (ack)
106 out_be64(&node_iic->iic_is, ack);
107 /* handle them */
108 for (cascade = 63; cascade >= 0; cascade--)
109 if (bits & (0x8000000000000000UL >> cascade)) {
110 unsigned int cirq =
111 irq_linear_revmap(iic_host,
112 base | cascade);
113 if (cirq)
114 generic_handle_irq(cirq);
115 }
116 /* post-ack level interrupts */
117 ack = bits & ~IIC_ISR_EDGE_MASK;
118 if (ack)
119 out_be64(&node_iic->iic_is, ack);
120 }
121 chip->irq_eoi(&desc->irq_data);
122 }
123
124
125 static struct irq_chip iic_ioexc_chip = {
126 .name = "CELL-IOEX",
127 .irq_mask = iic_mask,
128 .irq_unmask = iic_unmask,
129 .irq_eoi = iic_ioexc_eoi,
130 };
131
132 /* Get an IRQ number from the pending state register of the IIC */
iic_get_irq(void)133 static unsigned int iic_get_irq(void)
134 {
135 struct cbe_iic_pending_bits pending;
136 struct iic *iic;
137 unsigned int virq;
138
139 iic = this_cpu_ptr(&cpu_iic);
140 *(unsigned long *) &pending =
141 in_be64((u64 __iomem *) &iic->regs->pending_destr);
142 if (!(pending.flags & CBE_IIC_IRQ_VALID))
143 return 0;
144 virq = irq_linear_revmap(iic_host, iic_pending_to_hwnum(pending));
145 if (!virq)
146 return 0;
147 iic->eoi_stack[++iic->eoi_ptr] = pending.prio;
148 BUG_ON(iic->eoi_ptr > 15);
149 return virq;
150 }
151
iic_setup_cpu(void)152 void iic_setup_cpu(void)
153 {
154 out_be64(&this_cpu_ptr(&cpu_iic)->regs->prio, 0xff);
155 }
156
iic_get_target_id(int cpu)157 u8 iic_get_target_id(int cpu)
158 {
159 return per_cpu(cpu_iic, cpu).target_id;
160 }
161
162 EXPORT_SYMBOL_GPL(iic_get_target_id);
163
164 #ifdef CONFIG_SMP
165
166 /* Use the highest interrupt priorities for IPI */
iic_msg_to_irq(int msg)167 static inline int iic_msg_to_irq(int msg)
168 {
169 return IIC_IRQ_TYPE_IPI + 0xf - msg;
170 }
171
iic_message_pass(int cpu,int msg)172 void iic_message_pass(int cpu, int msg)
173 {
174 out_be64(&per_cpu(cpu_iic, cpu).regs->generate, (0xf - msg) << 4);
175 }
176
iic_request_ipi(int msg)177 static void iic_request_ipi(int msg)
178 {
179 int virq;
180
181 virq = irq_create_mapping(iic_host, iic_msg_to_irq(msg));
182 if (!virq) {
183 printk(KERN_ERR
184 "iic: failed to map IPI %s\n", smp_ipi_name[msg]);
185 return;
186 }
187
188 /*
189 * If smp_request_message_ipi encounters an error it will notify
190 * the error. If a message is not needed it will return non-zero.
191 */
192 if (smp_request_message_ipi(virq, msg))
193 irq_dispose_mapping(virq);
194 }
195
iic_request_IPIs(void)196 void iic_request_IPIs(void)
197 {
198 iic_request_ipi(PPC_MSG_CALL_FUNCTION);
199 iic_request_ipi(PPC_MSG_RESCHEDULE);
200 iic_request_ipi(PPC_MSG_TICK_BROADCAST);
201 iic_request_ipi(PPC_MSG_NMI_IPI);
202 }
203
204 #endif /* CONFIG_SMP */
205
206
iic_host_match(struct irq_domain * h,struct device_node * node,enum irq_domain_bus_token bus_token)207 static int iic_host_match(struct irq_domain *h, struct device_node *node,
208 enum irq_domain_bus_token bus_token)
209 {
210 return of_device_is_compatible(node,
211 "IBM,CBEA-Internal-Interrupt-Controller");
212 }
213
iic_host_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)214 static int iic_host_map(struct irq_domain *h, unsigned int virq,
215 irq_hw_number_t hw)
216 {
217 switch (hw & IIC_IRQ_TYPE_MASK) {
218 case IIC_IRQ_TYPE_IPI:
219 irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
220 break;
221 case IIC_IRQ_TYPE_IOEXC:
222 irq_set_chip_and_handler(virq, &iic_ioexc_chip,
223 handle_edge_eoi_irq);
224 break;
225 default:
226 irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
227 }
228 return 0;
229 }
230
iic_host_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)231 static int iic_host_xlate(struct irq_domain *h, struct device_node *ct,
232 const u32 *intspec, unsigned int intsize,
233 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
234
235 {
236 unsigned int node, ext, unit, class;
237 const u32 *val;
238
239 if (!of_device_is_compatible(ct,
240 "IBM,CBEA-Internal-Interrupt-Controller"))
241 return -ENODEV;
242 if (intsize != 1)
243 return -ENODEV;
244 val = of_get_property(ct, "#interrupt-cells", NULL);
245 if (val == NULL || *val != 1)
246 return -ENODEV;
247
248 node = intspec[0] >> 24;
249 ext = (intspec[0] >> 16) & 0xff;
250 class = (intspec[0] >> 8) & 0xff;
251 unit = intspec[0] & 0xff;
252
253 /* Check if node is in supported range */
254 if (node > 1)
255 return -EINVAL;
256
257 /* Build up interrupt number, special case for IO exceptions */
258 *out_hwirq = (node << IIC_IRQ_NODE_SHIFT);
259 if (unit == IIC_UNIT_IIC && class == 1)
260 *out_hwirq |= IIC_IRQ_TYPE_IOEXC | ext;
261 else
262 *out_hwirq |= IIC_IRQ_TYPE_NORMAL |
263 (class << IIC_IRQ_CLASS_SHIFT) | unit;
264
265 /* Dummy flags, ignored by iic code */
266 *out_flags = IRQ_TYPE_EDGE_RISING;
267
268 return 0;
269 }
270
271 static const struct irq_domain_ops iic_host_ops = {
272 .match = iic_host_match,
273 .map = iic_host_map,
274 .xlate = iic_host_xlate,
275 };
276
init_one_iic(unsigned int hw_cpu,unsigned long addr,struct device_node * node)277 static void __init init_one_iic(unsigned int hw_cpu, unsigned long addr,
278 struct device_node *node)
279 {
280 /* XXX FIXME: should locate the linux CPU number from the HW cpu
281 * number properly. We are lucky for now
282 */
283 struct iic *iic = &per_cpu(cpu_iic, hw_cpu);
284
285 iic->regs = ioremap(addr, sizeof(struct cbe_iic_thread_regs));
286 BUG_ON(iic->regs == NULL);
287
288 iic->target_id = ((hw_cpu & 2) << 3) | ((hw_cpu & 1) ? 0xf : 0xe);
289 iic->eoi_stack[0] = 0xff;
290 iic->node = of_node_get(node);
291 out_be64(&iic->regs->prio, 0);
292
293 printk(KERN_INFO "IIC for CPU %d target id 0x%x : %pOF\n",
294 hw_cpu, iic->target_id, node);
295 }
296
setup_iic(void)297 static int __init setup_iic(void)
298 {
299 struct device_node *dn;
300 struct resource r0, r1;
301 unsigned int node, cascade, found = 0;
302 struct cbe_iic_regs __iomem *node_iic;
303 const u32 *np;
304
305 for_each_node_by_name(dn, "interrupt-controller") {
306 if (!of_device_is_compatible(dn,
307 "IBM,CBEA-Internal-Interrupt-Controller"))
308 continue;
309 np = of_get_property(dn, "ibm,interrupt-server-ranges", NULL);
310 if (np == NULL) {
311 printk(KERN_WARNING "IIC: CPU association not found\n");
312 of_node_put(dn);
313 return -ENODEV;
314 }
315 if (of_address_to_resource(dn, 0, &r0) ||
316 of_address_to_resource(dn, 1, &r1)) {
317 printk(KERN_WARNING "IIC: Can't resolve addresses\n");
318 of_node_put(dn);
319 return -ENODEV;
320 }
321 found++;
322 init_one_iic(np[0], r0.start, dn);
323 init_one_iic(np[1], r1.start, dn);
324
325 /* Setup cascade for IO exceptions. XXX cleanup tricks to get
326 * node vs CPU etc...
327 * Note that we configure the IIC_IRR here with a hard coded
328 * priority of 1. We might want to improve that later.
329 */
330 node = np[0] >> 1;
331 node_iic = cbe_get_cpu_iic_regs(np[0]);
332 cascade = node << IIC_IRQ_NODE_SHIFT;
333 cascade |= 1 << IIC_IRQ_CLASS_SHIFT;
334 cascade |= IIC_UNIT_IIC;
335 cascade = irq_create_mapping(iic_host, cascade);
336 if (!cascade)
337 continue;
338 /*
339 * irq_data is a generic pointer that gets passed back
340 * to us later, so the forced cast is fine.
341 */
342 irq_set_handler_data(cascade, (void __force *)node_iic);
343 irq_set_chained_handler(cascade, iic_ioexc_cascade);
344 out_be64(&node_iic->iic_ir,
345 (1 << 12) /* priority */ |
346 (node << 4) /* dest node */ |
347 IIC_UNIT_THREAD_0 /* route them to thread 0 */);
348 /* Flush pending (make sure it triggers if there is
349 * anything pending
350 */
351 out_be64(&node_iic->iic_is, 0xfffffffffffffffful);
352 }
353
354 if (found)
355 return 0;
356 else
357 return -ENODEV;
358 }
359
iic_init_IRQ(void)360 void __init iic_init_IRQ(void)
361 {
362 /* Setup an irq host data structure */
363 iic_host = irq_domain_add_linear(NULL, IIC_SOURCE_COUNT, &iic_host_ops,
364 NULL);
365 BUG_ON(iic_host == NULL);
366 irq_set_default_host(iic_host);
367
368 /* Discover and initialize iics */
369 if (setup_iic() < 0)
370 panic("IIC: Failed to initialize !\n");
371
372 /* Set master interrupt handling function */
373 ppc_md.get_irq = iic_get_irq;
374
375 /* Enable on current CPU */
376 iic_setup_cpu();
377 }
378
iic_set_interrupt_routing(int cpu,int thread,int priority)379 void iic_set_interrupt_routing(int cpu, int thread, int priority)
380 {
381 struct cbe_iic_regs __iomem *iic_regs = cbe_get_cpu_iic_regs(cpu);
382 u64 iic_ir = 0;
383 int node = cpu >> 1;
384
385 /* Set which node and thread will handle the next interrupt */
386 iic_ir |= CBE_IIC_IR_PRIO(priority) |
387 CBE_IIC_IR_DEST_NODE(node);
388 if (thread == 0)
389 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_0);
390 else
391 iic_ir |= CBE_IIC_IR_DEST_UNIT(CBE_IIC_IR_PT_1);
392 out_be64(&iic_regs->iic_ir, iic_ir);
393 }
394
