1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018 Intel Corporation */
3
4 #include <linux/delay.h>
5
6 #include "igc_hw.h"
7 #include "igc_i225.h"
8 #include "igc_mac.h"
9 #include "igc_base.h"
10 #include "igc.h"
11
12 /**
13 * igc_reset_hw_base - Reset hardware
14 * @hw: pointer to the HW structure
15 *
16 * This resets the hardware into a known state. This is a
17 * function pointer entry point called by the api module.
18 */
igc_reset_hw_base(struct igc_hw * hw)19 static s32 igc_reset_hw_base(struct igc_hw *hw)
20 {
21 s32 ret_val;
22 u32 ctrl;
23
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection
25 * on the last TLP read/write transaction when MAC is reset.
26 */
27 ret_val = igc_disable_pcie_master(hw);
28 if (ret_val)
29 hw_dbg("PCI-E Master disable polling has failed\n");
30
31 hw_dbg("Masking off all interrupts\n");
32 wr32(IGC_IMC, 0xffffffff);
33
34 wr32(IGC_RCTL, 0);
35 wr32(IGC_TCTL, IGC_TCTL_PSP);
36 wrfl();
37
38 usleep_range(10000, 20000);
39
40 ctrl = rd32(IGC_CTRL);
41
42 hw_dbg("Issuing a global reset to MAC\n");
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_DEV_RST);
44
45 ret_val = igc_get_auto_rd_done(hw);
46 if (ret_val) {
47 /* When auto config read does not complete, do not
48 * return with an error. This can happen in situations
49 * where there is no eeprom and prevents getting link.
50 */
51 hw_dbg("Auto Read Done did not complete\n");
52 }
53
54 /* Clear any pending interrupt events. */
55 wr32(IGC_IMC, 0xffffffff);
56 rd32(IGC_ICR);
57
58 return ret_val;
59 }
60
61 /**
62 * igc_init_nvm_params_base - Init NVM func ptrs.
63 * @hw: pointer to the HW structure
64 */
igc_init_nvm_params_base(struct igc_hw * hw)65 static s32 igc_init_nvm_params_base(struct igc_hw *hw)
66 {
67 struct igc_nvm_info *nvm = &hw->nvm;
68 u32 eecd = rd32(IGC_EECD);
69 u16 size;
70
71 size = (u16)((eecd & IGC_EECD_SIZE_EX_MASK) >>
72 IGC_EECD_SIZE_EX_SHIFT);
73
74 /* Added to a constant, "size" becomes the left-shift value
75 * for setting word_size.
76 */
77 size += NVM_WORD_SIZE_BASE_SHIFT;
78
79 /* Just in case size is out of range, cap it to the largest
80 * EEPROM size supported
81 */
82 if (size > 15)
83 size = 15;
84
85 nvm->type = igc_nvm_eeprom_spi;
86 nvm->word_size = BIT(size);
87 nvm->opcode_bits = 8;
88 nvm->delay_usec = 1;
89
90 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8;
91 nvm->address_bits = eecd & IGC_EECD_ADDR_BITS ?
92 16 : 8;
93
94 if (nvm->word_size == BIT(15))
95 nvm->page_size = 128;
96
97 return 0;
98 }
99
100 /**
101 * igc_setup_copper_link_base - Configure copper link settings
102 * @hw: pointer to the HW structure
103 *
104 * Configures the link for auto-neg or forced speed and duplex. Then we check
105 * for link, once link is established calls to configure collision distance
106 * and flow control are called.
107 */
igc_setup_copper_link_base(struct igc_hw * hw)108 static s32 igc_setup_copper_link_base(struct igc_hw *hw)
109 {
110 s32 ret_val = 0;
111 u32 ctrl;
112
113 ctrl = rd32(IGC_CTRL);
114 ctrl |= IGC_CTRL_SLU;
115 ctrl &= ~(IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
116 wr32(IGC_CTRL, ctrl);
117
118 ret_val = igc_setup_copper_link(hw);
119
120 return ret_val;
121 }
122
123 /**
124 * igc_init_mac_params_base - Init MAC func ptrs.
125 * @hw: pointer to the HW structure
126 */
igc_init_mac_params_base(struct igc_hw * hw)127 static s32 igc_init_mac_params_base(struct igc_hw *hw)
128 {
129 struct igc_dev_spec_base *dev_spec = &hw->dev_spec._base;
130 struct igc_mac_info *mac = &hw->mac;
131
132 /* Set mta register count */
133 mac->mta_reg_count = 128;
134 mac->rar_entry_count = IGC_RAR_ENTRIES;
135
136 /* reset */
137 mac->ops.reset_hw = igc_reset_hw_base;
138
139 mac->ops.acquire_swfw_sync = igc_acquire_swfw_sync_i225;
140 mac->ops.release_swfw_sync = igc_release_swfw_sync_i225;
141
142 /* Allow a single clear of the SW semaphore on I225 */
143 if (mac->type == igc_i225)
144 dev_spec->clear_semaphore_once = true;
145
146 /* physical interface link setup */
147 mac->ops.setup_physical_interface = igc_setup_copper_link_base;
148
149 return 0;
150 }
151
152 /**
153 * igc_init_phy_params_base - Init PHY func ptrs.
154 * @hw: pointer to the HW structure
155 */
igc_init_phy_params_base(struct igc_hw * hw)156 static s32 igc_init_phy_params_base(struct igc_hw *hw)
157 {
158 struct igc_phy_info *phy = &hw->phy;
159 s32 ret_val = 0;
160
161 if (hw->phy.media_type != igc_media_type_copper) {
162 phy->type = igc_phy_none;
163 goto out;
164 }
165
166 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT_2500;
167 phy->reset_delay_us = 100;
168
169 /* set lan id */
170 hw->bus.func = (rd32(IGC_STATUS) & IGC_STATUS_FUNC_MASK) >>
171 IGC_STATUS_FUNC_SHIFT;
172
173 /* Make sure the PHY is in a good state. Several people have reported
174 * firmware leaving the PHY's page select register set to something
175 * other than the default of zero, which causes the PHY ID read to
176 * access something other than the intended register.
177 */
178 ret_val = hw->phy.ops.reset(hw);
179 if (ret_val) {
180 hw_dbg("Error resetting the PHY\n");
181 goto out;
182 }
183
184 ret_val = igc_get_phy_id(hw);
185 if (ret_val)
186 return ret_val;
187
188 igc_check_for_copper_link(hw);
189
190 phy->type = igc_phy_i225;
191
192 out:
193 return ret_val;
194 }
195
igc_get_invariants_base(struct igc_hw * hw)196 static s32 igc_get_invariants_base(struct igc_hw *hw)
197 {
198 struct igc_mac_info *mac = &hw->mac;
199 s32 ret_val = 0;
200
201 switch (hw->device_id) {
202 case IGC_DEV_ID_I225_LM:
203 case IGC_DEV_ID_I225_V:
204 case IGC_DEV_ID_I225_I:
205 case IGC_DEV_ID_I220_V:
206 case IGC_DEV_ID_I225_K:
207 case IGC_DEV_ID_I225_K2:
208 case IGC_DEV_ID_I226_K:
209 case IGC_DEV_ID_I225_LMVP:
210 case IGC_DEV_ID_I225_IT:
211 case IGC_DEV_ID_I226_LM:
212 case IGC_DEV_ID_I226_V:
213 case IGC_DEV_ID_I226_IT:
214 case IGC_DEV_ID_I221_V:
215 case IGC_DEV_ID_I226_BLANK_NVM:
216 case IGC_DEV_ID_I225_BLANK_NVM:
217 mac->type = igc_i225;
218 break;
219 default:
220 return -IGC_ERR_MAC_INIT;
221 }
222
223 hw->phy.media_type = igc_media_type_copper;
224
225 /* mac initialization and operations */
226 ret_val = igc_init_mac_params_base(hw);
227 if (ret_val)
228 goto out;
229
230 /* NVM initialization */
231 ret_val = igc_init_nvm_params_base(hw);
232 switch (hw->mac.type) {
233 case igc_i225:
234 ret_val = igc_init_nvm_params_i225(hw);
235 break;
236 default:
237 break;
238 }
239
240 /* setup PHY parameters */
241 ret_val = igc_init_phy_params_base(hw);
242 if (ret_val)
243 goto out;
244
245 out:
246 return ret_val;
247 }
248
249 /**
250 * igc_acquire_phy_base - Acquire rights to access PHY
251 * @hw: pointer to the HW structure
252 *
253 * Acquire access rights to the correct PHY. This is a
254 * function pointer entry point called by the api module.
255 */
igc_acquire_phy_base(struct igc_hw * hw)256 static s32 igc_acquire_phy_base(struct igc_hw *hw)
257 {
258 u16 mask = IGC_SWFW_PHY0_SM;
259
260 return hw->mac.ops.acquire_swfw_sync(hw, mask);
261 }
262
263 /**
264 * igc_release_phy_base - Release rights to access PHY
265 * @hw: pointer to the HW structure
266 *
267 * A wrapper to release access rights to the correct PHY. This is a
268 * function pointer entry point called by the api module.
269 */
igc_release_phy_base(struct igc_hw * hw)270 static void igc_release_phy_base(struct igc_hw *hw)
271 {
272 u16 mask = IGC_SWFW_PHY0_SM;
273
274 hw->mac.ops.release_swfw_sync(hw, mask);
275 }
276
277 /**
278 * igc_init_hw_base - Initialize hardware
279 * @hw: pointer to the HW structure
280 *
281 * This inits the hardware readying it for operation.
282 */
igc_init_hw_base(struct igc_hw * hw)283 static s32 igc_init_hw_base(struct igc_hw *hw)
284 {
285 struct igc_mac_info *mac = &hw->mac;
286 u16 i, rar_count = mac->rar_entry_count;
287 s32 ret_val = 0;
288
289 /* Setup the receive address */
290 igc_init_rx_addrs(hw, rar_count);
291
292 /* Zero out the Multicast HASH table */
293 hw_dbg("Zeroing the MTA\n");
294 for (i = 0; i < mac->mta_reg_count; i++)
295 array_wr32(IGC_MTA, i, 0);
296
297 /* Zero out the Unicast HASH table */
298 hw_dbg("Zeroing the UTA\n");
299 for (i = 0; i < mac->uta_reg_count; i++)
300 array_wr32(IGC_UTA, i, 0);
301
302 /* Setup link and flow control */
303 ret_val = igc_setup_link(hw);
304
305 /* Clear all of the statistics registers (clear on read). It is
306 * important that we do this after we have tried to establish link
307 * because the symbol error count will increment wildly if there
308 * is no link.
309 */
310 igc_clear_hw_cntrs_base(hw);
311
312 return ret_val;
313 }
314
315 /**
316 * igc_power_down_phy_copper_base - Remove link during PHY power down
317 * @hw: pointer to the HW structure
318 *
319 * In the case of a PHY power down to save power, or to turn off link during a
320 * driver unload, or wake on lan is not enabled, remove the link.
321 */
igc_power_down_phy_copper_base(struct igc_hw * hw)322 void igc_power_down_phy_copper_base(struct igc_hw *hw)
323 {
324 /* If the management interface is not enabled, then power down */
325 if (!(igc_enable_mng_pass_thru(hw) || igc_check_reset_block(hw)))
326 igc_power_down_phy_copper(hw);
327 }
328
329 /**
330 * igc_rx_fifo_flush_base - Clean rx fifo after Rx enable
331 * @hw: pointer to the HW structure
332 *
333 * After Rx enable, if manageability is enabled then there is likely some
334 * bad data at the start of the fifo and possibly in the DMA fifo. This
335 * function clears the fifos and flushes any packets that came in as rx was
336 * being enabled.
337 */
igc_rx_fifo_flush_base(struct igc_hw * hw)338 void igc_rx_fifo_flush_base(struct igc_hw *hw)
339 {
340 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
341 int i, ms_wait;
342
343 /* disable IPv6 options as per hardware errata */
344 rfctl = rd32(IGC_RFCTL);
345 rfctl |= IGC_RFCTL_IPV6_EX_DIS;
346 wr32(IGC_RFCTL, rfctl);
347
348 if (!(rd32(IGC_MANC) & IGC_MANC_RCV_TCO_EN))
349 return;
350
351 /* Disable all Rx queues */
352 for (i = 0; i < 4; i++) {
353 rxdctl[i] = rd32(IGC_RXDCTL(i));
354 wr32(IGC_RXDCTL(i),
355 rxdctl[i] & ~IGC_RXDCTL_QUEUE_ENABLE);
356 }
357 /* Poll all queues to verify they have shut down */
358 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
359 usleep_range(1000, 2000);
360 rx_enabled = 0;
361 for (i = 0; i < 4; i++)
362 rx_enabled |= rd32(IGC_RXDCTL(i));
363 if (!(rx_enabled & IGC_RXDCTL_QUEUE_ENABLE))
364 break;
365 }
366
367 if (ms_wait == 10)
368 hw_dbg("Queue disable timed out after 10ms\n");
369
370 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
371 * incoming packets are rejected. Set enable and wait 2ms so that
372 * any packet that was coming in as RCTL.EN was set is flushed
373 */
374 wr32(IGC_RFCTL, rfctl & ~IGC_RFCTL_LEF);
375
376 rlpml = rd32(IGC_RLPML);
377 wr32(IGC_RLPML, 0);
378
379 rctl = rd32(IGC_RCTL);
380 temp_rctl = rctl & ~(IGC_RCTL_EN | IGC_RCTL_SBP);
381 temp_rctl |= IGC_RCTL_LPE;
382
383 wr32(IGC_RCTL, temp_rctl);
384 wr32(IGC_RCTL, temp_rctl | IGC_RCTL_EN);
385 wrfl();
386 usleep_range(2000, 3000);
387
388 /* Enable Rx queues that were previously enabled and restore our
389 * previous state
390 */
391 for (i = 0; i < 4; i++)
392 wr32(IGC_RXDCTL(i), rxdctl[i]);
393 wr32(IGC_RCTL, rctl);
394 wrfl();
395
396 wr32(IGC_RLPML, rlpml);
397 wr32(IGC_RFCTL, rfctl);
398
399 /* Flush receive errors generated by workaround */
400 rd32(IGC_ROC);
401 rd32(IGC_RNBC);
402 rd32(IGC_MPC);
403 }
404
405 static struct igc_mac_operations igc_mac_ops_base = {
406 .init_hw = igc_init_hw_base,
407 .check_for_link = igc_check_for_copper_link,
408 .rar_set = igc_rar_set,
409 .read_mac_addr = igc_read_mac_addr,
410 .get_speed_and_duplex = igc_get_speed_and_duplex_copper,
411 };
412
413 static const struct igc_phy_operations igc_phy_ops_base = {
414 .acquire = igc_acquire_phy_base,
415 .release = igc_release_phy_base,
416 .reset = igc_phy_hw_reset,
417 .read_reg = igc_read_phy_reg_gpy,
418 .write_reg = igc_write_phy_reg_gpy,
419 };
420
421 const struct igc_info igc_base_info = {
422 .get_invariants = igc_get_invariants_base,
423 .mac_ops = &igc_mac_ops_base,
424 .phy_ops = &igc_phy_ops_base,
425 };
426
