1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, Intel Corporation. */
3
4 #include "ice_common.h"
5 #include "ice_sched.h"
6 #include "ice_adminq_cmd.h"
7
8 #define ICE_PF_RESET_WAIT_COUNT 200
9
10 #define ICE_PROG_FLEX_ENTRY(hw, rxdid, mdid, idx) \
11 wr32((hw), GLFLXP_RXDID_FLX_WRD_##idx(rxdid), \
12 ((ICE_RX_OPC_MDID << \
13 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_S) & \
14 GLFLXP_RXDID_FLX_WRD_##idx##_RXDID_OPCODE_M) | \
15 (((mdid) << GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_S) & \
16 GLFLXP_RXDID_FLX_WRD_##idx##_PROT_MDID_M))
17
18 #define ICE_PROG_FLG_ENTRY(hw, rxdid, flg_0, flg_1, flg_2, flg_3, idx) \
19 wr32((hw), GLFLXP_RXDID_FLAGS(rxdid, idx), \
20 (((flg_0) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S) & \
21 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M) | \
22 (((flg_1) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_S) & \
23 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_1_M) | \
24 (((flg_2) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_S) & \
25 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_2_M) | \
26 (((flg_3) << GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_S) & \
27 GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_3_M))
28
29 /**
30 * ice_set_mac_type - Sets MAC type
31 * @hw: pointer to the HW structure
32 *
33 * This function sets the MAC type of the adapter based on the
34 * vendor ID and device ID stored in the HW structure.
35 */
ice_set_mac_type(struct ice_hw * hw)36 static enum ice_status ice_set_mac_type(struct ice_hw *hw)
37 {
38 if (hw->vendor_id != PCI_VENDOR_ID_INTEL)
39 return ICE_ERR_DEVICE_NOT_SUPPORTED;
40
41 hw->mac_type = ICE_MAC_GENERIC;
42 return 0;
43 }
44
45 /**
46 * ice_dev_onetime_setup - Temporary HW/FW workarounds
47 * @hw: pointer to the HW structure
48 *
49 * This function provides temporary workarounds for certain issues
50 * that are expected to be fixed in the HW/FW.
51 */
ice_dev_onetime_setup(struct ice_hw * hw)52 void ice_dev_onetime_setup(struct ice_hw *hw)
53 {
54 #define MBX_PF_VT_PFALLOC 0x00231E80
55 /* set VFs per PF */
56 wr32(hw, MBX_PF_VT_PFALLOC, rd32(hw, PF_VT_PFALLOC_HIF));
57 }
58
59 /**
60 * ice_clear_pf_cfg - Clear PF configuration
61 * @hw: pointer to the hardware structure
62 *
63 * Clears any existing PF configuration (VSIs, VSI lists, switch rules, port
64 * configuration, flow director filters, etc.).
65 */
ice_clear_pf_cfg(struct ice_hw * hw)66 enum ice_status ice_clear_pf_cfg(struct ice_hw *hw)
67 {
68 struct ice_aq_desc desc;
69
70 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pf_cfg);
71
72 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
73 }
74
75 /**
76 * ice_aq_manage_mac_read - manage MAC address read command
77 * @hw: pointer to the HW struct
78 * @buf: a virtual buffer to hold the manage MAC read response
79 * @buf_size: Size of the virtual buffer
80 * @cd: pointer to command details structure or NULL
81 *
82 * This function is used to return per PF station MAC address (0x0107).
83 * NOTE: Upon successful completion of this command, MAC address information
84 * is returned in user specified buffer. Please interpret user specified
85 * buffer as "manage_mac_read" response.
86 * Response such as various MAC addresses are stored in HW struct (port.mac)
87 * ice_aq_discover_caps is expected to be called before this function is called.
88 */
89 static enum ice_status
ice_aq_manage_mac_read(struct ice_hw * hw,void * buf,u16 buf_size,struct ice_sq_cd * cd)90 ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16 buf_size,
91 struct ice_sq_cd *cd)
92 {
93 struct ice_aqc_manage_mac_read_resp *resp;
94 struct ice_aqc_manage_mac_read *cmd;
95 struct ice_aq_desc desc;
96 enum ice_status status;
97 u16 flags;
98 u8 i;
99
100 cmd = &desc.params.mac_read;
101
102 if (buf_size < sizeof(*resp))
103 return ICE_ERR_BUF_TOO_SHORT;
104
105 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_read);
106
107 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
108 if (status)
109 return status;
110
111 resp = (struct ice_aqc_manage_mac_read_resp *)buf;
112 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M;
113
114 if (!(flags & ICE_AQC_MAN_MAC_LAN_ADDR_VALID)) {
115 ice_debug(hw, ICE_DBG_LAN, "got invalid MAC address\n");
116 return ICE_ERR_CFG;
117 }
118
119 /* A single port can report up to two (LAN and WoL) addresses */
120 for (i = 0; i < cmd->num_addr; i++)
121 if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
122 ether_addr_copy(hw->port_info->mac.lan_addr,
123 resp[i].mac_addr);
124 ether_addr_copy(hw->port_info->mac.perm_addr,
125 resp[i].mac_addr);
126 break;
127 }
128
129 return 0;
130 }
131
132 /**
133 * ice_aq_get_phy_caps - returns PHY capabilities
134 * @pi: port information structure
135 * @qual_mods: report qualified modules
136 * @report_mode: report mode capabilities
137 * @pcaps: structure for PHY capabilities to be filled
138 * @cd: pointer to command details structure or NULL
139 *
140 * Returns the various PHY capabilities supported on the Port (0x0600)
141 */
142 enum ice_status
ice_aq_get_phy_caps(struct ice_port_info * pi,bool qual_mods,u8 report_mode,struct ice_aqc_get_phy_caps_data * pcaps,struct ice_sq_cd * cd)143 ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
144 struct ice_aqc_get_phy_caps_data *pcaps,
145 struct ice_sq_cd *cd)
146 {
147 struct ice_aqc_get_phy_caps *cmd;
148 u16 pcaps_size = sizeof(*pcaps);
149 struct ice_aq_desc desc;
150 enum ice_status status;
151
152 cmd = &desc.params.get_phy;
153
154 if (!pcaps || (report_mode & ~ICE_AQC_REPORT_MODE_M) || !pi)
155 return ICE_ERR_PARAM;
156
157 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_phy_caps);
158
159 if (qual_mods)
160 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM);
161
162 cmd->param0 |= cpu_to_le16(report_mode);
163 status = ice_aq_send_cmd(pi->hw, &desc, pcaps, pcaps_size, cd);
164
165 if (!status && report_mode == ICE_AQC_REPORT_TOPO_CAP) {
166 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low);
167 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high);
168 }
169
170 return status;
171 }
172
173 /**
174 * ice_get_media_type - Gets media type
175 * @pi: port information structure
176 */
ice_get_media_type(struct ice_port_info * pi)177 static enum ice_media_type ice_get_media_type(struct ice_port_info *pi)
178 {
179 struct ice_link_status *hw_link_info;
180
181 if (!pi)
182 return ICE_MEDIA_UNKNOWN;
183
184 hw_link_info = &pi->phy.link_info;
185 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high)
186 /* If more than one media type is selected, report unknown */
187 return ICE_MEDIA_UNKNOWN;
188
189 if (hw_link_info->phy_type_low) {
190 switch (hw_link_info->phy_type_low) {
191 case ICE_PHY_TYPE_LOW_1000BASE_SX:
192 case ICE_PHY_TYPE_LOW_1000BASE_LX:
193 case ICE_PHY_TYPE_LOW_10GBASE_SR:
194 case ICE_PHY_TYPE_LOW_10GBASE_LR:
195 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
196 case ICE_PHY_TYPE_LOW_25GBASE_SR:
197 case ICE_PHY_TYPE_LOW_25GBASE_LR:
198 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
199 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
200 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
201 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
202 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
203 case ICE_PHY_TYPE_LOW_50GBASE_SR:
204 case ICE_PHY_TYPE_LOW_50GBASE_FR:
205 case ICE_PHY_TYPE_LOW_50GBASE_LR:
206 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
207 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
208 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
209 case ICE_PHY_TYPE_LOW_100GBASE_DR:
210 return ICE_MEDIA_FIBER;
211 case ICE_PHY_TYPE_LOW_100BASE_TX:
212 case ICE_PHY_TYPE_LOW_1000BASE_T:
213 case ICE_PHY_TYPE_LOW_2500BASE_T:
214 case ICE_PHY_TYPE_LOW_5GBASE_T:
215 case ICE_PHY_TYPE_LOW_10GBASE_T:
216 case ICE_PHY_TYPE_LOW_25GBASE_T:
217 return ICE_MEDIA_BASET;
218 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
219 case ICE_PHY_TYPE_LOW_25GBASE_CR:
220 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
221 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
222 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
223 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
224 case ICE_PHY_TYPE_LOW_50GBASE_CP:
225 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
226 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
227 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
228 return ICE_MEDIA_DA;
229 case ICE_PHY_TYPE_LOW_1000BASE_KX:
230 case ICE_PHY_TYPE_LOW_2500BASE_KX:
231 case ICE_PHY_TYPE_LOW_2500BASE_X:
232 case ICE_PHY_TYPE_LOW_5GBASE_KR:
233 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
234 case ICE_PHY_TYPE_LOW_25GBASE_KR:
235 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
236 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
237 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
238 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
239 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
240 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
241 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
242 return ICE_MEDIA_BACKPLANE;
243 }
244 } else {
245 switch (hw_link_info->phy_type_high) {
246 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
247 return ICE_MEDIA_BACKPLANE;
248 }
249 }
250 return ICE_MEDIA_UNKNOWN;
251 }
252
253 /**
254 * ice_aq_get_link_info
255 * @pi: port information structure
256 * @ena_lse: enable/disable LinkStatusEvent reporting
257 * @link: pointer to link status structure - optional
258 * @cd: pointer to command details structure or NULL
259 *
260 * Get Link Status (0x607). Returns the link status of the adapter.
261 */
262 enum ice_status
ice_aq_get_link_info(struct ice_port_info * pi,bool ena_lse,struct ice_link_status * link,struct ice_sq_cd * cd)263 ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
264 struct ice_link_status *link, struct ice_sq_cd *cd)
265 {
266 struct ice_aqc_get_link_status_data link_data = { 0 };
267 struct ice_aqc_get_link_status *resp;
268 struct ice_link_status *li_old, *li;
269 enum ice_media_type *hw_media_type;
270 struct ice_fc_info *hw_fc_info;
271 bool tx_pause, rx_pause;
272 struct ice_aq_desc desc;
273 enum ice_status status;
274 struct ice_hw *hw;
275 u16 cmd_flags;
276
277 if (!pi)
278 return ICE_ERR_PARAM;
279 hw = pi->hw;
280 li_old = &pi->phy.link_info_old;
281 hw_media_type = &pi->phy.media_type;
282 li = &pi->phy.link_info;
283 hw_fc_info = &pi->fc;
284
285 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_status);
286 cmd_flags = (ena_lse) ? ICE_AQ_LSE_ENA : ICE_AQ_LSE_DIS;
287 resp = &desc.params.get_link_status;
288 resp->cmd_flags = cpu_to_le16(cmd_flags);
289 resp->lport_num = pi->lport;
290
291 status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
292
293 if (status)
294 return status;
295
296 /* save off old link status information */
297 *li_old = *li;
298
299 /* update current link status information */
300 li->link_speed = le16_to_cpu(link_data.link_speed);
301 li->phy_type_low = le64_to_cpu(link_data.phy_type_low);
302 li->phy_type_high = le64_to_cpu(link_data.phy_type_high);
303 *hw_media_type = ice_get_media_type(pi);
304 li->link_info = link_data.link_info;
305 li->an_info = link_data.an_info;
306 li->ext_info = link_data.ext_info;
307 li->max_frame_size = le16_to_cpu(link_data.max_frame_size);
308 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK;
309 li->topo_media_conflict = link_data.topo_media_conflict;
310 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M |
311 ICE_AQ_CFG_PACING_TYPE_M);
312
313 /* update fc info */
314 tx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_TX);
315 rx_pause = !!(link_data.an_info & ICE_AQ_LINK_PAUSE_RX);
316 if (tx_pause && rx_pause)
317 hw_fc_info->current_mode = ICE_FC_FULL;
318 else if (tx_pause)
319 hw_fc_info->current_mode = ICE_FC_TX_PAUSE;
320 else if (rx_pause)
321 hw_fc_info->current_mode = ICE_FC_RX_PAUSE;
322 else
323 hw_fc_info->current_mode = ICE_FC_NONE;
324
325 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED));
326
327 ice_debug(hw, ICE_DBG_LINK, "link_speed = 0x%x\n", li->link_speed);
328 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
329 (unsigned long long)li->phy_type_low);
330 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
331 (unsigned long long)li->phy_type_high);
332 ice_debug(hw, ICE_DBG_LINK, "media_type = 0x%x\n", *hw_media_type);
333 ice_debug(hw, ICE_DBG_LINK, "link_info = 0x%x\n", li->link_info);
334 ice_debug(hw, ICE_DBG_LINK, "an_info = 0x%x\n", li->an_info);
335 ice_debug(hw, ICE_DBG_LINK, "ext_info = 0x%x\n", li->ext_info);
336 ice_debug(hw, ICE_DBG_LINK, "lse_ena = 0x%x\n", li->lse_ena);
337 ice_debug(hw, ICE_DBG_LINK, "max_frame = 0x%x\n", li->max_frame_size);
338 ice_debug(hw, ICE_DBG_LINK, "pacing = 0x%x\n", li->pacing);
339
340 /* save link status information */
341 if (link)
342 *link = *li;
343
344 /* flag cleared so calling functions don't call AQ again */
345 pi->phy.get_link_info = false;
346
347 return 0;
348 }
349
350 /**
351 * ice_init_flex_flags
352 * @hw: pointer to the hardware structure
353 * @prof_id: Rx Descriptor Builder profile ID
354 *
355 * Function to initialize Rx flex flags
356 */
ice_init_flex_flags(struct ice_hw * hw,enum ice_rxdid prof_id)357 static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
358 {
359 u8 idx = 0;
360
361 /* Flex-flag fields (0-2) are programmed with FLG64 bits with layout:
362 * flexiflags0[5:0] - TCP flags, is_packet_fragmented, is_packet_UDP_GRE
363 * flexiflags1[3:0] - Not used for flag programming
364 * flexiflags2[7:0] - Tunnel and VLAN types
365 * 2 invalid fields in last index
366 */
367 switch (prof_id) {
368 /* Rx flex flags are currently programmed for the NIC profiles only.
369 * Different flag bit programming configurations can be added per
370 * profile as needed.
371 */
372 case ICE_RXDID_FLEX_NIC:
373 case ICE_RXDID_FLEX_NIC_2:
374 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
375 ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
376 ICE_FLG_FIN, idx++);
377 /* flex flag 1 is not used for flexi-flag programming, skipping
378 * these four FLG64 bits.
379 */
380 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
381 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
382 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
383 ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
384 ICE_FLG_EVLAN_x9100, idx++);
385 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
386 ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
387 ICE_FLG_TNL0, idx++);
388 ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
389 ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
390 break;
391
392 default:
393 ice_debug(hw, ICE_DBG_INIT,
394 "Flag programming for profile ID %d not supported\n",
395 prof_id);
396 }
397 }
398
399 /**
400 * ice_init_flex_flds
401 * @hw: pointer to the hardware structure
402 * @prof_id: Rx Descriptor Builder profile ID
403 *
404 * Function to initialize flex descriptors
405 */
ice_init_flex_flds(struct ice_hw * hw,enum ice_rxdid prof_id)406 static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
407 {
408 enum ice_flex_rx_mdid mdid;
409
410 switch (prof_id) {
411 case ICE_RXDID_FLEX_NIC:
412 case ICE_RXDID_FLEX_NIC_2:
413 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);
414 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);
415 ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);
416
417 mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
418 ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;
419
420 ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
421
422 ice_init_flex_flags(hw, prof_id);
423 break;
424
425 default:
426 ice_debug(hw, ICE_DBG_INIT,
427 "Field init for profile ID %d not supported\n",
428 prof_id);
429 }
430 }
431
432 /**
433 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
434 * @hw: pointer to the HW struct
435 */
ice_init_fltr_mgmt_struct(struct ice_hw * hw)436 static enum ice_status ice_init_fltr_mgmt_struct(struct ice_hw *hw)
437 {
438 struct ice_switch_info *sw;
439
440 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw),
441 sizeof(*hw->switch_info), GFP_KERNEL);
442 sw = hw->switch_info;
443
444 if (!sw)
445 return ICE_ERR_NO_MEMORY;
446
447 INIT_LIST_HEAD(&sw->vsi_list_map_head);
448
449 return ice_init_def_sw_recp(hw);
450 }
451
452 /**
453 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
454 * @hw: pointer to the HW struct
455 */
ice_cleanup_fltr_mgmt_struct(struct ice_hw * hw)456 static void ice_cleanup_fltr_mgmt_struct(struct ice_hw *hw)
457 {
458 struct ice_switch_info *sw = hw->switch_info;
459 struct ice_vsi_list_map_info *v_pos_map;
460 struct ice_vsi_list_map_info *v_tmp_map;
461 struct ice_sw_recipe *recps;
462 u8 i;
463
464 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head,
465 list_entry) {
466 list_del(&v_pos_map->list_entry);
467 devm_kfree(ice_hw_to_dev(hw), v_pos_map);
468 }
469 recps = hw->switch_info->recp_list;
470 for (i = 0; i < ICE_SW_LKUP_LAST; i++) {
471 struct ice_fltr_mgmt_list_entry *lst_itr, *tmp_entry;
472
473 recps[i].root_rid = i;
474 mutex_destroy(&recps[i].filt_rule_lock);
475 list_for_each_entry_safe(lst_itr, tmp_entry,
476 &recps[i].filt_rules, list_entry) {
477 list_del(&lst_itr->list_entry);
478 devm_kfree(ice_hw_to_dev(hw), lst_itr);
479 }
480 }
481 ice_rm_all_sw_replay_rule_info(hw);
482 devm_kfree(ice_hw_to_dev(hw), sw->recp_list);
483 devm_kfree(ice_hw_to_dev(hw), sw);
484 }
485
486 #define ICE_FW_LOG_DESC_SIZE(n) (sizeof(struct ice_aqc_fw_logging_data) + \
487 (((n) - 1) * sizeof(((struct ice_aqc_fw_logging_data *)0)->entry)))
488 #define ICE_FW_LOG_DESC_SIZE_MAX \
489 ICE_FW_LOG_DESC_SIZE(ICE_AQC_FW_LOG_ID_MAX)
490
491 /**
492 * ice_get_fw_log_cfg - get FW logging configuration
493 * @hw: pointer to the HW struct
494 */
ice_get_fw_log_cfg(struct ice_hw * hw)495 static enum ice_status ice_get_fw_log_cfg(struct ice_hw *hw)
496 {
497 struct ice_aqc_fw_logging_data *config;
498 struct ice_aq_desc desc;
499 enum ice_status status;
500 u16 size;
501
502 size = ICE_FW_LOG_DESC_SIZE_MAX;
503 config = devm_kzalloc(ice_hw_to_dev(hw), size, GFP_KERNEL);
504 if (!config)
505 return ICE_ERR_NO_MEMORY;
506
507 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging_info);
508
509 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_BUF);
510 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
511
512 status = ice_aq_send_cmd(hw, &desc, config, size, NULL);
513 if (!status) {
514 u16 i;
515
516 /* Save FW logging information into the HW structure */
517 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
518 u16 v, m, flgs;
519
520 v = le16_to_cpu(config->entry[i]);
521 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
522 flgs = (v & ICE_AQC_FW_LOG_EN_M) >> ICE_AQC_FW_LOG_EN_S;
523
524 if (m < ICE_AQC_FW_LOG_ID_MAX)
525 hw->fw_log.evnts[m].cur = flgs;
526 }
527 }
528
529 devm_kfree(ice_hw_to_dev(hw), config);
530
531 return status;
532 }
533
534 /**
535 * ice_cfg_fw_log - configure FW logging
536 * @hw: pointer to the HW struct
537 * @enable: enable certain FW logging events if true, disable all if false
538 *
539 * This function enables/disables the FW logging via Rx CQ events and a UART
540 * port based on predetermined configurations. FW logging via the Rx CQ can be
541 * enabled/disabled for individual PF's. However, FW logging via the UART can
542 * only be enabled/disabled for all PFs on the same device.
543 *
544 * To enable overall FW logging, the "cq_en" and "uart_en" enable bits in
545 * hw->fw_log need to be set accordingly, e.g. based on user-provided input,
546 * before initializing the device.
547 *
548 * When re/configuring FW logging, callers need to update the "cfg" elements of
549 * the hw->fw_log.evnts array with the desired logging event configurations for
550 * modules of interest. When disabling FW logging completely, the callers can
551 * just pass false in the "enable" parameter. On completion, the function will
552 * update the "cur" element of the hw->fw_log.evnts array with the resulting
553 * logging event configurations of the modules that are being re/configured. FW
554 * logging modules that are not part of a reconfiguration operation retain their
555 * previous states.
556 *
557 * Before resetting the device, it is recommended that the driver disables FW
558 * logging before shutting down the control queue. When disabling FW logging
559 * ("enable" = false), the latest configurations of FW logging events stored in
560 * hw->fw_log.evnts[] are not overridden to allow them to be reconfigured after
561 * a device reset.
562 *
563 * When enabling FW logging to emit log messages via the Rx CQ during the
564 * device's initialization phase, a mechanism alternative to interrupt handlers
565 * needs to be used to extract FW log messages from the Rx CQ periodically and
566 * to prevent the Rx CQ from being full and stalling other types of control
567 * messages from FW to SW. Interrupts are typically disabled during the device's
568 * initialization phase.
569 */
ice_cfg_fw_log(struct ice_hw * hw,bool enable)570 static enum ice_status ice_cfg_fw_log(struct ice_hw *hw, bool enable)
571 {
572 struct ice_aqc_fw_logging_data *data = NULL;
573 struct ice_aqc_fw_logging *cmd;
574 enum ice_status status = 0;
575 u16 i, chgs = 0, len = 0;
576 struct ice_aq_desc desc;
577 u8 actv_evnts = 0;
578 void *buf = NULL;
579
580 if (!hw->fw_log.cq_en && !hw->fw_log.uart_en)
581 return 0;
582
583 /* Disable FW logging only when the control queue is still responsive */
584 if (!enable &&
585 (!hw->fw_log.actv_evnts || !ice_check_sq_alive(hw, &hw->adminq)))
586 return 0;
587
588 /* Get current FW log settings */
589 status = ice_get_fw_log_cfg(hw);
590 if (status)
591 return status;
592
593 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_fw_logging);
594 cmd = &desc.params.fw_logging;
595
596 /* Indicate which controls are valid */
597 if (hw->fw_log.cq_en)
598 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_AQ_VALID;
599
600 if (hw->fw_log.uart_en)
601 cmd->log_ctrl_valid |= ICE_AQC_FW_LOG_UART_VALID;
602
603 if (enable) {
604 /* Fill in an array of entries with FW logging modules and
605 * logging events being reconfigured.
606 */
607 for (i = 0; i < ICE_AQC_FW_LOG_ID_MAX; i++) {
608 u16 val;
609
610 /* Keep track of enabled event types */
611 actv_evnts |= hw->fw_log.evnts[i].cfg;
612
613 if (hw->fw_log.evnts[i].cfg == hw->fw_log.evnts[i].cur)
614 continue;
615
616 if (!data) {
617 data = devm_kzalloc(ice_hw_to_dev(hw),
618 ICE_FW_LOG_DESC_SIZE_MAX,
619 GFP_KERNEL);
620 if (!data)
621 return ICE_ERR_NO_MEMORY;
622 }
623
624 val = i << ICE_AQC_FW_LOG_ID_S;
625 val |= hw->fw_log.evnts[i].cfg << ICE_AQC_FW_LOG_EN_S;
626 data->entry[chgs++] = cpu_to_le16(val);
627 }
628
629 /* Only enable FW logging if at least one module is specified.
630 * If FW logging is currently enabled but all modules are not
631 * enabled to emit log messages, disable FW logging altogether.
632 */
633 if (actv_evnts) {
634 /* Leave if there is effectively no change */
635 if (!chgs)
636 goto out;
637
638 if (hw->fw_log.cq_en)
639 cmd->log_ctrl |= ICE_AQC_FW_LOG_AQ_EN;
640
641 if (hw->fw_log.uart_en)
642 cmd->log_ctrl |= ICE_AQC_FW_LOG_UART_EN;
643
644 buf = data;
645 len = ICE_FW_LOG_DESC_SIZE(chgs);
646 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
647 }
648 }
649
650 status = ice_aq_send_cmd(hw, &desc, buf, len, NULL);
651 if (!status) {
652 /* Update the current configuration to reflect events enabled.
653 * hw->fw_log.cq_en and hw->fw_log.uart_en indicate if the FW
654 * logging mode is enabled for the device. They do not reflect
655 * actual modules being enabled to emit log messages. So, their
656 * values remain unchanged even when all modules are disabled.
657 */
658 u16 cnt = enable ? chgs : (u16)ICE_AQC_FW_LOG_ID_MAX;
659
660 hw->fw_log.actv_evnts = actv_evnts;
661 for (i = 0; i < cnt; i++) {
662 u16 v, m;
663
664 if (!enable) {
665 /* When disabling all FW logging events as part
666 * of device's de-initialization, the original
667 * configurations are retained, and can be used
668 * to reconfigure FW logging later if the device
669 * is re-initialized.
670 */
671 hw->fw_log.evnts[i].cur = 0;
672 continue;
673 }
674
675 v = le16_to_cpu(data->entry[i]);
676 m = (v & ICE_AQC_FW_LOG_ID_M) >> ICE_AQC_FW_LOG_ID_S;
677 hw->fw_log.evnts[m].cur = hw->fw_log.evnts[m].cfg;
678 }
679 }
680
681 out:
682 if (data)
683 devm_kfree(ice_hw_to_dev(hw), data);
684
685 return status;
686 }
687
688 /**
689 * ice_output_fw_log
690 * @hw: pointer to the HW struct
691 * @desc: pointer to the AQ message descriptor
692 * @buf: pointer to the buffer accompanying the AQ message
693 *
694 * Formats a FW Log message and outputs it via the standard driver logs.
695 */
ice_output_fw_log(struct ice_hw * hw,struct ice_aq_desc * desc,void * buf)696 void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf)
697 {
698 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg Start ]\n");
699 ice_debug_array(hw, ICE_DBG_FW_LOG, 16, 1, (u8 *)buf,
700 le16_to_cpu(desc->datalen));
701 ice_debug(hw, ICE_DBG_FW_LOG, "[ FW Log Msg End ]\n");
702 }
703
704 /**
705 * ice_get_itr_intrl_gran - determine int/intrl granularity
706 * @hw: pointer to the HW struct
707 *
708 * Determines the ITR/intrl granularities based on the maximum aggregate
709 * bandwidth according to the device's configuration during power-on.
710 */
ice_get_itr_intrl_gran(struct ice_hw * hw)711 static void ice_get_itr_intrl_gran(struct ice_hw *hw)
712 {
713 u8 max_agg_bw = (rd32(hw, GL_PWR_MODE_CTL) &
714 GL_PWR_MODE_CTL_CAR_MAX_BW_M) >>
715 GL_PWR_MODE_CTL_CAR_MAX_BW_S;
716
717 switch (max_agg_bw) {
718 case ICE_MAX_AGG_BW_200G:
719 case ICE_MAX_AGG_BW_100G:
720 case ICE_MAX_AGG_BW_50G:
721 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25;
722 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25;
723 break;
724 case ICE_MAX_AGG_BW_25G:
725 hw->itr_gran = ICE_ITR_GRAN_MAX_25;
726 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25;
727 break;
728 }
729 }
730
731 /**
732 * ice_get_nvm_version - get cached NVM version data
733 * @hw: pointer to the hardware structure
734 * @oem_ver: 8 bit NVM version
735 * @oem_build: 16 bit NVM build number
736 * @oem_patch: 8 NVM patch number
737 * @ver_hi: high 16 bits of the NVM version
738 * @ver_lo: low 16 bits of the NVM version
739 */
740 void
ice_get_nvm_version(struct ice_hw * hw,u8 * oem_ver,u16 * oem_build,u8 * oem_patch,u8 * ver_hi,u8 * ver_lo)741 ice_get_nvm_version(struct ice_hw *hw, u8 *oem_ver, u16 *oem_build,
742 u8 *oem_patch, u8 *ver_hi, u8 *ver_lo)
743 {
744 struct ice_nvm_info *nvm = &hw->nvm;
745
746 *oem_ver = (u8)((nvm->oem_ver & ICE_OEM_VER_MASK) >> ICE_OEM_VER_SHIFT);
747 *oem_patch = (u8)(nvm->oem_ver & ICE_OEM_VER_PATCH_MASK);
748 *oem_build = (u16)((nvm->oem_ver & ICE_OEM_VER_BUILD_MASK) >>
749 ICE_OEM_VER_BUILD_SHIFT);
750 *ver_hi = (nvm->ver & ICE_NVM_VER_HI_MASK) >> ICE_NVM_VER_HI_SHIFT;
751 *ver_lo = (nvm->ver & ICE_NVM_VER_LO_MASK) >> ICE_NVM_VER_LO_SHIFT;
752 }
753
754 /**
755 * ice_init_hw - main hardware initialization routine
756 * @hw: pointer to the hardware structure
757 */
ice_init_hw(struct ice_hw * hw)758 enum ice_status ice_init_hw(struct ice_hw *hw)
759 {
760 struct ice_aqc_get_phy_caps_data *pcaps;
761 enum ice_status status;
762 u16 mac_buf_len;
763 void *mac_buf;
764
765 /* Set MAC type based on DeviceID */
766 status = ice_set_mac_type(hw);
767 if (status)
768 return status;
769
770 hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) &
771 PF_FUNC_RID_FUNC_NUM_M) >>
772 PF_FUNC_RID_FUNC_NUM_S;
773
774 status = ice_reset(hw, ICE_RESET_PFR);
775 if (status)
776 return status;
777
778 ice_get_itr_intrl_gran(hw);
779
780 status = ice_create_all_ctrlq(hw);
781 if (status)
782 goto err_unroll_cqinit;
783
784 /* Enable FW logging. Not fatal if this fails. */
785 status = ice_cfg_fw_log(hw, true);
786 if (status)
787 ice_debug(hw, ICE_DBG_INIT, "Failed to enable FW logging.\n");
788
789 status = ice_clear_pf_cfg(hw);
790 if (status)
791 goto err_unroll_cqinit;
792
793 ice_clear_pxe_mode(hw);
794
795 status = ice_init_nvm(hw);
796 if (status)
797 goto err_unroll_cqinit;
798
799 status = ice_get_caps(hw);
800 if (status)
801 goto err_unroll_cqinit;
802
803 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw),
804 sizeof(*hw->port_info), GFP_KERNEL);
805 if (!hw->port_info) {
806 status = ICE_ERR_NO_MEMORY;
807 goto err_unroll_cqinit;
808 }
809
810 /* set the back pointer to HW */
811 hw->port_info->hw = hw;
812
813 /* Initialize port_info struct with switch configuration data */
814 status = ice_get_initial_sw_cfg(hw);
815 if (status)
816 goto err_unroll_alloc;
817
818 hw->evb_veb = true;
819
820 /* Query the allocated resources for Tx scheduler */
821 status = ice_sched_query_res_alloc(hw);
822 if (status) {
823 ice_debug(hw, ICE_DBG_SCHED,
824 "Failed to get scheduler allocated resources\n");
825 goto err_unroll_alloc;
826 }
827
828 /* Initialize port_info struct with scheduler data */
829 status = ice_sched_init_port(hw->port_info);
830 if (status)
831 goto err_unroll_sched;
832
833 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
834 if (!pcaps) {
835 status = ICE_ERR_NO_MEMORY;
836 goto err_unroll_sched;
837 }
838
839 /* Initialize port_info struct with PHY capabilities */
840 status = ice_aq_get_phy_caps(hw->port_info, false,
841 ICE_AQC_REPORT_TOPO_CAP, pcaps, NULL);
842 devm_kfree(ice_hw_to_dev(hw), pcaps);
843 if (status)
844 goto err_unroll_sched;
845
846 /* Initialize port_info struct with link information */
847 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL);
848 if (status)
849 goto err_unroll_sched;
850
851 /* need a valid SW entry point to build a Tx tree */
852 if (!hw->sw_entry_point_layer) {
853 ice_debug(hw, ICE_DBG_SCHED, "invalid sw entry point\n");
854 status = ICE_ERR_CFG;
855 goto err_unroll_sched;
856 }
857 INIT_LIST_HEAD(&hw->agg_list);
858
859 status = ice_init_fltr_mgmt_struct(hw);
860 if (status)
861 goto err_unroll_sched;
862
863 ice_dev_onetime_setup(hw);
864
865 /* Get MAC information */
866 /* A single port can report up to two (LAN and WoL) addresses */
867 mac_buf = devm_kcalloc(ice_hw_to_dev(hw), 2,
868 sizeof(struct ice_aqc_manage_mac_read_resp),
869 GFP_KERNEL);
870 mac_buf_len = 2 * sizeof(struct ice_aqc_manage_mac_read_resp);
871
872 if (!mac_buf) {
873 status = ICE_ERR_NO_MEMORY;
874 goto err_unroll_fltr_mgmt_struct;
875 }
876
877 status = ice_aq_manage_mac_read(hw, mac_buf, mac_buf_len, NULL);
878 devm_kfree(ice_hw_to_dev(hw), mac_buf);
879
880 if (status)
881 goto err_unroll_fltr_mgmt_struct;
882
883 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC);
884 ice_init_flex_flds(hw, ICE_RXDID_FLEX_NIC_2);
885 status = ice_init_hw_tbls(hw);
886 if (status)
887 goto err_unroll_fltr_mgmt_struct;
888 return 0;
889
890 err_unroll_fltr_mgmt_struct:
891 ice_cleanup_fltr_mgmt_struct(hw);
892 err_unroll_sched:
893 ice_sched_cleanup_all(hw);
894 err_unroll_alloc:
895 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
896 err_unroll_cqinit:
897 ice_destroy_all_ctrlq(hw);
898 return status;
899 }
900
901 /**
902 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
903 * @hw: pointer to the hardware structure
904 *
905 * This should be called only during nominal operation, not as a result of
906 * ice_init_hw() failing since ice_init_hw() will take care of unrolling
907 * applicable initializations if it fails for any reason.
908 */
ice_deinit_hw(struct ice_hw * hw)909 void ice_deinit_hw(struct ice_hw *hw)
910 {
911 ice_cleanup_fltr_mgmt_struct(hw);
912
913 ice_sched_cleanup_all(hw);
914 ice_sched_clear_agg(hw);
915 ice_free_seg(hw);
916 ice_free_hw_tbls(hw);
917
918 if (hw->port_info) {
919 devm_kfree(ice_hw_to_dev(hw), hw->port_info);
920 hw->port_info = NULL;
921 }
922
923 /* Attempt to disable FW logging before shutting down control queues */
924 ice_cfg_fw_log(hw, false);
925 ice_destroy_all_ctrlq(hw);
926
927 /* Clear VSI contexts if not already cleared */
928 ice_clear_all_vsi_ctx(hw);
929 }
930
931 /**
932 * ice_check_reset - Check to see if a global reset is complete
933 * @hw: pointer to the hardware structure
934 */
ice_check_reset(struct ice_hw * hw)935 enum ice_status ice_check_reset(struct ice_hw *hw)
936 {
937 u32 cnt, reg = 0, grst_delay;
938
939 /* Poll for Device Active state in case a recent CORER, GLOBR,
940 * or EMPR has occurred. The grst delay value is in 100ms units.
941 * Add 1sec for outstanding AQ commands that can take a long time.
942 */
943 grst_delay = ((rd32(hw, GLGEN_RSTCTL) & GLGEN_RSTCTL_GRSTDEL_M) >>
944 GLGEN_RSTCTL_GRSTDEL_S) + 10;
945
946 for (cnt = 0; cnt < grst_delay; cnt++) {
947 mdelay(100);
948 reg = rd32(hw, GLGEN_RSTAT);
949 if (!(reg & GLGEN_RSTAT_DEVSTATE_M))
950 break;
951 }
952
953 if (cnt == grst_delay) {
954 ice_debug(hw, ICE_DBG_INIT,
955 "Global reset polling failed to complete.\n");
956 return ICE_ERR_RESET_FAILED;
957 }
958
959 #define ICE_RESET_DONE_MASK (GLNVM_ULD_CORER_DONE_M | \
960 GLNVM_ULD_GLOBR_DONE_M)
961
962 /* Device is Active; check Global Reset processes are done */
963 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
964 reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;
965 if (reg == ICE_RESET_DONE_MASK) {
966 ice_debug(hw, ICE_DBG_INIT,
967 "Global reset processes done. %d\n", cnt);
968 break;
969 }
970 mdelay(10);
971 }
972
973 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
974 ice_debug(hw, ICE_DBG_INIT,
975 "Wait for Reset Done timed out. GLNVM_ULD = 0x%x\n",
976 reg);
977 return ICE_ERR_RESET_FAILED;
978 }
979
980 return 0;
981 }
982
983 /**
984 * ice_pf_reset - Reset the PF
985 * @hw: pointer to the hardware structure
986 *
987 * If a global reset has been triggered, this function checks
988 * for its completion and then issues the PF reset
989 */
ice_pf_reset(struct ice_hw * hw)990 static enum ice_status ice_pf_reset(struct ice_hw *hw)
991 {
992 u32 cnt, reg;
993
994 /* If at function entry a global reset was already in progress, i.e.
995 * state is not 'device active' or any of the reset done bits are not
996 * set in GLNVM_ULD, there is no need for a PF Reset; poll until the
997 * global reset is done.
998 */
999 if ((rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_DEVSTATE_M) ||
1000 (rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK) ^ ICE_RESET_DONE_MASK) {
1001 /* poll on global reset currently in progress until done */
1002 if (ice_check_reset(hw))
1003 return ICE_ERR_RESET_FAILED;
1004
1005 return 0;
1006 }
1007
1008 /* Reset the PF */
1009 reg = rd32(hw, PFGEN_CTRL);
1010
1011 wr32(hw, PFGEN_CTRL, (reg | PFGEN_CTRL_PFSWR_M));
1012
1013 for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {
1014 reg = rd32(hw, PFGEN_CTRL);
1015 if (!(reg & PFGEN_CTRL_PFSWR_M))
1016 break;
1017
1018 mdelay(1);
1019 }
1020
1021 if (cnt == ICE_PF_RESET_WAIT_COUNT) {
1022 ice_debug(hw, ICE_DBG_INIT,
1023 "PF reset polling failed to complete.\n");
1024 return ICE_ERR_RESET_FAILED;
1025 }
1026
1027 return 0;
1028 }
1029
1030 /**
1031 * ice_reset - Perform different types of reset
1032 * @hw: pointer to the hardware structure
1033 * @req: reset request
1034 *
1035 * This function triggers a reset as specified by the req parameter.
1036 *
1037 * Note:
1038 * If anything other than a PF reset is triggered, PXE mode is restored.
1039 * This has to be cleared using ice_clear_pxe_mode again, once the AQ
1040 * interface has been restored in the rebuild flow.
1041 */
ice_reset(struct ice_hw * hw,enum ice_reset_req req)1042 enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req)
1043 {
1044 u32 val = 0;
1045
1046 switch (req) {
1047 case ICE_RESET_PFR:
1048 return ice_pf_reset(hw);
1049 case ICE_RESET_CORER:
1050 ice_debug(hw, ICE_DBG_INIT, "CoreR requested\n");
1051 val = GLGEN_RTRIG_CORER_M;
1052 break;
1053 case ICE_RESET_GLOBR:
1054 ice_debug(hw, ICE_DBG_INIT, "GlobalR requested\n");
1055 val = GLGEN_RTRIG_GLOBR_M;
1056 break;
1057 default:
1058 return ICE_ERR_PARAM;
1059 }
1060
1061 val |= rd32(hw, GLGEN_RTRIG);
1062 wr32(hw, GLGEN_RTRIG, val);
1063 ice_flush(hw);
1064
1065 /* wait for the FW to be ready */
1066 return ice_check_reset(hw);
1067 }
1068
1069 /**
1070 * ice_copy_rxq_ctx_to_hw
1071 * @hw: pointer to the hardware structure
1072 * @ice_rxq_ctx: pointer to the rxq context
1073 * @rxq_index: the index of the Rx queue
1074 *
1075 * Copies rxq context from dense structure to HW register space
1076 */
1077 static enum ice_status
ice_copy_rxq_ctx_to_hw(struct ice_hw * hw,u8 * ice_rxq_ctx,u32 rxq_index)1078 ice_copy_rxq_ctx_to_hw(struct ice_hw *hw, u8 *ice_rxq_ctx, u32 rxq_index)
1079 {
1080 u8 i;
1081
1082 if (!ice_rxq_ctx)
1083 return ICE_ERR_BAD_PTR;
1084
1085 if (rxq_index > QRX_CTRL_MAX_INDEX)
1086 return ICE_ERR_PARAM;
1087
1088 /* Copy each dword separately to HW */
1089 for (i = 0; i < ICE_RXQ_CTX_SIZE_DWORDS; i++) {
1090 wr32(hw, QRX_CONTEXT(i, rxq_index),
1091 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1092
1093 ice_debug(hw, ICE_DBG_QCTX, "qrxdata[%d]: %08X\n", i,
1094 *((u32 *)(ice_rxq_ctx + (i * sizeof(u32)))));
1095 }
1096
1097 return 0;
1098 }
1099
1100 /* LAN Rx Queue Context */
1101 static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
1102 /* Field Width LSB */
1103 ICE_CTX_STORE(ice_rlan_ctx, head, 13, 0),
1104 ICE_CTX_STORE(ice_rlan_ctx, cpuid, 8, 13),
1105 ICE_CTX_STORE(ice_rlan_ctx, base, 57, 32),
1106 ICE_CTX_STORE(ice_rlan_ctx, qlen, 13, 89),
1107 ICE_CTX_STORE(ice_rlan_ctx, dbuf, 7, 102),
1108 ICE_CTX_STORE(ice_rlan_ctx, hbuf, 5, 109),
1109 ICE_CTX_STORE(ice_rlan_ctx, dtype, 2, 114),
1110 ICE_CTX_STORE(ice_rlan_ctx, dsize, 1, 116),
1111 ICE_CTX_STORE(ice_rlan_ctx, crcstrip, 1, 117),
1112 ICE_CTX_STORE(ice_rlan_ctx, l2tsel, 1, 119),
1113 ICE_CTX_STORE(ice_rlan_ctx, hsplit_0, 4, 120),
1114 ICE_CTX_STORE(ice_rlan_ctx, hsplit_1, 2, 124),
1115 ICE_CTX_STORE(ice_rlan_ctx, showiv, 1, 127),
1116 ICE_CTX_STORE(ice_rlan_ctx, rxmax, 14, 174),
1117 ICE_CTX_STORE(ice_rlan_ctx, tphrdesc_ena, 1, 193),
1118 ICE_CTX_STORE(ice_rlan_ctx, tphwdesc_ena, 1, 194),
1119 ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
1120 ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
1121 ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
1122 ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
1123 { 0 }
1124 };
1125
1126 /**
1127 * ice_write_rxq_ctx
1128 * @hw: pointer to the hardware structure
1129 * @rlan_ctx: pointer to the rxq context
1130 * @rxq_index: the index of the Rx queue
1131 *
1132 * Converts rxq context from sparse to dense structure and then writes
1133 * it to HW register space and enables the hardware to prefetch descriptors
1134 * instead of only fetching them on demand
1135 */
1136 enum ice_status
ice_write_rxq_ctx(struct ice_hw * hw,struct ice_rlan_ctx * rlan_ctx,u32 rxq_index)1137 ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
1138 u32 rxq_index)
1139 {
1140 u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
1141
1142 if (!rlan_ctx)
1143 return ICE_ERR_BAD_PTR;
1144
1145 rlan_ctx->prefena = 1;
1146
1147 ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
1148 return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
1149 }
1150
1151 /* LAN Tx Queue Context */
1152 const struct ice_ctx_ele ice_tlan_ctx_info[] = {
1153 /* Field Width LSB */
1154 ICE_CTX_STORE(ice_tlan_ctx, base, 57, 0),
1155 ICE_CTX_STORE(ice_tlan_ctx, port_num, 3, 57),
1156 ICE_CTX_STORE(ice_tlan_ctx, cgd_num, 5, 60),
1157 ICE_CTX_STORE(ice_tlan_ctx, pf_num, 3, 65),
1158 ICE_CTX_STORE(ice_tlan_ctx, vmvf_num, 10, 68),
1159 ICE_CTX_STORE(ice_tlan_ctx, vmvf_type, 2, 78),
1160 ICE_CTX_STORE(ice_tlan_ctx, src_vsi, 10, 80),
1161 ICE_CTX_STORE(ice_tlan_ctx, tsyn_ena, 1, 90),
1162 ICE_CTX_STORE(ice_tlan_ctx, internal_usage_flag, 1, 91),
1163 ICE_CTX_STORE(ice_tlan_ctx, alt_vlan, 1, 92),
1164 ICE_CTX_STORE(ice_tlan_ctx, cpuid, 8, 93),
1165 ICE_CTX_STORE(ice_tlan_ctx, wb_mode, 1, 101),
1166 ICE_CTX_STORE(ice_tlan_ctx, tphrd_desc, 1, 102),
1167 ICE_CTX_STORE(ice_tlan_ctx, tphrd, 1, 103),
1168 ICE_CTX_STORE(ice_tlan_ctx, tphwr_desc, 1, 104),
1169 ICE_CTX_STORE(ice_tlan_ctx, cmpq_id, 9, 105),
1170 ICE_CTX_STORE(ice_tlan_ctx, qnum_in_func, 14, 114),
1171 ICE_CTX_STORE(ice_tlan_ctx, itr_notification_mode, 1, 128),
1172 ICE_CTX_STORE(ice_tlan_ctx, adjust_prof_id, 6, 129),
1173 ICE_CTX_STORE(ice_tlan_ctx, qlen, 13, 135),
1174 ICE_CTX_STORE(ice_tlan_ctx, quanta_prof_idx, 4, 148),
1175 ICE_CTX_STORE(ice_tlan_ctx, tso_ena, 1, 152),
1176 ICE_CTX_STORE(ice_tlan_ctx, tso_qnum, 11, 153),
1177 ICE_CTX_STORE(ice_tlan_ctx, legacy_int, 1, 164),
1178 ICE_CTX_STORE(ice_tlan_ctx, drop_ena, 1, 165),
1179 ICE_CTX_STORE(ice_tlan_ctx, cache_prof_idx, 2, 166),
1180 ICE_CTX_STORE(ice_tlan_ctx, pkt_shaper_prof_idx, 3, 168),
1181 ICE_CTX_STORE(ice_tlan_ctx, int_q_state, 122, 171),
1182 { 0 }
1183 };
1184
1185 /**
1186 * ice_debug_cq
1187 * @hw: pointer to the hardware structure
1188 * @mask: debug mask
1189 * @desc: pointer to control queue descriptor
1190 * @buf: pointer to command buffer
1191 * @buf_len: max length of buf
1192 *
1193 * Dumps debug log about control command with descriptor contents.
1194 */
1195 void
ice_debug_cq(struct ice_hw * hw,u32 __maybe_unused mask,void * desc,void * buf,u16 buf_len)1196 ice_debug_cq(struct ice_hw *hw, u32 __maybe_unused mask, void *desc, void *buf,
1197 u16 buf_len)
1198 {
1199 struct ice_aq_desc *cq_desc = (struct ice_aq_desc *)desc;
1200 u16 len;
1201
1202 #ifndef CONFIG_DYNAMIC_DEBUG
1203 if (!(mask & hw->debug_mask))
1204 return;
1205 #endif
1206
1207 if (!desc)
1208 return;
1209
1210 len = le16_to_cpu(cq_desc->datalen);
1211
1212 ice_debug(hw, mask,
1213 "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
1214 le16_to_cpu(cq_desc->opcode),
1215 le16_to_cpu(cq_desc->flags),
1216 le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
1217 ice_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
1218 le32_to_cpu(cq_desc->cookie_high),
1219 le32_to_cpu(cq_desc->cookie_low));
1220 ice_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
1221 le32_to_cpu(cq_desc->params.generic.param0),
1222 le32_to_cpu(cq_desc->params.generic.param1));
1223 ice_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
1224 le32_to_cpu(cq_desc->params.generic.addr_high),
1225 le32_to_cpu(cq_desc->params.generic.addr_low));
1226 if (buf && cq_desc->datalen != 0) {
1227 ice_debug(hw, mask, "Buffer:\n");
1228 if (buf_len < len)
1229 len = buf_len;
1230
1231 ice_debug_array(hw, mask, 16, 1, (u8 *)buf, len);
1232 }
1233 }
1234
1235 /* FW Admin Queue command wrappers */
1236
1237 /* Software lock/mutex that is meant to be held while the Global Config Lock
1238 * in firmware is acquired by the software to prevent most (but not all) types
1239 * of AQ commands from being sent to FW
1240 */
1241 DEFINE_MUTEX(ice_global_cfg_lock_sw);
1242
1243 /**
1244 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1245 * @hw: pointer to the HW struct
1246 * @desc: descriptor describing the command
1247 * @buf: buffer to use for indirect commands (NULL for direct commands)
1248 * @buf_size: size of buffer for indirect commands (0 for direct commands)
1249 * @cd: pointer to command details structure
1250 *
1251 * Helper function to send FW Admin Queue commands to the FW Admin Queue.
1252 */
1253 enum ice_status
ice_aq_send_cmd(struct ice_hw * hw,struct ice_aq_desc * desc,void * buf,u16 buf_size,struct ice_sq_cd * cd)1254 ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf,
1255 u16 buf_size, struct ice_sq_cd *cd)
1256 {
1257 struct ice_aqc_req_res *cmd = &desc->params.res_owner;
1258 bool lock_acquired = false;
1259 enum ice_status status;
1260
1261 /* When a package download is in process (i.e. when the firmware's
1262 * Global Configuration Lock resource is held), only the Download
1263 * Package, Get Version, Get Package Info List and Release Resource
1264 * (with resource ID set to Global Config Lock) AdminQ commands are
1265 * allowed; all others must block until the package download completes
1266 * and the Global Config Lock is released. See also
1267 * ice_acquire_global_cfg_lock().
1268 */
1269 switch (le16_to_cpu(desc->opcode)) {
1270 case ice_aqc_opc_download_pkg:
1271 case ice_aqc_opc_get_pkg_info_list:
1272 case ice_aqc_opc_get_ver:
1273 break;
1274 case ice_aqc_opc_release_res:
1275 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK)
1276 break;
1277 /* fall-through */
1278 default:
1279 mutex_lock(&ice_global_cfg_lock_sw);
1280 lock_acquired = true;
1281 break;
1282 }
1283
1284 status = ice_sq_send_cmd(hw, &hw->adminq, desc, buf, buf_size, cd);
1285 if (lock_acquired)
1286 mutex_unlock(&ice_global_cfg_lock_sw);
1287
1288 return status;
1289 }
1290
1291 /**
1292 * ice_aq_get_fw_ver
1293 * @hw: pointer to the HW struct
1294 * @cd: pointer to command details structure or NULL
1295 *
1296 * Get the firmware version (0x0001) from the admin queue commands
1297 */
ice_aq_get_fw_ver(struct ice_hw * hw,struct ice_sq_cd * cd)1298 enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd)
1299 {
1300 struct ice_aqc_get_ver *resp;
1301 struct ice_aq_desc desc;
1302 enum ice_status status;
1303
1304 resp = &desc.params.get_ver;
1305
1306 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_ver);
1307
1308 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1309
1310 if (!status) {
1311 hw->fw_branch = resp->fw_branch;
1312 hw->fw_maj_ver = resp->fw_major;
1313 hw->fw_min_ver = resp->fw_minor;
1314 hw->fw_patch = resp->fw_patch;
1315 hw->fw_build = le32_to_cpu(resp->fw_build);
1316 hw->api_branch = resp->api_branch;
1317 hw->api_maj_ver = resp->api_major;
1318 hw->api_min_ver = resp->api_minor;
1319 hw->api_patch = resp->api_patch;
1320 }
1321
1322 return status;
1323 }
1324
1325 /**
1326 * ice_aq_send_driver_ver
1327 * @hw: pointer to the HW struct
1328 * @dv: driver's major, minor version
1329 * @cd: pointer to command details structure or NULL
1330 *
1331 * Send the driver version (0x0002) to the firmware
1332 */
1333 enum ice_status
ice_aq_send_driver_ver(struct ice_hw * hw,struct ice_driver_ver * dv,struct ice_sq_cd * cd)1334 ice_aq_send_driver_ver(struct ice_hw *hw, struct ice_driver_ver *dv,
1335 struct ice_sq_cd *cd)
1336 {
1337 struct ice_aqc_driver_ver *cmd;
1338 struct ice_aq_desc desc;
1339 u16 len;
1340
1341 cmd = &desc.params.driver_ver;
1342
1343 if (!dv)
1344 return ICE_ERR_PARAM;
1345
1346 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_ver);
1347
1348 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
1349 cmd->major_ver = dv->major_ver;
1350 cmd->minor_ver = dv->minor_ver;
1351 cmd->build_ver = dv->build_ver;
1352 cmd->subbuild_ver = dv->subbuild_ver;
1353
1354 len = 0;
1355 while (len < sizeof(dv->driver_string) &&
1356 isascii(dv->driver_string[len]) && dv->driver_string[len])
1357 len++;
1358
1359 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd);
1360 }
1361
1362 /**
1363 * ice_aq_q_shutdown
1364 * @hw: pointer to the HW struct
1365 * @unloading: is the driver unloading itself
1366 *
1367 * Tell the Firmware that we're shutting down the AdminQ and whether
1368 * or not the driver is unloading as well (0x0003).
1369 */
ice_aq_q_shutdown(struct ice_hw * hw,bool unloading)1370 enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading)
1371 {
1372 struct ice_aqc_q_shutdown *cmd;
1373 struct ice_aq_desc desc;
1374
1375 cmd = &desc.params.q_shutdown;
1376
1377 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_q_shutdown);
1378
1379 if (unloading)
1380 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING;
1381
1382 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1383 }
1384
1385 /**
1386 * ice_aq_req_res
1387 * @hw: pointer to the HW struct
1388 * @res: resource ID
1389 * @access: access type
1390 * @sdp_number: resource number
1391 * @timeout: the maximum time in ms that the driver may hold the resource
1392 * @cd: pointer to command details structure or NULL
1393 *
1394 * Requests common resource using the admin queue commands (0x0008).
1395 * When attempting to acquire the Global Config Lock, the driver can
1396 * learn of three states:
1397 * 1) ICE_SUCCESS - acquired lock, and can perform download package
1398 * 2) ICE_ERR_AQ_ERROR - did not get lock, driver should fail to load
1399 * 3) ICE_ERR_AQ_NO_WORK - did not get lock, but another driver has
1400 * successfully downloaded the package; the driver does
1401 * not have to download the package and can continue
1402 * loading
1403 *
1404 * Note that if the caller is in an acquire lock, perform action, release lock
1405 * phase of operation, it is possible that the FW may detect a timeout and issue
1406 * a CORER. In this case, the driver will receive a CORER interrupt and will
1407 * have to determine its cause. The calling thread that is handling this flow
1408 * will likely get an error propagated back to it indicating the Download
1409 * Package, Update Package or the Release Resource AQ commands timed out.
1410 */
1411 static enum ice_status
ice_aq_req_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u8 sdp_number,u32 * timeout,struct ice_sq_cd * cd)1412 ice_aq_req_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1413 enum ice_aq_res_access_type access, u8 sdp_number, u32 *timeout,
1414 struct ice_sq_cd *cd)
1415 {
1416 struct ice_aqc_req_res *cmd_resp;
1417 struct ice_aq_desc desc;
1418 enum ice_status status;
1419
1420 cmd_resp = &desc.params.res_owner;
1421
1422 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_req_res);
1423
1424 cmd_resp->res_id = cpu_to_le16(res);
1425 cmd_resp->access_type = cpu_to_le16(access);
1426 cmd_resp->res_number = cpu_to_le32(sdp_number);
1427 cmd_resp->timeout = cpu_to_le32(*timeout);
1428 *timeout = 0;
1429
1430 status = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1431
1432 /* The completion specifies the maximum time in ms that the driver
1433 * may hold the resource in the Timeout field.
1434 */
1435
1436 /* Global config lock response utilizes an additional status field.
1437 *
1438 * If the Global config lock resource is held by some other driver, the
1439 * command completes with ICE_AQ_RES_GLBL_IN_PROG in the status field
1440 * and the timeout field indicates the maximum time the current owner
1441 * of the resource has to free it.
1442 */
1443 if (res == ICE_GLOBAL_CFG_LOCK_RES_ID) {
1444 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) {
1445 *timeout = le32_to_cpu(cmd_resp->timeout);
1446 return 0;
1447 } else if (le16_to_cpu(cmd_resp->status) ==
1448 ICE_AQ_RES_GLBL_IN_PROG) {
1449 *timeout = le32_to_cpu(cmd_resp->timeout);
1450 return ICE_ERR_AQ_ERROR;
1451 } else if (le16_to_cpu(cmd_resp->status) ==
1452 ICE_AQ_RES_GLBL_DONE) {
1453 return ICE_ERR_AQ_NO_WORK;
1454 }
1455
1456 /* invalid FW response, force a timeout immediately */
1457 *timeout = 0;
1458 return ICE_ERR_AQ_ERROR;
1459 }
1460
1461 /* If the resource is held by some other driver, the command completes
1462 * with a busy return value and the timeout field indicates the maximum
1463 * time the current owner of the resource has to free it.
1464 */
1465 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY)
1466 *timeout = le32_to_cpu(cmd_resp->timeout);
1467
1468 return status;
1469 }
1470
1471 /**
1472 * ice_aq_release_res
1473 * @hw: pointer to the HW struct
1474 * @res: resource ID
1475 * @sdp_number: resource number
1476 * @cd: pointer to command details structure or NULL
1477 *
1478 * release common resource using the admin queue commands (0x0009)
1479 */
1480 static enum ice_status
ice_aq_release_res(struct ice_hw * hw,enum ice_aq_res_ids res,u8 sdp_number,struct ice_sq_cd * cd)1481 ice_aq_release_res(struct ice_hw *hw, enum ice_aq_res_ids res, u8 sdp_number,
1482 struct ice_sq_cd *cd)
1483 {
1484 struct ice_aqc_req_res *cmd;
1485 struct ice_aq_desc desc;
1486
1487 cmd = &desc.params.res_owner;
1488
1489 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_release_res);
1490
1491 cmd->res_id = cpu_to_le16(res);
1492 cmd->res_number = cpu_to_le32(sdp_number);
1493
1494 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1495 }
1496
1497 /**
1498 * ice_acquire_res
1499 * @hw: pointer to the HW structure
1500 * @res: resource ID
1501 * @access: access type (read or write)
1502 * @timeout: timeout in milliseconds
1503 *
1504 * This function will attempt to acquire the ownership of a resource.
1505 */
1506 enum ice_status
ice_acquire_res(struct ice_hw * hw,enum ice_aq_res_ids res,enum ice_aq_res_access_type access,u32 timeout)1507 ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
1508 enum ice_aq_res_access_type access, u32 timeout)
1509 {
1510 #define ICE_RES_POLLING_DELAY_MS 10
1511 u32 delay = ICE_RES_POLLING_DELAY_MS;
1512 u32 time_left = timeout;
1513 enum ice_status status;
1514
1515 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1516
1517 /* A return code of ICE_ERR_AQ_NO_WORK means that another driver has
1518 * previously acquired the resource and performed any necessary updates;
1519 * in this case the caller does not obtain the resource and has no
1520 * further work to do.
1521 */
1522 if (status == ICE_ERR_AQ_NO_WORK)
1523 goto ice_acquire_res_exit;
1524
1525 if (status)
1526 ice_debug(hw, ICE_DBG_RES,
1527 "resource %d acquire type %d failed.\n", res, access);
1528
1529 /* If necessary, poll until the current lock owner timeouts */
1530 timeout = time_left;
1531 while (status && timeout && time_left) {
1532 mdelay(delay);
1533 timeout = (timeout > delay) ? timeout - delay : 0;
1534 status = ice_aq_req_res(hw, res, access, 0, &time_left, NULL);
1535
1536 if (status == ICE_ERR_AQ_NO_WORK)
1537 /* lock free, but no work to do */
1538 break;
1539
1540 if (!status)
1541 /* lock acquired */
1542 break;
1543 }
1544 if (status && status != ICE_ERR_AQ_NO_WORK)
1545 ice_debug(hw, ICE_DBG_RES, "resource acquire timed out.\n");
1546
1547 ice_acquire_res_exit:
1548 if (status == ICE_ERR_AQ_NO_WORK) {
1549 if (access == ICE_RES_WRITE)
1550 ice_debug(hw, ICE_DBG_RES,
1551 "resource indicates no work to do.\n");
1552 else
1553 ice_debug(hw, ICE_DBG_RES,
1554 "Warning: ICE_ERR_AQ_NO_WORK not expected\n");
1555 }
1556 return status;
1557 }
1558
1559 /**
1560 * ice_release_res
1561 * @hw: pointer to the HW structure
1562 * @res: resource ID
1563 *
1564 * This function will release a resource using the proper Admin Command.
1565 */
ice_release_res(struct ice_hw * hw,enum ice_aq_res_ids res)1566 void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res)
1567 {
1568 enum ice_status status;
1569 u32 total_delay = 0;
1570
1571 status = ice_aq_release_res(hw, res, 0, NULL);
1572
1573 /* there are some rare cases when trying to release the resource
1574 * results in an admin queue timeout, so handle them correctly
1575 */
1576 while ((status == ICE_ERR_AQ_TIMEOUT) &&
1577 (total_delay < hw->adminq.sq_cmd_timeout)) {
1578 mdelay(1);
1579 status = ice_aq_release_res(hw, res, 0, NULL);
1580 total_delay++;
1581 }
1582 }
1583
1584 /**
1585 * ice_get_num_per_func - determine number of resources per PF
1586 * @hw: pointer to the HW structure
1587 * @max: value to be evenly split between each PF
1588 *
1589 * Determine the number of valid functions by going through the bitmap returned
1590 * from parsing capabilities and use this to calculate the number of resources
1591 * per PF based on the max value passed in.
1592 */
ice_get_num_per_func(struct ice_hw * hw,u32 max)1593 static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)
1594 {
1595 u8 funcs;
1596
1597 #define ICE_CAPS_VALID_FUNCS_M 0xFF
1598 funcs = hweight8(hw->dev_caps.common_cap.valid_functions &
1599 ICE_CAPS_VALID_FUNCS_M);
1600
1601 if (!funcs)
1602 return 0;
1603
1604 return max / funcs;
1605 }
1606
1607 /**
1608 * ice_parse_caps - parse function/device capabilities
1609 * @hw: pointer to the HW struct
1610 * @buf: pointer to a buffer containing function/device capability records
1611 * @cap_count: number of capability records in the list
1612 * @opc: type of capabilities list to parse
1613 *
1614 * Helper function to parse function(0x000a)/device(0x000b) capabilities list.
1615 */
1616 static void
ice_parse_caps(struct ice_hw * hw,void * buf,u32 cap_count,enum ice_adminq_opc opc)1617 ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,
1618 enum ice_adminq_opc opc)
1619 {
1620 struct ice_aqc_list_caps_elem *cap_resp;
1621 struct ice_hw_func_caps *func_p = NULL;
1622 struct ice_hw_dev_caps *dev_p = NULL;
1623 struct ice_hw_common_caps *caps;
1624 char const *prefix;
1625 u32 i;
1626
1627 if (!buf)
1628 return;
1629
1630 cap_resp = (struct ice_aqc_list_caps_elem *)buf;
1631
1632 if (opc == ice_aqc_opc_list_dev_caps) {
1633 dev_p = &hw->dev_caps;
1634 caps = &dev_p->common_cap;
1635 prefix = "dev cap";
1636 } else if (opc == ice_aqc_opc_list_func_caps) {
1637 func_p = &hw->func_caps;
1638 caps = &func_p->common_cap;
1639 prefix = "func cap";
1640 } else {
1641 ice_debug(hw, ICE_DBG_INIT, "wrong opcode\n");
1642 return;
1643 }
1644
1645 for (i = 0; caps && i < cap_count; i++, cap_resp++) {
1646 u32 logical_id = le32_to_cpu(cap_resp->logical_id);
1647 u32 phys_id = le32_to_cpu(cap_resp->phys_id);
1648 u32 number = le32_to_cpu(cap_resp->number);
1649 u16 cap = le16_to_cpu(cap_resp->cap);
1650
1651 switch (cap) {
1652 case ICE_AQC_CAPS_VALID_FUNCTIONS:
1653 caps->valid_functions = number;
1654 ice_debug(hw, ICE_DBG_INIT,
1655 "%s: valid_functions (bitmap) = %d\n", prefix,
1656 caps->valid_functions);
1657 break;
1658 case ICE_AQC_CAPS_SRIOV:
1659 caps->sr_iov_1_1 = (number == 1);
1660 ice_debug(hw, ICE_DBG_INIT,
1661 "%s: sr_iov_1_1 = %d\n", prefix,
1662 caps->sr_iov_1_1);
1663 break;
1664 case ICE_AQC_CAPS_VF:
1665 if (dev_p) {
1666 dev_p->num_vfs_exposed = number;
1667 ice_debug(hw, ICE_DBG_INIT,
1668 "%s: num_vfs_exposed = %d\n", prefix,
1669 dev_p->num_vfs_exposed);
1670 } else if (func_p) {
1671 func_p->num_allocd_vfs = number;
1672 func_p->vf_base_id = logical_id;
1673 ice_debug(hw, ICE_DBG_INIT,
1674 "%s: num_allocd_vfs = %d\n", prefix,
1675 func_p->num_allocd_vfs);
1676 ice_debug(hw, ICE_DBG_INIT,
1677 "%s: vf_base_id = %d\n", prefix,
1678 func_p->vf_base_id);
1679 }
1680 break;
1681 case ICE_AQC_CAPS_VSI:
1682 if (dev_p) {
1683 dev_p->num_vsi_allocd_to_host = number;
1684 ice_debug(hw, ICE_DBG_INIT,
1685 "%s: num_vsi_allocd_to_host = %d\n",
1686 prefix,
1687 dev_p->num_vsi_allocd_to_host);
1688 } else if (func_p) {
1689 func_p->guar_num_vsi =
1690 ice_get_num_per_func(hw, ICE_MAX_VSI);
1691 ice_debug(hw, ICE_DBG_INIT,
1692 "%s: guar_num_vsi (fw) = %d\n",
1693 prefix, number);
1694 ice_debug(hw, ICE_DBG_INIT,
1695 "%s: guar_num_vsi = %d\n",
1696 prefix, func_p->guar_num_vsi);
1697 }
1698 break;
1699 case ICE_AQC_CAPS_DCB:
1700 caps->dcb = (number == 1);
1701 caps->active_tc_bitmap = logical_id;
1702 caps->maxtc = phys_id;
1703 ice_debug(hw, ICE_DBG_INIT,
1704 "%s: dcb = %d\n", prefix, caps->dcb);
1705 ice_debug(hw, ICE_DBG_INIT,
1706 "%s: active_tc_bitmap = %d\n", prefix,
1707 caps->active_tc_bitmap);
1708 ice_debug(hw, ICE_DBG_INIT,
1709 "%s: maxtc = %d\n", prefix, caps->maxtc);
1710 break;
1711 case ICE_AQC_CAPS_RSS:
1712 caps->rss_table_size = number;
1713 caps->rss_table_entry_width = logical_id;
1714 ice_debug(hw, ICE_DBG_INIT,
1715 "%s: rss_table_size = %d\n", prefix,
1716 caps->rss_table_size);
1717 ice_debug(hw, ICE_DBG_INIT,
1718 "%s: rss_table_entry_width = %d\n", prefix,
1719 caps->rss_table_entry_width);
1720 break;
1721 case ICE_AQC_CAPS_RXQS:
1722 caps->num_rxq = number;
1723 caps->rxq_first_id = phys_id;
1724 ice_debug(hw, ICE_DBG_INIT,
1725 "%s: num_rxq = %d\n", prefix,
1726 caps->num_rxq);
1727 ice_debug(hw, ICE_DBG_INIT,
1728 "%s: rxq_first_id = %d\n", prefix,
1729 caps->rxq_first_id);
1730 break;
1731 case ICE_AQC_CAPS_TXQS:
1732 caps->num_txq = number;
1733 caps->txq_first_id = phys_id;
1734 ice_debug(hw, ICE_DBG_INIT,
1735 "%s: num_txq = %d\n", prefix,
1736 caps->num_txq);
1737 ice_debug(hw, ICE_DBG_INIT,
1738 "%s: txq_first_id = %d\n", prefix,
1739 caps->txq_first_id);
1740 break;
1741 case ICE_AQC_CAPS_MSIX:
1742 caps->num_msix_vectors = number;
1743 caps->msix_vector_first_id = phys_id;
1744 ice_debug(hw, ICE_DBG_INIT,
1745 "%s: num_msix_vectors = %d\n", prefix,
1746 caps->num_msix_vectors);
1747 ice_debug(hw, ICE_DBG_INIT,
1748 "%s: msix_vector_first_id = %d\n", prefix,
1749 caps->msix_vector_first_id);
1750 break;
1751 case ICE_AQC_CAPS_MAX_MTU:
1752 caps->max_mtu = number;
1753 ice_debug(hw, ICE_DBG_INIT, "%s: max_mtu = %d\n",
1754 prefix, caps->max_mtu);
1755 break;
1756 default:
1757 ice_debug(hw, ICE_DBG_INIT,
1758 "%s: unknown capability[%d]: 0x%x\n", prefix,
1759 i, cap);
1760 break;
1761 }
1762 }
1763 }
1764
1765 /**
1766 * ice_aq_discover_caps - query function/device capabilities
1767 * @hw: pointer to the HW struct
1768 * @buf: a virtual buffer to hold the capabilities
1769 * @buf_size: Size of the virtual buffer
1770 * @cap_count: cap count needed if AQ err==ENOMEM
1771 * @opc: capabilities type to discover - pass in the command opcode
1772 * @cd: pointer to command details structure or NULL
1773 *
1774 * Get the function(0x000a)/device(0x000b) capabilities description from
1775 * the firmware.
1776 */
1777 static enum ice_status
ice_aq_discover_caps(struct ice_hw * hw,void * buf,u16 buf_size,u32 * cap_count,enum ice_adminq_opc opc,struct ice_sq_cd * cd)1778 ice_aq_discover_caps(struct ice_hw *hw, void *buf, u16 buf_size, u32 *cap_count,
1779 enum ice_adminq_opc opc, struct ice_sq_cd *cd)
1780 {
1781 struct ice_aqc_list_caps *cmd;
1782 struct ice_aq_desc desc;
1783 enum ice_status status;
1784
1785 cmd = &desc.params.get_cap;
1786
1787 if (opc != ice_aqc_opc_list_func_caps &&
1788 opc != ice_aqc_opc_list_dev_caps)
1789 return ICE_ERR_PARAM;
1790
1791 ice_fill_dflt_direct_cmd_desc(&desc, opc);
1792
1793 status = ice_aq_send_cmd(hw, &desc, buf, buf_size, cd);
1794 if (!status)
1795 ice_parse_caps(hw, buf, le32_to_cpu(cmd->count), opc);
1796 else if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOMEM)
1797 *cap_count = le32_to_cpu(cmd->count);
1798 return status;
1799 }
1800
1801 /**
1802 * ice_discover_caps - get info about the HW
1803 * @hw: pointer to the hardware structure
1804 * @opc: capabilities type to discover - pass in the command opcode
1805 */
1806 static enum ice_status
ice_discover_caps(struct ice_hw * hw,enum ice_adminq_opc opc)1807 ice_discover_caps(struct ice_hw *hw, enum ice_adminq_opc opc)
1808 {
1809 enum ice_status status;
1810 u32 cap_count;
1811 u16 cbuf_len;
1812 u8 retries;
1813
1814 /* The driver doesn't know how many capabilities the device will return
1815 * so the buffer size required isn't known ahead of time. The driver
1816 * starts with cbuf_len and if this turns out to be insufficient, the
1817 * device returns ICE_AQ_RC_ENOMEM and also the cap_count it needs.
1818 * The driver then allocates the buffer based on the count and retries
1819 * the operation. So it follows that the retry count is 2.
1820 */
1821 #define ICE_GET_CAP_BUF_COUNT 40
1822 #define ICE_GET_CAP_RETRY_COUNT 2
1823
1824 cap_count = ICE_GET_CAP_BUF_COUNT;
1825 retries = ICE_GET_CAP_RETRY_COUNT;
1826
1827 do {
1828 void *cbuf;
1829
1830 cbuf_len = (u16)(cap_count *
1831 sizeof(struct ice_aqc_list_caps_elem));
1832 cbuf = devm_kzalloc(ice_hw_to_dev(hw), cbuf_len, GFP_KERNEL);
1833 if (!cbuf)
1834 return ICE_ERR_NO_MEMORY;
1835
1836 status = ice_aq_discover_caps(hw, cbuf, cbuf_len, &cap_count,
1837 opc, NULL);
1838 devm_kfree(ice_hw_to_dev(hw), cbuf);
1839
1840 if (!status || hw->adminq.sq_last_status != ICE_AQ_RC_ENOMEM)
1841 break;
1842
1843 /* If ENOMEM is returned, try again with bigger buffer */
1844 } while (--retries);
1845
1846 return status;
1847 }
1848
1849 /**
1850 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
1851 * @hw: pointer to the hardware structure
1852 */
ice_set_safe_mode_caps(struct ice_hw * hw)1853 void ice_set_safe_mode_caps(struct ice_hw *hw)
1854 {
1855 struct ice_hw_func_caps *func_caps = &hw->func_caps;
1856 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps;
1857 u32 valid_func, rxq_first_id, txq_first_id;
1858 u32 msix_vector_first_id, max_mtu;
1859 u32 num_func = 0;
1860 u8 i;
1861
1862 /* cache some func_caps values that should be restored after memset */
1863 valid_func = func_caps->common_cap.valid_functions;
1864 txq_first_id = func_caps->common_cap.txq_first_id;
1865 rxq_first_id = func_caps->common_cap.rxq_first_id;
1866 msix_vector_first_id = func_caps->common_cap.msix_vector_first_id;
1867 max_mtu = func_caps->common_cap.max_mtu;
1868
1869 /* unset func capabilities */
1870 memset(func_caps, 0, sizeof(*func_caps));
1871
1872 /* restore cached values */
1873 func_caps->common_cap.valid_functions = valid_func;
1874 func_caps->common_cap.txq_first_id = txq_first_id;
1875 func_caps->common_cap.rxq_first_id = rxq_first_id;
1876 func_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
1877 func_caps->common_cap.max_mtu = max_mtu;
1878
1879 /* one Tx and one Rx queue in safe mode */
1880 func_caps->common_cap.num_rxq = 1;
1881 func_caps->common_cap.num_txq = 1;
1882
1883 /* two MSIX vectors, one for traffic and one for misc causes */
1884 func_caps->common_cap.num_msix_vectors = 2;
1885 func_caps->guar_num_vsi = 1;
1886
1887 /* cache some dev_caps values that should be restored after memset */
1888 valid_func = dev_caps->common_cap.valid_functions;
1889 txq_first_id = dev_caps->common_cap.txq_first_id;
1890 rxq_first_id = dev_caps->common_cap.rxq_first_id;
1891 msix_vector_first_id = dev_caps->common_cap.msix_vector_first_id;
1892 max_mtu = dev_caps->common_cap.max_mtu;
1893
1894 /* unset dev capabilities */
1895 memset(dev_caps, 0, sizeof(*dev_caps));
1896
1897 /* restore cached values */
1898 dev_caps->common_cap.valid_functions = valid_func;
1899 dev_caps->common_cap.txq_first_id = txq_first_id;
1900 dev_caps->common_cap.rxq_first_id = rxq_first_id;
1901 dev_caps->common_cap.msix_vector_first_id = msix_vector_first_id;
1902 dev_caps->common_cap.max_mtu = max_mtu;
1903
1904 /* valid_func is a bitmap. get number of functions */
1905 #define ICE_MAX_FUNCS 8
1906 for (i = 0; i < ICE_MAX_FUNCS; i++)
1907 if (valid_func & BIT(i))
1908 num_func++;
1909
1910 /* one Tx and one Rx queue per function in safe mode */
1911 dev_caps->common_cap.num_rxq = num_func;
1912 dev_caps->common_cap.num_txq = num_func;
1913
1914 /* two MSIX vectors per function */
1915 dev_caps->common_cap.num_msix_vectors = 2 * num_func;
1916 }
1917
1918 /**
1919 * ice_get_caps - get info about the HW
1920 * @hw: pointer to the hardware structure
1921 */
ice_get_caps(struct ice_hw * hw)1922 enum ice_status ice_get_caps(struct ice_hw *hw)
1923 {
1924 enum ice_status status;
1925
1926 status = ice_discover_caps(hw, ice_aqc_opc_list_dev_caps);
1927 if (!status)
1928 status = ice_discover_caps(hw, ice_aqc_opc_list_func_caps);
1929
1930 return status;
1931 }
1932
1933 /**
1934 * ice_aq_manage_mac_write - manage MAC address write command
1935 * @hw: pointer to the HW struct
1936 * @mac_addr: MAC address to be written as LAA/LAA+WoL/Port address
1937 * @flags: flags to control write behavior
1938 * @cd: pointer to command details structure or NULL
1939 *
1940 * This function is used to write MAC address to the NVM (0x0108).
1941 */
1942 enum ice_status
ice_aq_manage_mac_write(struct ice_hw * hw,const u8 * mac_addr,u8 flags,struct ice_sq_cd * cd)1943 ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
1944 struct ice_sq_cd *cd)
1945 {
1946 struct ice_aqc_manage_mac_write *cmd;
1947 struct ice_aq_desc desc;
1948
1949 cmd = &desc.params.mac_write;
1950 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_manage_mac_write);
1951
1952 cmd->flags = flags;
1953
1954 /* Prep values for flags, sah, sal */
1955 cmd->sah = htons(*((const u16 *)mac_addr));
1956 cmd->sal = htonl(*((const u32 *)(mac_addr + 2)));
1957
1958 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
1959 }
1960
1961 /**
1962 * ice_aq_clear_pxe_mode
1963 * @hw: pointer to the HW struct
1964 *
1965 * Tell the firmware that the driver is taking over from PXE (0x0110).
1966 */
ice_aq_clear_pxe_mode(struct ice_hw * hw)1967 static enum ice_status ice_aq_clear_pxe_mode(struct ice_hw *hw)
1968 {
1969 struct ice_aq_desc desc;
1970
1971 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_clear_pxe_mode);
1972 desc.params.clear_pxe.rx_cnt = ICE_AQC_CLEAR_PXE_RX_CNT;
1973
1974 return ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
1975 }
1976
1977 /**
1978 * ice_clear_pxe_mode - clear pxe operations mode
1979 * @hw: pointer to the HW struct
1980 *
1981 * Make sure all PXE mode settings are cleared, including things
1982 * like descriptor fetch/write-back mode.
1983 */
ice_clear_pxe_mode(struct ice_hw * hw)1984 void ice_clear_pxe_mode(struct ice_hw *hw)
1985 {
1986 if (ice_check_sq_alive(hw, &hw->adminq))
1987 ice_aq_clear_pxe_mode(hw);
1988 }
1989
1990 /**
1991 * ice_get_link_speed_based_on_phy_type - returns link speed
1992 * @phy_type_low: lower part of phy_type
1993 * @phy_type_high: higher part of phy_type
1994 *
1995 * This helper function will convert an entry in PHY type structure
1996 * [phy_type_low, phy_type_high] to its corresponding link speed.
1997 * Note: In the structure of [phy_type_low, phy_type_high], there should
1998 * be one bit set, as this function will convert one PHY type to its
1999 * speed.
2000 * If no bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2001 * If more than one bit gets set, ICE_LINK_SPEED_UNKNOWN will be returned
2002 */
2003 static u16
ice_get_link_speed_based_on_phy_type(u64 phy_type_low,u64 phy_type_high)2004 ice_get_link_speed_based_on_phy_type(u64 phy_type_low, u64 phy_type_high)
2005 {
2006 u16 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2007 u16 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2008
2009 switch (phy_type_low) {
2010 case ICE_PHY_TYPE_LOW_100BASE_TX:
2011 case ICE_PHY_TYPE_LOW_100M_SGMII:
2012 speed_phy_type_low = ICE_AQ_LINK_SPEED_100MB;
2013 break;
2014 case ICE_PHY_TYPE_LOW_1000BASE_T:
2015 case ICE_PHY_TYPE_LOW_1000BASE_SX:
2016 case ICE_PHY_TYPE_LOW_1000BASE_LX:
2017 case ICE_PHY_TYPE_LOW_1000BASE_KX:
2018 case ICE_PHY_TYPE_LOW_1G_SGMII:
2019 speed_phy_type_low = ICE_AQ_LINK_SPEED_1000MB;
2020 break;
2021 case ICE_PHY_TYPE_LOW_2500BASE_T:
2022 case ICE_PHY_TYPE_LOW_2500BASE_X:
2023 case ICE_PHY_TYPE_LOW_2500BASE_KX:
2024 speed_phy_type_low = ICE_AQ_LINK_SPEED_2500MB;
2025 break;
2026 case ICE_PHY_TYPE_LOW_5GBASE_T:
2027 case ICE_PHY_TYPE_LOW_5GBASE_KR:
2028 speed_phy_type_low = ICE_AQ_LINK_SPEED_5GB;
2029 break;
2030 case ICE_PHY_TYPE_LOW_10GBASE_T:
2031 case ICE_PHY_TYPE_LOW_10G_SFI_DA:
2032 case ICE_PHY_TYPE_LOW_10GBASE_SR:
2033 case ICE_PHY_TYPE_LOW_10GBASE_LR:
2034 case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
2035 case ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:
2036 case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
2037 speed_phy_type_low = ICE_AQ_LINK_SPEED_10GB;
2038 break;
2039 case ICE_PHY_TYPE_LOW_25GBASE_T:
2040 case ICE_PHY_TYPE_LOW_25GBASE_CR:
2041 case ICE_PHY_TYPE_LOW_25GBASE_CR_S:
2042 case ICE_PHY_TYPE_LOW_25GBASE_CR1:
2043 case ICE_PHY_TYPE_LOW_25GBASE_SR:
2044 case ICE_PHY_TYPE_LOW_25GBASE_LR:
2045 case ICE_PHY_TYPE_LOW_25GBASE_KR:
2046 case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
2047 case ICE_PHY_TYPE_LOW_25GBASE_KR1:
2048 case ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:
2049 case ICE_PHY_TYPE_LOW_25G_AUI_C2C:
2050 speed_phy_type_low = ICE_AQ_LINK_SPEED_25GB;
2051 break;
2052 case ICE_PHY_TYPE_LOW_40GBASE_CR4:
2053 case ICE_PHY_TYPE_LOW_40GBASE_SR4:
2054 case ICE_PHY_TYPE_LOW_40GBASE_LR4:
2055 case ICE_PHY_TYPE_LOW_40GBASE_KR4:
2056 case ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC:
2057 case ICE_PHY_TYPE_LOW_40G_XLAUI:
2058 speed_phy_type_low = ICE_AQ_LINK_SPEED_40GB;
2059 break;
2060 case ICE_PHY_TYPE_LOW_50GBASE_CR2:
2061 case ICE_PHY_TYPE_LOW_50GBASE_SR2:
2062 case ICE_PHY_TYPE_LOW_50GBASE_LR2:
2063 case ICE_PHY_TYPE_LOW_50GBASE_KR2:
2064 case ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC:
2065 case ICE_PHY_TYPE_LOW_50G_LAUI2:
2066 case ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC:
2067 case ICE_PHY_TYPE_LOW_50G_AUI2:
2068 case ICE_PHY_TYPE_LOW_50GBASE_CP:
2069 case ICE_PHY_TYPE_LOW_50GBASE_SR:
2070 case ICE_PHY_TYPE_LOW_50GBASE_FR:
2071 case ICE_PHY_TYPE_LOW_50GBASE_LR:
2072 case ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4:
2073 case ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC:
2074 case ICE_PHY_TYPE_LOW_50G_AUI1:
2075 speed_phy_type_low = ICE_AQ_LINK_SPEED_50GB;
2076 break;
2077 case ICE_PHY_TYPE_LOW_100GBASE_CR4:
2078 case ICE_PHY_TYPE_LOW_100GBASE_SR4:
2079 case ICE_PHY_TYPE_LOW_100GBASE_LR4:
2080 case ICE_PHY_TYPE_LOW_100GBASE_KR4:
2081 case ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC:
2082 case ICE_PHY_TYPE_LOW_100G_CAUI4:
2083 case ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC:
2084 case ICE_PHY_TYPE_LOW_100G_AUI4:
2085 case ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4:
2086 case ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4:
2087 case ICE_PHY_TYPE_LOW_100GBASE_CP2:
2088 case ICE_PHY_TYPE_LOW_100GBASE_SR2:
2089 case ICE_PHY_TYPE_LOW_100GBASE_DR:
2090 speed_phy_type_low = ICE_AQ_LINK_SPEED_100GB;
2091 break;
2092 default:
2093 speed_phy_type_low = ICE_AQ_LINK_SPEED_UNKNOWN;
2094 break;
2095 }
2096
2097 switch (phy_type_high) {
2098 case ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4:
2099 case ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC:
2100 case ICE_PHY_TYPE_HIGH_100G_CAUI2:
2101 case ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC:
2102 case ICE_PHY_TYPE_HIGH_100G_AUI2:
2103 speed_phy_type_high = ICE_AQ_LINK_SPEED_100GB;
2104 break;
2105 default:
2106 speed_phy_type_high = ICE_AQ_LINK_SPEED_UNKNOWN;
2107 break;
2108 }
2109
2110 if (speed_phy_type_low == ICE_AQ_LINK_SPEED_UNKNOWN &&
2111 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2112 return ICE_AQ_LINK_SPEED_UNKNOWN;
2113 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2114 speed_phy_type_high != ICE_AQ_LINK_SPEED_UNKNOWN)
2115 return ICE_AQ_LINK_SPEED_UNKNOWN;
2116 else if (speed_phy_type_low != ICE_AQ_LINK_SPEED_UNKNOWN &&
2117 speed_phy_type_high == ICE_AQ_LINK_SPEED_UNKNOWN)
2118 return speed_phy_type_low;
2119 else
2120 return speed_phy_type_high;
2121 }
2122
2123 /**
2124 * ice_update_phy_type
2125 * @phy_type_low: pointer to the lower part of phy_type
2126 * @phy_type_high: pointer to the higher part of phy_type
2127 * @link_speeds_bitmap: targeted link speeds bitmap
2128 *
2129 * Note: For the link_speeds_bitmap structure, you can check it at
2130 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
2131 * link_speeds_bitmap include multiple speeds.
2132 *
2133 * Each entry in this [phy_type_low, phy_type_high] structure will
2134 * present a certain link speed. This helper function will turn on bits
2135 * in [phy_type_low, phy_type_high] structure based on the value of
2136 * link_speeds_bitmap input parameter.
2137 */
2138 void
ice_update_phy_type(u64 * phy_type_low,u64 * phy_type_high,u16 link_speeds_bitmap)2139 ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
2140 u16 link_speeds_bitmap)
2141 {
2142 u64 pt_high;
2143 u64 pt_low;
2144 int index;
2145 u16 speed;
2146
2147 /* We first check with low part of phy_type */
2148 for (index = 0; index <= ICE_PHY_TYPE_LOW_MAX_INDEX; index++) {
2149 pt_low = BIT_ULL(index);
2150 speed = ice_get_link_speed_based_on_phy_type(pt_low, 0);
2151
2152 if (link_speeds_bitmap & speed)
2153 *phy_type_low |= BIT_ULL(index);
2154 }
2155
2156 /* We then check with high part of phy_type */
2157 for (index = 0; index <= ICE_PHY_TYPE_HIGH_MAX_INDEX; index++) {
2158 pt_high = BIT_ULL(index);
2159 speed = ice_get_link_speed_based_on_phy_type(0, pt_high);
2160
2161 if (link_speeds_bitmap & speed)
2162 *phy_type_high |= BIT_ULL(index);
2163 }
2164 }
2165
2166 /**
2167 * ice_aq_set_phy_cfg
2168 * @hw: pointer to the HW struct
2169 * @lport: logical port number
2170 * @cfg: structure with PHY configuration data to be set
2171 * @cd: pointer to command details structure or NULL
2172 *
2173 * Set the various PHY configuration parameters supported on the Port.
2174 * One or more of the Set PHY config parameters may be ignored in an MFP
2175 * mode as the PF may not have the privilege to set some of the PHY Config
2176 * parameters. This status will be indicated by the command response (0x0601).
2177 */
2178 enum ice_status
ice_aq_set_phy_cfg(struct ice_hw * hw,u8 lport,struct ice_aqc_set_phy_cfg_data * cfg,struct ice_sq_cd * cd)2179 ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
2180 struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd)
2181 {
2182 struct ice_aq_desc desc;
2183
2184 if (!cfg)
2185 return ICE_ERR_PARAM;
2186
2187 /* Ensure that only valid bits of cfg->caps can be turned on. */
2188 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) {
2189 ice_debug(hw, ICE_DBG_PHY,
2190 "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n",
2191 cfg->caps);
2192
2193 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK;
2194 }
2195
2196 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_phy_cfg);
2197 desc.params.set_phy.lport_num = lport;
2198 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2199
2200 ice_debug(hw, ICE_DBG_LINK, "phy_type_low = 0x%llx\n",
2201 (unsigned long long)le64_to_cpu(cfg->phy_type_low));
2202 ice_debug(hw, ICE_DBG_LINK, "phy_type_high = 0x%llx\n",
2203 (unsigned long long)le64_to_cpu(cfg->phy_type_high));
2204 ice_debug(hw, ICE_DBG_LINK, "caps = 0x%x\n", cfg->caps);
2205 ice_debug(hw, ICE_DBG_LINK, "low_power_ctrl = 0x%x\n",
2206 cfg->low_power_ctrl);
2207 ice_debug(hw, ICE_DBG_LINK, "eee_cap = 0x%x\n", cfg->eee_cap);
2208 ice_debug(hw, ICE_DBG_LINK, "eeer_value = 0x%x\n", cfg->eeer_value);
2209 ice_debug(hw, ICE_DBG_LINK, "link_fec_opt = 0x%x\n", cfg->link_fec_opt);
2210
2211 return ice_aq_send_cmd(hw, &desc, cfg, sizeof(*cfg), cd);
2212 }
2213
2214 /**
2215 * ice_update_link_info - update status of the HW network link
2216 * @pi: port info structure of the interested logical port
2217 */
ice_update_link_info(struct ice_port_info * pi)2218 enum ice_status ice_update_link_info(struct ice_port_info *pi)
2219 {
2220 struct ice_link_status *li;
2221 enum ice_status status;
2222
2223 if (!pi)
2224 return ICE_ERR_PARAM;
2225
2226 li = &pi->phy.link_info;
2227
2228 status = ice_aq_get_link_info(pi, true, NULL, NULL);
2229 if (status)
2230 return status;
2231
2232 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) {
2233 struct ice_aqc_get_phy_caps_data *pcaps;
2234 struct ice_hw *hw;
2235
2236 hw = pi->hw;
2237 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps),
2238 GFP_KERNEL);
2239 if (!pcaps)
2240 return ICE_ERR_NO_MEMORY;
2241
2242 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP,
2243 pcaps, NULL);
2244 if (!status)
2245 memcpy(li->module_type, &pcaps->module_type,
2246 sizeof(li->module_type));
2247
2248 devm_kfree(ice_hw_to_dev(hw), pcaps);
2249 }
2250
2251 return status;
2252 }
2253
2254 /**
2255 * ice_set_fc
2256 * @pi: port information structure
2257 * @aq_failures: pointer to status code, specific to ice_set_fc routine
2258 * @ena_auto_link_update: enable automatic link update
2259 *
2260 * Set the requested flow control mode.
2261 */
2262 enum ice_status
ice_set_fc(struct ice_port_info * pi,u8 * aq_failures,bool ena_auto_link_update)2263 ice_set_fc(struct ice_port_info *pi, u8 *aq_failures, bool ena_auto_link_update)
2264 {
2265 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2266 struct ice_aqc_get_phy_caps_data *pcaps;
2267 enum ice_status status;
2268 u8 pause_mask = 0x0;
2269 struct ice_hw *hw;
2270
2271 if (!pi)
2272 return ICE_ERR_PARAM;
2273 hw = pi->hw;
2274 *aq_failures = ICE_SET_FC_AQ_FAIL_NONE;
2275
2276 switch (pi->fc.req_mode) {
2277 case ICE_FC_FULL:
2278 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2279 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2280 break;
2281 case ICE_FC_RX_PAUSE:
2282 pause_mask |= ICE_AQC_PHY_EN_RX_LINK_PAUSE;
2283 break;
2284 case ICE_FC_TX_PAUSE:
2285 pause_mask |= ICE_AQC_PHY_EN_TX_LINK_PAUSE;
2286 break;
2287 default:
2288 break;
2289 }
2290
2291 pcaps = devm_kzalloc(ice_hw_to_dev(hw), sizeof(*pcaps), GFP_KERNEL);
2292 if (!pcaps)
2293 return ICE_ERR_NO_MEMORY;
2294
2295 /* Get the current PHY config */
2296 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2297 NULL);
2298 if (status) {
2299 *aq_failures = ICE_SET_FC_AQ_FAIL_GET;
2300 goto out;
2301 }
2302
2303 /* clear the old pause settings */
2304 cfg.caps = pcaps->caps & ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE |
2305 ICE_AQC_PHY_EN_RX_LINK_PAUSE);
2306
2307 /* set the new capabilities */
2308 cfg.caps |= pause_mask;
2309
2310 /* If the capabilities have changed, then set the new config */
2311 if (cfg.caps != pcaps->caps) {
2312 int retry_count, retry_max = 10;
2313
2314 /* Auto restart link so settings take effect */
2315 if (ena_auto_link_update)
2316 cfg.caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2317 /* Copy over all the old settings */
2318 cfg.phy_type_high = pcaps->phy_type_high;
2319 cfg.phy_type_low = pcaps->phy_type_low;
2320 cfg.low_power_ctrl = pcaps->low_power_ctrl;
2321 cfg.eee_cap = pcaps->eee_cap;
2322 cfg.eeer_value = pcaps->eeer_value;
2323 cfg.link_fec_opt = pcaps->link_fec_options;
2324
2325 status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2326 if (status) {
2327 *aq_failures = ICE_SET_FC_AQ_FAIL_SET;
2328 goto out;
2329 }
2330
2331 /* Update the link info
2332 * It sometimes takes a really long time for link to
2333 * come back from the atomic reset. Thus, we wait a
2334 * little bit.
2335 */
2336 for (retry_count = 0; retry_count < retry_max; retry_count++) {
2337 status = ice_update_link_info(pi);
2338
2339 if (!status)
2340 break;
2341
2342 mdelay(100);
2343 }
2344
2345 if (status)
2346 *aq_failures = ICE_SET_FC_AQ_FAIL_UPDATE;
2347 }
2348
2349 out:
2350 devm_kfree(ice_hw_to_dev(hw), pcaps);
2351 return status;
2352 }
2353
2354 /**
2355 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
2356 * @caps: PHY ability structure to copy date from
2357 * @cfg: PHY configuration structure to copy data to
2358 *
2359 * Helper function to copy AQC PHY get ability data to PHY set configuration
2360 * data structure
2361 */
2362 void
ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data * caps,struct ice_aqc_set_phy_cfg_data * cfg)2363 ice_copy_phy_caps_to_cfg(struct ice_aqc_get_phy_caps_data *caps,
2364 struct ice_aqc_set_phy_cfg_data *cfg)
2365 {
2366 if (!caps || !cfg)
2367 return;
2368
2369 cfg->phy_type_low = caps->phy_type_low;
2370 cfg->phy_type_high = caps->phy_type_high;
2371 cfg->caps = caps->caps;
2372 cfg->low_power_ctrl = caps->low_power_ctrl;
2373 cfg->eee_cap = caps->eee_cap;
2374 cfg->eeer_value = caps->eeer_value;
2375 cfg->link_fec_opt = caps->link_fec_options;
2376 }
2377
2378 /**
2379 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
2380 * @cfg: PHY configuration data to set FEC mode
2381 * @fec: FEC mode to configure
2382 *
2383 * Caller should copy ice_aqc_get_phy_caps_data.caps ICE_AQC_PHY_EN_AUTO_FEC
2384 * (bit 7) and ice_aqc_get_phy_caps_data.link_fec_options to cfg.caps
2385 * ICE_AQ_PHY_ENA_AUTO_FEC (bit 7) and cfg.link_fec_options before calling.
2386 */
2387 void
ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data * cfg,enum ice_fec_mode fec)2388 ice_cfg_phy_fec(struct ice_aqc_set_phy_cfg_data *cfg, enum ice_fec_mode fec)
2389 {
2390 switch (fec) {
2391 case ICE_FEC_BASER:
2392 /* Clear RS bits, and AND BASE-R ability
2393 * bits and OR request bits.
2394 */
2395 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |
2396 ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;
2397 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |
2398 ICE_AQC_PHY_FEC_25G_KR_REQ;
2399 break;
2400 case ICE_FEC_RS:
2401 /* Clear BASE-R bits, and AND RS ability
2402 * bits and OR request bits.
2403 */
2404 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;
2405 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |
2406 ICE_AQC_PHY_FEC_25G_RS_544_REQ;
2407 break;
2408 case ICE_FEC_NONE:
2409 /* Clear all FEC option bits. */
2410 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK;
2411 break;
2412 case ICE_FEC_AUTO:
2413 /* AND auto FEC bit, and all caps bits. */
2414 cfg->caps &= ICE_AQC_PHY_CAPS_MASK;
2415 break;
2416 }
2417 }
2418
2419 /**
2420 * ice_get_link_status - get status of the HW network link
2421 * @pi: port information structure
2422 * @link_up: pointer to bool (true/false = linkup/linkdown)
2423 *
2424 * Variable link_up is true if link is up, false if link is down.
2425 * The variable link_up is invalid if status is non zero. As a
2426 * result of this call, link status reporting becomes enabled
2427 */
ice_get_link_status(struct ice_port_info * pi,bool * link_up)2428 enum ice_status ice_get_link_status(struct ice_port_info *pi, bool *link_up)
2429 {
2430 struct ice_phy_info *phy_info;
2431 enum ice_status status = 0;
2432
2433 if (!pi || !link_up)
2434 return ICE_ERR_PARAM;
2435
2436 phy_info = &pi->phy;
2437
2438 if (phy_info->get_link_info) {
2439 status = ice_update_link_info(pi);
2440
2441 if (status)
2442 ice_debug(pi->hw, ICE_DBG_LINK,
2443 "get link status error, status = %d\n",
2444 status);
2445 }
2446
2447 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP;
2448
2449 return status;
2450 }
2451
2452 /**
2453 * ice_aq_set_link_restart_an
2454 * @pi: pointer to the port information structure
2455 * @ena_link: if true: enable link, if false: disable link
2456 * @cd: pointer to command details structure or NULL
2457 *
2458 * Sets up the link and restarts the Auto-Negotiation over the link.
2459 */
2460 enum ice_status
ice_aq_set_link_restart_an(struct ice_port_info * pi,bool ena_link,struct ice_sq_cd * cd)2461 ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
2462 struct ice_sq_cd *cd)
2463 {
2464 struct ice_aqc_restart_an *cmd;
2465 struct ice_aq_desc desc;
2466
2467 cmd = &desc.params.restart_an;
2468
2469 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_restart_an);
2470
2471 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART;
2472 cmd->lport_num = pi->lport;
2473 if (ena_link)
2474 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE;
2475 else
2476 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE;
2477
2478 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd);
2479 }
2480
2481 /**
2482 * ice_aq_set_event_mask
2483 * @hw: pointer to the HW struct
2484 * @port_num: port number of the physical function
2485 * @mask: event mask to be set
2486 * @cd: pointer to command details structure or NULL
2487 *
2488 * Set event mask (0x0613)
2489 */
2490 enum ice_status
ice_aq_set_event_mask(struct ice_hw * hw,u8 port_num,u16 mask,struct ice_sq_cd * cd)2491 ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
2492 struct ice_sq_cd *cd)
2493 {
2494 struct ice_aqc_set_event_mask *cmd;
2495 struct ice_aq_desc desc;
2496
2497 cmd = &desc.params.set_event_mask;
2498
2499 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_event_mask);
2500
2501 cmd->lport_num = port_num;
2502
2503 cmd->event_mask = cpu_to_le16(mask);
2504 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2505 }
2506
2507 /**
2508 * ice_aq_set_mac_loopback
2509 * @hw: pointer to the HW struct
2510 * @ena_lpbk: Enable or Disable loopback
2511 * @cd: pointer to command details structure or NULL
2512 *
2513 * Enable/disable loopback on a given port
2514 */
2515 enum ice_status
ice_aq_set_mac_loopback(struct ice_hw * hw,bool ena_lpbk,struct ice_sq_cd * cd)2516 ice_aq_set_mac_loopback(struct ice_hw *hw, bool ena_lpbk, struct ice_sq_cd *cd)
2517 {
2518 struct ice_aqc_set_mac_lb *cmd;
2519 struct ice_aq_desc desc;
2520
2521 cmd = &desc.params.set_mac_lb;
2522
2523 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_mac_lb);
2524 if (ena_lpbk)
2525 cmd->lb_mode = ICE_AQ_MAC_LB_EN;
2526
2527 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2528 }
2529
2530 /**
2531 * ice_aq_set_port_id_led
2532 * @pi: pointer to the port information
2533 * @is_orig_mode: is this LED set to original mode (by the net-list)
2534 * @cd: pointer to command details structure or NULL
2535 *
2536 * Set LED value for the given port (0x06e9)
2537 */
2538 enum ice_status
ice_aq_set_port_id_led(struct ice_port_info * pi,bool is_orig_mode,struct ice_sq_cd * cd)2539 ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
2540 struct ice_sq_cd *cd)
2541 {
2542 struct ice_aqc_set_port_id_led *cmd;
2543 struct ice_hw *hw = pi->hw;
2544 struct ice_aq_desc desc;
2545
2546 cmd = &desc.params.set_port_id_led;
2547
2548 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_port_id_led);
2549
2550 if (is_orig_mode)
2551 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG;
2552 else
2553 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK;
2554
2555 return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
2556 }
2557
2558 /**
2559 * __ice_aq_get_set_rss_lut
2560 * @hw: pointer to the hardware structure
2561 * @vsi_id: VSI FW index
2562 * @lut_type: LUT table type
2563 * @lut: pointer to the LUT buffer provided by the caller
2564 * @lut_size: size of the LUT buffer
2565 * @glob_lut_idx: global LUT index
2566 * @set: set true to set the table, false to get the table
2567 *
2568 * Internal function to get (0x0B05) or set (0x0B03) RSS look up table
2569 */
2570 static enum ice_status
__ice_aq_get_set_rss_lut(struct ice_hw * hw,u16 vsi_id,u8 lut_type,u8 * lut,u16 lut_size,u8 glob_lut_idx,bool set)2571 __ice_aq_get_set_rss_lut(struct ice_hw *hw, u16 vsi_id, u8 lut_type, u8 *lut,
2572 u16 lut_size, u8 glob_lut_idx, bool set)
2573 {
2574 struct ice_aqc_get_set_rss_lut *cmd_resp;
2575 struct ice_aq_desc desc;
2576 enum ice_status status;
2577 u16 flags = 0;
2578
2579 cmd_resp = &desc.params.get_set_rss_lut;
2580
2581 if (set) {
2582 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_lut);
2583 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2584 } else {
2585 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_lut);
2586 }
2587
2588 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2589 ICE_AQC_GSET_RSS_LUT_VSI_ID_S) &
2590 ICE_AQC_GSET_RSS_LUT_VSI_ID_M) |
2591 ICE_AQC_GSET_RSS_LUT_VSI_VALID);
2592
2593 switch (lut_type) {
2594 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI:
2595 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF:
2596 case ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL:
2597 flags |= ((lut_type << ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_S) &
2598 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_M);
2599 break;
2600 default:
2601 status = ICE_ERR_PARAM;
2602 goto ice_aq_get_set_rss_lut_exit;
2603 }
2604
2605 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_GLOBAL) {
2606 flags |= ((glob_lut_idx << ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_S) &
2607 ICE_AQC_GSET_RSS_LUT_GLOBAL_IDX_M);
2608
2609 if (!set)
2610 goto ice_aq_get_set_rss_lut_send;
2611 } else if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2612 if (!set)
2613 goto ice_aq_get_set_rss_lut_send;
2614 } else {
2615 goto ice_aq_get_set_rss_lut_send;
2616 }
2617
2618 /* LUT size is only valid for Global and PF table types */
2619 switch (lut_size) {
2620 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128:
2621 break;
2622 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512:
2623 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512_FLAG <<
2624 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2625 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2626 break;
2627 case ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K:
2628 if (lut_type == ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF) {
2629 flags |= (ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K_FLAG <<
2630 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_S) &
2631 ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_M;
2632 break;
2633 }
2634 /* fall-through */
2635 default:
2636 status = ICE_ERR_PARAM;
2637 goto ice_aq_get_set_rss_lut_exit;
2638 }
2639
2640 ice_aq_get_set_rss_lut_send:
2641 cmd_resp->flags = cpu_to_le16(flags);
2642 status = ice_aq_send_cmd(hw, &desc, lut, lut_size, NULL);
2643
2644 ice_aq_get_set_rss_lut_exit:
2645 return status;
2646 }
2647
2648 /**
2649 * ice_aq_get_rss_lut
2650 * @hw: pointer to the hardware structure
2651 * @vsi_handle: software VSI handle
2652 * @lut_type: LUT table type
2653 * @lut: pointer to the LUT buffer provided by the caller
2654 * @lut_size: size of the LUT buffer
2655 *
2656 * get the RSS lookup table, PF or VSI type
2657 */
2658 enum ice_status
ice_aq_get_rss_lut(struct ice_hw * hw,u16 vsi_handle,u8 lut_type,u8 * lut,u16 lut_size)2659 ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2660 u8 *lut, u16 lut_size)
2661 {
2662 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2663 return ICE_ERR_PARAM;
2664
2665 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2666 lut_type, lut, lut_size, 0, false);
2667 }
2668
2669 /**
2670 * ice_aq_set_rss_lut
2671 * @hw: pointer to the hardware structure
2672 * @vsi_handle: software VSI handle
2673 * @lut_type: LUT table type
2674 * @lut: pointer to the LUT buffer provided by the caller
2675 * @lut_size: size of the LUT buffer
2676 *
2677 * set the RSS lookup table, PF or VSI type
2678 */
2679 enum ice_status
ice_aq_set_rss_lut(struct ice_hw * hw,u16 vsi_handle,u8 lut_type,u8 * lut,u16 lut_size)2680 ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type,
2681 u8 *lut, u16 lut_size)
2682 {
2683 if (!ice_is_vsi_valid(hw, vsi_handle) || !lut)
2684 return ICE_ERR_PARAM;
2685
2686 return __ice_aq_get_set_rss_lut(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2687 lut_type, lut, lut_size, 0, true);
2688 }
2689
2690 /**
2691 * __ice_aq_get_set_rss_key
2692 * @hw: pointer to the HW struct
2693 * @vsi_id: VSI FW index
2694 * @key: pointer to key info struct
2695 * @set: set true to set the key, false to get the key
2696 *
2697 * get (0x0B04) or set (0x0B02) the RSS key per VSI
2698 */
2699 static enum
__ice_aq_get_set_rss_key(struct ice_hw * hw,u16 vsi_id,struct ice_aqc_get_set_rss_keys * key,bool set)2700 ice_status __ice_aq_get_set_rss_key(struct ice_hw *hw, u16 vsi_id,
2701 struct ice_aqc_get_set_rss_keys *key,
2702 bool set)
2703 {
2704 struct ice_aqc_get_set_rss_key *cmd_resp;
2705 u16 key_size = sizeof(*key);
2706 struct ice_aq_desc desc;
2707
2708 cmd_resp = &desc.params.get_set_rss_key;
2709
2710 if (set) {
2711 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_set_rss_key);
2712 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2713 } else {
2714 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_rss_key);
2715 }
2716
2717 cmd_resp->vsi_id = cpu_to_le16(((vsi_id <<
2718 ICE_AQC_GSET_RSS_KEY_VSI_ID_S) &
2719 ICE_AQC_GSET_RSS_KEY_VSI_ID_M) |
2720 ICE_AQC_GSET_RSS_KEY_VSI_VALID);
2721
2722 return ice_aq_send_cmd(hw, &desc, key, key_size, NULL);
2723 }
2724
2725 /**
2726 * ice_aq_get_rss_key
2727 * @hw: pointer to the HW struct
2728 * @vsi_handle: software VSI handle
2729 * @key: pointer to key info struct
2730 *
2731 * get the RSS key per VSI
2732 */
2733 enum ice_status
ice_aq_get_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * key)2734 ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
2735 struct ice_aqc_get_set_rss_keys *key)
2736 {
2737 if (!ice_is_vsi_valid(hw, vsi_handle) || !key)
2738 return ICE_ERR_PARAM;
2739
2740 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2741 key, false);
2742 }
2743
2744 /**
2745 * ice_aq_set_rss_key
2746 * @hw: pointer to the HW struct
2747 * @vsi_handle: software VSI handle
2748 * @keys: pointer to key info struct
2749 *
2750 * set the RSS key per VSI
2751 */
2752 enum ice_status
ice_aq_set_rss_key(struct ice_hw * hw,u16 vsi_handle,struct ice_aqc_get_set_rss_keys * keys)2753 ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
2754 struct ice_aqc_get_set_rss_keys *keys)
2755 {
2756 if (!ice_is_vsi_valid(hw, vsi_handle) || !keys)
2757 return ICE_ERR_PARAM;
2758
2759 return __ice_aq_get_set_rss_key(hw, ice_get_hw_vsi_num(hw, vsi_handle),
2760 keys, true);
2761 }
2762
2763 /**
2764 * ice_aq_add_lan_txq
2765 * @hw: pointer to the hardware structure
2766 * @num_qgrps: Number of added queue groups
2767 * @qg_list: list of queue groups to be added
2768 * @buf_size: size of buffer for indirect command
2769 * @cd: pointer to command details structure or NULL
2770 *
2771 * Add Tx LAN queue (0x0C30)
2772 *
2773 * NOTE:
2774 * Prior to calling add Tx LAN queue:
2775 * Initialize the following as part of the Tx queue context:
2776 * Completion queue ID if the queue uses Completion queue, Quanta profile,
2777 * Cache profile and Packet shaper profile.
2778 *
2779 * After add Tx LAN queue AQ command is completed:
2780 * Interrupts should be associated with specific queues,
2781 * Association of Tx queue to Doorbell queue is not part of Add LAN Tx queue
2782 * flow.
2783 */
2784 static enum ice_status
ice_aq_add_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * qg_list,u16 buf_size,struct ice_sq_cd * cd)2785 ice_aq_add_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2786 struct ice_aqc_add_tx_qgrp *qg_list, u16 buf_size,
2787 struct ice_sq_cd *cd)
2788 {
2789 u16 i, sum_header_size, sum_q_size = 0;
2790 struct ice_aqc_add_tx_qgrp *list;
2791 struct ice_aqc_add_txqs *cmd;
2792 struct ice_aq_desc desc;
2793
2794 cmd = &desc.params.add_txqs;
2795
2796 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_add_txqs);
2797
2798 if (!qg_list)
2799 return ICE_ERR_PARAM;
2800
2801 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2802 return ICE_ERR_PARAM;
2803
2804 sum_header_size = num_qgrps *
2805 (sizeof(*qg_list) - sizeof(*qg_list->txqs));
2806
2807 list = qg_list;
2808 for (i = 0; i < num_qgrps; i++) {
2809 struct ice_aqc_add_txqs_perq *q = list->txqs;
2810
2811 sum_q_size += list->num_txqs * sizeof(*q);
2812 list = (struct ice_aqc_add_tx_qgrp *)(q + list->num_txqs);
2813 }
2814
2815 if (buf_size != (sum_header_size + sum_q_size))
2816 return ICE_ERR_PARAM;
2817
2818 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2819
2820 cmd->num_qgrps = num_qgrps;
2821
2822 return ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2823 }
2824
2825 /**
2826 * ice_aq_dis_lan_txq
2827 * @hw: pointer to the hardware structure
2828 * @num_qgrps: number of groups in the list
2829 * @qg_list: the list of groups to disable
2830 * @buf_size: the total size of the qg_list buffer in bytes
2831 * @rst_src: if called due to reset, specifies the reset source
2832 * @vmvf_num: the relative VM or VF number that is undergoing the reset
2833 * @cd: pointer to command details structure or NULL
2834 *
2835 * Disable LAN Tx queue (0x0C31)
2836 */
2837 static enum ice_status
ice_aq_dis_lan_txq(struct ice_hw * hw,u8 num_qgrps,struct ice_aqc_dis_txq_item * qg_list,u16 buf_size,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)2838 ice_aq_dis_lan_txq(struct ice_hw *hw, u8 num_qgrps,
2839 struct ice_aqc_dis_txq_item *qg_list, u16 buf_size,
2840 enum ice_disq_rst_src rst_src, u16 vmvf_num,
2841 struct ice_sq_cd *cd)
2842 {
2843 struct ice_aqc_dis_txqs *cmd;
2844 struct ice_aq_desc desc;
2845 enum ice_status status;
2846 u16 i, sz = 0;
2847
2848 cmd = &desc.params.dis_txqs;
2849 ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_dis_txqs);
2850
2851 /* qg_list can be NULL only in VM/VF reset flow */
2852 if (!qg_list && !rst_src)
2853 return ICE_ERR_PARAM;
2854
2855 if (num_qgrps > ICE_LAN_TXQ_MAX_QGRPS)
2856 return ICE_ERR_PARAM;
2857
2858 cmd->num_entries = num_qgrps;
2859
2860 cmd->vmvf_and_timeout = cpu_to_le16((5 << ICE_AQC_Q_DIS_TIMEOUT_S) &
2861 ICE_AQC_Q_DIS_TIMEOUT_M);
2862
2863 switch (rst_src) {
2864 case ICE_VM_RESET:
2865 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET;
2866 cmd->vmvf_and_timeout |=
2867 cpu_to_le16(vmvf_num & ICE_AQC_Q_DIS_VMVF_NUM_M);
2868 break;
2869 case ICE_VF_RESET:
2870 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET;
2871 /* In this case, FW expects vmvf_num to be absolute VF ID */
2872 cmd->vmvf_and_timeout |=
2873 cpu_to_le16((vmvf_num + hw->func_caps.vf_base_id) &
2874 ICE_AQC_Q_DIS_VMVF_NUM_M);
2875 break;
2876 case ICE_NO_RESET:
2877 default:
2878 break;
2879 }
2880
2881 /* flush pipe on time out */
2882 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE;
2883 /* If no queue group info, we are in a reset flow. Issue the AQ */
2884 if (!qg_list)
2885 goto do_aq;
2886
2887 /* set RD bit to indicate that command buffer is provided by the driver
2888 * and it needs to be read by the firmware
2889 */
2890 desc.flags |= cpu_to_le16(ICE_AQ_FLAG_RD);
2891
2892 for (i = 0; i < num_qgrps; ++i) {
2893 /* Calculate the size taken up by the queue IDs in this group */
2894 sz += qg_list[i].num_qs * sizeof(qg_list[i].q_id);
2895
2896 /* Add the size of the group header */
2897 sz += sizeof(qg_list[i]) - sizeof(qg_list[i].q_id);
2898
2899 /* If the num of queues is even, add 2 bytes of padding */
2900 if ((qg_list[i].num_qs % 2) == 0)
2901 sz += 2;
2902 }
2903
2904 if (buf_size != sz)
2905 return ICE_ERR_PARAM;
2906
2907 do_aq:
2908 status = ice_aq_send_cmd(hw, &desc, qg_list, buf_size, cd);
2909 if (status) {
2910 if (!qg_list)
2911 ice_debug(hw, ICE_DBG_SCHED, "VM%d disable failed %d\n",
2912 vmvf_num, hw->adminq.sq_last_status);
2913 else
2914 ice_debug(hw, ICE_DBG_SCHED, "disable queue %d failed %d\n",
2915 le16_to_cpu(qg_list[0].q_id[0]),
2916 hw->adminq.sq_last_status);
2917 }
2918 return status;
2919 }
2920
2921 /* End of FW Admin Queue command wrappers */
2922
2923 /**
2924 * ice_write_byte - write a byte to a packed context structure
2925 * @src_ctx: the context structure to read from
2926 * @dest_ctx: the context to be written to
2927 * @ce_info: a description of the struct to be filled
2928 */
2929 static void
ice_write_byte(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)2930 ice_write_byte(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2931 {
2932 u8 src_byte, dest_byte, mask;
2933 u8 *from, *dest;
2934 u16 shift_width;
2935
2936 /* copy from the next struct field */
2937 from = src_ctx + ce_info->offset;
2938
2939 /* prepare the bits and mask */
2940 shift_width = ce_info->lsb % 8;
2941 mask = (u8)(BIT(ce_info->width) - 1);
2942
2943 src_byte = *from;
2944 src_byte &= mask;
2945
2946 /* shift to correct alignment */
2947 mask <<= shift_width;
2948 src_byte <<= shift_width;
2949
2950 /* get the current bits from the target bit string */
2951 dest = dest_ctx + (ce_info->lsb / 8);
2952
2953 memcpy(&dest_byte, dest, sizeof(dest_byte));
2954
2955 dest_byte &= ~mask; /* get the bits not changing */
2956 dest_byte |= src_byte; /* add in the new bits */
2957
2958 /* put it all back */
2959 memcpy(dest, &dest_byte, sizeof(dest_byte));
2960 }
2961
2962 /**
2963 * ice_write_word - write a word to a packed context structure
2964 * @src_ctx: the context structure to read from
2965 * @dest_ctx: the context to be written to
2966 * @ce_info: a description of the struct to be filled
2967 */
2968 static void
ice_write_word(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)2969 ice_write_word(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
2970 {
2971 u16 src_word, mask;
2972 __le16 dest_word;
2973 u8 *from, *dest;
2974 u16 shift_width;
2975
2976 /* copy from the next struct field */
2977 from = src_ctx + ce_info->offset;
2978
2979 /* prepare the bits and mask */
2980 shift_width = ce_info->lsb % 8;
2981 mask = BIT(ce_info->width) - 1;
2982
2983 /* don't swizzle the bits until after the mask because the mask bits
2984 * will be in a different bit position on big endian machines
2985 */
2986 src_word = *(u16 *)from;
2987 src_word &= mask;
2988
2989 /* shift to correct alignment */
2990 mask <<= shift_width;
2991 src_word <<= shift_width;
2992
2993 /* get the current bits from the target bit string */
2994 dest = dest_ctx + (ce_info->lsb / 8);
2995
2996 memcpy(&dest_word, dest, sizeof(dest_word));
2997
2998 dest_word &= ~(cpu_to_le16(mask)); /* get the bits not changing */
2999 dest_word |= cpu_to_le16(src_word); /* add in the new bits */
3000
3001 /* put it all back */
3002 memcpy(dest, &dest_word, sizeof(dest_word));
3003 }
3004
3005 /**
3006 * ice_write_dword - write a dword to a packed context structure
3007 * @src_ctx: the context structure to read from
3008 * @dest_ctx: the context to be written to
3009 * @ce_info: a description of the struct to be filled
3010 */
3011 static void
ice_write_dword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)3012 ice_write_dword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3013 {
3014 u32 src_dword, mask;
3015 __le32 dest_dword;
3016 u8 *from, *dest;
3017 u16 shift_width;
3018
3019 /* copy from the next struct field */
3020 from = src_ctx + ce_info->offset;
3021
3022 /* prepare the bits and mask */
3023 shift_width = ce_info->lsb % 8;
3024
3025 /* if the field width is exactly 32 on an x86 machine, then the shift
3026 * operation will not work because the SHL instructions count is masked
3027 * to 5 bits so the shift will do nothing
3028 */
3029 if (ce_info->width < 32)
3030 mask = BIT(ce_info->width) - 1;
3031 else
3032 mask = (u32)~0;
3033
3034 /* don't swizzle the bits until after the mask because the mask bits
3035 * will be in a different bit position on big endian machines
3036 */
3037 src_dword = *(u32 *)from;
3038 src_dword &= mask;
3039
3040 /* shift to correct alignment */
3041 mask <<= shift_width;
3042 src_dword <<= shift_width;
3043
3044 /* get the current bits from the target bit string */
3045 dest = dest_ctx + (ce_info->lsb / 8);
3046
3047 memcpy(&dest_dword, dest, sizeof(dest_dword));
3048
3049 dest_dword &= ~(cpu_to_le32(mask)); /* get the bits not changing */
3050 dest_dword |= cpu_to_le32(src_dword); /* add in the new bits */
3051
3052 /* put it all back */
3053 memcpy(dest, &dest_dword, sizeof(dest_dword));
3054 }
3055
3056 /**
3057 * ice_write_qword - write a qword to a packed context structure
3058 * @src_ctx: the context structure to read from
3059 * @dest_ctx: the context to be written to
3060 * @ce_info: a description of the struct to be filled
3061 */
3062 static void
ice_write_qword(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)3063 ice_write_qword(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3064 {
3065 u64 src_qword, mask;
3066 __le64 dest_qword;
3067 u8 *from, *dest;
3068 u16 shift_width;
3069
3070 /* copy from the next struct field */
3071 from = src_ctx + ce_info->offset;
3072
3073 /* prepare the bits and mask */
3074 shift_width = ce_info->lsb % 8;
3075
3076 /* if the field width is exactly 64 on an x86 machine, then the shift
3077 * operation will not work because the SHL instructions count is masked
3078 * to 6 bits so the shift will do nothing
3079 */
3080 if (ce_info->width < 64)
3081 mask = BIT_ULL(ce_info->width) - 1;
3082 else
3083 mask = (u64)~0;
3084
3085 /* don't swizzle the bits until after the mask because the mask bits
3086 * will be in a different bit position on big endian machines
3087 */
3088 src_qword = *(u64 *)from;
3089 src_qword &= mask;
3090
3091 /* shift to correct alignment */
3092 mask <<= shift_width;
3093 src_qword <<= shift_width;
3094
3095 /* get the current bits from the target bit string */
3096 dest = dest_ctx + (ce_info->lsb / 8);
3097
3098 memcpy(&dest_qword, dest, sizeof(dest_qword));
3099
3100 dest_qword &= ~(cpu_to_le64(mask)); /* get the bits not changing */
3101 dest_qword |= cpu_to_le64(src_qword); /* add in the new bits */
3102
3103 /* put it all back */
3104 memcpy(dest, &dest_qword, sizeof(dest_qword));
3105 }
3106
3107 /**
3108 * ice_set_ctx - set context bits in packed structure
3109 * @src_ctx: pointer to a generic non-packed context structure
3110 * @dest_ctx: pointer to memory for the packed structure
3111 * @ce_info: a description of the structure to be transformed
3112 */
3113 enum ice_status
ice_set_ctx(u8 * src_ctx,u8 * dest_ctx,const struct ice_ctx_ele * ce_info)3114 ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info)
3115 {
3116 int f;
3117
3118 for (f = 0; ce_info[f].width; f++) {
3119 /* We have to deal with each element of the FW response
3120 * using the correct size so that we are correct regardless
3121 * of the endianness of the machine.
3122 */
3123 switch (ce_info[f].size_of) {
3124 case sizeof(u8):
3125 ice_write_byte(src_ctx, dest_ctx, &ce_info[f]);
3126 break;
3127 case sizeof(u16):
3128 ice_write_word(src_ctx, dest_ctx, &ce_info[f]);
3129 break;
3130 case sizeof(u32):
3131 ice_write_dword(src_ctx, dest_ctx, &ce_info[f]);
3132 break;
3133 case sizeof(u64):
3134 ice_write_qword(src_ctx, dest_ctx, &ce_info[f]);
3135 break;
3136 default:
3137 return ICE_ERR_INVAL_SIZE;
3138 }
3139 }
3140
3141 return 0;
3142 }
3143
3144 /**
3145 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
3146 * @hw: pointer to the HW struct
3147 * @vsi_handle: software VSI handle
3148 * @tc: TC number
3149 * @q_handle: software queue handle
3150 */
3151 static struct ice_q_ctx *
ice_get_lan_q_ctx(struct ice_hw * hw,u16 vsi_handle,u8 tc,u16 q_handle)3152 ice_get_lan_q_ctx(struct ice_hw *hw, u16 vsi_handle, u8 tc, u16 q_handle)
3153 {
3154 struct ice_vsi_ctx *vsi;
3155 struct ice_q_ctx *q_ctx;
3156
3157 vsi = ice_get_vsi_ctx(hw, vsi_handle);
3158 if (!vsi)
3159 return NULL;
3160 if (q_handle >= vsi->num_lan_q_entries[tc])
3161 return NULL;
3162 if (!vsi->lan_q_ctx[tc])
3163 return NULL;
3164 q_ctx = vsi->lan_q_ctx[tc];
3165 return &q_ctx[q_handle];
3166 }
3167
3168 /**
3169 * ice_ena_vsi_txq
3170 * @pi: port information structure
3171 * @vsi_handle: software VSI handle
3172 * @tc: TC number
3173 * @q_handle: software queue handle
3174 * @num_qgrps: Number of added queue groups
3175 * @buf: list of queue groups to be added
3176 * @buf_size: size of buffer for indirect command
3177 * @cd: pointer to command details structure or NULL
3178 *
3179 * This function adds one LAN queue
3180 */
3181 enum ice_status
ice_ena_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u16 q_handle,u8 num_qgrps,struct ice_aqc_add_tx_qgrp * buf,u16 buf_size,struct ice_sq_cd * cd)3182 ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle,
3183 u8 num_qgrps, struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
3184 struct ice_sq_cd *cd)
3185 {
3186 struct ice_aqc_txsched_elem_data node = { 0 };
3187 struct ice_sched_node *parent;
3188 struct ice_q_ctx *q_ctx;
3189 enum ice_status status;
3190 struct ice_hw *hw;
3191
3192 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3193 return ICE_ERR_CFG;
3194
3195 if (num_qgrps > 1 || buf->num_txqs > 1)
3196 return ICE_ERR_MAX_LIMIT;
3197
3198 hw = pi->hw;
3199
3200 if (!ice_is_vsi_valid(hw, vsi_handle))
3201 return ICE_ERR_PARAM;
3202
3203 mutex_lock(&pi->sched_lock);
3204
3205 q_ctx = ice_get_lan_q_ctx(hw, vsi_handle, tc, q_handle);
3206 if (!q_ctx) {
3207 ice_debug(hw, ICE_DBG_SCHED, "Enaq: invalid queue handle %d\n",
3208 q_handle);
3209 status = ICE_ERR_PARAM;
3210 goto ena_txq_exit;
3211 }
3212
3213 /* find a parent node */
3214 parent = ice_sched_get_free_qparent(pi, vsi_handle, tc,
3215 ICE_SCHED_NODE_OWNER_LAN);
3216 if (!parent) {
3217 status = ICE_ERR_PARAM;
3218 goto ena_txq_exit;
3219 }
3220
3221 buf->parent_teid = parent->info.node_teid;
3222 node.parent_teid = parent->info.node_teid;
3223 /* Mark that the values in the "generic" section as valid. The default
3224 * value in the "generic" section is zero. This means that :
3225 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0.
3226 * - 0 priority among siblings, indicated by Bit 1-3.
3227 * - WFQ, indicated by Bit 4.
3228 * - 0 Adjustment value is used in PSM credit update flow, indicated by
3229 * Bit 5-6.
3230 * - Bit 7 is reserved.
3231 * Without setting the generic section as valid in valid_sections, the
3232 * Admin queue command will fail with error code ICE_AQ_RC_EINVAL.
3233 */
3234 buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC;
3235
3236 /* add the LAN queue */
3237 status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd);
3238 if (status) {
3239 ice_debug(hw, ICE_DBG_SCHED, "enable queue %d failed %d\n",
3240 le16_to_cpu(buf->txqs[0].txq_id),
3241 hw->adminq.sq_last_status);
3242 goto ena_txq_exit;
3243 }
3244
3245 node.node_teid = buf->txqs[0].q_teid;
3246 node.data.elem_type = ICE_AQC_ELEM_TYPE_LEAF;
3247 q_ctx->q_handle = q_handle;
3248
3249 /* add a leaf node into schduler tree queue layer */
3250 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node);
3251
3252 ena_txq_exit:
3253 mutex_unlock(&pi->sched_lock);
3254 return status;
3255 }
3256
3257 /**
3258 * ice_dis_vsi_txq
3259 * @pi: port information structure
3260 * @vsi_handle: software VSI handle
3261 * @tc: TC number
3262 * @num_queues: number of queues
3263 * @q_handles: pointer to software queue handle array
3264 * @q_ids: pointer to the q_id array
3265 * @q_teids: pointer to queue node teids
3266 * @rst_src: if called due to reset, specifies the reset source
3267 * @vmvf_num: the relative VM or VF number that is undergoing the reset
3268 * @cd: pointer to command details structure or NULL
3269 *
3270 * This function removes queues and their corresponding nodes in SW DB
3271 */
3272 enum ice_status
ice_dis_vsi_txq(struct ice_port_info * pi,u16 vsi_handle,u8 tc,u8 num_queues,u16 * q_handles,u16 * q_ids,u32 * q_teids,enum ice_disq_rst_src rst_src,u16 vmvf_num,struct ice_sq_cd * cd)3273 ice_dis_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_queues,
3274 u16 *q_handles, u16 *q_ids, u32 *q_teids,
3275 enum ice_disq_rst_src rst_src, u16 vmvf_num,
3276 struct ice_sq_cd *cd)
3277 {
3278 enum ice_status status = ICE_ERR_DOES_NOT_EXIST;
3279 struct ice_aqc_dis_txq_item qg_list;
3280 struct ice_q_ctx *q_ctx;
3281 u16 i;
3282
3283 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3284 return ICE_ERR_CFG;
3285
3286 if (!num_queues) {
3287 /* if queue is disabled already yet the disable queue command
3288 * has to be sent to complete the VF reset, then call
3289 * ice_aq_dis_lan_txq without any queue information
3290 */
3291 if (rst_src)
3292 return ice_aq_dis_lan_txq(pi->hw, 0, NULL, 0, rst_src,
3293 vmvf_num, NULL);
3294 return ICE_ERR_CFG;
3295 }
3296
3297 mutex_lock(&pi->sched_lock);
3298
3299 for (i = 0; i < num_queues; i++) {
3300 struct ice_sched_node *node;
3301
3302 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]);
3303 if (!node)
3304 continue;
3305 q_ctx = ice_get_lan_q_ctx(pi->hw, vsi_handle, tc, q_handles[i]);
3306 if (!q_ctx) {
3307 ice_debug(pi->hw, ICE_DBG_SCHED, "invalid queue handle%d\n",
3308 q_handles[i]);
3309 continue;
3310 }
3311 if (q_ctx->q_handle != q_handles[i]) {
3312 ice_debug(pi->hw, ICE_DBG_SCHED, "Err:handles %d %d\n",
3313 q_ctx->q_handle, q_handles[i]);
3314 continue;
3315 }
3316 qg_list.parent_teid = node->info.parent_teid;
3317 qg_list.num_qs = 1;
3318 qg_list.q_id[0] = cpu_to_le16(q_ids[i]);
3319 status = ice_aq_dis_lan_txq(pi->hw, 1, &qg_list,
3320 sizeof(qg_list), rst_src, vmvf_num,
3321 cd);
3322
3323 if (status)
3324 break;
3325 ice_free_sched_node(pi, node);
3326 q_ctx->q_handle = ICE_INVAL_Q_HANDLE;
3327 }
3328 mutex_unlock(&pi->sched_lock);
3329 return status;
3330 }
3331
3332 /**
3333 * ice_cfg_vsi_qs - configure the new/existing VSI queues
3334 * @pi: port information structure
3335 * @vsi_handle: software VSI handle
3336 * @tc_bitmap: TC bitmap
3337 * @maxqs: max queues array per TC
3338 * @owner: LAN or RDMA
3339 *
3340 * This function adds/updates the VSI queues per TC.
3341 */
3342 static enum ice_status
ice_cfg_vsi_qs(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * maxqs,u8 owner)3343 ice_cfg_vsi_qs(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3344 u16 *maxqs, u8 owner)
3345 {
3346 enum ice_status status = 0;
3347 u8 i;
3348
3349 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY)
3350 return ICE_ERR_CFG;
3351
3352 if (!ice_is_vsi_valid(pi->hw, vsi_handle))
3353 return ICE_ERR_PARAM;
3354
3355 mutex_lock(&pi->sched_lock);
3356
3357 ice_for_each_traffic_class(i) {
3358 /* configuration is possible only if TC node is present */
3359 if (!ice_sched_get_tc_node(pi, i))
3360 continue;
3361
3362 status = ice_sched_cfg_vsi(pi, vsi_handle, i, maxqs[i], owner,
3363 ice_is_tc_ena(tc_bitmap, i));
3364 if (status)
3365 break;
3366 }
3367
3368 mutex_unlock(&pi->sched_lock);
3369 return status;
3370 }
3371
3372 /**
3373 * ice_cfg_vsi_lan - configure VSI LAN queues
3374 * @pi: port information structure
3375 * @vsi_handle: software VSI handle
3376 * @tc_bitmap: TC bitmap
3377 * @max_lanqs: max LAN queues array per TC
3378 *
3379 * This function adds/updates the VSI LAN queues per TC.
3380 */
3381 enum ice_status
ice_cfg_vsi_lan(struct ice_port_info * pi,u16 vsi_handle,u8 tc_bitmap,u16 * max_lanqs)3382 ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
3383 u16 *max_lanqs)
3384 {
3385 return ice_cfg_vsi_qs(pi, vsi_handle, tc_bitmap, max_lanqs,
3386 ICE_SCHED_NODE_OWNER_LAN);
3387 }
3388
3389 /**
3390 * ice_replay_pre_init - replay pre initialization
3391 * @hw: pointer to the HW struct
3392 *
3393 * Initializes required config data for VSI, FD, ACL, and RSS before replay.
3394 */
ice_replay_pre_init(struct ice_hw * hw)3395 static enum ice_status ice_replay_pre_init(struct ice_hw *hw)
3396 {
3397 struct ice_switch_info *sw = hw->switch_info;
3398 u8 i;
3399
3400 /* Delete old entries from replay filter list head if there is any */
3401 ice_rm_all_sw_replay_rule_info(hw);
3402 /* In start of replay, move entries into replay_rules list, it
3403 * will allow adding rules entries back to filt_rules list,
3404 * which is operational list.
3405 */
3406 for (i = 0; i < ICE_SW_LKUP_LAST; i++)
3407 list_replace_init(&sw->recp_list[i].filt_rules,
3408 &sw->recp_list[i].filt_replay_rules);
3409
3410 return 0;
3411 }
3412
3413 /**
3414 * ice_replay_vsi - replay VSI configuration
3415 * @hw: pointer to the HW struct
3416 * @vsi_handle: driver VSI handle
3417 *
3418 * Restore all VSI configuration after reset. It is required to call this
3419 * function with main VSI first.
3420 */
ice_replay_vsi(struct ice_hw * hw,u16 vsi_handle)3421 enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle)
3422 {
3423 enum ice_status status;
3424
3425 if (!ice_is_vsi_valid(hw, vsi_handle))
3426 return ICE_ERR_PARAM;
3427
3428 /* Replay pre-initialization if there is any */
3429 if (vsi_handle == ICE_MAIN_VSI_HANDLE) {
3430 status = ice_replay_pre_init(hw);
3431 if (status)
3432 return status;
3433 }
3434
3435 /* Replay per VSI all filters */
3436 status = ice_replay_vsi_all_fltr(hw, vsi_handle);
3437 return status;
3438 }
3439
3440 /**
3441 * ice_replay_post - post replay configuration cleanup
3442 * @hw: pointer to the HW struct
3443 *
3444 * Post replay cleanup.
3445 */
ice_replay_post(struct ice_hw * hw)3446 void ice_replay_post(struct ice_hw *hw)
3447 {
3448 /* Delete old entries from replay filter list head */
3449 ice_rm_all_sw_replay_rule_info(hw);
3450 }
3451
3452 /**
3453 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
3454 * @hw: ptr to the hardware info
3455 * @reg: offset of 64 bit HW register to read from
3456 * @prev_stat_loaded: bool to specify if previous stats are loaded
3457 * @prev_stat: ptr to previous loaded stat value
3458 * @cur_stat: ptr to current stat value
3459 */
3460 void
ice_stat_update40(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)3461 ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3462 u64 *prev_stat, u64 *cur_stat)
3463 {
3464 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
3465
3466 /* device stats are not reset at PFR, they likely will not be zeroed
3467 * when the driver starts. Thus, save the value from the first read
3468 * without adding to the statistic value so that we report stats which
3469 * count up from zero.
3470 */
3471 if (!prev_stat_loaded) {
3472 *prev_stat = new_data;
3473 return;
3474 }
3475
3476 /* Calculate the difference between the new and old values, and then
3477 * add it to the software stat value.
3478 */
3479 if (new_data >= *prev_stat)
3480 *cur_stat += new_data - *prev_stat;
3481 else
3482 /* to manage the potential roll-over */
3483 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
3484
3485 /* Update the previously stored value to prepare for next read */
3486 *prev_stat = new_data;
3487 }
3488
3489 /**
3490 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
3491 * @hw: ptr to the hardware info
3492 * @reg: offset of HW register to read from
3493 * @prev_stat_loaded: bool to specify if previous stats are loaded
3494 * @prev_stat: ptr to previous loaded stat value
3495 * @cur_stat: ptr to current stat value
3496 */
3497 void
ice_stat_update32(struct ice_hw * hw,u32 reg,bool prev_stat_loaded,u64 * prev_stat,u64 * cur_stat)3498 ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
3499 u64 *prev_stat, u64 *cur_stat)
3500 {
3501 u32 new_data;
3502
3503 new_data = rd32(hw, reg);
3504
3505 /* device stats are not reset at PFR, they likely will not be zeroed
3506 * when the driver starts. Thus, save the value from the first read
3507 * without adding to the statistic value so that we report stats which
3508 * count up from zero.
3509 */
3510 if (!prev_stat_loaded) {
3511 *prev_stat = new_data;
3512 return;
3513 }
3514
3515 /* Calculate the difference between the new and old values, and then
3516 * add it to the software stat value.
3517 */
3518 if (new_data >= *prev_stat)
3519 *cur_stat += new_data - *prev_stat;
3520 else
3521 /* to manage the potential roll-over */
3522 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
3523
3524 /* Update the previously stored value to prepare for next read */
3525 *prev_stat = new_data;
3526 }
3527
3528 /**
3529 * ice_sched_query_elem - query element information from HW
3530 * @hw: pointer to the HW struct
3531 * @node_teid: node TEID to be queried
3532 * @buf: buffer to element information
3533 *
3534 * This function queries HW element information
3535 */
3536 enum ice_status
ice_sched_query_elem(struct ice_hw * hw,u32 node_teid,struct ice_aqc_get_elem * buf)3537 ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
3538 struct ice_aqc_get_elem *buf)
3539 {
3540 u16 buf_size, num_elem_ret = 0;
3541 enum ice_status status;
3542
3543 buf_size = sizeof(*buf);
3544 memset(buf, 0, buf_size);
3545 buf->generic[0].node_teid = cpu_to_le32(node_teid);
3546 status = ice_aq_query_sched_elems(hw, 1, buf, buf_size, &num_elem_ret,
3547 NULL);
3548 if (status || num_elem_ret != 1)
3549 ice_debug(hw, ICE_DBG_SCHED, "query element failed\n");
3550 return status;
3551 }
3552
