1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2012 ARM Ltd.
4 */
5 #ifndef __ASM_CACHE_H
6 #define __ASM_CACHE_H
7
8 #define L1_CACHE_SHIFT (6)
9 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
10
11 #define CLIDR_LOUU_SHIFT 27
12 #define CLIDR_LOC_SHIFT 24
13 #define CLIDR_LOUIS_SHIFT 21
14
15 #define CLIDR_LOUU(clidr) (((clidr) >> CLIDR_LOUU_SHIFT) & 0x7)
16 #define CLIDR_LOC(clidr) (((clidr) >> CLIDR_LOC_SHIFT) & 0x7)
17 #define CLIDR_LOUIS(clidr) (((clidr) >> CLIDR_LOUIS_SHIFT) & 0x7)
18
19 /*
20 * Memory returned by kmalloc() may be used for DMA, so we must make
21 * sure that all such allocations are cache aligned. Otherwise,
22 * unrelated code may cause parts of the buffer to be read into the
23 * cache before the transfer is done, causing old data to be seen by
24 * the CPU.
25 */
26 #define ARCH_DMA_MINALIGN (128)
27
28 #ifndef __ASSEMBLY__
29
30 #include <linux/bitops.h>
31 #include <linux/kasan-enabled.h>
32
33 #include <asm/cputype.h>
34 #include <asm/mte-def.h>
35 #include <asm/sysreg.h>
36
37 #ifdef CONFIG_KASAN_SW_TAGS
38 #define ARCH_SLAB_MINALIGN (1ULL << KASAN_SHADOW_SCALE_SHIFT)
39 #elif defined(CONFIG_KASAN_HW_TAGS)
arch_slab_minalign(void)40 static inline unsigned int arch_slab_minalign(void)
41 {
42 return kasan_hw_tags_enabled() ? MTE_GRANULE_SIZE :
43 __alignof__(unsigned long long);
44 }
45 #define arch_slab_minalign() arch_slab_minalign()
46 #endif
47
48 #define CTR_L1IP(ctr) SYS_FIELD_GET(CTR_EL0, L1Ip, ctr)
49
50 #define ICACHEF_ALIASING 0
51 #define ICACHEF_VPIPT 1
52 extern unsigned long __icache_flags;
53
54 /*
55 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
56 * permitted in the I-cache.
57 */
icache_is_aliasing(void)58 static inline int icache_is_aliasing(void)
59 {
60 return test_bit(ICACHEF_ALIASING, &__icache_flags);
61 }
62
icache_is_vpipt(void)63 static __always_inline int icache_is_vpipt(void)
64 {
65 return test_bit(ICACHEF_VPIPT, &__icache_flags);
66 }
67
cache_type_cwg(void)68 static inline u32 cache_type_cwg(void)
69 {
70 return SYS_FIELD_GET(CTR_EL0, CWG, read_cpuid_cachetype());
71 }
72
73 #define __read_mostly __section(".data..read_mostly")
74
cache_line_size_of_cpu(void)75 static inline int cache_line_size_of_cpu(void)
76 {
77 u32 cwg = cache_type_cwg();
78
79 return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
80 }
81
82 int cache_line_size(void);
83
84 /*
85 * Read the effective value of CTR_EL0.
86 *
87 * According to ARM ARM for ARMv8-A (ARM DDI 0487C.a),
88 * section D10.2.33 "CTR_EL0, Cache Type Register" :
89 *
90 * CTR_EL0.IDC reports the data cache clean requirements for
91 * instruction to data coherence.
92 *
93 * 0 - dcache clean to PoU is required unless :
94 * (CLIDR_EL1.LoC == 0) || (CLIDR_EL1.LoUIS == 0 && CLIDR_EL1.LoUU == 0)
95 * 1 - dcache clean to PoU is not required for i-to-d coherence.
96 *
97 * This routine provides the CTR_EL0 with the IDC field updated to the
98 * effective state.
99 */
read_cpuid_effective_cachetype(void)100 static inline u32 __attribute_const__ read_cpuid_effective_cachetype(void)
101 {
102 u32 ctr = read_cpuid_cachetype();
103
104 if (!(ctr & BIT(CTR_EL0_IDC_SHIFT))) {
105 u64 clidr = read_sysreg(clidr_el1);
106
107 if (CLIDR_LOC(clidr) == 0 ||
108 (CLIDR_LOUIS(clidr) == 0 && CLIDR_LOUU(clidr) == 0))
109 ctr |= BIT(CTR_EL0_IDC_SHIFT);
110 }
111
112 return ctr;
113 }
114
115 #endif /* __ASSEMBLY__ */
116
117 #endif
118
