1 /*
2 * Copyright © 2008-2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 #include <drm/drm_vma_manager.h>
29 #include <linux/dma-fence-array.h>
30 #include <linux/kthread.h>
31 #include <linux/dma-resv.h>
32 #include <linux/shmem_fs.h>
33 #include <linux/slab.h>
34 #include <linux/stop_machine.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
38 #include <linux/mman.h>
39
40 #include "display/intel_display.h"
41 #include "display/intel_frontbuffer.h"
42
43 #include "gem/i915_gem_clflush.h"
44 #include "gem/i915_gem_context.h"
45 #include "gem/i915_gem_ioctls.h"
46 #include "gem/i915_gem_mman.h"
47 #include "gem/i915_gem_region.h"
48 #include "gt/intel_engine_user.h"
49 #include "gt/intel_gt.h"
50 #include "gt/intel_gt_pm.h"
51 #include "gt/intel_workarounds.h"
52
53 #include "i915_drv.h"
54 #include "i915_trace.h"
55 #include "i915_vgpu.h"
56
57 #include "intel_pm.h"
58
59 static int
insert_mappable_node(struct i915_ggtt * ggtt,struct drm_mm_node * node,u32 size)60 insert_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node, u32 size)
61 {
62 int err;
63
64 err = mutex_lock_interruptible(&ggtt->vm.mutex);
65 if (err)
66 return err;
67
68 memset(node, 0, sizeof(*node));
69 err = drm_mm_insert_node_in_range(&ggtt->vm.mm, node,
70 size, 0, I915_COLOR_UNEVICTABLE,
71 0, ggtt->mappable_end,
72 DRM_MM_INSERT_LOW);
73
74 mutex_unlock(&ggtt->vm.mutex);
75
76 return err;
77 }
78
79 static void
remove_mappable_node(struct i915_ggtt * ggtt,struct drm_mm_node * node)80 remove_mappable_node(struct i915_ggtt *ggtt, struct drm_mm_node *node)
81 {
82 mutex_lock(&ggtt->vm.mutex);
83 drm_mm_remove_node(node);
84 mutex_unlock(&ggtt->vm.mutex);
85 }
86
87 int
i915_gem_get_aperture_ioctl(struct drm_device * dev,void * data,struct drm_file * file)88 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
89 struct drm_file *file)
90 {
91 struct i915_ggtt *ggtt = &to_i915(dev)->ggtt;
92 struct drm_i915_gem_get_aperture *args = data;
93 struct i915_vma *vma;
94 u64 pinned;
95
96 if (mutex_lock_interruptible(&ggtt->vm.mutex))
97 return -EINTR;
98
99 pinned = ggtt->vm.reserved;
100 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link)
101 if (i915_vma_is_pinned(vma))
102 pinned += vma->node.size;
103
104 mutex_unlock(&ggtt->vm.mutex);
105
106 args->aper_size = ggtt->vm.total;
107 args->aper_available_size = args->aper_size - pinned;
108
109 return 0;
110 }
111
i915_gem_object_unbind(struct drm_i915_gem_object * obj,unsigned long flags)112 int i915_gem_object_unbind(struct drm_i915_gem_object *obj,
113 unsigned long flags)
114 {
115 struct intel_runtime_pm *rpm = &to_i915(obj->base.dev)->runtime_pm;
116 LIST_HEAD(still_in_list);
117 intel_wakeref_t wakeref;
118 struct i915_vma *vma;
119 int ret;
120
121 if (list_empty(&obj->vma.list))
122 return 0;
123
124 /*
125 * As some machines use ACPI to handle runtime-resume callbacks, and
126 * ACPI is quite kmalloc happy, we cannot resume beneath the vm->mutex
127 * as they are required by the shrinker. Ergo, we wake the device up
128 * first just in case.
129 */
130 wakeref = intel_runtime_pm_get(rpm);
131
132 try_again:
133 ret = 0;
134 spin_lock(&obj->vma.lock);
135 while (!ret && (vma = list_first_entry_or_null(&obj->vma.list,
136 struct i915_vma,
137 obj_link))) {
138 struct i915_address_space *vm = vma->vm;
139
140 list_move_tail(&vma->obj_link, &still_in_list);
141 if (!i915_vma_is_bound(vma, I915_VMA_BIND_MASK))
142 continue;
143
144 if (flags & I915_GEM_OBJECT_UNBIND_TEST) {
145 ret = -EBUSY;
146 break;
147 }
148
149 ret = -EAGAIN;
150 if (!i915_vm_tryopen(vm))
151 break;
152
153 /* Prevent vma being freed by i915_vma_parked as we unbind */
154 vma = __i915_vma_get(vma);
155 spin_unlock(&obj->vma.lock);
156
157 if (vma) {
158 ret = -EBUSY;
159 if (flags & I915_GEM_OBJECT_UNBIND_ACTIVE ||
160 !i915_vma_is_active(vma)) {
161 if (flags & I915_GEM_OBJECT_UNBIND_VM_TRYLOCK) {
162 if (mutex_trylock(&vma->vm->mutex)) {
163 ret = __i915_vma_unbind(vma);
164 mutex_unlock(&vma->vm->mutex);
165 } else {
166 ret = -EBUSY;
167 }
168 } else {
169 ret = i915_vma_unbind(vma);
170 }
171 }
172
173 __i915_vma_put(vma);
174 }
175
176 i915_vm_close(vm);
177 spin_lock(&obj->vma.lock);
178 }
179 list_splice_init(&still_in_list, &obj->vma.list);
180 spin_unlock(&obj->vma.lock);
181
182 if (ret == -EAGAIN && flags & I915_GEM_OBJECT_UNBIND_BARRIER) {
183 rcu_barrier(); /* flush the i915_vm_release() */
184 goto try_again;
185 }
186
187 intel_runtime_pm_put(rpm, wakeref);
188
189 return ret;
190 }
191
192 static int
shmem_pread(struct page * page,int offset,int len,char __user * user_data,bool needs_clflush)193 shmem_pread(struct page *page, int offset, int len, char __user *user_data,
194 bool needs_clflush)
195 {
196 char *vaddr;
197 int ret;
198
199 vaddr = kmap(page);
200
201 if (needs_clflush)
202 drm_clflush_virt_range(vaddr + offset, len);
203
204 ret = __copy_to_user(user_data, vaddr + offset, len);
205
206 kunmap(page);
207
208 return ret ? -EFAULT : 0;
209 }
210
211 static int
i915_gem_shmem_pread(struct drm_i915_gem_object * obj,struct drm_i915_gem_pread * args)212 i915_gem_shmem_pread(struct drm_i915_gem_object *obj,
213 struct drm_i915_gem_pread *args)
214 {
215 unsigned int needs_clflush;
216 unsigned int idx, offset;
217 char __user *user_data;
218 u64 remain;
219 int ret;
220
221 ret = i915_gem_object_lock_interruptible(obj, NULL);
222 if (ret)
223 return ret;
224
225 ret = i915_gem_object_pin_pages(obj);
226 if (ret)
227 goto err_unlock;
228
229 ret = i915_gem_object_prepare_read(obj, &needs_clflush);
230 if (ret)
231 goto err_unpin;
232
233 i915_gem_object_finish_access(obj);
234 i915_gem_object_unlock(obj);
235
236 remain = args->size;
237 user_data = u64_to_user_ptr(args->data_ptr);
238 offset = offset_in_page(args->offset);
239 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
240 struct page *page = i915_gem_object_get_page(obj, idx);
241 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
242
243 ret = shmem_pread(page, offset, length, user_data,
244 needs_clflush);
245 if (ret)
246 break;
247
248 remain -= length;
249 user_data += length;
250 offset = 0;
251 }
252
253 i915_gem_object_unpin_pages(obj);
254 return ret;
255
256 err_unpin:
257 i915_gem_object_unpin_pages(obj);
258 err_unlock:
259 i915_gem_object_unlock(obj);
260 return ret;
261 }
262
263 static inline bool
gtt_user_read(struct io_mapping * mapping,loff_t base,int offset,char __user * user_data,int length)264 gtt_user_read(struct io_mapping *mapping,
265 loff_t base, int offset,
266 char __user *user_data, int length)
267 {
268 void __iomem *vaddr;
269 unsigned long unwritten;
270
271 /* We can use the cpu mem copy function because this is X86. */
272 vaddr = io_mapping_map_atomic_wc(mapping, base);
273 unwritten = __copy_to_user_inatomic(user_data,
274 (void __force *)vaddr + offset,
275 length);
276 io_mapping_unmap_atomic(vaddr);
277 if (unwritten) {
278 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
279 unwritten = copy_to_user(user_data,
280 (void __force *)vaddr + offset,
281 length);
282 io_mapping_unmap(vaddr);
283 }
284 return unwritten;
285 }
286
i915_gem_gtt_prepare(struct drm_i915_gem_object * obj,struct drm_mm_node * node,bool write)287 static struct i915_vma *i915_gem_gtt_prepare(struct drm_i915_gem_object *obj,
288 struct drm_mm_node *node,
289 bool write)
290 {
291 struct drm_i915_private *i915 = to_i915(obj->base.dev);
292 struct i915_ggtt *ggtt = &i915->ggtt;
293 struct i915_vma *vma;
294 struct i915_gem_ww_ctx ww;
295 int ret;
296
297 i915_gem_ww_ctx_init(&ww, true);
298 retry:
299 vma = ERR_PTR(-ENODEV);
300 ret = i915_gem_object_lock(obj, &ww);
301 if (ret)
302 goto err_ww;
303
304 ret = i915_gem_object_set_to_gtt_domain(obj, write);
305 if (ret)
306 goto err_ww;
307
308 if (!i915_gem_object_is_tiled(obj))
309 vma = i915_gem_object_ggtt_pin_ww(obj, &ww, NULL, 0, 0,
310 PIN_MAPPABLE |
311 PIN_NONBLOCK /* NOWARN */ |
312 PIN_NOEVICT);
313 if (vma == ERR_PTR(-EDEADLK)) {
314 ret = -EDEADLK;
315 goto err_ww;
316 } else if (!IS_ERR(vma)) {
317 node->start = i915_ggtt_offset(vma);
318 node->flags = 0;
319 } else {
320 ret = insert_mappable_node(ggtt, node, PAGE_SIZE);
321 if (ret)
322 goto err_ww;
323 GEM_BUG_ON(!drm_mm_node_allocated(node));
324 vma = NULL;
325 }
326
327 ret = i915_gem_object_pin_pages(obj);
328 if (ret) {
329 if (drm_mm_node_allocated(node)) {
330 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
331 remove_mappable_node(ggtt, node);
332 } else {
333 i915_vma_unpin(vma);
334 }
335 }
336
337 err_ww:
338 if (ret == -EDEADLK) {
339 ret = i915_gem_ww_ctx_backoff(&ww);
340 if (!ret)
341 goto retry;
342 }
343 i915_gem_ww_ctx_fini(&ww);
344
345 return ret ? ERR_PTR(ret) : vma;
346 }
347
i915_gem_gtt_cleanup(struct drm_i915_gem_object * obj,struct drm_mm_node * node,struct i915_vma * vma)348 static void i915_gem_gtt_cleanup(struct drm_i915_gem_object *obj,
349 struct drm_mm_node *node,
350 struct i915_vma *vma)
351 {
352 struct drm_i915_private *i915 = to_i915(obj->base.dev);
353 struct i915_ggtt *ggtt = &i915->ggtt;
354
355 i915_gem_object_unpin_pages(obj);
356 if (drm_mm_node_allocated(node)) {
357 ggtt->vm.clear_range(&ggtt->vm, node->start, node->size);
358 remove_mappable_node(ggtt, node);
359 } else {
360 i915_vma_unpin(vma);
361 }
362 }
363
364 static int
i915_gem_gtt_pread(struct drm_i915_gem_object * obj,const struct drm_i915_gem_pread * args)365 i915_gem_gtt_pread(struct drm_i915_gem_object *obj,
366 const struct drm_i915_gem_pread *args)
367 {
368 struct drm_i915_private *i915 = to_i915(obj->base.dev);
369 struct i915_ggtt *ggtt = &i915->ggtt;
370 intel_wakeref_t wakeref;
371 struct drm_mm_node node;
372 void __user *user_data;
373 struct i915_vma *vma;
374 u64 remain, offset;
375 int ret = 0;
376
377 wakeref = intel_runtime_pm_get(&i915->runtime_pm);
378
379 vma = i915_gem_gtt_prepare(obj, &node, false);
380 if (IS_ERR(vma)) {
381 ret = PTR_ERR(vma);
382 goto out_rpm;
383 }
384
385 user_data = u64_to_user_ptr(args->data_ptr);
386 remain = args->size;
387 offset = args->offset;
388
389 while (remain > 0) {
390 /* Operation in this page
391 *
392 * page_base = page offset within aperture
393 * page_offset = offset within page
394 * page_length = bytes to copy for this page
395 */
396 u32 page_base = node.start;
397 unsigned page_offset = offset_in_page(offset);
398 unsigned page_length = PAGE_SIZE - page_offset;
399 page_length = remain < page_length ? remain : page_length;
400 if (drm_mm_node_allocated(&node)) {
401 ggtt->vm.insert_page(&ggtt->vm,
402 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
403 node.start, I915_CACHE_NONE, 0);
404 } else {
405 page_base += offset & PAGE_MASK;
406 }
407
408 if (gtt_user_read(&ggtt->iomap, page_base, page_offset,
409 user_data, page_length)) {
410 ret = -EFAULT;
411 break;
412 }
413
414 remain -= page_length;
415 user_data += page_length;
416 offset += page_length;
417 }
418
419 i915_gem_gtt_cleanup(obj, &node, vma);
420 out_rpm:
421 intel_runtime_pm_put(&i915->runtime_pm, wakeref);
422 return ret;
423 }
424
425 /**
426 * Reads data from the object referenced by handle.
427 * @dev: drm device pointer
428 * @data: ioctl data blob
429 * @file: drm file pointer
430 *
431 * On error, the contents of *data are undefined.
432 */
433 int
i915_gem_pread_ioctl(struct drm_device * dev,void * data,struct drm_file * file)434 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
435 struct drm_file *file)
436 {
437 struct drm_i915_private *i915 = to_i915(dev);
438 struct drm_i915_gem_pread *args = data;
439 struct drm_i915_gem_object *obj;
440 int ret;
441
442 /* PREAD is disallowed for all platforms after TGL-LP. This also
443 * covers all platforms with local memory.
444 */
445 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
446 return -EOPNOTSUPP;
447
448 if (args->size == 0)
449 return 0;
450
451 if (!access_ok(u64_to_user_ptr(args->data_ptr),
452 args->size))
453 return -EFAULT;
454
455 obj = i915_gem_object_lookup(file, args->handle);
456 if (!obj)
457 return -ENOENT;
458
459 /* Bounds check source. */
460 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
461 ret = -EINVAL;
462 goto out;
463 }
464
465 trace_i915_gem_object_pread(obj, args->offset, args->size);
466 ret = -ENODEV;
467 if (obj->ops->pread)
468 ret = obj->ops->pread(obj, args);
469 if (ret != -ENODEV)
470 goto out;
471
472 ret = i915_gem_object_wait(obj,
473 I915_WAIT_INTERRUPTIBLE,
474 MAX_SCHEDULE_TIMEOUT);
475 if (ret)
476 goto out;
477
478 ret = i915_gem_shmem_pread(obj, args);
479 if (ret == -EFAULT || ret == -ENODEV)
480 ret = i915_gem_gtt_pread(obj, args);
481
482 out:
483 i915_gem_object_put(obj);
484 return ret;
485 }
486
487 /* This is the fast write path which cannot handle
488 * page faults in the source data
489 */
490
491 static inline bool
ggtt_write(struct io_mapping * mapping,loff_t base,int offset,char __user * user_data,int length)492 ggtt_write(struct io_mapping *mapping,
493 loff_t base, int offset,
494 char __user *user_data, int length)
495 {
496 void __iomem *vaddr;
497 unsigned long unwritten;
498
499 /* We can use the cpu mem copy function because this is X86. */
500 vaddr = io_mapping_map_atomic_wc(mapping, base);
501 unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset,
502 user_data, length);
503 io_mapping_unmap_atomic(vaddr);
504 if (unwritten) {
505 vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE);
506 unwritten = copy_from_user((void __force *)vaddr + offset,
507 user_data, length);
508 io_mapping_unmap(vaddr);
509 }
510
511 return unwritten;
512 }
513
514 /**
515 * This is the fast pwrite path, where we copy the data directly from the
516 * user into the GTT, uncached.
517 * @obj: i915 GEM object
518 * @args: pwrite arguments structure
519 */
520 static int
i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object * obj,const struct drm_i915_gem_pwrite * args)521 i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj,
522 const struct drm_i915_gem_pwrite *args)
523 {
524 struct drm_i915_private *i915 = to_i915(obj->base.dev);
525 struct i915_ggtt *ggtt = &i915->ggtt;
526 struct intel_runtime_pm *rpm = &i915->runtime_pm;
527 intel_wakeref_t wakeref;
528 struct drm_mm_node node;
529 struct i915_vma *vma;
530 u64 remain, offset;
531 void __user *user_data;
532 int ret = 0;
533
534 if (i915_gem_object_has_struct_page(obj)) {
535 /*
536 * Avoid waking the device up if we can fallback, as
537 * waking/resuming is very slow (worst-case 10-100 ms
538 * depending on PCI sleeps and our own resume time).
539 * This easily dwarfs any performance advantage from
540 * using the cache bypass of indirect GGTT access.
541 */
542 wakeref = intel_runtime_pm_get_if_in_use(rpm);
543 if (!wakeref)
544 return -EFAULT;
545 } else {
546 /* No backing pages, no fallback, we must force GGTT access */
547 wakeref = intel_runtime_pm_get(rpm);
548 }
549
550 vma = i915_gem_gtt_prepare(obj, &node, true);
551 if (IS_ERR(vma)) {
552 ret = PTR_ERR(vma);
553 goto out_rpm;
554 }
555
556 i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
557
558 user_data = u64_to_user_ptr(args->data_ptr);
559 offset = args->offset;
560 remain = args->size;
561 while (remain) {
562 /* Operation in this page
563 *
564 * page_base = page offset within aperture
565 * page_offset = offset within page
566 * page_length = bytes to copy for this page
567 */
568 u32 page_base = node.start;
569 unsigned int page_offset = offset_in_page(offset);
570 unsigned int page_length = PAGE_SIZE - page_offset;
571 page_length = remain < page_length ? remain : page_length;
572 if (drm_mm_node_allocated(&node)) {
573 /* flush the write before we modify the GGTT */
574 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
575 ggtt->vm.insert_page(&ggtt->vm,
576 i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
577 node.start, I915_CACHE_NONE, 0);
578 wmb(); /* flush modifications to the GGTT (insert_page) */
579 } else {
580 page_base += offset & PAGE_MASK;
581 }
582 /* If we get a fault while copying data, then (presumably) our
583 * source page isn't available. Return the error and we'll
584 * retry in the slow path.
585 * If the object is non-shmem backed, we retry again with the
586 * path that handles page fault.
587 */
588 if (ggtt_write(&ggtt->iomap, page_base, page_offset,
589 user_data, page_length)) {
590 ret = -EFAULT;
591 break;
592 }
593
594 remain -= page_length;
595 user_data += page_length;
596 offset += page_length;
597 }
598
599 intel_gt_flush_ggtt_writes(ggtt->vm.gt);
600 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
601
602 i915_gem_gtt_cleanup(obj, &node, vma);
603 out_rpm:
604 intel_runtime_pm_put(rpm, wakeref);
605 return ret;
606 }
607
608 /* Per-page copy function for the shmem pwrite fastpath.
609 * Flushes invalid cachelines before writing to the target if
610 * needs_clflush_before is set and flushes out any written cachelines after
611 * writing if needs_clflush is set.
612 */
613 static int
shmem_pwrite(struct page * page,int offset,int len,char __user * user_data,bool needs_clflush_before,bool needs_clflush_after)614 shmem_pwrite(struct page *page, int offset, int len, char __user *user_data,
615 bool needs_clflush_before,
616 bool needs_clflush_after)
617 {
618 char *vaddr;
619 int ret;
620
621 vaddr = kmap(page);
622
623 if (needs_clflush_before)
624 drm_clflush_virt_range(vaddr + offset, len);
625
626 ret = __copy_from_user(vaddr + offset, user_data, len);
627 if (!ret && needs_clflush_after)
628 drm_clflush_virt_range(vaddr + offset, len);
629
630 kunmap(page);
631
632 return ret ? -EFAULT : 0;
633 }
634
635 static int
i915_gem_shmem_pwrite(struct drm_i915_gem_object * obj,const struct drm_i915_gem_pwrite * args)636 i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj,
637 const struct drm_i915_gem_pwrite *args)
638 {
639 unsigned int partial_cacheline_write;
640 unsigned int needs_clflush;
641 unsigned int offset, idx;
642 void __user *user_data;
643 u64 remain;
644 int ret;
645
646 ret = i915_gem_object_lock_interruptible(obj, NULL);
647 if (ret)
648 return ret;
649
650 ret = i915_gem_object_pin_pages(obj);
651 if (ret)
652 goto err_unlock;
653
654 ret = i915_gem_object_prepare_write(obj, &needs_clflush);
655 if (ret)
656 goto err_unpin;
657
658 i915_gem_object_finish_access(obj);
659 i915_gem_object_unlock(obj);
660
661 /* If we don't overwrite a cacheline completely we need to be
662 * careful to have up-to-date data by first clflushing. Don't
663 * overcomplicate things and flush the entire patch.
664 */
665 partial_cacheline_write = 0;
666 if (needs_clflush & CLFLUSH_BEFORE)
667 partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;
668
669 user_data = u64_to_user_ptr(args->data_ptr);
670 remain = args->size;
671 offset = offset_in_page(args->offset);
672 for (idx = args->offset >> PAGE_SHIFT; remain; idx++) {
673 struct page *page = i915_gem_object_get_page(obj, idx);
674 unsigned int length = min_t(u64, remain, PAGE_SIZE - offset);
675
676 ret = shmem_pwrite(page, offset, length, user_data,
677 (offset | length) & partial_cacheline_write,
678 needs_clflush & CLFLUSH_AFTER);
679 if (ret)
680 break;
681
682 remain -= length;
683 user_data += length;
684 offset = 0;
685 }
686
687 i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
688
689 i915_gem_object_unpin_pages(obj);
690 return ret;
691
692 err_unpin:
693 i915_gem_object_unpin_pages(obj);
694 err_unlock:
695 i915_gem_object_unlock(obj);
696 return ret;
697 }
698
699 /**
700 * Writes data to the object referenced by handle.
701 * @dev: drm device
702 * @data: ioctl data blob
703 * @file: drm file
704 *
705 * On error, the contents of the buffer that were to be modified are undefined.
706 */
707 int
i915_gem_pwrite_ioctl(struct drm_device * dev,void * data,struct drm_file * file)708 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
709 struct drm_file *file)
710 {
711 struct drm_i915_private *i915 = to_i915(dev);
712 struct drm_i915_gem_pwrite *args = data;
713 struct drm_i915_gem_object *obj;
714 int ret;
715
716 /* PWRITE is disallowed for all platforms after TGL-LP. This also
717 * covers all platforms with local memory.
718 */
719 if (GRAPHICS_VER(i915) >= 12 && !IS_TIGERLAKE(i915))
720 return -EOPNOTSUPP;
721
722 if (args->size == 0)
723 return 0;
724
725 if (!access_ok(u64_to_user_ptr(args->data_ptr), args->size))
726 return -EFAULT;
727
728 obj = i915_gem_object_lookup(file, args->handle);
729 if (!obj)
730 return -ENOENT;
731
732 /* Bounds check destination. */
733 if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) {
734 ret = -EINVAL;
735 goto err;
736 }
737
738 /* Writes not allowed into this read-only object */
739 if (i915_gem_object_is_readonly(obj)) {
740 ret = -EINVAL;
741 goto err;
742 }
743
744 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
745
746 ret = -ENODEV;
747 if (obj->ops->pwrite)
748 ret = obj->ops->pwrite(obj, args);
749 if (ret != -ENODEV)
750 goto err;
751
752 ret = i915_gem_object_wait(obj,
753 I915_WAIT_INTERRUPTIBLE |
754 I915_WAIT_ALL,
755 MAX_SCHEDULE_TIMEOUT);
756 if (ret)
757 goto err;
758
759 ret = -EFAULT;
760 /* We can only do the GTT pwrite on untiled buffers, as otherwise
761 * it would end up going through the fenced access, and we'll get
762 * different detiling behavior between reading and writing.
763 * pread/pwrite currently are reading and writing from the CPU
764 * perspective, requiring manual detiling by the client.
765 */
766 if (!i915_gem_object_has_struct_page(obj) ||
767 cpu_write_needs_clflush(obj))
768 /* Note that the gtt paths might fail with non-page-backed user
769 * pointers (e.g. gtt mappings when moving data between
770 * textures). Fallback to the shmem path in that case.
771 */
772 ret = i915_gem_gtt_pwrite_fast(obj, args);
773
774 if (ret == -EFAULT || ret == -ENOSPC) {
775 if (i915_gem_object_has_struct_page(obj))
776 ret = i915_gem_shmem_pwrite(obj, args);
777 }
778
779 err:
780 i915_gem_object_put(obj);
781 return ret;
782 }
783
784 /**
785 * Called when user space has done writes to this buffer
786 * @dev: drm device
787 * @data: ioctl data blob
788 * @file: drm file
789 */
790 int
i915_gem_sw_finish_ioctl(struct drm_device * dev,void * data,struct drm_file * file)791 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
792 struct drm_file *file)
793 {
794 struct drm_i915_gem_sw_finish *args = data;
795 struct drm_i915_gem_object *obj;
796
797 obj = i915_gem_object_lookup(file, args->handle);
798 if (!obj)
799 return -ENOENT;
800
801 /*
802 * Proxy objects are barred from CPU access, so there is no
803 * need to ban sw_finish as it is a nop.
804 */
805
806 /* Pinned buffers may be scanout, so flush the cache */
807 i915_gem_object_flush_if_display(obj);
808 i915_gem_object_put(obj);
809
810 return 0;
811 }
812
i915_gem_runtime_suspend(struct drm_i915_private * i915)813 void i915_gem_runtime_suspend(struct drm_i915_private *i915)
814 {
815 struct drm_i915_gem_object *obj, *on;
816 int i;
817
818 /*
819 * Only called during RPM suspend. All users of the userfault_list
820 * must be holding an RPM wakeref to ensure that this can not
821 * run concurrently with themselves (and use the struct_mutex for
822 * protection between themselves).
823 */
824
825 list_for_each_entry_safe(obj, on,
826 &i915->ggtt.userfault_list, userfault_link)
827 __i915_gem_object_release_mmap_gtt(obj);
828
829 /*
830 * The fence will be lost when the device powers down. If any were
831 * in use by hardware (i.e. they are pinned), we should not be powering
832 * down! All other fences will be reacquired by the user upon waking.
833 */
834 for (i = 0; i < i915->ggtt.num_fences; i++) {
835 struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
836
837 /*
838 * Ideally we want to assert that the fence register is not
839 * live at this point (i.e. that no piece of code will be
840 * trying to write through fence + GTT, as that both violates
841 * our tracking of activity and associated locking/barriers,
842 * but also is illegal given that the hw is powered down).
843 *
844 * Previously we used reg->pin_count as a "liveness" indicator.
845 * That is not sufficient, and we need a more fine-grained
846 * tool if we want to have a sanity check here.
847 */
848
849 if (!reg->vma)
850 continue;
851
852 GEM_BUG_ON(i915_vma_has_userfault(reg->vma));
853 reg->dirty = true;
854 }
855 }
856
discard_ggtt_vma(struct i915_vma * vma)857 static void discard_ggtt_vma(struct i915_vma *vma)
858 {
859 struct drm_i915_gem_object *obj = vma->obj;
860
861 spin_lock(&obj->vma.lock);
862 if (!RB_EMPTY_NODE(&vma->obj_node)) {
863 rb_erase(&vma->obj_node, &obj->vma.tree);
864 RB_CLEAR_NODE(&vma->obj_node);
865 }
866 spin_unlock(&obj->vma.lock);
867 }
868
869 struct i915_vma *
i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object * obj,struct i915_gem_ww_ctx * ww,const struct i915_ggtt_view * view,u64 size,u64 alignment,u64 flags)870 i915_gem_object_ggtt_pin_ww(struct drm_i915_gem_object *obj,
871 struct i915_gem_ww_ctx *ww,
872 const struct i915_ggtt_view *view,
873 u64 size, u64 alignment, u64 flags)
874 {
875 struct drm_i915_private *i915 = to_i915(obj->base.dev);
876 struct i915_ggtt *ggtt = &i915->ggtt;
877 struct i915_vma *vma;
878 int ret;
879
880 if (flags & PIN_MAPPABLE &&
881 (!view || view->type == I915_GGTT_VIEW_NORMAL)) {
882 /*
883 * If the required space is larger than the available
884 * aperture, we will not able to find a slot for the
885 * object and unbinding the object now will be in
886 * vain. Worse, doing so may cause us to ping-pong
887 * the object in and out of the Global GTT and
888 * waste a lot of cycles under the mutex.
889 */
890 if (obj->base.size > ggtt->mappable_end)
891 return ERR_PTR(-E2BIG);
892
893 /*
894 * If NONBLOCK is set the caller is optimistically
895 * trying to cache the full object within the mappable
896 * aperture, and *must* have a fallback in place for
897 * situations where we cannot bind the object. We
898 * can be a little more lax here and use the fallback
899 * more often to avoid costly migrations of ourselves
900 * and other objects within the aperture.
901 *
902 * Half-the-aperture is used as a simple heuristic.
903 * More interesting would to do search for a free
904 * block prior to making the commitment to unbind.
905 * That caters for the self-harm case, and with a
906 * little more heuristics (e.g. NOFAULT, NOEVICT)
907 * we could try to minimise harm to others.
908 */
909 if (flags & PIN_NONBLOCK &&
910 obj->base.size > ggtt->mappable_end / 2)
911 return ERR_PTR(-ENOSPC);
912 }
913
914 new_vma:
915 vma = i915_vma_instance(obj, &ggtt->vm, view);
916 if (IS_ERR(vma))
917 return vma;
918
919 if (i915_vma_misplaced(vma, size, alignment, flags)) {
920 if (flags & PIN_NONBLOCK) {
921 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))
922 return ERR_PTR(-ENOSPC);
923
924 if (flags & PIN_MAPPABLE &&
925 vma->fence_size > ggtt->mappable_end / 2)
926 return ERR_PTR(-ENOSPC);
927 }
928
929 if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) {
930 discard_ggtt_vma(vma);
931 goto new_vma;
932 }
933
934 ret = i915_vma_unbind(vma);
935 if (ret)
936 return ERR_PTR(ret);
937 }
938
939 if (ww)
940 ret = i915_vma_pin_ww(vma, ww, size, alignment, flags | PIN_GLOBAL);
941 else
942 ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL);
943
944 if (ret)
945 return ERR_PTR(ret);
946
947 if (vma->fence && !i915_gem_object_is_tiled(obj)) {
948 mutex_lock(&ggtt->vm.mutex);
949 i915_vma_revoke_fence(vma);
950 mutex_unlock(&ggtt->vm.mutex);
951 }
952
953 ret = i915_vma_wait_for_bind(vma);
954 if (ret) {
955 i915_vma_unpin(vma);
956 return ERR_PTR(ret);
957 }
958
959 return vma;
960 }
961
962 int
i915_gem_madvise_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)963 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
964 struct drm_file *file_priv)
965 {
966 struct drm_i915_private *i915 = to_i915(dev);
967 struct drm_i915_gem_madvise *args = data;
968 struct drm_i915_gem_object *obj;
969 int err;
970
971 switch (args->madv) {
972 case I915_MADV_DONTNEED:
973 case I915_MADV_WILLNEED:
974 break;
975 default:
976 return -EINVAL;
977 }
978
979 obj = i915_gem_object_lookup(file_priv, args->handle);
980 if (!obj)
981 return -ENOENT;
982
983 err = i915_gem_object_lock_interruptible(obj, NULL);
984 if (err)
985 goto out;
986
987 if (i915_gem_object_has_pages(obj) &&
988 i915_gem_object_is_tiled(obj) &&
989 i915->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
990 if (obj->mm.madv == I915_MADV_WILLNEED) {
991 GEM_BUG_ON(!i915_gem_object_has_tiling_quirk(obj));
992 i915_gem_object_clear_tiling_quirk(obj);
993 i915_gem_object_make_shrinkable(obj);
994 }
995 if (args->madv == I915_MADV_WILLNEED) {
996 GEM_BUG_ON(i915_gem_object_has_tiling_quirk(obj));
997 i915_gem_object_make_unshrinkable(obj);
998 i915_gem_object_set_tiling_quirk(obj);
999 }
1000 }
1001
1002 if (obj->mm.madv != __I915_MADV_PURGED) {
1003 obj->mm.madv = args->madv;
1004 if (obj->ops->adjust_lru)
1005 obj->ops->adjust_lru(obj);
1006 }
1007
1008 if (i915_gem_object_has_pages(obj)) {
1009 unsigned long flags;
1010
1011 spin_lock_irqsave(&i915->mm.obj_lock, flags);
1012 if (!list_empty(&obj->mm.link)) {
1013 struct list_head *list;
1014
1015 if (obj->mm.madv != I915_MADV_WILLNEED)
1016 list = &i915->mm.purge_list;
1017 else
1018 list = &i915->mm.shrink_list;
1019 list_move_tail(&obj->mm.link, list);
1020
1021 }
1022 spin_unlock_irqrestore(&i915->mm.obj_lock, flags);
1023 }
1024
1025 /* if the object is no longer attached, discard its backing storage */
1026 if (obj->mm.madv == I915_MADV_DONTNEED &&
1027 !i915_gem_object_has_pages(obj))
1028 i915_gem_object_truncate(obj);
1029
1030 args->retained = obj->mm.madv != __I915_MADV_PURGED;
1031
1032 i915_gem_object_unlock(obj);
1033 out:
1034 i915_gem_object_put(obj);
1035 return err;
1036 }
1037
i915_gem_init(struct drm_i915_private * dev_priv)1038 int i915_gem_init(struct drm_i915_private *dev_priv)
1039 {
1040 int ret;
1041
1042 /* We need to fallback to 4K pages if host doesn't support huge gtt. */
1043 if (intel_vgpu_active(dev_priv) && !intel_vgpu_has_huge_gtt(dev_priv))
1044 mkwrite_device_info(dev_priv)->page_sizes =
1045 I915_GTT_PAGE_SIZE_4K;
1046
1047 ret = i915_gem_init_userptr(dev_priv);
1048 if (ret)
1049 return ret;
1050
1051 intel_uc_fetch_firmwares(&dev_priv->gt.uc);
1052 intel_wopcm_init(&dev_priv->wopcm);
1053
1054 ret = i915_init_ggtt(dev_priv);
1055 if (ret) {
1056 GEM_BUG_ON(ret == -EIO);
1057 goto err_unlock;
1058 }
1059
1060 /*
1061 * Despite its name intel_init_clock_gating applies both display
1062 * clock gating workarounds; GT mmio workarounds and the occasional
1063 * GT power context workaround. Worse, sometimes it includes a context
1064 * register workaround which we need to apply before we record the
1065 * default HW state for all contexts.
1066 *
1067 * FIXME: break up the workarounds and apply them at the right time!
1068 */
1069 intel_init_clock_gating(dev_priv);
1070
1071 ret = intel_gt_init(&dev_priv->gt);
1072 if (ret)
1073 goto err_unlock;
1074
1075 return 0;
1076
1077 /*
1078 * Unwinding is complicated by that we want to handle -EIO to mean
1079 * disable GPU submission but keep KMS alive. We want to mark the
1080 * HW as irrevisibly wedged, but keep enough state around that the
1081 * driver doesn't explode during runtime.
1082 */
1083 err_unlock:
1084 i915_gem_drain_workqueue(dev_priv);
1085
1086 if (ret != -EIO)
1087 intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
1088
1089 if (ret == -EIO) {
1090 /*
1091 * Allow engines or uC initialisation to fail by marking the GPU
1092 * as wedged. But we only want to do this when the GPU is angry,
1093 * for all other failure, such as an allocation failure, bail.
1094 */
1095 if (!intel_gt_is_wedged(&dev_priv->gt)) {
1096 i915_probe_error(dev_priv,
1097 "Failed to initialize GPU, declaring it wedged!\n");
1098 intel_gt_set_wedged(&dev_priv->gt);
1099 }
1100
1101 /* Minimal basic recovery for KMS */
1102 ret = i915_ggtt_enable_hw(dev_priv);
1103 i915_ggtt_resume(&dev_priv->ggtt);
1104 intel_init_clock_gating(dev_priv);
1105 }
1106
1107 i915_gem_drain_freed_objects(dev_priv);
1108
1109 return ret;
1110 }
1111
i915_gem_driver_register(struct drm_i915_private * i915)1112 void i915_gem_driver_register(struct drm_i915_private *i915)
1113 {
1114 i915_gem_driver_register__shrinker(i915);
1115
1116 intel_engines_driver_register(i915);
1117 }
1118
i915_gem_driver_unregister(struct drm_i915_private * i915)1119 void i915_gem_driver_unregister(struct drm_i915_private *i915)
1120 {
1121 i915_gem_driver_unregister__shrinker(i915);
1122 }
1123
i915_gem_driver_remove(struct drm_i915_private * dev_priv)1124 void i915_gem_driver_remove(struct drm_i915_private *dev_priv)
1125 {
1126 intel_wakeref_auto_fini(&dev_priv->ggtt.userfault_wakeref);
1127
1128 i915_gem_suspend_late(dev_priv);
1129 intel_gt_driver_remove(&dev_priv->gt);
1130 dev_priv->uabi_engines = RB_ROOT;
1131
1132 /* Flush any outstanding unpin_work. */
1133 i915_gem_drain_workqueue(dev_priv);
1134
1135 i915_gem_drain_freed_objects(dev_priv);
1136 }
1137
i915_gem_driver_release(struct drm_i915_private * dev_priv)1138 void i915_gem_driver_release(struct drm_i915_private *dev_priv)
1139 {
1140 intel_gt_driver_release(&dev_priv->gt);
1141
1142 intel_wa_list_free(&dev_priv->gt_wa_list);
1143
1144 intel_uc_cleanup_firmwares(&dev_priv->gt.uc);
1145
1146 i915_gem_drain_freed_objects(dev_priv);
1147
1148 drm_WARN_ON(&dev_priv->drm, !list_empty(&dev_priv->gem.contexts.list));
1149 }
1150
i915_gem_init__mm(struct drm_i915_private * i915)1151 static void i915_gem_init__mm(struct drm_i915_private *i915)
1152 {
1153 spin_lock_init(&i915->mm.obj_lock);
1154
1155 init_llist_head(&i915->mm.free_list);
1156
1157 INIT_LIST_HEAD(&i915->mm.purge_list);
1158 INIT_LIST_HEAD(&i915->mm.shrink_list);
1159
1160 i915_gem_init__objects(i915);
1161 }
1162
i915_gem_init_early(struct drm_i915_private * dev_priv)1163 void i915_gem_init_early(struct drm_i915_private *dev_priv)
1164 {
1165 i915_gem_init__mm(dev_priv);
1166 i915_gem_init__contexts(dev_priv);
1167
1168 spin_lock_init(&dev_priv->fb_tracking.lock);
1169 }
1170
i915_gem_cleanup_early(struct drm_i915_private * dev_priv)1171 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
1172 {
1173 i915_gem_drain_freed_objects(dev_priv);
1174 GEM_BUG_ON(!llist_empty(&dev_priv->mm.free_list));
1175 GEM_BUG_ON(atomic_read(&dev_priv->mm.free_count));
1176 drm_WARN_ON(&dev_priv->drm, dev_priv->mm.shrink_count);
1177 }
1178
i915_gem_open(struct drm_i915_private * i915,struct drm_file * file)1179 int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
1180 {
1181 struct drm_i915_file_private *file_priv;
1182 int ret;
1183
1184 DRM_DEBUG("\n");
1185
1186 file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
1187 if (!file_priv)
1188 return -ENOMEM;
1189
1190 file->driver_priv = file_priv;
1191 file_priv->dev_priv = i915;
1192 file_priv->file = file;
1193
1194 file_priv->bsd_engine = -1;
1195 file_priv->hang_timestamp = jiffies;
1196
1197 ret = i915_gem_context_open(i915, file);
1198 if (ret)
1199 kfree(file_priv);
1200
1201 return ret;
1202 }
1203
1204 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1205 #include "selftests/mock_gem_device.c"
1206 #include "selftests/i915_gem.c"
1207 #endif
1208
