1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include <drm/intel_lpe_audio.h>
28 #include "intel_drv.h"
29
30 #include <drm/drmP.h>
31 #include <drm/drm_edid.h>
32 #include "i915_drv.h"
33
34 /**
35 * DOC: High Definition Audio over HDMI and Display Port
36 *
37 * The graphics and audio drivers together support High Definition Audio over
38 * HDMI and Display Port. The audio programming sequences are divided into audio
39 * codec and controller enable and disable sequences. The graphics driver
40 * handles the audio codec sequences, while the audio driver handles the audio
41 * controller sequences.
42 *
43 * The disable sequences must be performed before disabling the transcoder or
44 * port. The enable sequences may only be performed after enabling the
45 * transcoder and port, and after completed link training. Therefore the audio
46 * enable/disable sequences are part of the modeset sequence.
47 *
48 * The codec and controller sequences could be done either parallel or serial,
49 * but generally the ELDV/PD change in the codec sequence indicates to the audio
50 * driver that the controller sequence should start. Indeed, most of the
51 * co-operation between the graphics and audio drivers is handled via audio
52 * related registers. (The notable exception is the power management, not
53 * covered here.)
54 *
55 * The struct &i915_audio_component is used to interact between the graphics
56 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
57 * defined in graphics driver and called in audio driver. The
58 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
59 */
60
61 /* DP N/M table */
62 #define LC_810M 810000
63 #define LC_540M 540000
64 #define LC_270M 270000
65 #define LC_162M 162000
66
67 struct dp_aud_n_m {
68 int sample_rate;
69 int clock;
70 u16 m;
71 u16 n;
72 };
73
74 /* Values according to DP 1.4 Table 2-104 */
75 static const struct dp_aud_n_m dp_aud_n_m[] = {
76 { 32000, LC_162M, 1024, 10125 },
77 { 44100, LC_162M, 784, 5625 },
78 { 48000, LC_162M, 512, 3375 },
79 { 64000, LC_162M, 2048, 10125 },
80 { 88200, LC_162M, 1568, 5625 },
81 { 96000, LC_162M, 1024, 3375 },
82 { 128000, LC_162M, 4096, 10125 },
83 { 176400, LC_162M, 3136, 5625 },
84 { 192000, LC_162M, 2048, 3375 },
85 { 32000, LC_270M, 1024, 16875 },
86 { 44100, LC_270M, 784, 9375 },
87 { 48000, LC_270M, 512, 5625 },
88 { 64000, LC_270M, 2048, 16875 },
89 { 88200, LC_270M, 1568, 9375 },
90 { 96000, LC_270M, 1024, 5625 },
91 { 128000, LC_270M, 4096, 16875 },
92 { 176400, LC_270M, 3136, 9375 },
93 { 192000, LC_270M, 2048, 5625 },
94 { 32000, LC_540M, 1024, 33750 },
95 { 44100, LC_540M, 784, 18750 },
96 { 48000, LC_540M, 512, 11250 },
97 { 64000, LC_540M, 2048, 33750 },
98 { 88200, LC_540M, 1568, 18750 },
99 { 96000, LC_540M, 1024, 11250 },
100 { 128000, LC_540M, 4096, 33750 },
101 { 176400, LC_540M, 3136, 18750 },
102 { 192000, LC_540M, 2048, 11250 },
103 { 32000, LC_810M, 1024, 50625 },
104 { 44100, LC_810M, 784, 28125 },
105 { 48000, LC_810M, 512, 16875 },
106 { 64000, LC_810M, 2048, 50625 },
107 { 88200, LC_810M, 1568, 28125 },
108 { 96000, LC_810M, 1024, 16875 },
109 { 128000, LC_810M, 4096, 50625 },
110 { 176400, LC_810M, 3136, 28125 },
111 { 192000, LC_810M, 2048, 16875 },
112 };
113
114 static const struct dp_aud_n_m *
audio_config_dp_get_n_m(const struct intel_crtc_state * crtc_state,int rate)115 audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate)
116 {
117 int i;
118
119 for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) {
120 if (rate == dp_aud_n_m[i].sample_rate &&
121 crtc_state->port_clock == dp_aud_n_m[i].clock)
122 return &dp_aud_n_m[i];
123 }
124
125 return NULL;
126 }
127
128 static const struct {
129 int clock;
130 u32 config;
131 } hdmi_audio_clock[] = {
132 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
133 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
134 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
135 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
136 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
137 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
138 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
139 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
140 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
141 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
142 };
143
144 /* HDMI N/CTS table */
145 #define TMDS_297M 297000
146 #define TMDS_296M 296703
147 static const struct {
148 int sample_rate;
149 int clock;
150 int n;
151 int cts;
152 } hdmi_aud_ncts[] = {
153 { 44100, TMDS_296M, 4459, 234375 },
154 { 44100, TMDS_297M, 4704, 247500 },
155 { 48000, TMDS_296M, 5824, 281250 },
156 { 48000, TMDS_297M, 5120, 247500 },
157 { 32000, TMDS_296M, 5824, 421875 },
158 { 32000, TMDS_297M, 3072, 222750 },
159 { 88200, TMDS_296M, 8918, 234375 },
160 { 88200, TMDS_297M, 9408, 247500 },
161 { 96000, TMDS_296M, 11648, 281250 },
162 { 96000, TMDS_297M, 10240, 247500 },
163 { 176400, TMDS_296M, 17836, 234375 },
164 { 176400, TMDS_297M, 18816, 247500 },
165 { 192000, TMDS_296M, 23296, 281250 },
166 { 192000, TMDS_297M, 20480, 247500 },
167 };
168
169 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
audio_config_hdmi_pixel_clock(const struct intel_crtc_state * crtc_state)170 static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state)
171 {
172 const struct drm_display_mode *adjusted_mode =
173 &crtc_state->base.adjusted_mode;
174 int i;
175
176 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
177 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
178 break;
179 }
180
181 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
182 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
183 adjusted_mode->crtc_clock);
184 i = 1;
185 }
186
187 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
188 hdmi_audio_clock[i].clock,
189 hdmi_audio_clock[i].config);
190
191 return hdmi_audio_clock[i].config;
192 }
193
audio_config_hdmi_get_n(const struct intel_crtc_state * crtc_state,int rate)194 static int audio_config_hdmi_get_n(const struct intel_crtc_state *crtc_state,
195 int rate)
196 {
197 const struct drm_display_mode *adjusted_mode =
198 &crtc_state->base.adjusted_mode;
199 int i;
200
201 for (i = 0; i < ARRAY_SIZE(hdmi_aud_ncts); i++) {
202 if (rate == hdmi_aud_ncts[i].sample_rate &&
203 adjusted_mode->crtc_clock == hdmi_aud_ncts[i].clock) {
204 return hdmi_aud_ncts[i].n;
205 }
206 }
207 return 0;
208 }
209
intel_eld_uptodate(struct drm_connector * connector,i915_reg_t reg_eldv,u32 bits_eldv,i915_reg_t reg_elda,u32 bits_elda,i915_reg_t reg_edid)210 static bool intel_eld_uptodate(struct drm_connector *connector,
211 i915_reg_t reg_eldv, u32 bits_eldv,
212 i915_reg_t reg_elda, u32 bits_elda,
213 i915_reg_t reg_edid)
214 {
215 struct drm_i915_private *dev_priv = to_i915(connector->dev);
216 const u8 *eld = connector->eld;
217 u32 tmp;
218 int i;
219
220 tmp = I915_READ(reg_eldv);
221 tmp &= bits_eldv;
222
223 if (!tmp)
224 return false;
225
226 tmp = I915_READ(reg_elda);
227 tmp &= ~bits_elda;
228 I915_WRITE(reg_elda, tmp);
229
230 for (i = 0; i < drm_eld_size(eld) / 4; i++)
231 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
232 return false;
233
234 return true;
235 }
236
g4x_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)237 static void g4x_audio_codec_disable(struct intel_encoder *encoder,
238 const struct intel_crtc_state *old_crtc_state,
239 const struct drm_connector_state *old_conn_state)
240 {
241 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
242 u32 eldv, tmp;
243
244 DRM_DEBUG_KMS("Disable audio codec\n");
245
246 tmp = I915_READ(G4X_AUD_VID_DID);
247 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
248 eldv = G4X_ELDV_DEVCL_DEVBLC;
249 else
250 eldv = G4X_ELDV_DEVCTG;
251
252 /* Invalidate ELD */
253 tmp = I915_READ(G4X_AUD_CNTL_ST);
254 tmp &= ~eldv;
255 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
256 }
257
g4x_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)258 static void g4x_audio_codec_enable(struct intel_encoder *encoder,
259 const struct intel_crtc_state *crtc_state,
260 const struct drm_connector_state *conn_state)
261 {
262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
263 struct drm_connector *connector = conn_state->connector;
264 const u8 *eld = connector->eld;
265 u32 eldv;
266 u32 tmp;
267 int len, i;
268
269 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", drm_eld_size(eld));
270
271 tmp = I915_READ(G4X_AUD_VID_DID);
272 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
273 eldv = G4X_ELDV_DEVCL_DEVBLC;
274 else
275 eldv = G4X_ELDV_DEVCTG;
276
277 if (intel_eld_uptodate(connector,
278 G4X_AUD_CNTL_ST, eldv,
279 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
280 G4X_HDMIW_HDMIEDID))
281 return;
282
283 tmp = I915_READ(G4X_AUD_CNTL_ST);
284 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
285 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
286 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
287
288 len = min(drm_eld_size(eld) / 4, len);
289 DRM_DEBUG_DRIVER("ELD size %d\n", len);
290 for (i = 0; i < len; i++)
291 I915_WRITE(G4X_HDMIW_HDMIEDID, *((const u32 *)eld + i));
292
293 tmp = I915_READ(G4X_AUD_CNTL_ST);
294 tmp |= eldv;
295 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
296 }
297
298 static void
hsw_dp_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)299 hsw_dp_audio_config_update(struct intel_encoder *encoder,
300 const struct intel_crtc_state *crtc_state)
301 {
302 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
303 struct i915_audio_component *acomp = dev_priv->audio_component;
304 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
305 enum port port = encoder->port;
306 enum pipe pipe = crtc->pipe;
307 const struct dp_aud_n_m *nm;
308 int rate;
309 u32 tmp;
310
311 rate = acomp ? acomp->aud_sample_rate[port] : 0;
312 nm = audio_config_dp_get_n_m(crtc_state, rate);
313 if (nm)
314 DRM_DEBUG_KMS("using Maud %u, Naud %u\n", nm->m, nm->n);
315 else
316 DRM_DEBUG_KMS("using automatic Maud, Naud\n");
317
318 tmp = I915_READ(HSW_AUD_CFG(pipe));
319 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
320 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
321 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
322 tmp |= AUD_CONFIG_N_VALUE_INDEX;
323
324 if (nm) {
325 tmp &= ~AUD_CONFIG_N_MASK;
326 tmp |= AUD_CONFIG_N(nm->n);
327 tmp |= AUD_CONFIG_N_PROG_ENABLE;
328 }
329
330 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
331
332 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
333 tmp &= ~AUD_CONFIG_M_MASK;
334 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
335 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
336
337 if (nm) {
338 tmp |= nm->m;
339 tmp |= AUD_M_CTS_M_VALUE_INDEX;
340 tmp |= AUD_M_CTS_M_PROG_ENABLE;
341 }
342
343 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
344 }
345
346 static void
hsw_hdmi_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)347 hsw_hdmi_audio_config_update(struct intel_encoder *encoder,
348 const struct intel_crtc_state *crtc_state)
349 {
350 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
351 struct i915_audio_component *acomp = dev_priv->audio_component;
352 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
353 enum port port = encoder->port;
354 enum pipe pipe = crtc->pipe;
355 int n, rate;
356 u32 tmp;
357
358 rate = acomp ? acomp->aud_sample_rate[port] : 0;
359
360 tmp = I915_READ(HSW_AUD_CFG(pipe));
361 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
362 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
363 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
364 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
365
366 n = audio_config_hdmi_get_n(crtc_state, rate);
367 if (n != 0) {
368 DRM_DEBUG_KMS("using N %d\n", n);
369
370 tmp &= ~AUD_CONFIG_N_MASK;
371 tmp |= AUD_CONFIG_N(n);
372 tmp |= AUD_CONFIG_N_PROG_ENABLE;
373 } else {
374 DRM_DEBUG_KMS("using automatic N\n");
375 }
376
377 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
378
379 /*
380 * Let's disable "Enable CTS or M Prog bit"
381 * and let HW calculate the value
382 */
383 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe));
384 tmp &= ~AUD_M_CTS_M_PROG_ENABLE;
385 tmp &= ~AUD_M_CTS_M_VALUE_INDEX;
386 I915_WRITE(HSW_AUD_M_CTS_ENABLE(pipe), tmp);
387 }
388
389 static void
hsw_audio_config_update(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)390 hsw_audio_config_update(struct intel_encoder *encoder,
391 const struct intel_crtc_state *crtc_state)
392 {
393 if (intel_crtc_has_dp_encoder(crtc_state))
394 hsw_dp_audio_config_update(encoder, crtc_state);
395 else
396 hsw_hdmi_audio_config_update(encoder, crtc_state);
397 }
398
hsw_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)399 static void hsw_audio_codec_disable(struct intel_encoder *encoder,
400 const struct intel_crtc_state *old_crtc_state,
401 const struct drm_connector_state *old_conn_state)
402 {
403 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
404 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
405 enum pipe pipe = crtc->pipe;
406 u32 tmp;
407
408 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
409
410 mutex_lock(&dev_priv->av_mutex);
411
412 /* Disable timestamps */
413 tmp = I915_READ(HSW_AUD_CFG(pipe));
414 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
415 tmp |= AUD_CONFIG_N_PROG_ENABLE;
416 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
417 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
418 if (intel_crtc_has_dp_encoder(old_crtc_state))
419 tmp |= AUD_CONFIG_N_VALUE_INDEX;
420 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
421
422 /* Invalidate ELD */
423 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
424 tmp &= ~AUDIO_ELD_VALID(pipe);
425 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
426 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
427
428 mutex_unlock(&dev_priv->av_mutex);
429 }
430
hsw_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)431 static void hsw_audio_codec_enable(struct intel_encoder *encoder,
432 const struct intel_crtc_state *crtc_state,
433 const struct drm_connector_state *conn_state)
434 {
435 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
436 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
437 struct drm_connector *connector = conn_state->connector;
438 enum pipe pipe = crtc->pipe;
439 const u8 *eld = connector->eld;
440 u32 tmp;
441 int len, i;
442
443 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
444 pipe_name(pipe), drm_eld_size(eld));
445
446 mutex_lock(&dev_priv->av_mutex);
447
448 /* Enable audio presence detect, invalidate ELD */
449 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
450 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
451 tmp &= ~AUDIO_ELD_VALID(pipe);
452 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
453
454 /*
455 * FIXME: We're supposed to wait for vblank here, but we have vblanks
456 * disabled during the mode set. The proper fix would be to push the
457 * rest of the setup into a vblank work item, queued here, but the
458 * infrastructure is not there yet.
459 */
460
461 /* Reset ELD write address */
462 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
463 tmp &= ~IBX_ELD_ADDRESS_MASK;
464 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
465
466 /* Up to 84 bytes of hw ELD buffer */
467 len = min(drm_eld_size(eld), 84);
468 for (i = 0; i < len / 4; i++)
469 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((const u32 *)eld + i));
470
471 /* ELD valid */
472 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
473 tmp |= AUDIO_ELD_VALID(pipe);
474 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
475
476 /* Enable timestamps */
477 hsw_audio_config_update(encoder, crtc_state);
478
479 mutex_unlock(&dev_priv->av_mutex);
480 }
481
ilk_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)482 static void ilk_audio_codec_disable(struct intel_encoder *encoder,
483 const struct intel_crtc_state *old_crtc_state,
484 const struct drm_connector_state *old_conn_state)
485 {
486 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
487 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
488 enum pipe pipe = crtc->pipe;
489 enum port port = encoder->port;
490 u32 tmp, eldv;
491 i915_reg_t aud_config, aud_cntrl_st2;
492
493 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
494 port_name(port), pipe_name(pipe));
495
496 if (WARN_ON(port == PORT_A))
497 return;
498
499 if (HAS_PCH_IBX(dev_priv)) {
500 aud_config = IBX_AUD_CFG(pipe);
501 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
502 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
503 aud_config = VLV_AUD_CFG(pipe);
504 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
505 } else {
506 aud_config = CPT_AUD_CFG(pipe);
507 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
508 }
509
510 /* Disable timestamps */
511 tmp = I915_READ(aud_config);
512 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
513 tmp |= AUD_CONFIG_N_PROG_ENABLE;
514 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
515 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
516 if (intel_crtc_has_dp_encoder(old_crtc_state))
517 tmp |= AUD_CONFIG_N_VALUE_INDEX;
518 I915_WRITE(aud_config, tmp);
519
520 eldv = IBX_ELD_VALID(port);
521
522 /* Invalidate ELD */
523 tmp = I915_READ(aud_cntrl_st2);
524 tmp &= ~eldv;
525 I915_WRITE(aud_cntrl_st2, tmp);
526 }
527
ilk_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)528 static void ilk_audio_codec_enable(struct intel_encoder *encoder,
529 const struct intel_crtc_state *crtc_state,
530 const struct drm_connector_state *conn_state)
531 {
532 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
533 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
534 struct drm_connector *connector = conn_state->connector;
535 enum pipe pipe = crtc->pipe;
536 enum port port = encoder->port;
537 const u8 *eld = connector->eld;
538 u32 tmp, eldv;
539 int len, i;
540 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
541
542 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
543 port_name(port), pipe_name(pipe), drm_eld_size(eld));
544
545 if (WARN_ON(port == PORT_A))
546 return;
547
548 /*
549 * FIXME: We're supposed to wait for vblank here, but we have vblanks
550 * disabled during the mode set. The proper fix would be to push the
551 * rest of the setup into a vblank work item, queued here, but the
552 * infrastructure is not there yet.
553 */
554
555 if (HAS_PCH_IBX(dev_priv)) {
556 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
557 aud_config = IBX_AUD_CFG(pipe);
558 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
559 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
560 } else if (IS_VALLEYVIEW(dev_priv) ||
561 IS_CHERRYVIEW(dev_priv)) {
562 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
563 aud_config = VLV_AUD_CFG(pipe);
564 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
565 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
566 } else {
567 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
568 aud_config = CPT_AUD_CFG(pipe);
569 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
570 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
571 }
572
573 eldv = IBX_ELD_VALID(port);
574
575 /* Invalidate ELD */
576 tmp = I915_READ(aud_cntrl_st2);
577 tmp &= ~eldv;
578 I915_WRITE(aud_cntrl_st2, tmp);
579
580 /* Reset ELD write address */
581 tmp = I915_READ(aud_cntl_st);
582 tmp &= ~IBX_ELD_ADDRESS_MASK;
583 I915_WRITE(aud_cntl_st, tmp);
584
585 /* Up to 84 bytes of hw ELD buffer */
586 len = min(drm_eld_size(eld), 84);
587 for (i = 0; i < len / 4; i++)
588 I915_WRITE(hdmiw_hdmiedid, *((const u32 *)eld + i));
589
590 /* ELD valid */
591 tmp = I915_READ(aud_cntrl_st2);
592 tmp |= eldv;
593 I915_WRITE(aud_cntrl_st2, tmp);
594
595 /* Enable timestamps */
596 tmp = I915_READ(aud_config);
597 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
598 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
599 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
600 if (intel_crtc_has_dp_encoder(crtc_state))
601 tmp |= AUD_CONFIG_N_VALUE_INDEX;
602 else
603 tmp |= audio_config_hdmi_pixel_clock(crtc_state);
604 I915_WRITE(aud_config, tmp);
605 }
606
607 /**
608 * intel_audio_codec_enable - Enable the audio codec for HD audio
609 * @encoder: encoder on which to enable audio
610 * @crtc_state: pointer to the current crtc state.
611 * @conn_state: pointer to the current connector state.
612 *
613 * The enable sequences may only be performed after enabling the transcoder and
614 * port, and after completed link training.
615 */
intel_audio_codec_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,const struct drm_connector_state * conn_state)616 void intel_audio_codec_enable(struct intel_encoder *encoder,
617 const struct intel_crtc_state *crtc_state,
618 const struct drm_connector_state *conn_state)
619 {
620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
621 struct i915_audio_component *acomp = dev_priv->audio_component;
622 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
623 struct drm_connector *connector = conn_state->connector;
624 const struct drm_display_mode *adjusted_mode =
625 &crtc_state->base.adjusted_mode;
626 enum port port = encoder->port;
627 enum pipe pipe = crtc->pipe;
628
629 if (!connector->eld[0])
630 return;
631
632 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
633 connector->base.id,
634 connector->name,
635 connector->encoder->base.id,
636 connector->encoder->name);
637
638 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
639
640 if (dev_priv->display.audio_codec_enable)
641 dev_priv->display.audio_codec_enable(encoder,
642 crtc_state,
643 conn_state);
644
645 mutex_lock(&dev_priv->av_mutex);
646 encoder->audio_connector = connector;
647
648 /* referred in audio callbacks */
649 dev_priv->av_enc_map[pipe] = encoder;
650 mutex_unlock(&dev_priv->av_mutex);
651
652 if (acomp && acomp->base.audio_ops &&
653 acomp->base.audio_ops->pin_eld_notify) {
654 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
655 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
656 pipe = -1;
657 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
658 (int) port, (int) pipe);
659 }
660
661 intel_lpe_audio_notify(dev_priv, pipe, port, connector->eld,
662 crtc_state->port_clock,
663 intel_crtc_has_dp_encoder(crtc_state));
664 }
665
666 /**
667 * intel_audio_codec_disable - Disable the audio codec for HD audio
668 * @encoder: encoder on which to disable audio
669 * @old_crtc_state: pointer to the old crtc state.
670 * @old_conn_state: pointer to the old connector state.
671 *
672 * The disable sequences must be performed before disabling the transcoder or
673 * port.
674 */
intel_audio_codec_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state,const struct drm_connector_state * old_conn_state)675 void intel_audio_codec_disable(struct intel_encoder *encoder,
676 const struct intel_crtc_state *old_crtc_state,
677 const struct drm_connector_state *old_conn_state)
678 {
679 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
680 struct i915_audio_component *acomp = dev_priv->audio_component;
681 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
682 enum port port = encoder->port;
683 enum pipe pipe = crtc->pipe;
684
685 if (dev_priv->display.audio_codec_disable)
686 dev_priv->display.audio_codec_disable(encoder,
687 old_crtc_state,
688 old_conn_state);
689
690 mutex_lock(&dev_priv->av_mutex);
691 encoder->audio_connector = NULL;
692 dev_priv->av_enc_map[pipe] = NULL;
693 mutex_unlock(&dev_priv->av_mutex);
694
695 if (acomp && acomp->base.audio_ops &&
696 acomp->base.audio_ops->pin_eld_notify) {
697 /* audio drivers expect pipe = -1 to indicate Non-MST cases */
698 if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST))
699 pipe = -1;
700 acomp->base.audio_ops->pin_eld_notify(acomp->base.audio_ops->audio_ptr,
701 (int) port, (int) pipe);
702 }
703
704 intel_lpe_audio_notify(dev_priv, pipe, port, NULL, 0, false);
705 }
706
707 /**
708 * intel_init_audio_hooks - Set up chip specific audio hooks
709 * @dev_priv: device private
710 */
intel_init_audio_hooks(struct drm_i915_private * dev_priv)711 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
712 {
713 if (IS_G4X(dev_priv)) {
714 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
715 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
716 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
717 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
718 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
719 } else if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8) {
720 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
721 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
722 } else if (HAS_PCH_SPLIT(dev_priv)) {
723 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
724 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
725 }
726 }
727
i915_audio_component_get_power(struct device * kdev)728 static void i915_audio_component_get_power(struct device *kdev)
729 {
730 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
731 }
732
i915_audio_component_put_power(struct device * kdev)733 static void i915_audio_component_put_power(struct device *kdev)
734 {
735 intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
736 }
737
i915_audio_component_codec_wake_override(struct device * kdev,bool enable)738 static void i915_audio_component_codec_wake_override(struct device *kdev,
739 bool enable)
740 {
741 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
742 u32 tmp;
743
744 if (!IS_GEN9(dev_priv))
745 return;
746
747 i915_audio_component_get_power(kdev);
748
749 /*
750 * Enable/disable generating the codec wake signal, overriding the
751 * internal logic to generate the codec wake to controller.
752 */
753 tmp = I915_READ(HSW_AUD_CHICKENBIT);
754 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
755 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
756 usleep_range(1000, 1500);
757
758 if (enable) {
759 tmp = I915_READ(HSW_AUD_CHICKENBIT);
760 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
761 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
762 usleep_range(1000, 1500);
763 }
764
765 i915_audio_component_put_power(kdev);
766 }
767
768 /* Get CDCLK in kHz */
i915_audio_component_get_cdclk_freq(struct device * kdev)769 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
770 {
771 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
772
773 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
774 return -ENODEV;
775
776 return dev_priv->cdclk.hw.cdclk;
777 }
778
779 /*
780 * get the intel_encoder according to the parameter port and pipe
781 * intel_encoder is saved by the index of pipe
782 * MST & (pipe >= 0): return the av_enc_map[pipe],
783 * when port is matched
784 * MST & (pipe < 0): this is invalid
785 * Non-MST & (pipe >= 0): only pipe = 0 (the first device entry)
786 * will get the right intel_encoder with port matched
787 * Non-MST & (pipe < 0): get the right intel_encoder with port matched
788 */
get_saved_enc(struct drm_i915_private * dev_priv,int port,int pipe)789 static struct intel_encoder *get_saved_enc(struct drm_i915_private *dev_priv,
790 int port, int pipe)
791 {
792 struct intel_encoder *encoder;
793
794 /* MST */
795 if (pipe >= 0) {
796 if (WARN_ON(pipe >= ARRAY_SIZE(dev_priv->av_enc_map)))
797 return NULL;
798
799 encoder = dev_priv->av_enc_map[pipe];
800 /*
801 * when bootup, audio driver may not know it is
802 * MST or not. So it will poll all the port & pipe
803 * combinations
804 */
805 if (encoder != NULL && encoder->port == port &&
806 encoder->type == INTEL_OUTPUT_DP_MST)
807 return encoder;
808 }
809
810 /* Non-MST */
811 if (pipe > 0)
812 return NULL;
813
814 for_each_pipe(dev_priv, pipe) {
815 encoder = dev_priv->av_enc_map[pipe];
816 if (encoder == NULL)
817 continue;
818
819 if (encoder->type == INTEL_OUTPUT_DP_MST)
820 continue;
821
822 if (port == encoder->port)
823 return encoder;
824 }
825
826 return NULL;
827 }
828
i915_audio_component_sync_audio_rate(struct device * kdev,int port,int pipe,int rate)829 static int i915_audio_component_sync_audio_rate(struct device *kdev, int port,
830 int pipe, int rate)
831 {
832 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
833 struct i915_audio_component *acomp = dev_priv->audio_component;
834 struct intel_encoder *encoder;
835 struct intel_crtc *crtc;
836 int err = 0;
837
838 if (!HAS_DDI(dev_priv))
839 return 0;
840
841 i915_audio_component_get_power(kdev);
842 mutex_lock(&dev_priv->av_mutex);
843
844 /* 1. get the pipe */
845 encoder = get_saved_enc(dev_priv, port, pipe);
846 if (!encoder || !encoder->base.crtc) {
847 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
848 err = -ENODEV;
849 goto unlock;
850 }
851
852 crtc = to_intel_crtc(encoder->base.crtc);
853
854 /* port must be valid now, otherwise the pipe will be invalid */
855 acomp->aud_sample_rate[port] = rate;
856
857 hsw_audio_config_update(encoder, crtc->config);
858
859 unlock:
860 mutex_unlock(&dev_priv->av_mutex);
861 i915_audio_component_put_power(kdev);
862 return err;
863 }
864
i915_audio_component_get_eld(struct device * kdev,int port,int pipe,bool * enabled,unsigned char * buf,int max_bytes)865 static int i915_audio_component_get_eld(struct device *kdev, int port,
866 int pipe, bool *enabled,
867 unsigned char *buf, int max_bytes)
868 {
869 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
870 struct intel_encoder *intel_encoder;
871 const u8 *eld;
872 int ret = -EINVAL;
873
874 mutex_lock(&dev_priv->av_mutex);
875
876 intel_encoder = get_saved_enc(dev_priv, port, pipe);
877 if (!intel_encoder) {
878 DRM_DEBUG_KMS("Not valid for port %c\n", port_name(port));
879 mutex_unlock(&dev_priv->av_mutex);
880 return ret;
881 }
882
883 ret = 0;
884 *enabled = intel_encoder->audio_connector != NULL;
885 if (*enabled) {
886 eld = intel_encoder->audio_connector->eld;
887 ret = drm_eld_size(eld);
888 memcpy(buf, eld, min(max_bytes, ret));
889 }
890
891 mutex_unlock(&dev_priv->av_mutex);
892 return ret;
893 }
894
895 static const struct drm_audio_component_ops i915_audio_component_ops = {
896 .owner = THIS_MODULE,
897 .get_power = i915_audio_component_get_power,
898 .put_power = i915_audio_component_put_power,
899 .codec_wake_override = i915_audio_component_codec_wake_override,
900 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
901 .sync_audio_rate = i915_audio_component_sync_audio_rate,
902 .get_eld = i915_audio_component_get_eld,
903 };
904
i915_audio_component_bind(struct device * i915_kdev,struct device * hda_kdev,void * data)905 static int i915_audio_component_bind(struct device *i915_kdev,
906 struct device *hda_kdev, void *data)
907 {
908 struct i915_audio_component *acomp = data;
909 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
910 int i;
911
912 if (WARN_ON(acomp->base.ops || acomp->base.dev))
913 return -EEXIST;
914
915 drm_modeset_lock_all(&dev_priv->drm);
916 acomp->base.ops = &i915_audio_component_ops;
917 acomp->base.dev = i915_kdev;
918 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
919 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
920 acomp->aud_sample_rate[i] = 0;
921 dev_priv->audio_component = acomp;
922 drm_modeset_unlock_all(&dev_priv->drm);
923
924 return 0;
925 }
926
i915_audio_component_unbind(struct device * i915_kdev,struct device * hda_kdev,void * data)927 static void i915_audio_component_unbind(struct device *i915_kdev,
928 struct device *hda_kdev, void *data)
929 {
930 struct i915_audio_component *acomp = data;
931 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
932
933 drm_modeset_lock_all(&dev_priv->drm);
934 acomp->base.ops = NULL;
935 acomp->base.dev = NULL;
936 dev_priv->audio_component = NULL;
937 drm_modeset_unlock_all(&dev_priv->drm);
938 }
939
940 static const struct component_ops i915_audio_component_bind_ops = {
941 .bind = i915_audio_component_bind,
942 .unbind = i915_audio_component_unbind,
943 };
944
945 /**
946 * i915_audio_component_init - initialize and register the audio component
947 * @dev_priv: i915 device instance
948 *
949 * This will register with the component framework a child component which
950 * will bind dynamically to the snd_hda_intel driver's corresponding master
951 * component when the latter is registered. During binding the child
952 * initializes an instance of struct i915_audio_component which it receives
953 * from the master. The master can then start to use the interface defined by
954 * this struct. Each side can break the binding at any point by deregistering
955 * its own component after which each side's component unbind callback is
956 * called.
957 *
958 * We ignore any error during registration and continue with reduced
959 * functionality (i.e. without HDMI audio).
960 */
i915_audio_component_init(struct drm_i915_private * dev_priv)961 void i915_audio_component_init(struct drm_i915_private *dev_priv)
962 {
963 int ret;
964
965 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
966 if (ret < 0) {
967 DRM_ERROR("failed to add audio component (%d)\n", ret);
968 /* continue with reduced functionality */
969 return;
970 }
971
972 dev_priv->audio_component_registered = true;
973 }
974
975 /**
976 * i915_audio_component_cleanup - deregister the audio component
977 * @dev_priv: i915 device instance
978 *
979 * Deregisters the audio component, breaking any existing binding to the
980 * corresponding snd_hda_intel driver's master component.
981 */
i915_audio_component_cleanup(struct drm_i915_private * dev_priv)982 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
983 {
984 if (!dev_priv->audio_component_registered)
985 return;
986
987 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
988 dev_priv->audio_component_registered = false;
989 }
990
991 /**
992 * intel_audio_init() - Initialize the audio driver either using
993 * component framework or using lpe audio bridge
994 * @dev_priv: the i915 drm device private data
995 *
996 */
intel_audio_init(struct drm_i915_private * dev_priv)997 void intel_audio_init(struct drm_i915_private *dev_priv)
998 {
999 if (intel_lpe_audio_init(dev_priv) < 0)
1000 i915_audio_component_init(dev_priv);
1001 }
1002
1003 /**
1004 * intel_audio_deinit() - deinitialize the audio driver
1005 * @dev_priv: the i915 drm device private data
1006 *
1007 */
intel_audio_deinit(struct drm_i915_private * dev_priv)1008 void intel_audio_deinit(struct drm_i915_private *dev_priv)
1009 {
1010 if ((dev_priv)->lpe_audio.platdev != NULL)
1011 intel_lpe_audio_teardown(dev_priv);
1012 else
1013 i915_audio_component_cleanup(dev_priv);
1014 }
1015
