1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #include "i40e_type.h"
5 #include "i40e_adminq.h"
6 #include "i40e_prototype.h"
7 #include <linux/avf/virtchnl.h>
8
9 /**
10 * i40e_set_mac_type - Sets MAC type
11 * @hw: pointer to the HW structure
12 *
13 * This function sets the mac type of the adapter based on the
14 * vendor ID and device ID stored in the hw structure.
15 **/
i40e_set_mac_type(struct i40e_hw * hw)16 i40e_status i40e_set_mac_type(struct i40e_hw *hw)
17 {
18 i40e_status status = 0;
19
20 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
21 switch (hw->device_id) {
22 case I40E_DEV_ID_SFP_XL710:
23 case I40E_DEV_ID_QEMU:
24 case I40E_DEV_ID_KX_B:
25 case I40E_DEV_ID_KX_C:
26 case I40E_DEV_ID_QSFP_A:
27 case I40E_DEV_ID_QSFP_B:
28 case I40E_DEV_ID_QSFP_C:
29 case I40E_DEV_ID_10G_BASE_T:
30 case I40E_DEV_ID_10G_BASE_T4:
31 case I40E_DEV_ID_20G_KR2:
32 case I40E_DEV_ID_20G_KR2_A:
33 case I40E_DEV_ID_25G_B:
34 case I40E_DEV_ID_25G_SFP28:
35 hw->mac.type = I40E_MAC_XL710;
36 break;
37 case I40E_DEV_ID_SFP_X722:
38 case I40E_DEV_ID_1G_BASE_T_X722:
39 case I40E_DEV_ID_10G_BASE_T_X722:
40 case I40E_DEV_ID_SFP_I_X722:
41 hw->mac.type = I40E_MAC_X722;
42 break;
43 case I40E_DEV_ID_X722_VF:
44 hw->mac.type = I40E_MAC_X722_VF;
45 break;
46 case I40E_DEV_ID_VF:
47 case I40E_DEV_ID_VF_HV:
48 case I40E_DEV_ID_ADAPTIVE_VF:
49 hw->mac.type = I40E_MAC_VF;
50 break;
51 default:
52 hw->mac.type = I40E_MAC_GENERIC;
53 break;
54 }
55 } else {
56 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
57 }
58
59 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
60 hw->mac.type, status);
61 return status;
62 }
63
64 /**
65 * i40evf_aq_str - convert AQ err code to a string
66 * @hw: pointer to the HW structure
67 * @aq_err: the AQ error code to convert
68 **/
i40evf_aq_str(struct i40e_hw * hw,enum i40e_admin_queue_err aq_err)69 const char *i40evf_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
70 {
71 switch (aq_err) {
72 case I40E_AQ_RC_OK:
73 return "OK";
74 case I40E_AQ_RC_EPERM:
75 return "I40E_AQ_RC_EPERM";
76 case I40E_AQ_RC_ENOENT:
77 return "I40E_AQ_RC_ENOENT";
78 case I40E_AQ_RC_ESRCH:
79 return "I40E_AQ_RC_ESRCH";
80 case I40E_AQ_RC_EINTR:
81 return "I40E_AQ_RC_EINTR";
82 case I40E_AQ_RC_EIO:
83 return "I40E_AQ_RC_EIO";
84 case I40E_AQ_RC_ENXIO:
85 return "I40E_AQ_RC_ENXIO";
86 case I40E_AQ_RC_E2BIG:
87 return "I40E_AQ_RC_E2BIG";
88 case I40E_AQ_RC_EAGAIN:
89 return "I40E_AQ_RC_EAGAIN";
90 case I40E_AQ_RC_ENOMEM:
91 return "I40E_AQ_RC_ENOMEM";
92 case I40E_AQ_RC_EACCES:
93 return "I40E_AQ_RC_EACCES";
94 case I40E_AQ_RC_EFAULT:
95 return "I40E_AQ_RC_EFAULT";
96 case I40E_AQ_RC_EBUSY:
97 return "I40E_AQ_RC_EBUSY";
98 case I40E_AQ_RC_EEXIST:
99 return "I40E_AQ_RC_EEXIST";
100 case I40E_AQ_RC_EINVAL:
101 return "I40E_AQ_RC_EINVAL";
102 case I40E_AQ_RC_ENOTTY:
103 return "I40E_AQ_RC_ENOTTY";
104 case I40E_AQ_RC_ENOSPC:
105 return "I40E_AQ_RC_ENOSPC";
106 case I40E_AQ_RC_ENOSYS:
107 return "I40E_AQ_RC_ENOSYS";
108 case I40E_AQ_RC_ERANGE:
109 return "I40E_AQ_RC_ERANGE";
110 case I40E_AQ_RC_EFLUSHED:
111 return "I40E_AQ_RC_EFLUSHED";
112 case I40E_AQ_RC_BAD_ADDR:
113 return "I40E_AQ_RC_BAD_ADDR";
114 case I40E_AQ_RC_EMODE:
115 return "I40E_AQ_RC_EMODE";
116 case I40E_AQ_RC_EFBIG:
117 return "I40E_AQ_RC_EFBIG";
118 }
119
120 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
121 return hw->err_str;
122 }
123
124 /**
125 * i40evf_stat_str - convert status err code to a string
126 * @hw: pointer to the HW structure
127 * @stat_err: the status error code to convert
128 **/
i40evf_stat_str(struct i40e_hw * hw,i40e_status stat_err)129 const char *i40evf_stat_str(struct i40e_hw *hw, i40e_status stat_err)
130 {
131 switch (stat_err) {
132 case 0:
133 return "OK";
134 case I40E_ERR_NVM:
135 return "I40E_ERR_NVM";
136 case I40E_ERR_NVM_CHECKSUM:
137 return "I40E_ERR_NVM_CHECKSUM";
138 case I40E_ERR_PHY:
139 return "I40E_ERR_PHY";
140 case I40E_ERR_CONFIG:
141 return "I40E_ERR_CONFIG";
142 case I40E_ERR_PARAM:
143 return "I40E_ERR_PARAM";
144 case I40E_ERR_MAC_TYPE:
145 return "I40E_ERR_MAC_TYPE";
146 case I40E_ERR_UNKNOWN_PHY:
147 return "I40E_ERR_UNKNOWN_PHY";
148 case I40E_ERR_LINK_SETUP:
149 return "I40E_ERR_LINK_SETUP";
150 case I40E_ERR_ADAPTER_STOPPED:
151 return "I40E_ERR_ADAPTER_STOPPED";
152 case I40E_ERR_INVALID_MAC_ADDR:
153 return "I40E_ERR_INVALID_MAC_ADDR";
154 case I40E_ERR_DEVICE_NOT_SUPPORTED:
155 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
156 case I40E_ERR_MASTER_REQUESTS_PENDING:
157 return "I40E_ERR_MASTER_REQUESTS_PENDING";
158 case I40E_ERR_INVALID_LINK_SETTINGS:
159 return "I40E_ERR_INVALID_LINK_SETTINGS";
160 case I40E_ERR_AUTONEG_NOT_COMPLETE:
161 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
162 case I40E_ERR_RESET_FAILED:
163 return "I40E_ERR_RESET_FAILED";
164 case I40E_ERR_SWFW_SYNC:
165 return "I40E_ERR_SWFW_SYNC";
166 case I40E_ERR_NO_AVAILABLE_VSI:
167 return "I40E_ERR_NO_AVAILABLE_VSI";
168 case I40E_ERR_NO_MEMORY:
169 return "I40E_ERR_NO_MEMORY";
170 case I40E_ERR_BAD_PTR:
171 return "I40E_ERR_BAD_PTR";
172 case I40E_ERR_RING_FULL:
173 return "I40E_ERR_RING_FULL";
174 case I40E_ERR_INVALID_PD_ID:
175 return "I40E_ERR_INVALID_PD_ID";
176 case I40E_ERR_INVALID_QP_ID:
177 return "I40E_ERR_INVALID_QP_ID";
178 case I40E_ERR_INVALID_CQ_ID:
179 return "I40E_ERR_INVALID_CQ_ID";
180 case I40E_ERR_INVALID_CEQ_ID:
181 return "I40E_ERR_INVALID_CEQ_ID";
182 case I40E_ERR_INVALID_AEQ_ID:
183 return "I40E_ERR_INVALID_AEQ_ID";
184 case I40E_ERR_INVALID_SIZE:
185 return "I40E_ERR_INVALID_SIZE";
186 case I40E_ERR_INVALID_ARP_INDEX:
187 return "I40E_ERR_INVALID_ARP_INDEX";
188 case I40E_ERR_INVALID_FPM_FUNC_ID:
189 return "I40E_ERR_INVALID_FPM_FUNC_ID";
190 case I40E_ERR_QP_INVALID_MSG_SIZE:
191 return "I40E_ERR_QP_INVALID_MSG_SIZE";
192 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
193 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
194 case I40E_ERR_INVALID_FRAG_COUNT:
195 return "I40E_ERR_INVALID_FRAG_COUNT";
196 case I40E_ERR_QUEUE_EMPTY:
197 return "I40E_ERR_QUEUE_EMPTY";
198 case I40E_ERR_INVALID_ALIGNMENT:
199 return "I40E_ERR_INVALID_ALIGNMENT";
200 case I40E_ERR_FLUSHED_QUEUE:
201 return "I40E_ERR_FLUSHED_QUEUE";
202 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
203 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
204 case I40E_ERR_INVALID_IMM_DATA_SIZE:
205 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
206 case I40E_ERR_TIMEOUT:
207 return "I40E_ERR_TIMEOUT";
208 case I40E_ERR_OPCODE_MISMATCH:
209 return "I40E_ERR_OPCODE_MISMATCH";
210 case I40E_ERR_CQP_COMPL_ERROR:
211 return "I40E_ERR_CQP_COMPL_ERROR";
212 case I40E_ERR_INVALID_VF_ID:
213 return "I40E_ERR_INVALID_VF_ID";
214 case I40E_ERR_INVALID_HMCFN_ID:
215 return "I40E_ERR_INVALID_HMCFN_ID";
216 case I40E_ERR_BACKING_PAGE_ERROR:
217 return "I40E_ERR_BACKING_PAGE_ERROR";
218 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
219 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
220 case I40E_ERR_INVALID_PBLE_INDEX:
221 return "I40E_ERR_INVALID_PBLE_INDEX";
222 case I40E_ERR_INVALID_SD_INDEX:
223 return "I40E_ERR_INVALID_SD_INDEX";
224 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
225 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
226 case I40E_ERR_INVALID_SD_TYPE:
227 return "I40E_ERR_INVALID_SD_TYPE";
228 case I40E_ERR_MEMCPY_FAILED:
229 return "I40E_ERR_MEMCPY_FAILED";
230 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
231 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
232 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
233 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
234 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
235 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
236 case I40E_ERR_SRQ_ENABLED:
237 return "I40E_ERR_SRQ_ENABLED";
238 case I40E_ERR_ADMIN_QUEUE_ERROR:
239 return "I40E_ERR_ADMIN_QUEUE_ERROR";
240 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
241 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
242 case I40E_ERR_BUF_TOO_SHORT:
243 return "I40E_ERR_BUF_TOO_SHORT";
244 case I40E_ERR_ADMIN_QUEUE_FULL:
245 return "I40E_ERR_ADMIN_QUEUE_FULL";
246 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
247 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
248 case I40E_ERR_BAD_IWARP_CQE:
249 return "I40E_ERR_BAD_IWARP_CQE";
250 case I40E_ERR_NVM_BLANK_MODE:
251 return "I40E_ERR_NVM_BLANK_MODE";
252 case I40E_ERR_NOT_IMPLEMENTED:
253 return "I40E_ERR_NOT_IMPLEMENTED";
254 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
255 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
256 case I40E_ERR_DIAG_TEST_FAILED:
257 return "I40E_ERR_DIAG_TEST_FAILED";
258 case I40E_ERR_NOT_READY:
259 return "I40E_ERR_NOT_READY";
260 case I40E_NOT_SUPPORTED:
261 return "I40E_NOT_SUPPORTED";
262 case I40E_ERR_FIRMWARE_API_VERSION:
263 return "I40E_ERR_FIRMWARE_API_VERSION";
264 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
265 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
266 }
267
268 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
269 return hw->err_str;
270 }
271
272 /**
273 * i40evf_debug_aq
274 * @hw: debug mask related to admin queue
275 * @mask: debug mask
276 * @desc: pointer to admin queue descriptor
277 * @buffer: pointer to command buffer
278 * @buf_len: max length of buffer
279 *
280 * Dumps debug log about adminq command with descriptor contents.
281 **/
i40evf_debug_aq(struct i40e_hw * hw,enum i40e_debug_mask mask,void * desc,void * buffer,u16 buf_len)282 void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
283 void *buffer, u16 buf_len)
284 {
285 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
286 u8 *buf = (u8 *)buffer;
287
288 if ((!(mask & hw->debug_mask)) || (desc == NULL))
289 return;
290
291 i40e_debug(hw, mask,
292 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
293 le16_to_cpu(aq_desc->opcode),
294 le16_to_cpu(aq_desc->flags),
295 le16_to_cpu(aq_desc->datalen),
296 le16_to_cpu(aq_desc->retval));
297 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
298 le32_to_cpu(aq_desc->cookie_high),
299 le32_to_cpu(aq_desc->cookie_low));
300 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
301 le32_to_cpu(aq_desc->params.internal.param0),
302 le32_to_cpu(aq_desc->params.internal.param1));
303 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
304 le32_to_cpu(aq_desc->params.external.addr_high),
305 le32_to_cpu(aq_desc->params.external.addr_low));
306
307 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
308 u16 len = le16_to_cpu(aq_desc->datalen);
309
310 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
311 if (buf_len < len)
312 len = buf_len;
313 /* write the full 16-byte chunks */
314 if (hw->debug_mask & mask) {
315 char prefix[27];
316
317 snprintf(prefix, sizeof(prefix),
318 "i40evf %02x:%02x.%x: \t0x",
319 hw->bus.bus_id,
320 hw->bus.device,
321 hw->bus.func);
322
323 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
324 16, 1, buf, len, false);
325 }
326 }
327 }
328
329 /**
330 * i40evf_check_asq_alive
331 * @hw: pointer to the hw struct
332 *
333 * Returns true if Queue is enabled else false.
334 **/
i40evf_check_asq_alive(struct i40e_hw * hw)335 bool i40evf_check_asq_alive(struct i40e_hw *hw)
336 {
337 if (hw->aq.asq.len)
338 return !!(rd32(hw, hw->aq.asq.len) &
339 I40E_VF_ATQLEN1_ATQENABLE_MASK);
340 else
341 return false;
342 }
343
344 /**
345 * i40evf_aq_queue_shutdown
346 * @hw: pointer to the hw struct
347 * @unloading: is the driver unloading itself
348 *
349 * Tell the Firmware that we're shutting down the AdminQ and whether
350 * or not the driver is unloading as well.
351 **/
i40evf_aq_queue_shutdown(struct i40e_hw * hw,bool unloading)352 i40e_status i40evf_aq_queue_shutdown(struct i40e_hw *hw,
353 bool unloading)
354 {
355 struct i40e_aq_desc desc;
356 struct i40e_aqc_queue_shutdown *cmd =
357 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
358 i40e_status status;
359
360 i40evf_fill_default_direct_cmd_desc(&desc,
361 i40e_aqc_opc_queue_shutdown);
362
363 if (unloading)
364 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
365 status = i40evf_asq_send_command(hw, &desc, NULL, 0, NULL);
366
367 return status;
368 }
369
370 /**
371 * i40e_aq_get_set_rss_lut
372 * @hw: pointer to the hardware structure
373 * @vsi_id: vsi fw index
374 * @pf_lut: for PF table set true, for VSI table set false
375 * @lut: pointer to the lut buffer provided by the caller
376 * @lut_size: size of the lut buffer
377 * @set: set true to set the table, false to get the table
378 *
379 * Internal function to get or set RSS look up table
380 **/
i40e_aq_get_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size,bool set)381 static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
382 u16 vsi_id, bool pf_lut,
383 u8 *lut, u16 lut_size,
384 bool set)
385 {
386 i40e_status status;
387 struct i40e_aq_desc desc;
388 struct i40e_aqc_get_set_rss_lut *cmd_resp =
389 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
390
391 if (set)
392 i40evf_fill_default_direct_cmd_desc(&desc,
393 i40e_aqc_opc_set_rss_lut);
394 else
395 i40evf_fill_default_direct_cmd_desc(&desc,
396 i40e_aqc_opc_get_rss_lut);
397
398 /* Indirect command */
399 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
400 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
401
402 cmd_resp->vsi_id =
403 cpu_to_le16((u16)((vsi_id <<
404 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
405 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
406 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
407
408 if (pf_lut)
409 cmd_resp->flags |= cpu_to_le16((u16)
410 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
411 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
412 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
413 else
414 cmd_resp->flags |= cpu_to_le16((u16)
415 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
416 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
418
419 status = i40evf_asq_send_command(hw, &desc, lut, lut_size, NULL);
420
421 return status;
422 }
423
424 /**
425 * i40evf_aq_get_rss_lut
426 * @hw: pointer to the hardware structure
427 * @vsi_id: vsi fw index
428 * @pf_lut: for PF table set true, for VSI table set false
429 * @lut: pointer to the lut buffer provided by the caller
430 * @lut_size: size of the lut buffer
431 *
432 * get the RSS lookup table, PF or VSI type
433 **/
i40evf_aq_get_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)434 i40e_status i40evf_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
435 bool pf_lut, u8 *lut, u16 lut_size)
436 {
437 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
438 false);
439 }
440
441 /**
442 * i40evf_aq_set_rss_lut
443 * @hw: pointer to the hardware structure
444 * @vsi_id: vsi fw index
445 * @pf_lut: for PF table set true, for VSI table set false
446 * @lut: pointer to the lut buffer provided by the caller
447 * @lut_size: size of the lut buffer
448 *
449 * set the RSS lookup table, PF or VSI type
450 **/
i40evf_aq_set_rss_lut(struct i40e_hw * hw,u16 vsi_id,bool pf_lut,u8 * lut,u16 lut_size)451 i40e_status i40evf_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
452 bool pf_lut, u8 *lut, u16 lut_size)
453 {
454 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
455 }
456
457 /**
458 * i40e_aq_get_set_rss_key
459 * @hw: pointer to the hw struct
460 * @vsi_id: vsi fw index
461 * @key: pointer to key info struct
462 * @set: set true to set the key, false to get the key
463 *
464 * get the RSS key per VSI
465 **/
i40e_aq_get_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key,bool set)466 static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
467 u16 vsi_id,
468 struct i40e_aqc_get_set_rss_key_data *key,
469 bool set)
470 {
471 i40e_status status;
472 struct i40e_aq_desc desc;
473 struct i40e_aqc_get_set_rss_key *cmd_resp =
474 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
475 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
476
477 if (set)
478 i40evf_fill_default_direct_cmd_desc(&desc,
479 i40e_aqc_opc_set_rss_key);
480 else
481 i40evf_fill_default_direct_cmd_desc(&desc,
482 i40e_aqc_opc_get_rss_key);
483
484 /* Indirect command */
485 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
486 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
487
488 cmd_resp->vsi_id =
489 cpu_to_le16((u16)((vsi_id <<
490 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
491 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
492 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
493
494 status = i40evf_asq_send_command(hw, &desc, key, key_size, NULL);
495
496 return status;
497 }
498
499 /**
500 * i40evf_aq_get_rss_key
501 * @hw: pointer to the hw struct
502 * @vsi_id: vsi fw index
503 * @key: pointer to key info struct
504 *
505 **/
i40evf_aq_get_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)506 i40e_status i40evf_aq_get_rss_key(struct i40e_hw *hw,
507 u16 vsi_id,
508 struct i40e_aqc_get_set_rss_key_data *key)
509 {
510 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
511 }
512
513 /**
514 * i40evf_aq_set_rss_key
515 * @hw: pointer to the hw struct
516 * @vsi_id: vsi fw index
517 * @key: pointer to key info struct
518 *
519 * set the RSS key per VSI
520 **/
i40evf_aq_set_rss_key(struct i40e_hw * hw,u16 vsi_id,struct i40e_aqc_get_set_rss_key_data * key)521 i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,
522 u16 vsi_id,
523 struct i40e_aqc_get_set_rss_key_data *key)
524 {
525 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
526 }
527
528
529 /* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the
530 * hardware to a bit-field that can be used by SW to more easily determine the
531 * packet type.
532 *
533 * Macros are used to shorten the table lines and make this table human
534 * readable.
535 *
536 * We store the PTYPE in the top byte of the bit field - this is just so that
537 * we can check that the table doesn't have a row missing, as the index into
538 * the table should be the PTYPE.
539 *
540 * Typical work flow:
541 *
542 * IF NOT i40evf_ptype_lookup[ptype].known
543 * THEN
544 * Packet is unknown
545 * ELSE IF i40evf_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
546 * Use the rest of the fields to look at the tunnels, inner protocols, etc
547 * ELSE
548 * Use the enum i40e_rx_l2_ptype to decode the packet type
549 * ENDIF
550 */
551
552 /* macro to make the table lines short */
553 #define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
554 { PTYPE, \
555 1, \
556 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
557 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
558 I40E_RX_PTYPE_##OUTER_FRAG, \
559 I40E_RX_PTYPE_TUNNEL_##T, \
560 I40E_RX_PTYPE_TUNNEL_END_##TE, \
561 I40E_RX_PTYPE_##TEF, \
562 I40E_RX_PTYPE_INNER_PROT_##I, \
563 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
564
565 #define I40E_PTT_UNUSED_ENTRY(PTYPE) \
566 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
567
568 /* shorter macros makes the table fit but are terse */
569 #define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
570 #define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
571 #define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
572
573 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
574 struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {
575 /* L2 Packet types */
576 I40E_PTT_UNUSED_ENTRY(0),
577 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
578 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
579 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
580 I40E_PTT_UNUSED_ENTRY(4),
581 I40E_PTT_UNUSED_ENTRY(5),
582 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
584 I40E_PTT_UNUSED_ENTRY(8),
585 I40E_PTT_UNUSED_ENTRY(9),
586 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
587 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
588 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
589 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
590 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
591 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
593 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598
599 /* Non Tunneled IPv4 */
600 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
603 I40E_PTT_UNUSED_ENTRY(25),
604 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
605 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
606 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
607
608 /* IPv4 --> IPv4 */
609 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
610 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
611 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
612 I40E_PTT_UNUSED_ENTRY(32),
613 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
614 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
615 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
616
617 /* IPv4 --> IPv6 */
618 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
619 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
620 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
621 I40E_PTT_UNUSED_ENTRY(39),
622 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
623 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
624 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
625
626 /* IPv4 --> GRE/NAT */
627 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
628
629 /* IPv4 --> GRE/NAT --> IPv4 */
630 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
631 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
632 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
633 I40E_PTT_UNUSED_ENTRY(47),
634 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
635 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
636 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
637
638 /* IPv4 --> GRE/NAT --> IPv6 */
639 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
640 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
641 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
642 I40E_PTT_UNUSED_ENTRY(54),
643 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
644 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
645 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
646
647 /* IPv4 --> GRE/NAT --> MAC */
648 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
649
650 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
651 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
652 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
653 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
654 I40E_PTT_UNUSED_ENTRY(62),
655 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
656 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
657 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
658
659 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
660 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
661 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
662 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
663 I40E_PTT_UNUSED_ENTRY(69),
664 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
665 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
666 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
667
668 /* IPv4 --> GRE/NAT --> MAC/VLAN */
669 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
670
671 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
672 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
673 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
674 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
675 I40E_PTT_UNUSED_ENTRY(77),
676 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
677 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
678 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
679
680 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
681 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
682 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
683 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
684 I40E_PTT_UNUSED_ENTRY(84),
685 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
686 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
687 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
688
689 /* Non Tunneled IPv6 */
690 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
691 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
692 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
693 I40E_PTT_UNUSED_ENTRY(91),
694 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
695 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
696 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
697
698 /* IPv6 --> IPv4 */
699 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
700 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
701 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
702 I40E_PTT_UNUSED_ENTRY(98),
703 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
704 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
705 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
706
707 /* IPv6 --> IPv6 */
708 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
709 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
710 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
711 I40E_PTT_UNUSED_ENTRY(105),
712 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
713 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
714 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
715
716 /* IPv6 --> GRE/NAT */
717 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
718
719 /* IPv6 --> GRE/NAT -> IPv4 */
720 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
721 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
722 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
723 I40E_PTT_UNUSED_ENTRY(113),
724 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
725 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
726 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
727
728 /* IPv6 --> GRE/NAT -> IPv6 */
729 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
730 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
731 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
732 I40E_PTT_UNUSED_ENTRY(120),
733 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
734 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
735 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
736
737 /* IPv6 --> GRE/NAT -> MAC */
738 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
739
740 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
741 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
742 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
743 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
744 I40E_PTT_UNUSED_ENTRY(128),
745 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
746 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
747 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
748
749 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
750 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
751 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
752 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
753 I40E_PTT_UNUSED_ENTRY(135),
754 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
755 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
756 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
757
758 /* IPv6 --> GRE/NAT -> MAC/VLAN */
759 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
760
761 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
762 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
763 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
764 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
765 I40E_PTT_UNUSED_ENTRY(143),
766 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
767 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
768 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
769
770 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
771 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
772 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
773 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
774 I40E_PTT_UNUSED_ENTRY(150),
775 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
776 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
777 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
778
779 /* unused entries */
780 I40E_PTT_UNUSED_ENTRY(154),
781 I40E_PTT_UNUSED_ENTRY(155),
782 I40E_PTT_UNUSED_ENTRY(156),
783 I40E_PTT_UNUSED_ENTRY(157),
784 I40E_PTT_UNUSED_ENTRY(158),
785 I40E_PTT_UNUSED_ENTRY(159),
786
787 I40E_PTT_UNUSED_ENTRY(160),
788 I40E_PTT_UNUSED_ENTRY(161),
789 I40E_PTT_UNUSED_ENTRY(162),
790 I40E_PTT_UNUSED_ENTRY(163),
791 I40E_PTT_UNUSED_ENTRY(164),
792 I40E_PTT_UNUSED_ENTRY(165),
793 I40E_PTT_UNUSED_ENTRY(166),
794 I40E_PTT_UNUSED_ENTRY(167),
795 I40E_PTT_UNUSED_ENTRY(168),
796 I40E_PTT_UNUSED_ENTRY(169),
797
798 I40E_PTT_UNUSED_ENTRY(170),
799 I40E_PTT_UNUSED_ENTRY(171),
800 I40E_PTT_UNUSED_ENTRY(172),
801 I40E_PTT_UNUSED_ENTRY(173),
802 I40E_PTT_UNUSED_ENTRY(174),
803 I40E_PTT_UNUSED_ENTRY(175),
804 I40E_PTT_UNUSED_ENTRY(176),
805 I40E_PTT_UNUSED_ENTRY(177),
806 I40E_PTT_UNUSED_ENTRY(178),
807 I40E_PTT_UNUSED_ENTRY(179),
808
809 I40E_PTT_UNUSED_ENTRY(180),
810 I40E_PTT_UNUSED_ENTRY(181),
811 I40E_PTT_UNUSED_ENTRY(182),
812 I40E_PTT_UNUSED_ENTRY(183),
813 I40E_PTT_UNUSED_ENTRY(184),
814 I40E_PTT_UNUSED_ENTRY(185),
815 I40E_PTT_UNUSED_ENTRY(186),
816 I40E_PTT_UNUSED_ENTRY(187),
817 I40E_PTT_UNUSED_ENTRY(188),
818 I40E_PTT_UNUSED_ENTRY(189),
819
820 I40E_PTT_UNUSED_ENTRY(190),
821 I40E_PTT_UNUSED_ENTRY(191),
822 I40E_PTT_UNUSED_ENTRY(192),
823 I40E_PTT_UNUSED_ENTRY(193),
824 I40E_PTT_UNUSED_ENTRY(194),
825 I40E_PTT_UNUSED_ENTRY(195),
826 I40E_PTT_UNUSED_ENTRY(196),
827 I40E_PTT_UNUSED_ENTRY(197),
828 I40E_PTT_UNUSED_ENTRY(198),
829 I40E_PTT_UNUSED_ENTRY(199),
830
831 I40E_PTT_UNUSED_ENTRY(200),
832 I40E_PTT_UNUSED_ENTRY(201),
833 I40E_PTT_UNUSED_ENTRY(202),
834 I40E_PTT_UNUSED_ENTRY(203),
835 I40E_PTT_UNUSED_ENTRY(204),
836 I40E_PTT_UNUSED_ENTRY(205),
837 I40E_PTT_UNUSED_ENTRY(206),
838 I40E_PTT_UNUSED_ENTRY(207),
839 I40E_PTT_UNUSED_ENTRY(208),
840 I40E_PTT_UNUSED_ENTRY(209),
841
842 I40E_PTT_UNUSED_ENTRY(210),
843 I40E_PTT_UNUSED_ENTRY(211),
844 I40E_PTT_UNUSED_ENTRY(212),
845 I40E_PTT_UNUSED_ENTRY(213),
846 I40E_PTT_UNUSED_ENTRY(214),
847 I40E_PTT_UNUSED_ENTRY(215),
848 I40E_PTT_UNUSED_ENTRY(216),
849 I40E_PTT_UNUSED_ENTRY(217),
850 I40E_PTT_UNUSED_ENTRY(218),
851 I40E_PTT_UNUSED_ENTRY(219),
852
853 I40E_PTT_UNUSED_ENTRY(220),
854 I40E_PTT_UNUSED_ENTRY(221),
855 I40E_PTT_UNUSED_ENTRY(222),
856 I40E_PTT_UNUSED_ENTRY(223),
857 I40E_PTT_UNUSED_ENTRY(224),
858 I40E_PTT_UNUSED_ENTRY(225),
859 I40E_PTT_UNUSED_ENTRY(226),
860 I40E_PTT_UNUSED_ENTRY(227),
861 I40E_PTT_UNUSED_ENTRY(228),
862 I40E_PTT_UNUSED_ENTRY(229),
863
864 I40E_PTT_UNUSED_ENTRY(230),
865 I40E_PTT_UNUSED_ENTRY(231),
866 I40E_PTT_UNUSED_ENTRY(232),
867 I40E_PTT_UNUSED_ENTRY(233),
868 I40E_PTT_UNUSED_ENTRY(234),
869 I40E_PTT_UNUSED_ENTRY(235),
870 I40E_PTT_UNUSED_ENTRY(236),
871 I40E_PTT_UNUSED_ENTRY(237),
872 I40E_PTT_UNUSED_ENTRY(238),
873 I40E_PTT_UNUSED_ENTRY(239),
874
875 I40E_PTT_UNUSED_ENTRY(240),
876 I40E_PTT_UNUSED_ENTRY(241),
877 I40E_PTT_UNUSED_ENTRY(242),
878 I40E_PTT_UNUSED_ENTRY(243),
879 I40E_PTT_UNUSED_ENTRY(244),
880 I40E_PTT_UNUSED_ENTRY(245),
881 I40E_PTT_UNUSED_ENTRY(246),
882 I40E_PTT_UNUSED_ENTRY(247),
883 I40E_PTT_UNUSED_ENTRY(248),
884 I40E_PTT_UNUSED_ENTRY(249),
885
886 I40E_PTT_UNUSED_ENTRY(250),
887 I40E_PTT_UNUSED_ENTRY(251),
888 I40E_PTT_UNUSED_ENTRY(252),
889 I40E_PTT_UNUSED_ENTRY(253),
890 I40E_PTT_UNUSED_ENTRY(254),
891 I40E_PTT_UNUSED_ENTRY(255)
892 };
893
894 /**
895 * i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register
896 * @hw: pointer to the hw struct
897 * @reg_addr: register address
898 * @reg_val: ptr to register value
899 * @cmd_details: pointer to command details structure or NULL
900 *
901 * Use the firmware to read the Rx control register,
902 * especially useful if the Rx unit is under heavy pressure
903 **/
i40evf_aq_rx_ctl_read_register(struct i40e_hw * hw,u32 reg_addr,u32 * reg_val,struct i40e_asq_cmd_details * cmd_details)904 i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,
905 u32 reg_addr, u32 *reg_val,
906 struct i40e_asq_cmd_details *cmd_details)
907 {
908 struct i40e_aq_desc desc;
909 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
910 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
911 i40e_status status;
912
913 if (!reg_val)
914 return I40E_ERR_PARAM;
915
916 i40evf_fill_default_direct_cmd_desc(&desc,
917 i40e_aqc_opc_rx_ctl_reg_read);
918
919 cmd_resp->address = cpu_to_le32(reg_addr);
920
921 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
922
923 if (status == 0)
924 *reg_val = le32_to_cpu(cmd_resp->value);
925
926 return status;
927 }
928
929 /**
930 * i40evf_read_rx_ctl - read from an Rx control register
931 * @hw: pointer to the hw struct
932 * @reg_addr: register address
933 **/
i40evf_read_rx_ctl(struct i40e_hw * hw,u32 reg_addr)934 u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
935 {
936 i40e_status status = 0;
937 bool use_register;
938 int retry = 5;
939 u32 val = 0;
940
941 use_register = (((hw->aq.api_maj_ver == 1) &&
942 (hw->aq.api_min_ver < 5)) ||
943 (hw->mac.type == I40E_MAC_X722));
944 if (!use_register) {
945 do_retry:
946 status = i40evf_aq_rx_ctl_read_register(hw, reg_addr,
947 &val, NULL);
948 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
949 usleep_range(1000, 2000);
950 retry--;
951 goto do_retry;
952 }
953 }
954
955 /* if the AQ access failed, try the old-fashioned way */
956 if (status || use_register)
957 val = rd32(hw, reg_addr);
958
959 return val;
960 }
961
962 /**
963 * i40evf_aq_rx_ctl_write_register
964 * @hw: pointer to the hw struct
965 * @reg_addr: register address
966 * @reg_val: register value
967 * @cmd_details: pointer to command details structure or NULL
968 *
969 * Use the firmware to write to an Rx control register,
970 * especially useful if the Rx unit is under heavy pressure
971 **/
i40evf_aq_rx_ctl_write_register(struct i40e_hw * hw,u32 reg_addr,u32 reg_val,struct i40e_asq_cmd_details * cmd_details)972 i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,
973 u32 reg_addr, u32 reg_val,
974 struct i40e_asq_cmd_details *cmd_details)
975 {
976 struct i40e_aq_desc desc;
977 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
978 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
979 i40e_status status;
980
981 i40evf_fill_default_direct_cmd_desc(&desc,
982 i40e_aqc_opc_rx_ctl_reg_write);
983
984 cmd->address = cpu_to_le32(reg_addr);
985 cmd->value = cpu_to_le32(reg_val);
986
987 status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
988
989 return status;
990 }
991
992 /**
993 * i40evf_write_rx_ctl - write to an Rx control register
994 * @hw: pointer to the hw struct
995 * @reg_addr: register address
996 * @reg_val: register value
997 **/
i40evf_write_rx_ctl(struct i40e_hw * hw,u32 reg_addr,u32 reg_val)998 void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
999 {
1000 i40e_status status = 0;
1001 bool use_register;
1002 int retry = 5;
1003
1004 use_register = (((hw->aq.api_maj_ver == 1) &&
1005 (hw->aq.api_min_ver < 5)) ||
1006 (hw->mac.type == I40E_MAC_X722));
1007 if (!use_register) {
1008 do_retry:
1009 status = i40evf_aq_rx_ctl_write_register(hw, reg_addr,
1010 reg_val, NULL);
1011 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
1012 usleep_range(1000, 2000);
1013 retry--;
1014 goto do_retry;
1015 }
1016 }
1017
1018 /* if the AQ access failed, try the old-fashioned way */
1019 if (status || use_register)
1020 wr32(hw, reg_addr, reg_val);
1021 }
1022
1023 /**
1024 * i40e_aq_send_msg_to_pf
1025 * @hw: pointer to the hardware structure
1026 * @v_opcode: opcodes for VF-PF communication
1027 * @v_retval: return error code
1028 * @msg: pointer to the msg buffer
1029 * @msglen: msg length
1030 * @cmd_details: pointer to command details
1031 *
1032 * Send message to PF driver using admin queue. By default, this message
1033 * is sent asynchronously, i.e. i40evf_asq_send_command() does not wait for
1034 * completion before returning.
1035 **/
i40e_aq_send_msg_to_pf(struct i40e_hw * hw,enum virtchnl_ops v_opcode,i40e_status v_retval,u8 * msg,u16 msglen,struct i40e_asq_cmd_details * cmd_details)1036 i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
1037 enum virtchnl_ops v_opcode,
1038 i40e_status v_retval,
1039 u8 *msg, u16 msglen,
1040 struct i40e_asq_cmd_details *cmd_details)
1041 {
1042 struct i40e_aq_desc desc;
1043 struct i40e_asq_cmd_details details;
1044 i40e_status status;
1045
1046 i40evf_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_pf);
1047 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1048 desc.cookie_high = cpu_to_le32(v_opcode);
1049 desc.cookie_low = cpu_to_le32(v_retval);
1050 if (msglen) {
1051 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF
1052 | I40E_AQ_FLAG_RD));
1053 if (msglen > I40E_AQ_LARGE_BUF)
1054 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1055 desc.datalen = cpu_to_le16(msglen);
1056 }
1057 if (!cmd_details) {
1058 memset(&details, 0, sizeof(details));
1059 details.async = true;
1060 cmd_details = &details;
1061 }
1062 status = i40evf_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1063 return status;
1064 }
1065
1066 /**
1067 * i40e_vf_parse_hw_config
1068 * @hw: pointer to the hardware structure
1069 * @msg: pointer to the virtual channel VF resource structure
1070 *
1071 * Given a VF resource message from the PF, populate the hw struct
1072 * with appropriate information.
1073 **/
i40e_vf_parse_hw_config(struct i40e_hw * hw,struct virtchnl_vf_resource * msg)1074 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
1075 struct virtchnl_vf_resource *msg)
1076 {
1077 struct virtchnl_vsi_resource *vsi_res;
1078 int i;
1079
1080 vsi_res = &msg->vsi_res[0];
1081
1082 hw->dev_caps.num_vsis = msg->num_vsis;
1083 hw->dev_caps.num_rx_qp = msg->num_queue_pairs;
1084 hw->dev_caps.num_tx_qp = msg->num_queue_pairs;
1085 hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
1086 hw->dev_caps.dcb = msg->vf_cap_flags &
1087 VIRTCHNL_VF_OFFLOAD_L2;
1088 hw->dev_caps.fcoe = 0;
1089 for (i = 0; i < msg->num_vsis; i++) {
1090 if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
1091 ether_addr_copy(hw->mac.perm_addr,
1092 vsi_res->default_mac_addr);
1093 ether_addr_copy(hw->mac.addr,
1094 vsi_res->default_mac_addr);
1095 }
1096 vsi_res++;
1097 }
1098 }
1099
1100 /**
1101 * i40e_vf_reset
1102 * @hw: pointer to the hardware structure
1103 *
1104 * Send a VF_RESET message to the PF. Does not wait for response from PF
1105 * as none will be forthcoming. Immediately after calling this function,
1106 * the admin queue should be shut down and (optionally) reinitialized.
1107 **/
i40e_vf_reset(struct i40e_hw * hw)1108 i40e_status i40e_vf_reset(struct i40e_hw *hw)
1109 {
1110 return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
1111 0, NULL, 0, NULL);
1112 }
1113
1114 /**
1115 * i40evf_aq_write_ddp - Write dynamic device personalization (ddp)
1116 * @hw: pointer to the hw struct
1117 * @buff: command buffer (size in bytes = buff_size)
1118 * @buff_size: buffer size in bytes
1119 * @track_id: package tracking id
1120 * @error_offset: returns error offset
1121 * @error_info: returns error information
1122 * @cmd_details: pointer to command details structure or NULL
1123 **/
1124 enum
i40evf_aq_write_ddp(struct i40e_hw * hw,void * buff,u16 buff_size,u32 track_id,u32 * error_offset,u32 * error_info,struct i40e_asq_cmd_details * cmd_details)1125 i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,
1126 u16 buff_size, u32 track_id,
1127 u32 *error_offset, u32 *error_info,
1128 struct i40e_asq_cmd_details *cmd_details)
1129 {
1130 struct i40e_aq_desc desc;
1131 struct i40e_aqc_write_personalization_profile *cmd =
1132 (struct i40e_aqc_write_personalization_profile *)
1133 &desc.params.raw;
1134 struct i40e_aqc_write_ddp_resp *resp;
1135 i40e_status status;
1136
1137 i40evf_fill_default_direct_cmd_desc(&desc,
1138 i40e_aqc_opc_write_personalization_profile);
1139
1140 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
1141 if (buff_size > I40E_AQ_LARGE_BUF)
1142 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1143
1144 desc.datalen = cpu_to_le16(buff_size);
1145
1146 cmd->profile_track_id = cpu_to_le32(track_id);
1147
1148 status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1149 if (!status) {
1150 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
1151 if (error_offset)
1152 *error_offset = le32_to_cpu(resp->error_offset);
1153 if (error_info)
1154 *error_info = le32_to_cpu(resp->error_info);
1155 }
1156
1157 return status;
1158 }
1159
1160 /**
1161 * i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp)
1162 * @hw: pointer to the hw struct
1163 * @buff: command buffer (size in bytes = buff_size)
1164 * @buff_size: buffer size in bytes
1165 * @flags: AdminQ command flags
1166 * @cmd_details: pointer to command details structure or NULL
1167 **/
1168 enum
i40evf_aq_get_ddp_list(struct i40e_hw * hw,void * buff,u16 buff_size,u8 flags,struct i40e_asq_cmd_details * cmd_details)1169 i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
1170 u16 buff_size, u8 flags,
1171 struct i40e_asq_cmd_details *cmd_details)
1172 {
1173 struct i40e_aq_desc desc;
1174 struct i40e_aqc_get_applied_profiles *cmd =
1175 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
1176 i40e_status status;
1177
1178 i40evf_fill_default_direct_cmd_desc(&desc,
1179 i40e_aqc_opc_get_personalization_profile_list);
1180
1181 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1182 if (buff_size > I40E_AQ_LARGE_BUF)
1183 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1184 desc.datalen = cpu_to_le16(buff_size);
1185
1186 cmd->flags = flags;
1187
1188 status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1189
1190 return status;
1191 }
1192
1193 /**
1194 * i40evf_find_segment_in_package
1195 * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
1196 * @pkg_hdr: pointer to the package header to be searched
1197 *
1198 * This function searches a package file for a particular segment type. On
1199 * success it returns a pointer to the segment header, otherwise it will
1200 * return NULL.
1201 **/
1202 struct i40e_generic_seg_header *
i40evf_find_segment_in_package(u32 segment_type,struct i40e_package_header * pkg_hdr)1203 i40evf_find_segment_in_package(u32 segment_type,
1204 struct i40e_package_header *pkg_hdr)
1205 {
1206 struct i40e_generic_seg_header *segment;
1207 u32 i;
1208
1209 /* Search all package segments for the requested segment type */
1210 for (i = 0; i < pkg_hdr->segment_count; i++) {
1211 segment =
1212 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
1213 pkg_hdr->segment_offset[i]);
1214
1215 if (segment->type == segment_type)
1216 return segment;
1217 }
1218
1219 return NULL;
1220 }
1221
1222 /**
1223 * i40evf_write_profile
1224 * @hw: pointer to the hardware structure
1225 * @profile: pointer to the profile segment of the package to be downloaded
1226 * @track_id: package tracking id
1227 *
1228 * Handles the download of a complete package.
1229 */
1230 enum i40e_status_code
i40evf_write_profile(struct i40e_hw * hw,struct i40e_profile_segment * profile,u32 track_id)1231 i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
1232 u32 track_id)
1233 {
1234 i40e_status status = 0;
1235 struct i40e_section_table *sec_tbl;
1236 struct i40e_profile_section_header *sec = NULL;
1237 u32 dev_cnt;
1238 u32 vendor_dev_id;
1239 u32 *nvm;
1240 u32 section_size = 0;
1241 u32 offset = 0, info = 0;
1242 u32 i;
1243
1244 dev_cnt = profile->device_table_count;
1245
1246 for (i = 0; i < dev_cnt; i++) {
1247 vendor_dev_id = profile->device_table[i].vendor_dev_id;
1248 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
1249 if (hw->device_id == (vendor_dev_id & 0xFFFF))
1250 break;
1251 }
1252 if (i == dev_cnt) {
1253 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
1254 return I40E_ERR_DEVICE_NOT_SUPPORTED;
1255 }
1256
1257 nvm = (u32 *)&profile->device_table[dev_cnt];
1258 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
1259
1260 for (i = 0; i < sec_tbl->section_count; i++) {
1261 sec = (struct i40e_profile_section_header *)((u8 *)profile +
1262 sec_tbl->section_offset[i]);
1263
1264 /* Skip 'AQ', 'note' and 'name' sections */
1265 if (sec->section.type != SECTION_TYPE_MMIO)
1266 continue;
1267
1268 section_size = sec->section.size +
1269 sizeof(struct i40e_profile_section_header);
1270
1271 /* Write profile */
1272 status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
1273 track_id, &offset, &info, NULL);
1274 if (status) {
1275 i40e_debug(hw, I40E_DEBUG_PACKAGE,
1276 "Failed to write profile: offset %d, info %d",
1277 offset, info);
1278 break;
1279 }
1280 }
1281 return status;
1282 }
1283
1284 /**
1285 * i40evf_add_pinfo_to_list
1286 * @hw: pointer to the hardware structure
1287 * @profile: pointer to the profile segment of the package
1288 * @profile_info_sec: buffer for information section
1289 * @track_id: package tracking id
1290 *
1291 * Register a profile to the list of loaded profiles.
1292 */
1293 enum i40e_status_code
i40evf_add_pinfo_to_list(struct i40e_hw * hw,struct i40e_profile_segment * profile,u8 * profile_info_sec,u32 track_id)1294 i40evf_add_pinfo_to_list(struct i40e_hw *hw,
1295 struct i40e_profile_segment *profile,
1296 u8 *profile_info_sec, u32 track_id)
1297 {
1298 i40e_status status = 0;
1299 struct i40e_profile_section_header *sec = NULL;
1300 struct i40e_profile_info *pinfo;
1301 u32 offset = 0, info = 0;
1302
1303 sec = (struct i40e_profile_section_header *)profile_info_sec;
1304 sec->tbl_size = 1;
1305 sec->data_end = sizeof(struct i40e_profile_section_header) +
1306 sizeof(struct i40e_profile_info);
1307 sec->section.type = SECTION_TYPE_INFO;
1308 sec->section.offset = sizeof(struct i40e_profile_section_header);
1309 sec->section.size = sizeof(struct i40e_profile_info);
1310 pinfo = (struct i40e_profile_info *)(profile_info_sec +
1311 sec->section.offset);
1312 pinfo->track_id = track_id;
1313 pinfo->version = profile->version;
1314 pinfo->op = I40E_DDP_ADD_TRACKID;
1315 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
1316
1317 status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end,
1318 track_id, &offset, &info, NULL);
1319 return status;
1320 }
1321
