1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_mult.h"
18 #include "ccu_nk.h"
19 #include "ccu_nkm.h"
20 #include "ccu_nkmp.h"
21 #include "ccu_nm.h"
22
23 #include "ccu-sun50i-h6.h"
24
25 /*
26 * The CPU PLL is actually NP clock, with P being /1, /2 or /4. However
27 * P should only be used for output frequencies lower than 288 MHz.
28 *
29 * For now we can just model it as a multiplier clock, and force P to /1.
30 *
31 * The M factor is present in the register's description, but not in the
32 * frequency formula, and it's documented as "M is only used for backdoor
33 * testing", so it's not modelled and then force to 0.
34 */
35 #define SUN50I_H6_PLL_CPUX_REG 0x000
36 static struct ccu_mult pll_cpux_clk = {
37 .enable = BIT(31),
38 .lock = BIT(28),
39 .mult = _SUNXI_CCU_MULT_MIN(8, 8, 12),
40 .common = {
41 .reg = 0x000,
42 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
43 &ccu_mult_ops,
44 CLK_SET_RATE_UNGATE),
45 },
46 };
47
48 /* Some PLLs are input * N / div1 / P. Model them as NKMP with no K */
49 #define SUN50I_H6_PLL_DDR0_REG 0x010
50 static struct ccu_nkmp pll_ddr0_clk = {
51 .enable = BIT(31),
52 .lock = BIT(28),
53 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
54 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
55 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
56 .common = {
57 .reg = 0x010,
58 .hw.init = CLK_HW_INIT("pll-ddr0", "osc24M",
59 &ccu_nkmp_ops,
60 CLK_SET_RATE_UNGATE),
61 },
62 };
63
64 #define SUN50I_H6_PLL_PERIPH0_REG 0x020
65 static struct ccu_nkmp pll_periph0_clk = {
66 .enable = BIT(31),
67 .lock = BIT(28),
68 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
69 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
70 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
71 .fixed_post_div = 4,
72 .common = {
73 .reg = 0x020,
74 .features = CCU_FEATURE_FIXED_POSTDIV,
75 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
76 &ccu_nkmp_ops,
77 CLK_SET_RATE_UNGATE),
78 },
79 };
80
81 #define SUN50I_H6_PLL_PERIPH1_REG 0x028
82 static struct ccu_nkmp pll_periph1_clk = {
83 .enable = BIT(31),
84 .lock = BIT(28),
85 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
87 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
88 .fixed_post_div = 4,
89 .common = {
90 .reg = 0x028,
91 .features = CCU_FEATURE_FIXED_POSTDIV,
92 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
93 &ccu_nkmp_ops,
94 CLK_SET_RATE_UNGATE),
95 },
96 };
97
98 #define SUN50I_H6_PLL_GPU_REG 0x030
99 static struct ccu_nkmp pll_gpu_clk = {
100 .enable = BIT(31),
101 .lock = BIT(28),
102 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
103 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
104 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
105 .common = {
106 .reg = 0x030,
107 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
108 &ccu_nkmp_ops,
109 CLK_SET_RATE_UNGATE),
110 },
111 };
112
113 /*
114 * For Video PLLs, the output divider is described as "used for testing"
115 * in the user manual. So it's not modelled and forced to 0.
116 */
117 #define SUN50I_H6_PLL_VIDEO0_REG 0x040
118 static struct ccu_nm pll_video0_clk = {
119 .enable = BIT(31),
120 .lock = BIT(28),
121 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
122 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
123 .fixed_post_div = 4,
124 .min_rate = 288000000,
125 .max_rate = 2400000000UL,
126 .common = {
127 .reg = 0x040,
128 .features = CCU_FEATURE_FIXED_POSTDIV,
129 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
130 &ccu_nm_ops,
131 CLK_SET_RATE_UNGATE),
132 },
133 };
134
135 #define SUN50I_H6_PLL_VIDEO1_REG 0x048
136 static struct ccu_nm pll_video1_clk = {
137 .enable = BIT(31),
138 .lock = BIT(28),
139 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
140 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
141 .fixed_post_div = 4,
142 .min_rate = 288000000,
143 .max_rate = 2400000000UL,
144 .common = {
145 .reg = 0x048,
146 .features = CCU_FEATURE_FIXED_POSTDIV,
147 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
148 &ccu_nm_ops,
149 CLK_SET_RATE_UNGATE),
150 },
151 };
152
153 #define SUN50I_H6_PLL_VE_REG 0x058
154 static struct ccu_nkmp pll_ve_clk = {
155 .enable = BIT(31),
156 .lock = BIT(28),
157 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
158 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
159 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
160 .common = {
161 .reg = 0x058,
162 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
163 &ccu_nkmp_ops,
164 CLK_SET_RATE_UNGATE),
165 },
166 };
167
168 #define SUN50I_H6_PLL_DE_REG 0x060
169 static struct ccu_nkmp pll_de_clk = {
170 .enable = BIT(31),
171 .lock = BIT(28),
172 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
173 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
174 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
175 .common = {
176 .reg = 0x060,
177 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
178 &ccu_nkmp_ops,
179 CLK_SET_RATE_UNGATE),
180 },
181 };
182
183 #define SUN50I_H6_PLL_HSIC_REG 0x070
184 static struct ccu_nkmp pll_hsic_clk = {
185 .enable = BIT(31),
186 .lock = BIT(28),
187 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
188 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
189 .p = _SUNXI_CCU_DIV(0, 1), /* output divider */
190 .common = {
191 .reg = 0x070,
192 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
193 &ccu_nkmp_ops,
194 CLK_SET_RATE_UNGATE),
195 },
196 };
197
198 /*
199 * The Audio PLL is supposed to have 3 outputs: 2 fixed factors from
200 * the base (2x and 4x), and one variable divider (the one true pll audio).
201 *
202 * We don't have any need for the variable divider for now, so we just
203 * hardcode it to match with the clock names.
204 */
205 #define SUN50I_H6_PLL_AUDIO_REG 0x078
206 static struct ccu_nm pll_audio_base_clk = {
207 .enable = BIT(31),
208 .lock = BIT(28),
209 .n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
210 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
211 .common = {
212 .reg = 0x078,
213 .hw.init = CLK_HW_INIT("pll-audio-base", "osc24M",
214 &ccu_nm_ops,
215 CLK_SET_RATE_UNGATE),
216 },
217 };
218
219 static const char * const cpux_parents[] = { "osc24M", "osc32k",
220 "iosc", "pll-cpux" };
221 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
222 0x500, 24, 2, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
223 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x500, 0, 2, 0);
224 static SUNXI_CCU_M(cpux_apb_clk, "cpux-apb", "cpux", 0x500, 8, 2, 0);
225
226 static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
227 "iosc", "pll-periph0" };
228 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
229 psi_ahb1_ahb2_parents,
230 0x510,
231 0, 5, /* M */
232 8, 2, /* P */
233 24, 2, /* mux */
234 0);
235
236 static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
237 "psi-ahb1-ahb2",
238 "pll-periph0" };
239 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
240 0, 5, /* M */
241 8, 2, /* P */
242 24, 2, /* mux */
243 0);
244
245 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
246 0, 5, /* M */
247 8, 2, /* P */
248 24, 2, /* mux */
249 0);
250
251 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
252 0, 5, /* M */
253 8, 2, /* P */
254 24, 2, /* mux */
255 0);
256
257 static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x",
258 "pll-ddr0", "pll-periph0-4x" };
259 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents, 0x540,
260 0, 3, /* M */
261 24, 2, /* mux */
262 BIT(31), /* gate */
263 CLK_IS_CRITICAL);
264
265 static const char * const de_parents[] = { "pll-de", "pll-periph0-2x" };
266 static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents, 0x600,
267 0, 4, /* M */
268 24, 1, /* mux */
269 BIT(31), /* gate */
270 CLK_SET_RATE_PARENT);
271
272 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "psi-ahb1-ahb2",
273 0x60c, BIT(0), 0);
274
275 static const char * const deinterlace_parents[] = { "pll-periph0",
276 "pll-periph1" };
277 static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace",
278 deinterlace_parents,
279 0x620,
280 0, 4, /* M */
281 24, 1, /* mux */
282 BIT(31), /* gate */
283 0);
284
285 static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
286 0x62c, BIT(0), 0);
287
288 static const char * const gpu_parents[] = { "pll-gpu" };
289 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
290 0, 3, /* M */
291 24, 1, /* mux */
292 BIT(31), /* gate */
293 0);
294
295 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
296 0x67c, BIT(0), 0);
297
298 /* Also applies to EMCE */
299 static const char * const ce_parents[] = { "osc24M", "pll-periph0-2x" };
300 static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x680,
301 0, 4, /* M */
302 8, 2, /* N */
303 24, 1, /* mux */
304 BIT(31),/* gate */
305 0);
306
307 static SUNXI_CCU_GATE(bus_ce_clk, "bus-ce", "psi-ahb1-ahb2",
308 0x68c, BIT(0), 0);
309
310 static const char * const ve_parents[] = { "pll-ve" };
311 static SUNXI_CCU_M_WITH_MUX_GATE(ve_clk, "ve", ve_parents, 0x690,
312 0, 3, /* M */
313 24, 1, /* mux */
314 BIT(31), /* gate */
315 CLK_SET_RATE_PARENT);
316
317 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "psi-ahb1-ahb2",
318 0x69c, BIT(0), 0);
319
320 static SUNXI_CCU_MP_WITH_MUX_GATE(emce_clk, "emce", ce_parents, 0x6b0,
321 0, 4, /* M */
322 8, 2, /* N */
323 24, 1, /* mux */
324 BIT(31),/* gate */
325 0);
326
327 static SUNXI_CCU_GATE(bus_emce_clk, "bus-emce", "psi-ahb1-ahb2",
328 0x6bc, BIT(0), 0);
329
330 static const char * const vp9_parents[] = { "pll-ve", "pll-periph0-2x" };
331 static SUNXI_CCU_M_WITH_MUX_GATE(vp9_clk, "vp9", vp9_parents, 0x6c0,
332 0, 3, /* M */
333 24, 1, /* mux */
334 BIT(31), /* gate */
335 0);
336
337 static SUNXI_CCU_GATE(bus_vp9_clk, "bus-vp9", "psi-ahb1-ahb2",
338 0x6cc, BIT(0), 0);
339
340 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "psi-ahb1-ahb2",
341 0x70c, BIT(0), 0);
342
343 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "psi-ahb1-ahb2",
344 0x71c, BIT(0), 0);
345
346 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "psi-ahb1-ahb2",
347 0x72c, BIT(0), 0);
348
349 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "psi-ahb1-ahb2",
350 0x73c, BIT(0), 0);
351
352 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x740, BIT(31), 0);
353
354 static SUNXI_CCU_GATE(bus_dbg_clk, "bus-dbg", "psi-ahb1-ahb2",
355 0x78c, BIT(0), 0);
356
357 static SUNXI_CCU_GATE(bus_psi_clk, "bus-psi", "psi-ahb1-ahb2",
358 0x79c, BIT(0), 0);
359
360 static SUNXI_CCU_GATE(bus_pwm_clk, "bus-pwm", "apb1", 0x7ac, BIT(0), 0);
361
362 static SUNXI_CCU_GATE(bus_iommu_clk, "bus-iommu", "apb1", 0x7bc, BIT(0), 0);
363
364 static const char * const dram_parents[] = { "pll-ddr0" };
365 static struct ccu_div dram_clk = {
366 .div = _SUNXI_CCU_DIV(0, 2),
367 .mux = _SUNXI_CCU_MUX(24, 2),
368 .common = {
369 .reg = 0x800,
370 .hw.init = CLK_HW_INIT_PARENTS("dram",
371 dram_parents,
372 &ccu_div_ops,
373 CLK_IS_CRITICAL),
374 },
375 };
376
377 static SUNXI_CCU_GATE(mbus_dma_clk, "mbus-dma", "mbus",
378 0x804, BIT(0), 0);
379 static SUNXI_CCU_GATE(mbus_ve_clk, "mbus-ve", "mbus",
380 0x804, BIT(1), 0);
381 static SUNXI_CCU_GATE(mbus_ce_clk, "mbus-ce", "mbus",
382 0x804, BIT(2), 0);
383 static SUNXI_CCU_GATE(mbus_ts_clk, "mbus-ts", "mbus",
384 0x804, BIT(3), 0);
385 static SUNXI_CCU_GATE(mbus_nand_clk, "mbus-nand", "mbus",
386 0x804, BIT(5), 0);
387 static SUNXI_CCU_GATE(mbus_csi_clk, "mbus-csi", "mbus",
388 0x804, BIT(8), 0);
389 static SUNXI_CCU_GATE(mbus_deinterlace_clk, "mbus-deinterlace", "mbus",
390 0x804, BIT(11), 0);
391
392 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "psi-ahb1-ahb2",
393 0x80c, BIT(0), CLK_IS_CRITICAL);
394
395 static const char * const nand_spi_parents[] = { "osc24M", "pll-periph0",
396 "pll-periph1", "pll-periph0-2x",
397 "pll-periph1-2x" };
398 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_clk, "nand0", nand_spi_parents, 0x810,
399 0, 4, /* M */
400 8, 2, /* N */
401 24, 3, /* mux */
402 BIT(31),/* gate */
403 0);
404
405 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_clk, "nand1", nand_spi_parents, 0x814,
406 0, 4, /* M */
407 8, 2, /* N */
408 24, 3, /* mux */
409 BIT(31),/* gate */
410 0);
411
412 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb3", 0x82c, BIT(0), 0);
413
414 static const char * const mmc_parents[] = { "osc24M", "pll-periph0-2x",
415 "pll-periph1-2x" };
416 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0", mmc_parents, 0x830,
417 0, 4, /* M */
418 8, 2, /* N */
419 24, 2, /* mux */
420 BIT(31), /* gate */
421 2, /* post-div */
422 0);
423
424 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1", mmc_parents, 0x834,
425 0, 4, /* M */
426 8, 2, /* N */
427 24, 2, /* mux */
428 BIT(31), /* gate */
429 2, /* post-div */
430 0);
431
432 static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2", mmc_parents, 0x838,
433 0, 4, /* M */
434 8, 2, /* N */
435 24, 2, /* mux */
436 BIT(31), /* gate */
437 2, /* post-div */
438 0);
439
440 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb3", 0x84c, BIT(0), 0);
441 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb3", 0x84c, BIT(1), 0);
442 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb3", 0x84c, BIT(2), 0);
443
444 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2", 0x90c, BIT(0), 0);
445 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2", 0x90c, BIT(1), 0);
446 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2", 0x90c, BIT(2), 0);
447 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2", 0x90c, BIT(3), 0);
448
449 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2", 0x91c, BIT(0), 0);
450 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2", 0x91c, BIT(1), 0);
451 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2", 0x91c, BIT(2), 0);
452 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb2", 0x91c, BIT(3), 0);
453
454 static SUNXI_CCU_GATE(bus_scr0_clk, "bus-scr0", "apb2", 0x93c, BIT(0), 0);
455 static SUNXI_CCU_GATE(bus_scr1_clk, "bus-scr1", "apb2", 0x93c, BIT(1), 0);
456
457 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", nand_spi_parents, 0x940,
458 0, 4, /* M */
459 8, 2, /* N */
460 24, 3, /* mux */
461 BIT(31),/* gate */
462 0);
463
464 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", nand_spi_parents, 0x944,
465 0, 4, /* M */
466 8, 2, /* N */
467 24, 3, /* mux */
468 BIT(31),/* gate */
469 0);
470
471 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb3", 0x96c, BIT(0), 0);
472 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb3", 0x96c, BIT(1), 0);
473
474 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb3", 0x97c, BIT(0), 0);
475
476 static const char * const ts_parents[] = { "osc24M", "pll-periph0" };
477 static SUNXI_CCU_MP_WITH_MUX_GATE(ts_clk, "ts", ts_parents, 0x9b0,
478 0, 4, /* M */
479 8, 2, /* N */
480 24, 1, /* mux */
481 BIT(31),/* gate */
482 0);
483
484 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb3", 0x9bc, BIT(0), 0);
485
486 static const char * const ir_tx_parents[] = { "osc32k", "osc24M" };
487 static SUNXI_CCU_MP_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_parents, 0x9c0,
488 0, 4, /* M */
489 8, 2, /* N */
490 24, 1, /* mux */
491 BIT(31),/* gate */
492 0);
493
494 static SUNXI_CCU_GATE(bus_ir_tx_clk, "bus-ir-tx", "apb1", 0x9cc, BIT(0), 0);
495
496 static SUNXI_CCU_GATE(bus_ths_clk, "bus-ths", "apb1", 0x9fc, BIT(0), 0);
497
498 static const char * const audio_parents[] = { "pll-audio", "pll-audio-2x", "pll-audio-4x" };
499 static struct ccu_div i2s3_clk = {
500 .enable = BIT(31),
501 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
502 .mux = _SUNXI_CCU_MUX(24, 2),
503 .common = {
504 .reg = 0xa0c,
505 .hw.init = CLK_HW_INIT_PARENTS("i2s3",
506 audio_parents,
507 &ccu_div_ops,
508 CLK_SET_RATE_PARENT),
509 },
510 };
511
512 static struct ccu_div i2s0_clk = {
513 .enable = BIT(31),
514 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
515 .mux = _SUNXI_CCU_MUX(24, 2),
516 .common = {
517 .reg = 0xa10,
518 .hw.init = CLK_HW_INIT_PARENTS("i2s0",
519 audio_parents,
520 &ccu_div_ops,
521 CLK_SET_RATE_PARENT),
522 },
523 };
524
525 static struct ccu_div i2s1_clk = {
526 .enable = BIT(31),
527 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
528 .mux = _SUNXI_CCU_MUX(24, 2),
529 .common = {
530 .reg = 0xa14,
531 .hw.init = CLK_HW_INIT_PARENTS("i2s1",
532 audio_parents,
533 &ccu_div_ops,
534 CLK_SET_RATE_PARENT),
535 },
536 };
537
538 static struct ccu_div i2s2_clk = {
539 .enable = BIT(31),
540 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
541 .mux = _SUNXI_CCU_MUX(24, 2),
542 .common = {
543 .reg = 0xa18,
544 .hw.init = CLK_HW_INIT_PARENTS("i2s2",
545 audio_parents,
546 &ccu_div_ops,
547 CLK_SET_RATE_PARENT),
548 },
549 };
550
551 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1", 0xa1c, BIT(0), 0);
552 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1", 0xa1c, BIT(1), 0);
553 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1", 0xa1c, BIT(2), 0);
554 static SUNXI_CCU_GATE(bus_i2s3_clk, "bus-i2s3", "apb1", 0xa1c, BIT(3), 0);
555
556 static struct ccu_div spdif_clk = {
557 .enable = BIT(31),
558 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
559 .mux = _SUNXI_CCU_MUX(24, 2),
560 .common = {
561 .reg = 0xa20,
562 .hw.init = CLK_HW_INIT_PARENTS("spdif",
563 audio_parents,
564 &ccu_div_ops,
565 0),
566 },
567 };
568
569 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1", 0xa2c, BIT(0), 0);
570
571 static struct ccu_div dmic_clk = {
572 .enable = BIT(31),
573 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
574 .mux = _SUNXI_CCU_MUX(24, 2),
575 .common = {
576 .reg = 0xa40,
577 .hw.init = CLK_HW_INIT_PARENTS("dmic",
578 audio_parents,
579 &ccu_div_ops,
580 0),
581 },
582 };
583
584 static SUNXI_CCU_GATE(bus_dmic_clk, "bus-dmic", "apb1", 0xa4c, BIT(0), 0);
585
586 static struct ccu_div audio_hub_clk = {
587 .enable = BIT(31),
588 .div = _SUNXI_CCU_DIV_FLAGS(8, 2, CLK_DIVIDER_POWER_OF_TWO),
589 .mux = _SUNXI_CCU_MUX(24, 2),
590 .common = {
591 .reg = 0xa60,
592 .hw.init = CLK_HW_INIT_PARENTS("audio-hub",
593 audio_parents,
594 &ccu_div_ops,
595 0),
596 },
597 };
598
599 static SUNXI_CCU_GATE(bus_audio_hub_clk, "bus-audio-hub", "apb1", 0xa6c, BIT(0), 0);
600
601 /*
602 * There are OHCI 12M clock source selection bits for 2 USB 2.0 ports.
603 * We will force them to 0 (12M divided from 48M).
604 */
605 #define SUN50I_H6_USB0_CLK_REG 0xa70
606 #define SUN50I_H6_USB3_CLK_REG 0xa7c
607
608 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc12M", 0xa70, BIT(31), 0);
609 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M", 0xa70, BIT(29), 0);
610
611 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M", 0xa74, BIT(29), 0);
612
613 static SUNXI_CCU_GATE(usb_ohci3_clk, "usb-ohci3", "osc12M", 0xa7c, BIT(31), 0);
614 static SUNXI_CCU_GATE(usb_phy3_clk, "usb-phy3", "osc12M", 0xa7c, BIT(29), 0);
615 static SUNXI_CCU_GATE(usb_hsic_12m_clk, "usb-hsic-12M", "osc12M", 0xa7c, BIT(27), 0);
616 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic", 0xa7c, BIT(26), 0);
617
618 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb3", 0xa8c, BIT(0), 0);
619 static SUNXI_CCU_GATE(bus_ohci3_clk, "bus-ohci3", "ahb3", 0xa8c, BIT(3), 0);
620 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb3", 0xa8c, BIT(4), 0);
621 static SUNXI_CCU_GATE(bus_xhci_clk, "bus-xhci", "ahb3", 0xa8c, BIT(5), 0);
622 static SUNXI_CCU_GATE(bus_ehci3_clk, "bus-ehci3", "ahb3", 0xa8c, BIT(7), 0);
623 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb3", 0xa8c, BIT(8), 0);
624
625 static struct clk_fixed_factor pll_periph0_4x_clk;
626 static CLK_FIXED_FACTOR_HW(pcie_ref_100m_clk, "pcie-ref-100M",
627 &pll_periph0_4x_clk.hw, 24, 1, 0);
628 static SUNXI_CCU_GATE(pcie_ref_clk, "pcie-ref", "pcie-ref-100M",
629 0xab0, BIT(31), 0);
630 static SUNXI_CCU_GATE(pcie_ref_out_clk, "pcie-ref-out", "pcie-ref",
631 0xab0, BIT(30), 0);
632
633 static SUNXI_CCU_M_WITH_GATE(pcie_maxi_clk, "pcie-maxi",
634 "pll-periph0", 0xab4,
635 0, 4, /* M */
636 BIT(31), /* gate */
637 0);
638
639 static SUNXI_CCU_M_WITH_GATE(pcie_aux_clk, "pcie-aux", "osc24M", 0xab8,
640 0, 5, /* M */
641 BIT(31), /* gate */
642 0);
643
644 static SUNXI_CCU_GATE(bus_pcie_clk, "bus-pcie", "psi-ahb1-ahb2",
645 0xabc, BIT(0), 0);
646
647 static const char * const hdmi_parents[] = { "pll-video0", "pll-video1",
648 "pll-video1-4x" };
649 static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents, 0xb00,
650 0, 4, /* M */
651 24, 2, /* mux */
652 BIT(31), /* gate */
653 0);
654
655 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0xb04, BIT(31), 0);
656
657 static const char * const hdmi_cec_parents[] = { "osc32k", "pll-periph0-2x" };
658 static const struct ccu_mux_fixed_prediv hdmi_cec_predivs[] = {
659 { .index = 1, .div = 36621 },
660 };
661
662 #define SUN50I_H6_HDMI_CEC_CLK_REG 0xb10
663 static struct ccu_mux hdmi_cec_clk = {
664 .enable = BIT(31),
665
666 .mux = {
667 .shift = 24,
668 .width = 2,
669
670 .fixed_predivs = hdmi_cec_predivs,
671 .n_predivs = ARRAY_SIZE(hdmi_cec_predivs),
672 },
673
674 .common = {
675 .reg = 0xb10,
676 .features = CCU_FEATURE_VARIABLE_PREDIV,
677 .hw.init = CLK_HW_INIT_PARENTS("hdmi-cec",
678 hdmi_cec_parents,
679 &ccu_mux_ops,
680 0),
681 },
682 };
683
684 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb3", 0xb1c, BIT(0), 0);
685
686 static SUNXI_CCU_GATE(bus_tcon_top_clk, "bus-tcon-top", "ahb3",
687 0xb5c, BIT(0), 0);
688
689 static const char * const tcon_lcd0_parents[] = { "pll-video0",
690 "pll-video0-4x",
691 "pll-video1" };
692 static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0",
693 tcon_lcd0_parents, 0xb60,
694 24, 3, /* mux */
695 BIT(31), /* gate */
696 CLK_SET_RATE_PARENT);
697
698 static SUNXI_CCU_GATE(bus_tcon_lcd0_clk, "bus-tcon-lcd0", "ahb3",
699 0xb7c, BIT(0), 0);
700
701 static const char * const tcon_tv0_parents[] = { "pll-video0",
702 "pll-video0-4x",
703 "pll-video1",
704 "pll-video1-4x" };
705 static SUNXI_CCU_MP_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0",
706 tcon_tv0_parents, 0xb80,
707 0, 4, /* M */
708 8, 2, /* P */
709 24, 3, /* mux */
710 BIT(31), /* gate */
711 CLK_SET_RATE_PARENT);
712
713 static SUNXI_CCU_GATE(bus_tcon_tv0_clk, "bus-tcon-tv0", "ahb3",
714 0xb9c, BIT(0), 0);
715
716 static SUNXI_CCU_GATE(csi_cci_clk, "csi-cci", "osc24M", 0xc00, BIT(0), 0);
717
718 static const char * const csi_top_parents[] = { "pll-video0", "pll-ve",
719 "pll-periph0" };
720 static const u8 csi_top_table[] = { 0, 2, 3 };
721 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_top_clk, "csi-top",
722 csi_top_parents, csi_top_table, 0xc04,
723 0, 4, /* M */
724 24, 3, /* mux */
725 BIT(31), /* gate */
726 0);
727
728 static const char * const csi_mclk_parents[] = { "osc24M", "pll-video0",
729 "pll-periph0", "pll-periph1" };
730 static SUNXI_CCU_M_WITH_MUX_GATE(csi_mclk_clk, "csi-mclk",
731 csi_mclk_parents, 0xc08,
732 0, 5, /* M */
733 24, 3, /* mux */
734 BIT(31), /* gate */
735 0);
736
737 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb3", 0xc2c, BIT(0), 0);
738
739 static const char * const hdcp_parents[] = { "pll-periph0", "pll-periph1" };
740 static SUNXI_CCU_M_WITH_MUX_GATE(hdcp_clk, "hdcp", hdcp_parents, 0xc40,
741 0, 4, /* M */
742 24, 2, /* mux */
743 BIT(31), /* gate */
744 0);
745
746 static SUNXI_CCU_GATE(bus_hdcp_clk, "bus-hdcp", "ahb3", 0xc4c, BIT(0), 0);
747
748 /* Fixed factor clocks */
749 static CLK_FIXED_FACTOR_FW_NAME(osc12M_clk, "osc12M", "hosc", 2, 1, 0);
750
751 static const struct clk_hw *clk_parent_pll_audio[] = {
752 &pll_audio_base_clk.common.hw
753 };
754
755 /*
756 * The divider of pll-audio is fixed to 8 now, as pll-audio-4x has a
757 * fixed post-divider 2.
758 */
759 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
760 clk_parent_pll_audio,
761 8, 1, CLK_SET_RATE_PARENT);
762 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
763 clk_parent_pll_audio,
764 4, 1, CLK_SET_RATE_PARENT);
765 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
766 clk_parent_pll_audio,
767 2, 1, CLK_SET_RATE_PARENT);
768
769 static const struct clk_hw *pll_periph0_parents[] = {
770 &pll_periph0_clk.common.hw
771 };
772 static CLK_FIXED_FACTOR_HWS(pll_periph0_4x_clk, "pll-periph0-4x",
773 pll_periph0_parents,
774 1, 4, 0);
775 static CLK_FIXED_FACTOR_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
776 pll_periph0_parents,
777 1, 2, 0);
778
779 static const struct clk_hw *pll_periph1_parents[] = {
780 &pll_periph1_clk.common.hw
781 };
782 static CLK_FIXED_FACTOR_HWS(pll_periph1_4x_clk, "pll-periph1-4x",
783 pll_periph1_parents,
784 1, 4, 0);
785 static CLK_FIXED_FACTOR_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
786 pll_periph1_parents,
787 1, 2, 0);
788
789 static CLK_FIXED_FACTOR_HW(pll_video0_4x_clk, "pll-video0-4x",
790 &pll_video0_clk.common.hw,
791 1, 4, CLK_SET_RATE_PARENT);
792 static CLK_FIXED_FACTOR_HW(pll_video1_4x_clk, "pll-video1-4x",
793 &pll_video1_clk.common.hw,
794 1, 4, CLK_SET_RATE_PARENT);
795
796 static struct ccu_common *sun50i_h6_ccu_clks[] = {
797 &pll_cpux_clk.common,
798 &pll_ddr0_clk.common,
799 &pll_periph0_clk.common,
800 &pll_periph1_clk.common,
801 &pll_gpu_clk.common,
802 &pll_video0_clk.common,
803 &pll_video1_clk.common,
804 &pll_ve_clk.common,
805 &pll_de_clk.common,
806 &pll_hsic_clk.common,
807 &pll_audio_base_clk.common,
808 &cpux_clk.common,
809 &axi_clk.common,
810 &cpux_apb_clk.common,
811 &psi_ahb1_ahb2_clk.common,
812 &ahb3_clk.common,
813 &apb1_clk.common,
814 &apb2_clk.common,
815 &mbus_clk.common,
816 &de_clk.common,
817 &bus_de_clk.common,
818 &deinterlace_clk.common,
819 &bus_deinterlace_clk.common,
820 &gpu_clk.common,
821 &bus_gpu_clk.common,
822 &ce_clk.common,
823 &bus_ce_clk.common,
824 &ve_clk.common,
825 &bus_ve_clk.common,
826 &emce_clk.common,
827 &bus_emce_clk.common,
828 &vp9_clk.common,
829 &bus_vp9_clk.common,
830 &bus_dma_clk.common,
831 &bus_msgbox_clk.common,
832 &bus_spinlock_clk.common,
833 &bus_hstimer_clk.common,
834 &avs_clk.common,
835 &bus_dbg_clk.common,
836 &bus_psi_clk.common,
837 &bus_pwm_clk.common,
838 &bus_iommu_clk.common,
839 &dram_clk.common,
840 &mbus_dma_clk.common,
841 &mbus_ve_clk.common,
842 &mbus_ce_clk.common,
843 &mbus_ts_clk.common,
844 &mbus_nand_clk.common,
845 &mbus_csi_clk.common,
846 &mbus_deinterlace_clk.common,
847 &bus_dram_clk.common,
848 &nand0_clk.common,
849 &nand1_clk.common,
850 &bus_nand_clk.common,
851 &mmc0_clk.common,
852 &mmc1_clk.common,
853 &mmc2_clk.common,
854 &bus_mmc0_clk.common,
855 &bus_mmc1_clk.common,
856 &bus_mmc2_clk.common,
857 &bus_uart0_clk.common,
858 &bus_uart1_clk.common,
859 &bus_uart2_clk.common,
860 &bus_uart3_clk.common,
861 &bus_i2c0_clk.common,
862 &bus_i2c1_clk.common,
863 &bus_i2c2_clk.common,
864 &bus_i2c3_clk.common,
865 &bus_scr0_clk.common,
866 &bus_scr1_clk.common,
867 &spi0_clk.common,
868 &spi1_clk.common,
869 &bus_spi0_clk.common,
870 &bus_spi1_clk.common,
871 &bus_emac_clk.common,
872 &ts_clk.common,
873 &bus_ts_clk.common,
874 &ir_tx_clk.common,
875 &bus_ir_tx_clk.common,
876 &bus_ths_clk.common,
877 &i2s3_clk.common,
878 &i2s0_clk.common,
879 &i2s1_clk.common,
880 &i2s2_clk.common,
881 &bus_i2s0_clk.common,
882 &bus_i2s1_clk.common,
883 &bus_i2s2_clk.common,
884 &bus_i2s3_clk.common,
885 &spdif_clk.common,
886 &bus_spdif_clk.common,
887 &dmic_clk.common,
888 &bus_dmic_clk.common,
889 &audio_hub_clk.common,
890 &bus_audio_hub_clk.common,
891 &usb_ohci0_clk.common,
892 &usb_phy0_clk.common,
893 &usb_phy1_clk.common,
894 &usb_ohci3_clk.common,
895 &usb_phy3_clk.common,
896 &usb_hsic_12m_clk.common,
897 &usb_hsic_clk.common,
898 &bus_ohci0_clk.common,
899 &bus_ohci3_clk.common,
900 &bus_ehci0_clk.common,
901 &bus_xhci_clk.common,
902 &bus_ehci3_clk.common,
903 &bus_otg_clk.common,
904 &pcie_ref_clk.common,
905 &pcie_ref_out_clk.common,
906 &pcie_maxi_clk.common,
907 &pcie_aux_clk.common,
908 &bus_pcie_clk.common,
909 &hdmi_clk.common,
910 &hdmi_slow_clk.common,
911 &hdmi_cec_clk.common,
912 &bus_hdmi_clk.common,
913 &bus_tcon_top_clk.common,
914 &tcon_lcd0_clk.common,
915 &bus_tcon_lcd0_clk.common,
916 &tcon_tv0_clk.common,
917 &bus_tcon_tv0_clk.common,
918 &csi_cci_clk.common,
919 &csi_top_clk.common,
920 &csi_mclk_clk.common,
921 &bus_csi_clk.common,
922 &hdcp_clk.common,
923 &bus_hdcp_clk.common,
924 };
925
926 static struct clk_hw_onecell_data sun50i_h6_hw_clks = {
927 .hws = {
928 [CLK_OSC12M] = &osc12M_clk.hw,
929 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
930 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
931 [CLK_PLL_PERIPH0] = &pll_periph0_clk.common.hw,
932 [CLK_PLL_PERIPH0_2X] = &pll_periph0_2x_clk.hw,
933 [CLK_PLL_PERIPH0_4X] = &pll_periph0_4x_clk.hw,
934 [CLK_PLL_PERIPH1] = &pll_periph1_clk.common.hw,
935 [CLK_PLL_PERIPH1_2X] = &pll_periph1_2x_clk.hw,
936 [CLK_PLL_PERIPH1_4X] = &pll_periph1_4x_clk.hw,
937 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
938 [CLK_PLL_VIDEO0] = &pll_video0_clk.common.hw,
939 [CLK_PLL_VIDEO0_4X] = &pll_video0_4x_clk.hw,
940 [CLK_PLL_VIDEO1] = &pll_video1_clk.common.hw,
941 [CLK_PLL_VIDEO1_4X] = &pll_video1_4x_clk.hw,
942 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
943 [CLK_PLL_DE] = &pll_de_clk.common.hw,
944 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
945 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
946 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
947 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
948 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
949 [CLK_CPUX] = &cpux_clk.common.hw,
950 [CLK_AXI] = &axi_clk.common.hw,
951 [CLK_CPUX_APB] = &cpux_apb_clk.common.hw,
952 [CLK_PSI_AHB1_AHB2] = &psi_ahb1_ahb2_clk.common.hw,
953 [CLK_AHB3] = &ahb3_clk.common.hw,
954 [CLK_APB1] = &apb1_clk.common.hw,
955 [CLK_APB2] = &apb2_clk.common.hw,
956 [CLK_MBUS] = &mbus_clk.common.hw,
957 [CLK_DE] = &de_clk.common.hw,
958 [CLK_BUS_DE] = &bus_de_clk.common.hw,
959 [CLK_DEINTERLACE] = &deinterlace_clk.common.hw,
960 [CLK_BUS_DEINTERLACE] = &bus_deinterlace_clk.common.hw,
961 [CLK_GPU] = &gpu_clk.common.hw,
962 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
963 [CLK_CE] = &ce_clk.common.hw,
964 [CLK_BUS_CE] = &bus_ce_clk.common.hw,
965 [CLK_VE] = &ve_clk.common.hw,
966 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
967 [CLK_EMCE] = &emce_clk.common.hw,
968 [CLK_BUS_EMCE] = &bus_emce_clk.common.hw,
969 [CLK_VP9] = &vp9_clk.common.hw,
970 [CLK_BUS_VP9] = &bus_vp9_clk.common.hw,
971 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
972 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
973 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
974 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
975 [CLK_AVS] = &avs_clk.common.hw,
976 [CLK_BUS_DBG] = &bus_dbg_clk.common.hw,
977 [CLK_BUS_PSI] = &bus_psi_clk.common.hw,
978 [CLK_BUS_PWM] = &bus_pwm_clk.common.hw,
979 [CLK_BUS_IOMMU] = &bus_iommu_clk.common.hw,
980 [CLK_DRAM] = &dram_clk.common.hw,
981 [CLK_MBUS_DMA] = &mbus_dma_clk.common.hw,
982 [CLK_MBUS_VE] = &mbus_ve_clk.common.hw,
983 [CLK_MBUS_CE] = &mbus_ce_clk.common.hw,
984 [CLK_MBUS_TS] = &mbus_ts_clk.common.hw,
985 [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw,
986 [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw,
987 [CLK_MBUS_DEINTERLACE] = &mbus_deinterlace_clk.common.hw,
988 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
989 [CLK_NAND0] = &nand0_clk.common.hw,
990 [CLK_NAND1] = &nand1_clk.common.hw,
991 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
992 [CLK_MMC0] = &mmc0_clk.common.hw,
993 [CLK_MMC1] = &mmc1_clk.common.hw,
994 [CLK_MMC2] = &mmc2_clk.common.hw,
995 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
996 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
997 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
998 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
999 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
1000 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
1001 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
1002 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
1003 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
1004 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
1005 [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw,
1006 [CLK_BUS_SCR0] = &bus_scr0_clk.common.hw,
1007 [CLK_BUS_SCR1] = &bus_scr1_clk.common.hw,
1008 [CLK_SPI0] = &spi0_clk.common.hw,
1009 [CLK_SPI1] = &spi1_clk.common.hw,
1010 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
1011 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
1012 [CLK_BUS_EMAC] = &bus_emac_clk.common.hw,
1013 [CLK_TS] = &ts_clk.common.hw,
1014 [CLK_BUS_TS] = &bus_ts_clk.common.hw,
1015 [CLK_IR_TX] = &ir_tx_clk.common.hw,
1016 [CLK_BUS_IR_TX] = &bus_ir_tx_clk.common.hw,
1017 [CLK_BUS_THS] = &bus_ths_clk.common.hw,
1018 [CLK_I2S3] = &i2s3_clk.common.hw,
1019 [CLK_I2S0] = &i2s0_clk.common.hw,
1020 [CLK_I2S1] = &i2s1_clk.common.hw,
1021 [CLK_I2S2] = &i2s2_clk.common.hw,
1022 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
1023 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
1024 [CLK_BUS_I2S2] = &bus_i2s2_clk.common.hw,
1025 [CLK_BUS_I2S3] = &bus_i2s3_clk.common.hw,
1026 [CLK_SPDIF] = &spdif_clk.common.hw,
1027 [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw,
1028 [CLK_DMIC] = &dmic_clk.common.hw,
1029 [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw,
1030 [CLK_AUDIO_HUB] = &audio_hub_clk.common.hw,
1031 [CLK_BUS_AUDIO_HUB] = &bus_audio_hub_clk.common.hw,
1032 [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw,
1033 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
1034 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
1035 [CLK_USB_OHCI3] = &usb_ohci3_clk.common.hw,
1036 [CLK_USB_PHY3] = &usb_phy3_clk.common.hw,
1037 [CLK_USB_HSIC_12M] = &usb_hsic_12m_clk.common.hw,
1038 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
1039 [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw,
1040 [CLK_BUS_OHCI3] = &bus_ohci3_clk.common.hw,
1041 [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw,
1042 [CLK_BUS_XHCI] = &bus_xhci_clk.common.hw,
1043 [CLK_BUS_EHCI3] = &bus_ehci3_clk.common.hw,
1044 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
1045 [CLK_PCIE_REF_100M] = &pcie_ref_100m_clk.hw,
1046 [CLK_PCIE_REF] = &pcie_ref_clk.common.hw,
1047 [CLK_PCIE_REF_OUT] = &pcie_ref_out_clk.common.hw,
1048 [CLK_PCIE_MAXI] = &pcie_maxi_clk.common.hw,
1049 [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw,
1050 [CLK_BUS_PCIE] = &bus_pcie_clk.common.hw,
1051 [CLK_HDMI] = &hdmi_clk.common.hw,
1052 [CLK_HDMI_SLOW] = &hdmi_slow_clk.common.hw,
1053 [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw,
1054 [CLK_BUS_HDMI] = &bus_hdmi_clk.common.hw,
1055 [CLK_BUS_TCON_TOP] = &bus_tcon_top_clk.common.hw,
1056 [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw,
1057 [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw,
1058 [CLK_TCON_TV0] = &tcon_tv0_clk.common.hw,
1059 [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw,
1060 [CLK_CSI_CCI] = &csi_cci_clk.common.hw,
1061 [CLK_CSI_TOP] = &csi_top_clk.common.hw,
1062 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
1063 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
1064 [CLK_HDCP] = &hdcp_clk.common.hw,
1065 [CLK_BUS_HDCP] = &bus_hdcp_clk.common.hw,
1066 },
1067 .num = CLK_NUMBER,
1068 };
1069
1070 static struct ccu_reset_map sun50i_h6_ccu_resets[] = {
1071 [RST_MBUS] = { 0x540, BIT(30) },
1072
1073 [RST_BUS_DE] = { 0x60c, BIT(16) },
1074 [RST_BUS_DEINTERLACE] = { 0x62c, BIT(16) },
1075 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1076 [RST_BUS_CE] = { 0x68c, BIT(16) },
1077 [RST_BUS_VE] = { 0x69c, BIT(16) },
1078 [RST_BUS_EMCE] = { 0x6bc, BIT(16) },
1079 [RST_BUS_VP9] = { 0x6cc, BIT(16) },
1080 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1081 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1082 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1083 [RST_BUS_HSTIMER] = { 0x73c, BIT(16) },
1084 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1085 [RST_BUS_PSI] = { 0x79c, BIT(16) },
1086 [RST_BUS_PWM] = { 0x7ac, BIT(16) },
1087 [RST_BUS_IOMMU] = { 0x7bc, BIT(16) },
1088 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1089 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1090 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1091 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1092 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1093 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1094 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1095 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1096 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1097 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1098 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1099 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1100 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1101 [RST_BUS_SCR0] = { 0x93c, BIT(16) },
1102 [RST_BUS_SCR1] = { 0x93c, BIT(17) },
1103 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1104 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1105 [RST_BUS_EMAC] = { 0x97c, BIT(16) },
1106 [RST_BUS_TS] = { 0x9bc, BIT(16) },
1107 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1108 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1109 [RST_BUS_I2S0] = { 0xa1c, BIT(16) },
1110 [RST_BUS_I2S1] = { 0xa1c, BIT(17) },
1111 [RST_BUS_I2S2] = { 0xa1c, BIT(18) },
1112 [RST_BUS_I2S3] = { 0xa1c, BIT(19) },
1113 [RST_BUS_SPDIF] = { 0xa2c, BIT(16) },
1114 [RST_BUS_DMIC] = { 0xa4c, BIT(16) },
1115 [RST_BUS_AUDIO_HUB] = { 0xa6c, BIT(16) },
1116
1117 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1118 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1119 [RST_USB_PHY3] = { 0xa7c, BIT(30) },
1120 [RST_USB_HSIC] = { 0xa7c, BIT(28) },
1121
1122 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1123 [RST_BUS_OHCI3] = { 0xa8c, BIT(19) },
1124 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1125 [RST_BUS_XHCI] = { 0xa8c, BIT(21) },
1126 [RST_BUS_EHCI3] = { 0xa8c, BIT(23) },
1127 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1128 [RST_BUS_PCIE] = { 0xabc, BIT(16) },
1129
1130 [RST_PCIE_POWERUP] = { 0xabc, BIT(17) },
1131
1132 [RST_BUS_HDMI] = { 0xb1c, BIT(16) },
1133 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1134 [RST_BUS_TCON_TOP] = { 0xb5c, BIT(16) },
1135 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1136 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1137 [RST_BUS_CSI] = { 0xc2c, BIT(16) },
1138 [RST_BUS_HDCP] = { 0xc4c, BIT(16) },
1139 };
1140
1141 static const struct sunxi_ccu_desc sun50i_h6_ccu_desc = {
1142 .ccu_clks = sun50i_h6_ccu_clks,
1143 .num_ccu_clks = ARRAY_SIZE(sun50i_h6_ccu_clks),
1144
1145 .hw_clks = &sun50i_h6_hw_clks,
1146
1147 .resets = sun50i_h6_ccu_resets,
1148 .num_resets = ARRAY_SIZE(sun50i_h6_ccu_resets),
1149 };
1150
1151 static const u32 pll_regs[] = {
1152 SUN50I_H6_PLL_CPUX_REG,
1153 SUN50I_H6_PLL_DDR0_REG,
1154 SUN50I_H6_PLL_PERIPH0_REG,
1155 SUN50I_H6_PLL_PERIPH1_REG,
1156 SUN50I_H6_PLL_GPU_REG,
1157 SUN50I_H6_PLL_VIDEO0_REG,
1158 SUN50I_H6_PLL_VIDEO1_REG,
1159 SUN50I_H6_PLL_VE_REG,
1160 SUN50I_H6_PLL_DE_REG,
1161 SUN50I_H6_PLL_HSIC_REG,
1162 SUN50I_H6_PLL_AUDIO_REG,
1163 };
1164
1165 static const u32 pll_video_regs[] = {
1166 SUN50I_H6_PLL_VIDEO0_REG,
1167 SUN50I_H6_PLL_VIDEO1_REG,
1168 };
1169
1170 static const u32 usb2_clk_regs[] = {
1171 SUN50I_H6_USB0_CLK_REG,
1172 SUN50I_H6_USB3_CLK_REG,
1173 };
1174
sun50i_h6_ccu_probe(struct platform_device * pdev)1175 static int sun50i_h6_ccu_probe(struct platform_device *pdev)
1176 {
1177 struct resource *res;
1178 void __iomem *reg;
1179 u32 val;
1180 int i;
1181
1182 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1183 reg = devm_ioremap_resource(&pdev->dev, res);
1184 if (IS_ERR(reg))
1185 return PTR_ERR(reg);
1186
1187 /* Enable the lock bits on all PLLs */
1188 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
1189 val = readl(reg + pll_regs[i]);
1190 val |= BIT(29);
1191 writel(val, reg + pll_regs[i]);
1192 }
1193
1194 /*
1195 * Force the output divider of video PLLs to 0.
1196 *
1197 * See the comment before pll-video0 definition for the reason.
1198 */
1199 for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) {
1200 val = readl(reg + pll_video_regs[i]);
1201 val &= ~BIT(0);
1202 writel(val, reg + pll_video_regs[i]);
1203 }
1204
1205 /*
1206 * Force OHCI 12M clock sources to 00 (12MHz divided from 48MHz)
1207 *
1208 * This clock mux is still mysterious, and the code just enforces
1209 * it to have a valid clock parent.
1210 */
1211 for (i = 0; i < ARRAY_SIZE(usb2_clk_regs); i++) {
1212 val = readl(reg + usb2_clk_regs[i]);
1213 val &= ~GENMASK(25, 24);
1214 writel (val, reg + usb2_clk_regs[i]);
1215 }
1216
1217 /*
1218 * Force the post-divider of pll-audio to 8 and the output divider
1219 * of it to 1, to make the clock name represents the real frequency.
1220 */
1221 val = readl(reg + SUN50I_H6_PLL_AUDIO_REG);
1222 val &= ~(GENMASK(21, 16) | BIT(0));
1223 writel(val | (7 << 16), reg + SUN50I_H6_PLL_AUDIO_REG);
1224
1225 /*
1226 * First clock parent (osc32K) is unusable for CEC. But since there
1227 * is no good way to force parent switch (both run with same frequency),
1228 * just set second clock parent here.
1229 */
1230 val = readl(reg + SUN50I_H6_HDMI_CEC_CLK_REG);
1231 val |= BIT(24);
1232 writel(val, reg + SUN50I_H6_HDMI_CEC_CLK_REG);
1233
1234 return sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_h6_ccu_desc);
1235 }
1236
1237 static const struct of_device_id sun50i_h6_ccu_ids[] = {
1238 { .compatible = "allwinner,sun50i-h6-ccu" },
1239 { }
1240 };
1241
1242 static struct platform_driver sun50i_h6_ccu_driver = {
1243 .probe = sun50i_h6_ccu_probe,
1244 .driver = {
1245 .name = "sun50i-h6-ccu",
1246 .of_match_table = sun50i_h6_ccu_ids,
1247 },
1248 };
1249 builtin_platform_driver(sun50i_h6_ccu_driver);
1250
