1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * QLogic qlcnic NIC Driver
4 * Copyright (c) 2009-2013 QLogic Corporation
5 */
6
7 #ifndef _QLCNIC_H_
8 #define _QLCNIC_H_
9
10 #include <linux/module.h>
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/ioport.h>
14 #include <linux/pci.h>
15 #include <linux/netdevice.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ip.h>
18 #include <linux/in.h>
19 #include <linux/tcp.h>
20 #include <linux/skbuff.h>
21 #include <linux/firmware.h>
22 #include <linux/ethtool.h>
23 #include <linux/mii.h>
24 #include <linux/timer.h>
25 #include <linux/irq.h>
26 #include <linux/vmalloc.h>
27 #include <linux/io.h>
28 #include <asm/byteorder.h>
29 #include <linux/bitops.h>
30 #include <linux/if_vlan.h>
31
32 #include "qlcnic_hdr.h"
33 #include "qlcnic_hw.h"
34 #include "qlcnic_83xx_hw.h"
35 #include "qlcnic_dcb.h"
36
37 #define _QLCNIC_LINUX_MAJOR 5
38 #define _QLCNIC_LINUX_MINOR 3
39 #define _QLCNIC_LINUX_SUBVERSION 66
40 #define QLCNIC_LINUX_VERSIONID "5.3.66"
41 #define QLCNIC_DRV_IDC_VER 0x01
42 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
44
45 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
46 #define _major(v) (((v) >> 24) & 0xff)
47 #define _minor(v) (((v) >> 16) & 0xff)
48 #define _build(v) ((v) & 0xffff)
49
50 /* version in image has weird encoding:
51 * 7:0 - major
52 * 15:8 - minor
53 * 31:16 - build (little endian)
54 */
55 #define QLCNIC_DECODE_VERSION(v) \
56 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
57
58 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
59 #define QLCNIC_NUM_FLASH_SECTORS (64)
60 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
61 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
62 * QLCNIC_FLASH_SECTOR_SIZE)
63
64 #define RCV_DESC_RINGSIZE(rds_ring) \
65 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
66 #define RCV_BUFF_RINGSIZE(rds_ring) \
67 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
68 #define STATUS_DESC_RINGSIZE(sds_ring) \
69 (sizeof(struct status_desc) * (sds_ring)->num_desc)
70 #define TX_BUFF_RINGSIZE(tx_ring) \
71 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
72 #define TX_DESC_RINGSIZE(tx_ring) \
73 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
74
75 #define QLCNIC_P3P_A0 0x50
76 #define QLCNIC_P3P_C0 0x58
77
78 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
79
80 #define FIRST_PAGE_GROUP_START 0
81 #define FIRST_PAGE_GROUP_END 0x100000
82
83 #define P3P_MAX_MTU (9600)
84 #define P3P_MIN_MTU (68)
85 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
86
87 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
88 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
89 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
90 #define QLCNIC_LRO_BUFFER_EXTRA 2048
91
92 /* Tx defines */
93 #define QLCNIC_MAX_FRAGS_PER_TX 14
94 #define MAX_TSO_HEADER_DESC 2
95 #define MGMT_CMD_DESC_RESV 4
96 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
97 + MGMT_CMD_DESC_RESV)
98 #define QLCNIC_MAX_TX_TIMEOUTS 2
99
100 /* Driver will use 1 Tx ring in INT-x/MSI/SRIOV mode. */
101 #define QLCNIC_SINGLE_RING 1
102 #define QLCNIC_DEF_SDS_RINGS 4
103 #define QLCNIC_DEF_TX_RINGS 4
104 #define QLCNIC_MAX_VNIC_TX_RINGS 4
105 #define QLCNIC_MAX_VNIC_SDS_RINGS 4
106 #define QLCNIC_83XX_MINIMUM_VECTOR 3
107 #define QLCNIC_82XX_MINIMUM_VECTOR 2
108
109 enum qlcnic_queue_type {
110 QLCNIC_TX_QUEUE = 1,
111 QLCNIC_RX_QUEUE,
112 };
113
114 /* Operational mode for driver */
115 #define QLCNIC_VNIC_MODE 0xFF
116 #define QLCNIC_DEFAULT_MODE 0x0
117
118 /* Virtual NIC function count */
119 #define QLC_DEFAULT_VNIC_COUNT 8
120 #define QLC_84XX_VNIC_COUNT 16
121
122 /*
123 * Following are the states of the Phantom. Phantom will set them and
124 * Host will read to check if the fields are correct.
125 */
126 #define PHAN_INITIALIZE_FAILED 0xffff
127 #define PHAN_INITIALIZE_COMPLETE 0xff01
128
129 /* Host writes the following to notify that it has done the init-handshake */
130 #define PHAN_INITIALIZE_ACK 0xf00f
131 #define PHAN_PEG_RCV_INITIALIZED 0xff01
132
133 #define NUM_RCV_DESC_RINGS 3
134
135 #define RCV_RING_NORMAL 0
136 #define RCV_RING_JUMBO 1
137
138 #define MIN_CMD_DESCRIPTORS 64
139 #define MIN_RCV_DESCRIPTORS 64
140 #define MIN_JUMBO_DESCRIPTORS 32
141
142 #define MAX_CMD_DESCRIPTORS 1024
143 #define MAX_RCV_DESCRIPTORS_1G 4096
144 #define MAX_RCV_DESCRIPTORS_10G 8192
145 #define MAX_RCV_DESCRIPTORS_VF 2048
146 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
147 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
148
149 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
150 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
151 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
152 #define MAX_RDS_RINGS 2
153
154 #define get_next_index(index, length) \
155 (((index) + 1) & ((length) - 1))
156
157 /*
158 * Following data structures describe the descriptors that will be used.
159 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
160 * we are doing LSO (above the 1500 size packet) only.
161 */
162 struct cmd_desc_type0 {
163 u8 tcp_hdr_offset; /* For LSO only */
164 u8 ip_hdr_offset; /* For LSO only */
165 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
166 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
167
168 __le64 addr_buffer2;
169
170 __le16 encap_descr; /* 15:10 offset of outer L3 header,
171 * 9:6 number of 32bit words in outer L3 header,
172 * 5 offload outer L4 checksum,
173 * 4 offload outer L3 checksum,
174 * 3 Inner L4 type, TCP=0, UDP=1,
175 * 2 Inner L3 type, IPv4=0, IPv6=1,
176 * 1 Outer L3 type,IPv4=0, IPv6=1,
177 * 0 type of encapsulation, GRE=0, VXLAN=1
178 */
179 __le16 mss;
180 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
181 u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
182 u8 outer_hdr_length; /* Encapsulation only */
183 u8 rsvd1;
184
185 __le64 addr_buffer3;
186 __le64 addr_buffer1;
187
188 __le16 buffer_length[4];
189
190 __le64 addr_buffer4;
191
192 u8 eth_addr[ETH_ALEN];
193 __le16 vlan_TCI; /* In case of encapsulation,
194 * this is for outer VLAN
195 */
196
197 } __attribute__ ((aligned(64)));
198
199 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
200 struct rcv_desc {
201 __le16 reference_handle;
202 __le16 reserved;
203 __le32 buffer_length; /* allocated buffer length (usually 2K) */
204 __le64 addr_buffer;
205 } __packed;
206
207 struct status_desc {
208 __le64 status_desc_data[2];
209 } __attribute__ ((aligned(16)));
210
211 /* UNIFIED ROMIMAGE */
212 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
213 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
214 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
215 #define QLCNIC_UNI_DIR_SECT_FW 0x7
216
217 /*Offsets */
218 #define QLCNIC_UNI_CHIP_REV_OFF 10
219 #define QLCNIC_UNI_FLAGS_OFF 11
220 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
221 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
222 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
223
224 struct uni_table_desc{
225 __le32 findex;
226 __le32 num_entries;
227 __le32 entry_size;
228 __le32 reserved[5];
229 };
230
231 struct uni_data_desc{
232 __le32 findex;
233 __le32 size;
234 __le32 reserved[5];
235 };
236
237 /* Flash Defines and Structures */
238 #define QLCNIC_FLT_LOCATION 0x3F1000
239 #define QLCNIC_FDT_LOCATION 0x3F0000
240 #define QLCNIC_B0_FW_IMAGE_REGION 0x74
241 #define QLCNIC_C0_FW_IMAGE_REGION 0x97
242 #define QLCNIC_BOOTLD_REGION 0X72
243 struct qlcnic_flt_header {
244 u16 version;
245 u16 len;
246 u16 checksum;
247 u16 reserved;
248 };
249
250 struct qlcnic_flt_entry {
251 u8 region;
252 u8 reserved0;
253 u8 attrib;
254 u8 reserved1;
255 u32 size;
256 u32 start_addr;
257 u32 end_addr;
258 };
259
260 /* Flash Descriptor Table */
261 struct qlcnic_fdt {
262 u32 valid;
263 u16 ver;
264 u16 len;
265 u16 cksum;
266 u16 unused;
267 u8 model[16];
268 u8 mfg_id;
269 u16 id;
270 u8 flag;
271 u8 erase_cmd;
272 u8 alt_erase_cmd;
273 u8 write_enable_cmd;
274 u8 write_enable_bits;
275 u8 write_statusreg_cmd;
276 u8 unprotected_sec_cmd;
277 u8 read_manuf_cmd;
278 u32 block_size;
279 u32 alt_block_size;
280 u32 flash_size;
281 u32 write_enable_data;
282 u8 readid_addr_len;
283 u8 write_disable_bits;
284 u8 read_dev_id_len;
285 u8 chip_erase_cmd;
286 u16 read_timeo;
287 u8 protected_sec_cmd;
288 u8 resvd[65];
289 };
290 /* Magic number to let user know flash is programmed */
291 #define QLCNIC_BDINFO_MAGIC 0x12345678
292
293 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
294 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
295 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
296 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
297 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
298 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
299 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
300 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
301 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
302 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
303 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
304 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
305 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
306 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
307
308 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
309
310 /* Flash memory map */
311 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
312 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
313 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
314 #define QLCNIC_USER_START 0x3E8000 /* Firmware info */
315
316 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
317 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
318 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
319 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
320
321 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
322 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
323
324 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
325 #define QLCNIC_UNIFIED_ROMIMAGE 0
326 #define QLCNIC_FLASH_ROMIMAGE 1
327 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
328
329 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
330 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
331
332 extern char qlcnic_driver_name[];
333
334 extern int qlcnic_use_msi;
335 extern int qlcnic_use_msi_x;
336 extern int qlcnic_auto_fw_reset;
337 extern int qlcnic_load_fw_file;
338
339 /* Number of status descriptors to handle per interrupt */
340 #define MAX_STATUS_HANDLE (64)
341
342 /*
343 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
344 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
345 */
346 struct qlcnic_skb_frag {
347 u64 dma;
348 u64 length;
349 };
350
351 /* Following defines are for the state of the buffers */
352 #define QLCNIC_BUFFER_FREE 0
353 #define QLCNIC_BUFFER_BUSY 1
354
355 /*
356 * There will be one qlcnic_buffer per skb packet. These will be
357 * used to save the dma info for pci_unmap_page()
358 */
359 struct qlcnic_cmd_buffer {
360 struct sk_buff *skb;
361 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
362 u32 frag_count;
363 };
364
365 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
366 struct qlcnic_rx_buffer {
367 u16 ref_handle;
368 struct sk_buff *skb;
369 struct list_head list;
370 u64 dma;
371 };
372
373 /* Board types */
374 #define QLCNIC_GBE 0x01
375 #define QLCNIC_XGBE 0x02
376
377 /*
378 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
379 * adjusted based on configured MTU.
380 */
381 #define QLCNIC_INTR_COAL_TYPE_RX 1
382 #define QLCNIC_INTR_COAL_TYPE_TX 2
383 #define QLCNIC_INTR_COAL_TYPE_RX_TX 3
384
385 #define QLCNIC_DEF_INTR_COALESCE_RX_TIME_US 3
386 #define QLCNIC_DEF_INTR_COALESCE_RX_PACKETS 256
387
388 #define QLCNIC_DEF_INTR_COALESCE_TX_TIME_US 64
389 #define QLCNIC_DEF_INTR_COALESCE_TX_PACKETS 64
390
391 #define QLCNIC_INTR_DEFAULT 0x04
392 #define QLCNIC_CONFIG_INTR_COALESCE 3
393 #define QLCNIC_DEV_INFO_SIZE 2
394
395 struct qlcnic_nic_intr_coalesce {
396 u8 type;
397 u8 sts_ring_mask;
398 u16 rx_packets;
399 u16 rx_time_us;
400 u16 tx_packets;
401 u16 tx_time_us;
402 u16 flag;
403 u32 timer_out;
404 };
405
406 struct qlcnic_83xx_dump_template_hdr {
407 u32 type;
408 u32 offset;
409 u32 size;
410 u32 cap_mask;
411 u32 num_entries;
412 u32 version;
413 u32 timestamp;
414 u32 checksum;
415 u32 drv_cap_mask;
416 u32 sys_info[3];
417 u32 saved_state[16];
418 u32 cap_sizes[8];
419 u32 ocm_wnd_reg[16];
420 u32 rsvd[];
421 };
422
423 struct qlcnic_82xx_dump_template_hdr {
424 u32 type;
425 u32 offset;
426 u32 size;
427 u32 cap_mask;
428 u32 num_entries;
429 u32 version;
430 u32 timestamp;
431 u32 checksum;
432 u32 drv_cap_mask;
433 u32 sys_info[3];
434 u32 saved_state[16];
435 u32 cap_sizes[8];
436 u32 rsvd[7];
437 u32 capabilities;
438 u32 rsvd1[];
439 };
440
441 #define QLC_PEX_DMA_READ_SIZE (PAGE_SIZE * 16)
442
443 struct qlcnic_fw_dump {
444 u8 clr; /* flag to indicate if dump is cleared */
445 bool enable; /* enable/disable dump */
446 u32 size; /* total size of the dump */
447 u32 cap_mask; /* Current capture mask */
448 void *data; /* dump data area */
449 void *tmpl_hdr;
450 dma_addr_t phys_addr;
451 void *dma_buffer;
452 bool use_pex_dma;
453 /* Read only elements which are common between 82xx and 83xx
454 * template header. Update these values immediately after we read
455 * template header from Firmware
456 */
457 u32 tmpl_hdr_size;
458 u32 version;
459 u32 num_entries;
460 u32 offset;
461 };
462
463 /*
464 * One hardware_context{} per adapter
465 * contains interrupt info as well shared hardware info.
466 */
467 struct qlcnic_hardware_context {
468 void __iomem *pci_base0;
469 void __iomem *ocm_win_crb;
470
471 unsigned long pci_len0;
472
473 rwlock_t crb_lock;
474 struct mutex mem_lock;
475
476 u8 revision_id;
477 u8 pci_func;
478 u8 linkup;
479 u8 loopback_state;
480 u8 beacon_state;
481 u8 has_link_events;
482 u8 fw_type;
483 u8 physical_port;
484 u8 reset_context;
485 u8 msix_supported;
486 u8 max_mac_filters;
487 u8 mc_enabled;
488 u8 max_mc_count;
489 u8 diag_test;
490 u8 num_msix;
491 u8 nic_mode;
492 int diag_cnt;
493
494 u16 max_uc_count;
495 u16 port_type;
496 u16 board_type;
497 u16 supported_type;
498
499 u32 link_speed;
500 u16 link_duplex;
501 u16 link_autoneg;
502 u16 module_type;
503
504 u16 op_mode;
505 u16 switch_mode;
506 u16 max_tx_ques;
507 u16 max_rx_ques;
508 u16 max_mtu;
509 u32 msg_enable;
510 u16 total_nic_func;
511 u16 max_pci_func;
512 u32 max_vnic_func;
513 u32 total_pci_func;
514
515 u32 capabilities;
516 u32 extra_capability[3];
517 u32 temp;
518 u32 int_vec_bit;
519 u32 fw_hal_version;
520 u32 port_config;
521 struct qlcnic_hardware_ops *hw_ops;
522 struct qlcnic_nic_intr_coalesce coal;
523 struct qlcnic_fw_dump fw_dump;
524 struct qlcnic_fdt fdt;
525 struct qlc_83xx_reset reset;
526 struct qlc_83xx_idc idc;
527 struct qlc_83xx_fw_info *fw_info;
528 struct qlcnic_intrpt_config *intr_tbl;
529 struct qlcnic_sriov *sriov;
530 u32 *reg_tbl;
531 u32 *ext_reg_tbl;
532 u32 mbox_aen[QLC_83XX_MBX_AEN_CNT];
533 u32 mbox_reg[4];
534 struct qlcnic_mailbox *mailbox;
535 u8 extend_lb_time;
536 u8 phys_port_id[ETH_ALEN];
537 u8 lb_mode;
538 struct device *hwmon_dev;
539 u32 post_mode;
540 bool run_post;
541 };
542
543 struct qlcnic_adapter_stats {
544 u64 xmitcalled;
545 u64 xmitfinished;
546 u64 rxdropped;
547 u64 txdropped;
548 u64 csummed;
549 u64 rx_pkts;
550 u64 lro_pkts;
551 u64 rxbytes;
552 u64 txbytes;
553 u64 lrobytes;
554 u64 lso_frames;
555 u64 encap_lso_frames;
556 u64 encap_tx_csummed;
557 u64 encap_rx_csummed;
558 u64 xmit_on;
559 u64 xmit_off;
560 u64 skb_alloc_failure;
561 u64 null_rxbuf;
562 u64 rx_dma_map_error;
563 u64 tx_dma_map_error;
564 u64 spurious_intr;
565 u64 mac_filter_limit_overrun;
566 u64 mbx_spurious_intr;
567 };
568
569 /*
570 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
571 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
572 */
573 struct qlcnic_host_rds_ring {
574 void __iomem *crb_rcv_producer;
575 struct rcv_desc *desc_head;
576 struct qlcnic_rx_buffer *rx_buf_arr;
577 u32 num_desc;
578 u32 producer;
579 u32 dma_size;
580 u32 skb_size;
581 u32 flags;
582 struct list_head free_list;
583 spinlock_t lock;
584 dma_addr_t phys_addr;
585 } ____cacheline_internodealigned_in_smp;
586
587 struct qlcnic_host_sds_ring {
588 u32 consumer;
589 u32 num_desc;
590 void __iomem *crb_sts_consumer;
591
592 struct qlcnic_host_tx_ring *tx_ring;
593 struct status_desc *desc_head;
594 struct qlcnic_adapter *adapter;
595 struct napi_struct napi;
596 struct list_head free_list[NUM_RCV_DESC_RINGS];
597
598 void __iomem *crb_intr_mask;
599 int irq;
600
601 dma_addr_t phys_addr;
602 char name[IFNAMSIZ + 12];
603 } ____cacheline_internodealigned_in_smp;
604
605 struct qlcnic_tx_queue_stats {
606 u64 xmit_on;
607 u64 xmit_off;
608 u64 xmit_called;
609 u64 xmit_finished;
610 u64 tx_bytes;
611 };
612
613 struct qlcnic_host_tx_ring {
614 int irq;
615 void __iomem *crb_intr_mask;
616 char name[IFNAMSIZ + 12];
617 u16 ctx_id;
618
619 u32 state;
620 u32 producer;
621 u32 sw_consumer;
622 u32 num_desc;
623
624 struct qlcnic_tx_queue_stats tx_stats;
625
626 void __iomem *crb_cmd_producer;
627 struct cmd_desc_type0 *desc_head;
628 struct qlcnic_adapter *adapter;
629 struct napi_struct napi;
630 struct qlcnic_cmd_buffer *cmd_buf_arr;
631 __le32 *hw_consumer;
632
633 dma_addr_t phys_addr;
634 dma_addr_t hw_cons_phys_addr;
635 struct netdev_queue *txq;
636 /* Lock to protect Tx descriptors cleanup */
637 spinlock_t tx_clean_lock;
638 } ____cacheline_internodealigned_in_smp;
639
640 /*
641 * Receive context. There is one such structure per instance of the
642 * receive processing. Any state information that is relevant to
643 * the receive, and is must be in this structure. The global data may be
644 * present elsewhere.
645 */
646 struct qlcnic_recv_context {
647 struct qlcnic_host_rds_ring *rds_rings;
648 struct qlcnic_host_sds_ring *sds_rings;
649 u32 state;
650 u16 context_id;
651 u16 virt_port;
652 };
653
654 /* HW context creation */
655
656 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
657
658 #define QLCNIC_CDRP_CMD_BIT 0x80000000
659
660 /*
661 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
662 * in the crb QLCNIC_CDRP_CRB_OFFSET.
663 */
664 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
665 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
666
667 #define QLCNIC_CDRP_RSP_OK 0x00000001
668 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
669 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
670
671 /*
672 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
673 * the crb QLCNIC_CDRP_CRB_OFFSET.
674 */
675 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
676
677 #define QLCNIC_RCODE_SUCCESS 0
678 #define QLCNIC_RCODE_INVALID_ARGS 6
679 #define QLCNIC_RCODE_NOT_SUPPORTED 9
680 #define QLCNIC_RCODE_NOT_PERMITTED 10
681 #define QLCNIC_RCODE_NOT_IMPL 15
682 #define QLCNIC_RCODE_INVALID 16
683 #define QLCNIC_RCODE_TIMEOUT 17
684 #define QLCNIC_DESTROY_CTX_RESET 0
685
686 /*
687 * Capabilities Announced
688 */
689 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
690 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
691 #define QLCNIC_CAP0_LSO (1 << 6)
692 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
693 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
694 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
695 #define QLCNIC_CAP0_LRO_MSS (1 << 21)
696 #define QLCNIC_CAP0_TX_MULTI (1 << 22)
697
698 /*
699 * Context state
700 */
701 #define QLCNIC_HOST_CTX_STATE_FREED 0
702 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
703
704 /*
705 * Rx context
706 */
707
708 struct qlcnic_hostrq_sds_ring {
709 __le64 host_phys_addr; /* Ring base addr */
710 __le32 ring_size; /* Ring entries */
711 __le16 msi_index;
712 __le16 rsvd; /* Padding */
713 } __packed;
714
715 struct qlcnic_hostrq_rds_ring {
716 __le64 host_phys_addr; /* Ring base addr */
717 __le64 buff_size; /* Packet buffer size */
718 __le32 ring_size; /* Ring entries */
719 __le32 ring_kind; /* Class of ring */
720 } __packed;
721
722 struct qlcnic_hostrq_rx_ctx {
723 __le64 host_rsp_dma_addr; /* Response dma'd here */
724 __le32 capabilities[4]; /* Flag bit vector */
725 __le32 host_int_crb_mode; /* Interrupt crb usage */
726 __le32 host_rds_crb_mode; /* RDS crb usage */
727 /* These ring offsets are relative to data[0] below */
728 __le32 rds_ring_offset; /* Offset to RDS config */
729 __le32 sds_ring_offset; /* Offset to SDS config */
730 __le16 num_rds_rings; /* Count of RDS rings */
731 __le16 num_sds_rings; /* Count of SDS rings */
732 __le16 valid_field_offset;
733 u8 txrx_sds_binding;
734 u8 msix_handler;
735 u8 reserved[128]; /* reserve space for future expansion*/
736 /* MUST BE 64-bit aligned.
737 The following is packed:
738 - N hostrq_rds_rings
739 - N hostrq_sds_rings */
740 char data[];
741 } __packed;
742
743 struct qlcnic_cardrsp_rds_ring{
744 __le32 host_producer_crb; /* Crb to use */
745 __le32 rsvd1; /* Padding */
746 } __packed;
747
748 struct qlcnic_cardrsp_sds_ring {
749 __le32 host_consumer_crb; /* Crb to use */
750 __le32 interrupt_crb; /* Crb to use */
751 } __packed;
752
753 struct qlcnic_cardrsp_rx_ctx {
754 /* These ring offsets are relative to data[0] below */
755 __le32 rds_ring_offset; /* Offset to RDS config */
756 __le32 sds_ring_offset; /* Offset to SDS config */
757 __le32 host_ctx_state; /* Starting State */
758 __le32 num_fn_per_port; /* How many PCI fn share the port */
759 __le16 num_rds_rings; /* Count of RDS rings */
760 __le16 num_sds_rings; /* Count of SDS rings */
761 __le16 context_id; /* Handle for context */
762 u8 phys_port; /* Physical id of port */
763 u8 virt_port; /* Virtual/Logical id of port */
764 u8 reserved[128]; /* save space for future expansion */
765 /* MUST BE 64-bit aligned.
766 The following is packed:
767 - N cardrsp_rds_rings
768 - N cardrs_sds_rings */
769 char data[];
770 } __packed;
771
772 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
773 (sizeof(HOSTRQ_RX) + \
774 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
775 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
776
777 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
778 (sizeof(CARDRSP_RX) + \
779 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
780 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
781
782 /*
783 * Tx context
784 */
785
786 struct qlcnic_hostrq_cds_ring {
787 __le64 host_phys_addr; /* Ring base addr */
788 __le32 ring_size; /* Ring entries */
789 __le32 rsvd; /* Padding */
790 } __packed;
791
792 struct qlcnic_hostrq_tx_ctx {
793 __le64 host_rsp_dma_addr; /* Response dma'd here */
794 __le64 cmd_cons_dma_addr; /* */
795 __le64 dummy_dma_addr; /* */
796 __le32 capabilities[4]; /* Flag bit vector */
797 __le32 host_int_crb_mode; /* Interrupt crb usage */
798 __le32 rsvd1; /* Padding */
799 __le16 rsvd2; /* Padding */
800 __le16 interrupt_ctl;
801 __le16 msi_index;
802 __le16 rsvd3; /* Padding */
803 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
804 u8 reserved[128]; /* future expansion */
805 } __packed;
806
807 struct qlcnic_cardrsp_cds_ring {
808 __le32 host_producer_crb; /* Crb to use */
809 __le32 interrupt_crb; /* Crb to use */
810 } __packed;
811
812 struct qlcnic_cardrsp_tx_ctx {
813 __le32 host_ctx_state; /* Starting state */
814 __le16 context_id; /* Handle for context */
815 u8 phys_port; /* Physical id of port */
816 u8 virt_port; /* Virtual/Logical id of port */
817 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
818 u8 reserved[128]; /* future expansion */
819 } __packed;
820
821 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
822 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
823
824 /* CRB */
825
826 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
827 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
828 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
829 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
830
831 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
832 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
833 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
834 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
835 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
836
837
838 /* MAC */
839
840 #define MC_COUNT_P3P 38
841
842 #define QLCNIC_MAC_NOOP 0
843 #define QLCNIC_MAC_ADD 1
844 #define QLCNIC_MAC_DEL 2
845 #define QLCNIC_MAC_VLAN_ADD 3
846 #define QLCNIC_MAC_VLAN_DEL 4
847
848 enum qlcnic_mac_type {
849 QLCNIC_UNICAST_MAC,
850 QLCNIC_MULTICAST_MAC,
851 QLCNIC_BROADCAST_MAC,
852 };
853
854 struct qlcnic_mac_vlan_list {
855 struct list_head list;
856 uint8_t mac_addr[ETH_ALEN+2];
857 u16 vlan_id;
858 enum qlcnic_mac_type mac_type;
859 };
860
861 /* MAC Learn */
862 #define NO_MAC_LEARN 0
863 #define DRV_MAC_LEARN 1
864 #define FDB_MAC_LEARN 2
865
866 #define QLCNIC_HOST_REQUEST 0x13
867 #define QLCNIC_REQUEST 0x14
868
869 #define QLCNIC_MAC_EVENT 0x1
870
871 #define QLCNIC_IP_UP 2
872 #define QLCNIC_IP_DOWN 3
873
874 #define QLCNIC_ILB_MODE 0x1
875 #define QLCNIC_ELB_MODE 0x2
876 #define QLCNIC_LB_MODE_MASK 0x3
877
878 #define QLCNIC_LINKEVENT 0x1
879 #define QLCNIC_LB_RESPONSE 0x2
880 #define QLCNIC_IS_LB_CONFIGURED(VAL) \
881 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
882
883 /*
884 * Driver --> Firmware
885 */
886 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
887 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
888 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
889 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
890 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
891 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
892
893 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
894 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
895 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
896 #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 0x13
897
898 /*
899 * Firmware --> Driver
900 */
901
902 #define QLCNIC_C2H_OPCODE_CONFIG_LOOPBACK 0x8f
903 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 0x8D
904 #define QLCNIC_C2H_OPCODE_GET_DCB_AEN 0x90
905
906 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
907 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
908 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
909
910 #define QLCNIC_LRO_REQUEST_CLEANUP 4
911
912 /* Capabilites received */
913 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
914 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
915 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
916 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
917 #define QLCNIC_FW_CAPABILITY_2_MULTI_TX BIT_4
918 #define QLCNIC_FW_CAPABILITY_MULTI_LOOPBACK BIT_27
919 #define QLCNIC_FW_CAPABILITY_MORE_CAPS BIT_31
920
921 #define QLCNIC_FW_CAPABILITY_2_LRO_MAX_TCP_SEG BIT_2
922 #define QLCNIC_FW_CAP2_HW_LRO_IPV6 BIT_3
923 #define QLCNIC_FW_CAPABILITY_SET_DRV_VER BIT_5
924 #define QLCNIC_FW_CAPABILITY_2_BEACON BIT_7
925 #define QLCNIC_FW_CAPABILITY_2_PER_PORT_ESWITCH_CFG BIT_9
926 #define QLCNIC_FW_CAPABILITY_2_EXT_ISCSI_DUMP BIT_13
927
928 #define QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD BIT_0
929 #define QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD BIT_1
930 #define QLCNIC_83XX_FW_CAPAB_ENCAP_CKO_OFFLOAD BIT_4
931
932 /* module types */
933 #define LINKEVENT_MODULE_NOT_PRESENT 1
934 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
935 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
936 #define LINKEVENT_MODULE_OPTICAL_LRM 4
937 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
938 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
939 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
940 #define LINKEVENT_MODULE_TWINAX 8
941
942 #define LINKSPEED_10GBPS 10000
943 #define LINKSPEED_1GBPS 1000
944 #define LINKSPEED_100MBPS 100
945 #define LINKSPEED_10MBPS 10
946
947 #define LINKSPEED_ENCODED_10MBPS 0
948 #define LINKSPEED_ENCODED_100MBPS 1
949 #define LINKSPEED_ENCODED_1GBPS 2
950
951 #define LINKEVENT_AUTONEG_DISABLED 0
952 #define LINKEVENT_AUTONEG_ENABLED 1
953
954 #define LINKEVENT_HALF_DUPLEX 0
955 #define LINKEVENT_FULL_DUPLEX 1
956
957 #define LINKEVENT_LINKSPEED_MBPS 0
958 #define LINKEVENT_LINKSPEED_ENCODED 1
959
960 /* firmware response header:
961 * 63:58 - message type
962 * 57:56 - owner
963 * 55:53 - desc count
964 * 52:48 - reserved
965 * 47:40 - completion id
966 * 39:32 - opcode
967 * 31:16 - error code
968 * 15:00 - reserved
969 */
970 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
971 ((msg_hdr >> 32) & 0xFF)
972
973 struct qlcnic_fw_msg {
974 union {
975 struct {
976 u64 hdr;
977 u64 body[7];
978 };
979 u64 words[8];
980 };
981 };
982
983 struct qlcnic_nic_req {
984 __le64 qhdr;
985 __le64 req_hdr;
986 __le64 words[6];
987 } __packed;
988
989 struct qlcnic_mac_req {
990 u8 op;
991 u8 tag;
992 u8 mac_addr[6];
993 };
994
995 struct qlcnic_vlan_req {
996 __le16 vlan_id;
997 __le16 rsvd[3];
998 } __packed;
999
1000 struct qlcnic_ipaddr {
1001 __be32 ipv4;
1002 __be32 ipv6[4];
1003 };
1004
1005 #define QLCNIC_MSI_ENABLED 0x02
1006 #define QLCNIC_MSIX_ENABLED 0x04
1007 #define QLCNIC_LRO_ENABLED 0x01
1008 #define QLCNIC_LRO_DISABLED 0x00
1009 #define QLCNIC_BRIDGE_ENABLED 0X10
1010 #define QLCNIC_DIAG_ENABLED 0x20
1011 #define QLCNIC_ESWITCH_ENABLED 0x40
1012 #define QLCNIC_ADAPTER_INITIALIZED 0x80
1013 #define QLCNIC_TAGGING_ENABLED 0x100
1014 #define QLCNIC_MACSPOOF 0x200
1015 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
1016 #define QLCNIC_PROMISC_DISABLED 0x800
1017 #define QLCNIC_NEED_FLR 0x1000
1018 #define QLCNIC_FW_RESET_OWNER 0x2000
1019 #define QLCNIC_FW_HANG 0x4000
1020 #define QLCNIC_FW_LRO_MSS_CAP 0x8000
1021 #define QLCNIC_TX_INTR_SHARED 0x10000
1022 #define QLCNIC_APP_CHANGED_FLAGS 0x20000
1023 #define QLCNIC_HAS_PHYS_PORT_ID 0x40000
1024 #define QLCNIC_TSS_RSS 0x80000
1025
1026 #define QLCNIC_VLAN_FILTERING 0x800000
1027
1028 #define QLCNIC_IS_MSI_FAMILY(adapter) \
1029 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
1030 #define QLCNIC_IS_TSO_CAPABLE(adapter) \
1031 ((adapter)->ahw->capabilities & QLCNIC_FW_CAPABILITY_TSO)
1032
1033 #define QLCNIC_BEACON_EANBLE 0xC
1034 #define QLCNIC_BEACON_DISABLE 0xD
1035
1036 #define QLCNIC_BEACON_ON 2
1037 #define QLCNIC_BEACON_OFF 0
1038
1039 #define QLCNIC_MSIX_TBL_SPACE 8192
1040 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
1041 #define QLCNIC_MSIX_TBL_PGSIZE 4096
1042
1043 #define QLCNIC_ADAPTER_UP_MAGIC 777
1044
1045 #define __QLCNIC_FW_ATTACHED 0
1046 #define __QLCNIC_DEV_UP 1
1047 #define __QLCNIC_RESETTING 2
1048 #define __QLCNIC_START_FW 4
1049 #define __QLCNIC_AER 5
1050 #define __QLCNIC_DIAG_RES_ALLOC 6
1051 #define __QLCNIC_LED_ENABLE 7
1052 #define __QLCNIC_ELB_INPROGRESS 8
1053 #define __QLCNIC_MULTI_TX_UNIQUE 9
1054 #define __QLCNIC_SRIOV_ENABLE 10
1055 #define __QLCNIC_SRIOV_CAPABLE 11
1056 #define __QLCNIC_MBX_POLL_ENABLE 12
1057 #define __QLCNIC_DIAG_MODE 13
1058 #define __QLCNIC_MAINTENANCE_MODE 16
1059
1060 #define QLCNIC_INTERRUPT_TEST 1
1061 #define QLCNIC_LOOPBACK_TEST 2
1062 #define QLCNIC_LED_TEST 3
1063
1064 #define QLCNIC_FILTER_AGE 80
1065 #define QLCNIC_READD_AGE 20
1066 #define QLCNIC_LB_MAX_FILTERS 64
1067 #define QLCNIC_LB_BUCKET_SIZE 32
1068 #define QLCNIC_ILB_MAX_RCV_LOOP 10
1069
1070 struct qlcnic_filter {
1071 struct hlist_node fnode;
1072 u8 faddr[ETH_ALEN];
1073 u16 vlan_id;
1074 unsigned long ftime;
1075 };
1076
1077 struct qlcnic_filter_hash {
1078 struct hlist_head *fhead;
1079 u8 fnum;
1080 u16 fmax;
1081 u16 fbucket_size;
1082 };
1083
1084 /* Mailbox specific data structures */
1085 struct qlcnic_mailbox {
1086 struct workqueue_struct *work_q;
1087 struct qlcnic_adapter *adapter;
1088 const struct qlcnic_mbx_ops *ops;
1089 struct work_struct work;
1090 struct completion completion;
1091 struct list_head cmd_q;
1092 unsigned long status;
1093 spinlock_t queue_lock; /* Mailbox queue lock */
1094 spinlock_t aen_lock; /* Mailbox response/AEN lock */
1095 u32 rsp_status;
1096 u32 num_cmds;
1097 };
1098
1099 struct qlcnic_adapter {
1100 struct qlcnic_hardware_context *ahw;
1101 struct qlcnic_recv_context *recv_ctx;
1102 struct qlcnic_host_tx_ring *tx_ring;
1103 struct net_device *netdev;
1104 struct pci_dev *pdev;
1105
1106 unsigned long state;
1107 u32 flags;
1108
1109 u16 num_txd;
1110 u16 num_rxd;
1111 u16 num_jumbo_rxd;
1112 u16 max_rxd;
1113 u16 max_jumbo_rxd;
1114
1115 u8 max_rds_rings;
1116
1117 u8 max_sds_rings; /* max sds rings supported by adapter */
1118 u8 max_tx_rings; /* max tx rings supported by adapter */
1119
1120 u8 drv_tx_rings; /* max tx rings supported by driver */
1121 u8 drv_sds_rings; /* max sds rings supported by driver */
1122
1123 u8 drv_tss_rings; /* tss ring input */
1124 u8 drv_rss_rings; /* rss ring input */
1125
1126 u8 rx_csum;
1127 u8 portnum;
1128
1129 u8 fw_wait_cnt;
1130 u8 fw_fail_cnt;
1131 u8 tx_timeo_cnt;
1132 u8 need_fw_reset;
1133 u8 reset_ctx_cnt;
1134
1135 u16 is_up;
1136 u16 rx_pvid;
1137 u16 tx_pvid;
1138
1139 u32 irq;
1140 u32 heartbeat;
1141
1142 u8 dev_state;
1143 u8 reset_ack_timeo;
1144 u8 dev_init_timeo;
1145
1146 u8 mac_addr[ETH_ALEN];
1147
1148 u64 dev_rst_time;
1149 bool drv_mac_learn;
1150 bool fdb_mac_learn;
1151 bool rx_mac_learn;
1152 unsigned long vlans[BITS_TO_LONGS(VLAN_N_VID)];
1153 u8 flash_mfg_id;
1154 struct qlcnic_npar_info *npars;
1155 struct qlcnic_eswitch *eswitch;
1156 struct qlcnic_nic_template *nic_ops;
1157
1158 struct qlcnic_adapter_stats stats;
1159 struct list_head mac_list;
1160
1161 void __iomem *tgt_mask_reg;
1162 void __iomem *tgt_status_reg;
1163 void __iomem *crb_int_state_reg;
1164 void __iomem *isr_int_vec;
1165
1166 struct msix_entry *msix_entries;
1167 struct workqueue_struct *qlcnic_wq;
1168 struct delayed_work fw_work;
1169 struct delayed_work idc_aen_work;
1170 struct delayed_work mbx_poll_work;
1171 struct qlcnic_dcb *dcb;
1172
1173 struct qlcnic_filter_hash fhash;
1174 struct qlcnic_filter_hash rx_fhash;
1175 struct list_head vf_mc_list;
1176
1177 spinlock_t mac_learn_lock;
1178 /* spinlock for catching rcv filters for eswitch traffic */
1179 spinlock_t rx_mac_learn_lock;
1180 u32 file_prd_off; /*File fw product offset*/
1181 u32 fw_version;
1182 u32 offload_flags;
1183 const struct firmware *fw;
1184 };
1185
1186 struct qlcnic_info_le {
1187 __le16 pci_func;
1188 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1189 __le16 phys_port;
1190 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1191
1192 __le32 capabilities;
1193 u8 max_mac_filters;
1194 u8 reserved1;
1195 __le16 max_mtu;
1196
1197 __le16 max_tx_ques;
1198 __le16 max_rx_ques;
1199 __le16 min_tx_bw;
1200 __le16 max_tx_bw;
1201 __le32 op_type;
1202 __le16 max_bw_reg_offset;
1203 __le16 max_linkspeed_reg_offset;
1204 __le32 capability1;
1205 __le32 capability2;
1206 __le32 capability3;
1207 __le16 max_tx_mac_filters;
1208 __le16 max_rx_mcast_mac_filters;
1209 __le16 max_rx_ucast_mac_filters;
1210 __le16 max_rx_ip_addr;
1211 __le16 max_rx_lro_flow;
1212 __le16 max_rx_status_rings;
1213 __le16 max_rx_buf_rings;
1214 __le16 max_tx_vlan_keys;
1215 u8 total_pf;
1216 u8 total_rss_engines;
1217 __le16 max_vports;
1218 __le16 linkstate_reg_offset;
1219 __le16 bit_offsets;
1220 __le16 max_local_ipv6_addrs;
1221 __le16 max_remote_ipv6_addrs;
1222 u8 reserved2[56];
1223 } __packed;
1224
1225 struct qlcnic_info {
1226 u16 pci_func;
1227 u16 op_mode;
1228 u16 phys_port;
1229 u16 switch_mode;
1230 u32 capabilities;
1231 u8 max_mac_filters;
1232 u16 max_mtu;
1233 u16 max_tx_ques;
1234 u16 max_rx_ques;
1235 u16 min_tx_bw;
1236 u16 max_tx_bw;
1237 u32 op_type;
1238 u16 max_bw_reg_offset;
1239 u16 max_linkspeed_reg_offset;
1240 u32 capability1;
1241 u32 capability2;
1242 u32 capability3;
1243 u16 max_tx_mac_filters;
1244 u16 max_rx_mcast_mac_filters;
1245 u16 max_rx_ucast_mac_filters;
1246 u16 max_rx_ip_addr;
1247 u16 max_rx_lro_flow;
1248 u16 max_rx_status_rings;
1249 u16 max_rx_buf_rings;
1250 u16 max_tx_vlan_keys;
1251 u8 total_pf;
1252 u8 total_rss_engines;
1253 u16 max_vports;
1254 u16 linkstate_reg_offset;
1255 u16 bit_offsets;
1256 u16 max_local_ipv6_addrs;
1257 u16 max_remote_ipv6_addrs;
1258 };
1259
1260 struct qlcnic_pci_info_le {
1261 __le16 id; /* pci function id */
1262 __le16 active; /* 1 = Enabled */
1263 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1264 __le16 default_port; /* default port number */
1265
1266 __le16 tx_min_bw; /* Multiple of 100mbpc */
1267 __le16 tx_max_bw;
1268 __le16 reserved1[2];
1269
1270 u8 mac[ETH_ALEN];
1271 __le16 func_count;
1272 u8 reserved2[104];
1273
1274 } __packed;
1275
1276 struct qlcnic_pci_info {
1277 u16 id;
1278 u16 active;
1279 u16 type;
1280 u16 default_port;
1281 u16 tx_min_bw;
1282 u16 tx_max_bw;
1283 u8 mac[ETH_ALEN];
1284 u16 func_count;
1285 };
1286
1287 struct qlcnic_npar_info {
1288 bool eswitch_status;
1289 u16 pvid;
1290 u16 min_bw;
1291 u16 max_bw;
1292 u8 phy_port;
1293 u8 type;
1294 u8 active;
1295 u8 enable_pm;
1296 u8 dest_npar;
1297 u8 discard_tagged;
1298 u8 mac_override;
1299 u8 mac_anti_spoof;
1300 u8 promisc_mode;
1301 u8 offload_flags;
1302 u8 pci_func;
1303 u8 mac[ETH_ALEN];
1304 };
1305
1306 struct qlcnic_eswitch {
1307 u8 port;
1308 u8 active_vports;
1309 u8 active_vlans;
1310 u8 active_ucast_filters;
1311 u8 max_ucast_filters;
1312 u8 max_active_vlans;
1313
1314 u32 flags;
1315 #define QLCNIC_SWITCH_ENABLE BIT_1
1316 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1317 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1318 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1319 };
1320
1321
1322 #define MAX_BW 100 /* % of link speed */
1323 #define MIN_BW 1 /* % of link speed */
1324 #define MAX_VLAN_ID 4095
1325 #define MIN_VLAN_ID 2
1326 #define DEFAULT_MAC_LEARN 1
1327
1328 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1329 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1330
1331 struct qlcnic_pci_func_cfg {
1332 u16 func_type;
1333 u16 min_bw;
1334 u16 max_bw;
1335 u16 port_num;
1336 u8 pci_func;
1337 u8 func_state;
1338 u8 def_mac_addr[ETH_ALEN];
1339 };
1340
1341 struct qlcnic_npar_func_cfg {
1342 u32 fw_capab;
1343 u16 port_num;
1344 u16 min_bw;
1345 u16 max_bw;
1346 u16 max_tx_queues;
1347 u16 max_rx_queues;
1348 u8 pci_func;
1349 u8 op_mode;
1350 };
1351
1352 struct qlcnic_pm_func_cfg {
1353 u8 pci_func;
1354 u8 action;
1355 u8 dest_npar;
1356 u8 reserved[5];
1357 };
1358
1359 struct qlcnic_esw_func_cfg {
1360 u16 vlan_id;
1361 u8 op_mode;
1362 u8 op_type;
1363 u8 pci_func;
1364 u8 host_vlan_tag;
1365 u8 promisc_mode;
1366 u8 discard_tagged;
1367 u8 mac_override;
1368 u8 mac_anti_spoof;
1369 u8 offload_flags;
1370 u8 reserved[5];
1371 };
1372
1373 #define QLCNIC_STATS_VERSION 1
1374 #define QLCNIC_STATS_PORT 1
1375 #define QLCNIC_STATS_ESWITCH 2
1376 #define QLCNIC_QUERY_RX_COUNTER 0
1377 #define QLCNIC_QUERY_TX_COUNTER 1
1378 #define QLCNIC_STATS_NOT_AVAIL 0xffffffffffffffffULL
1379 #define QLCNIC_FILL_STATS(VAL1) \
1380 (((VAL1) == QLCNIC_STATS_NOT_AVAIL) ? 0 : VAL1)
1381 #define QLCNIC_MAC_STATS 1
1382 #define QLCNIC_ESW_STATS 2
1383
1384 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1385 do { \
1386 if (((VAL1) == QLCNIC_STATS_NOT_AVAIL) && \
1387 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1388 (VAL1) = (VAL2); \
1389 else if (((VAL1) != QLCNIC_STATS_NOT_AVAIL) && \
1390 ((VAL2) != QLCNIC_STATS_NOT_AVAIL)) \
1391 (VAL1) += (VAL2); \
1392 } while (0)
1393
1394 struct qlcnic_mac_statistics_le {
1395 __le64 mac_tx_frames;
1396 __le64 mac_tx_bytes;
1397 __le64 mac_tx_mcast_pkts;
1398 __le64 mac_tx_bcast_pkts;
1399 __le64 mac_tx_pause_cnt;
1400 __le64 mac_tx_ctrl_pkt;
1401 __le64 mac_tx_lt_64b_pkts;
1402 __le64 mac_tx_lt_127b_pkts;
1403 __le64 mac_tx_lt_255b_pkts;
1404 __le64 mac_tx_lt_511b_pkts;
1405 __le64 mac_tx_lt_1023b_pkts;
1406 __le64 mac_tx_lt_1518b_pkts;
1407 __le64 mac_tx_gt_1518b_pkts;
1408 __le64 rsvd1[3];
1409
1410 __le64 mac_rx_frames;
1411 __le64 mac_rx_bytes;
1412 __le64 mac_rx_mcast_pkts;
1413 __le64 mac_rx_bcast_pkts;
1414 __le64 mac_rx_pause_cnt;
1415 __le64 mac_rx_ctrl_pkt;
1416 __le64 mac_rx_lt_64b_pkts;
1417 __le64 mac_rx_lt_127b_pkts;
1418 __le64 mac_rx_lt_255b_pkts;
1419 __le64 mac_rx_lt_511b_pkts;
1420 __le64 mac_rx_lt_1023b_pkts;
1421 __le64 mac_rx_lt_1518b_pkts;
1422 __le64 mac_rx_gt_1518b_pkts;
1423 __le64 rsvd2[3];
1424
1425 __le64 mac_rx_length_error;
1426 __le64 mac_rx_length_small;
1427 __le64 mac_rx_length_large;
1428 __le64 mac_rx_jabber;
1429 __le64 mac_rx_dropped;
1430 __le64 mac_rx_crc_error;
1431 __le64 mac_align_error;
1432 } __packed;
1433
1434 struct qlcnic_mac_statistics {
1435 u64 mac_tx_frames;
1436 u64 mac_tx_bytes;
1437 u64 mac_tx_mcast_pkts;
1438 u64 mac_tx_bcast_pkts;
1439 u64 mac_tx_pause_cnt;
1440 u64 mac_tx_ctrl_pkt;
1441 u64 mac_tx_lt_64b_pkts;
1442 u64 mac_tx_lt_127b_pkts;
1443 u64 mac_tx_lt_255b_pkts;
1444 u64 mac_tx_lt_511b_pkts;
1445 u64 mac_tx_lt_1023b_pkts;
1446 u64 mac_tx_lt_1518b_pkts;
1447 u64 mac_tx_gt_1518b_pkts;
1448 u64 rsvd1[3];
1449 u64 mac_rx_frames;
1450 u64 mac_rx_bytes;
1451 u64 mac_rx_mcast_pkts;
1452 u64 mac_rx_bcast_pkts;
1453 u64 mac_rx_pause_cnt;
1454 u64 mac_rx_ctrl_pkt;
1455 u64 mac_rx_lt_64b_pkts;
1456 u64 mac_rx_lt_127b_pkts;
1457 u64 mac_rx_lt_255b_pkts;
1458 u64 mac_rx_lt_511b_pkts;
1459 u64 mac_rx_lt_1023b_pkts;
1460 u64 mac_rx_lt_1518b_pkts;
1461 u64 mac_rx_gt_1518b_pkts;
1462 u64 rsvd2[3];
1463 u64 mac_rx_length_error;
1464 u64 mac_rx_length_small;
1465 u64 mac_rx_length_large;
1466 u64 mac_rx_jabber;
1467 u64 mac_rx_dropped;
1468 u64 mac_rx_crc_error;
1469 u64 mac_align_error;
1470 };
1471
1472 struct qlcnic_esw_stats_le {
1473 __le16 context_id;
1474 __le16 version;
1475 __le16 size;
1476 __le16 unused;
1477 __le64 unicast_frames;
1478 __le64 multicast_frames;
1479 __le64 broadcast_frames;
1480 __le64 dropped_frames;
1481 __le64 errors;
1482 __le64 local_frames;
1483 __le64 numbytes;
1484 __le64 rsvd[3];
1485 } __packed;
1486
1487 struct __qlcnic_esw_statistics {
1488 u16 context_id;
1489 u16 version;
1490 u16 size;
1491 u16 unused;
1492 u64 unicast_frames;
1493 u64 multicast_frames;
1494 u64 broadcast_frames;
1495 u64 dropped_frames;
1496 u64 errors;
1497 u64 local_frames;
1498 u64 numbytes;
1499 u64 rsvd[3];
1500 };
1501
1502 struct qlcnic_esw_statistics {
1503 struct __qlcnic_esw_statistics rx;
1504 struct __qlcnic_esw_statistics tx;
1505 };
1506
1507 #define QLCNIC_FORCE_FW_DUMP_KEY 0xdeadfeed
1508 #define QLCNIC_ENABLE_FW_DUMP 0xaddfeed
1509 #define QLCNIC_DISABLE_FW_DUMP 0xbadfeed
1510 #define QLCNIC_FORCE_FW_RESET 0xdeaddead
1511 #define QLCNIC_SET_QUIESCENT 0xadd00010
1512 #define QLCNIC_RESET_QUIESCENT 0xadd00020
1513
1514 struct _cdrp_cmd {
1515 u32 num;
1516 u32 *arg;
1517 };
1518
1519 struct qlcnic_cmd_args {
1520 struct completion completion;
1521 struct list_head list;
1522 struct _cdrp_cmd req;
1523 struct _cdrp_cmd rsp;
1524 atomic_t rsp_status;
1525 int pay_size;
1526 u32 rsp_opcode;
1527 u32 total_cmds;
1528 u32 op_type;
1529 u32 type;
1530 u32 cmd_op;
1531 u32 *hdr; /* Back channel message header */
1532 u32 *pay; /* Back channel message payload */
1533 u8 func_num;
1534 };
1535
1536 int qlcnic_fw_cmd_get_minidump_temp(struct qlcnic_adapter *adapter);
1537 int qlcnic_fw_cmd_set_port(struct qlcnic_adapter *adapter, u32 config);
1538 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1539 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1540
1541 #define ADDR_IN_RANGE(addr, low, high) \
1542 (((addr) < (high)) && ((addr) >= (low)))
1543
1544 #define QLCRD32(adapter, off, err) \
1545 (adapter->ahw->hw_ops->read_reg)(adapter, off, err)
1546
1547 #define QLCWR32(adapter, off, val) \
1548 adapter->ahw->hw_ops->write_reg(adapter, off, val)
1549
1550 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1551 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1552
1553 #define qlcnic_rom_lock(a) \
1554 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1555 #define qlcnic_rom_unlock(a) \
1556 qlcnic_pcie_sem_unlock((a), 2)
1557 #define qlcnic_phy_lock(a) \
1558 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1559 #define qlcnic_phy_unlock(a) \
1560 qlcnic_pcie_sem_unlock((a), 3)
1561 #define qlcnic_sw_lock(a) \
1562 qlcnic_pcie_sem_lock((a), 6, 0)
1563 #define qlcnic_sw_unlock(a) \
1564 qlcnic_pcie_sem_unlock((a), 6)
1565 #define crb_win_lock(a) \
1566 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1567 #define crb_win_unlock(a) \
1568 qlcnic_pcie_sem_unlock((a), 7)
1569
1570 #define __QLCNIC_MAX_LED_RATE 0xf
1571 #define __QLCNIC_MAX_LED_STATE 0x2
1572
1573 #define MAX_CTL_CHECK 1000
1574
1575 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1576 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1577 int qlcnic_dump_fw(struct qlcnic_adapter *);
1578 int qlcnic_enable_fw_dump_state(struct qlcnic_adapter *);
1579 bool qlcnic_check_fw_dump_state(struct qlcnic_adapter *);
1580
1581 /* Functions from qlcnic_init.c */
1582 void qlcnic_schedule_work(struct qlcnic_adapter *, work_func_t, int);
1583 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1584 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1585 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1586 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1587 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1588 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1589 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1590
1591 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, u32 addr, u32 *valp);
1592 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1593 u8 *bytes, size_t size);
1594 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1595 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1596
1597 void __iomem *qlcnic_get_ioaddr(struct qlcnic_hardware_context *, u32);
1598
1599 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1600 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1601
1602 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1603 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1604
1605 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1606 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1607 void qlcnic_release_tx_buffers(struct qlcnic_adapter *,
1608 struct qlcnic_host_tx_ring *);
1609
1610 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1611 void qlcnic_watchdog_task(struct work_struct *work);
1612 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1613 struct qlcnic_host_rds_ring *rds_ring, u8 ring_id);
1614 void qlcnic_set_multi(struct net_device *netdev);
1615 void qlcnic_flush_mcast_mac(struct qlcnic_adapter *);
1616 int qlcnic_nic_add_mac(struct qlcnic_adapter *, const u8 *, u16,
1617 enum qlcnic_mac_type);
1618 int qlcnic_nic_del_mac(struct qlcnic_adapter *, const u8 *);
1619 void qlcnic_82xx_free_mac_list(struct qlcnic_adapter *adapter);
1620 int qlcnic_82xx_read_phys_port_id(struct qlcnic_adapter *);
1621
1622 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1623 int qlcnic_fw_cmd_set_drv_version(struct qlcnic_adapter *, u32);
1624 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1625 netdev_features_t qlcnic_fix_features(struct net_device *netdev,
1626 netdev_features_t features);
1627 int qlcnic_set_features(struct net_device *netdev, netdev_features_t features);
1628 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1629 void qlcnic_update_cmd_producer(struct qlcnic_host_tx_ring *);
1630
1631 /* Functions from qlcnic_ethtool.c */
1632 int qlcnic_check_loopback_buff(unsigned char *, u8 []);
1633 int qlcnic_do_lb_test(struct qlcnic_adapter *, u8);
1634
1635 /* Functions from qlcnic_main.c */
1636 int qlcnic_reset_context(struct qlcnic_adapter *);
1637 void qlcnic_diag_free_res(struct net_device *netdev, int);
1638 int qlcnic_diag_alloc_res(struct net_device *netdev, int);
1639 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *, struct net_device *);
1640 void qlcnic_set_tx_ring_count(struct qlcnic_adapter *, u8);
1641 void qlcnic_set_sds_ring_count(struct qlcnic_adapter *, u8);
1642 int qlcnic_setup_rings(struct qlcnic_adapter *);
1643 int qlcnic_validate_rings(struct qlcnic_adapter *, __u32, int);
1644 void qlcnic_alloc_lb_filters_mem(struct qlcnic_adapter *adapter);
1645 int qlcnic_enable_msix(struct qlcnic_adapter *, u32);
1646 void qlcnic_set_drv_version(struct qlcnic_adapter *);
1647
1648 /* eSwitch management functions */
1649 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1650 struct qlcnic_esw_func_cfg *);
1651
1652 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1653 struct qlcnic_esw_func_cfg *);
1654 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1655 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1656 struct __qlcnic_esw_statistics *);
1657 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1658 struct __qlcnic_esw_statistics *);
1659 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1660 int qlcnic_get_mac_stats(struct qlcnic_adapter *, struct qlcnic_mac_statistics *);
1661
1662 void qlcnic_free_mbx_args(struct qlcnic_cmd_args *cmd);
1663
1664 int qlcnic_alloc_sds_rings(struct qlcnic_recv_context *, int);
1665 void qlcnic_free_sds_rings(struct qlcnic_recv_context *);
1666 void qlcnic_advert_link_change(struct qlcnic_adapter *, int);
1667 void qlcnic_free_tx_rings(struct qlcnic_adapter *);
1668 int qlcnic_alloc_tx_rings(struct qlcnic_adapter *, struct net_device *);
1669 void qlcnic_dump_mbx(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1670
1671 void qlcnic_create_sysfs_entries(struct qlcnic_adapter *adapter);
1672 void qlcnic_remove_sysfs_entries(struct qlcnic_adapter *adapter);
1673 void qlcnic_82xx_add_sysfs(struct qlcnic_adapter *adapter);
1674 void qlcnic_82xx_remove_sysfs(struct qlcnic_adapter *adapter);
1675
1676 int qlcnicvf_config_bridged_mode(struct qlcnic_adapter *, u32);
1677 int qlcnicvf_config_led(struct qlcnic_adapter *, u32, u32);
1678 void qlcnic_set_vlan_config(struct qlcnic_adapter *,
1679 struct qlcnic_esw_func_cfg *);
1680 void qlcnic_set_eswitch_port_features(struct qlcnic_adapter *,
1681 struct qlcnic_esw_func_cfg *);
1682 int qlcnic_setup_tss_rss_intr(struct qlcnic_adapter *);
1683 void qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1684 int qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1685 void __qlcnic_down(struct qlcnic_adapter *, struct net_device *);
1686 void qlcnic_detach(struct qlcnic_adapter *);
1687 void qlcnic_teardown_intr(struct qlcnic_adapter *);
1688 int qlcnic_attach(struct qlcnic_adapter *);
1689 int __qlcnic_up(struct qlcnic_adapter *, struct net_device *);
1690 void qlcnic_restore_indev_addr(struct net_device *, unsigned long);
1691
1692 int qlcnic_check_temp(struct qlcnic_adapter *);
1693 int qlcnic_init_pci_info(struct qlcnic_adapter *);
1694 int qlcnic_set_default_offload_settings(struct qlcnic_adapter *);
1695 int qlcnic_reset_npar_config(struct qlcnic_adapter *);
1696 int qlcnic_set_eswitch_port_config(struct qlcnic_adapter *);
1697 int qlcnic_set_vxlan_port(struct qlcnic_adapter *adapter, u16 port);
1698 int qlcnic_set_vxlan_parsing(struct qlcnic_adapter *adapter, u16 port);
1699 int qlcnic_83xx_configure_opmode(struct qlcnic_adapter *adapter);
1700 int qlcnic_read_mac_addr(struct qlcnic_adapter *);
1701 int qlcnic_setup_netdev(struct qlcnic_adapter *, struct net_device *, int);
1702 void qlcnic_set_netdev_features(struct qlcnic_adapter *,
1703 struct qlcnic_esw_func_cfg *);
1704 void qlcnic_sriov_vf_set_multi(struct net_device *);
1705 int qlcnic_is_valid_nic_func(struct qlcnic_adapter *, u8);
1706 int qlcnic_get_pci_func_type(struct qlcnic_adapter *, u16, u16 *, u16 *,
1707 u16 *);
1708
1709 /*
1710 * QLOGIC Board information
1711 */
1712
1713 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1714 struct qlcnic_board_info {
1715 unsigned short vendor;
1716 unsigned short device;
1717 unsigned short sub_vendor;
1718 unsigned short sub_device;
1719 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1720 };
1721
qlcnic_tx_avail(struct qlcnic_host_tx_ring * tx_ring)1722 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1723 {
1724 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1725 return tx_ring->sw_consumer - tx_ring->producer;
1726 else
1727 return tx_ring->sw_consumer + tx_ring->num_desc -
1728 tx_ring->producer;
1729 }
1730
1731 struct qlcnic_nic_template {
1732 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1733 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1734 int (*start_firmware) (struct qlcnic_adapter *);
1735 int (*init_driver) (struct qlcnic_adapter *);
1736 void (*request_reset) (struct qlcnic_adapter *, u32);
1737 void (*cancel_idc_work) (struct qlcnic_adapter *);
1738 int (*napi_add)(struct qlcnic_adapter *, struct net_device *);
1739 void (*napi_del)(struct qlcnic_adapter *);
1740 void (*config_ipaddr)(struct qlcnic_adapter *, __be32, int);
1741 irqreturn_t (*clear_legacy_intr)(struct qlcnic_adapter *);
1742 int (*shutdown)(struct pci_dev *);
1743 int (*resume)(struct qlcnic_adapter *);
1744 };
1745
1746 struct qlcnic_mbx_ops {
1747 int (*enqueue_cmd) (struct qlcnic_adapter *,
1748 struct qlcnic_cmd_args *, unsigned long *);
1749 void (*dequeue_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1750 void (*decode_resp) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1751 void (*encode_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1752 void (*nofity_fw) (struct qlcnic_adapter *, u8);
1753 };
1754
1755 int qlcnic_83xx_init_mailbox_work(struct qlcnic_adapter *);
1756 void qlcnic_83xx_detach_mailbox_work(struct qlcnic_adapter *);
1757 void qlcnic_83xx_reinit_mbx_work(struct qlcnic_mailbox *mbx);
1758 void qlcnic_83xx_free_mailbox(struct qlcnic_mailbox *mbx);
1759 void qlcnic_update_stats(struct qlcnic_adapter *);
1760
1761 /* Adapter hardware abstraction */
1762 struct qlcnic_hardware_ops {
1763 void (*read_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1764 void (*write_crb) (struct qlcnic_adapter *, char *, loff_t, size_t);
1765 int (*read_reg) (struct qlcnic_adapter *, ulong, int *);
1766 int (*write_reg) (struct qlcnic_adapter *, ulong, u32);
1767 void (*get_ocm_win) (struct qlcnic_hardware_context *);
1768 int (*get_mac_address) (struct qlcnic_adapter *, u8 *, u8);
1769 int (*setup_intr) (struct qlcnic_adapter *);
1770 int (*alloc_mbx_args)(struct qlcnic_cmd_args *,
1771 struct qlcnic_adapter *, u32);
1772 int (*mbx_cmd) (struct qlcnic_adapter *, struct qlcnic_cmd_args *);
1773 void (*get_func_no) (struct qlcnic_adapter *);
1774 int (*api_lock) (struct qlcnic_adapter *);
1775 void (*api_unlock) (struct qlcnic_adapter *);
1776 void (*add_sysfs) (struct qlcnic_adapter *);
1777 void (*remove_sysfs) (struct qlcnic_adapter *);
1778 void (*process_lb_rcv_ring_diag) (struct qlcnic_host_sds_ring *);
1779 int (*create_rx_ctx) (struct qlcnic_adapter *);
1780 int (*create_tx_ctx) (struct qlcnic_adapter *,
1781 struct qlcnic_host_tx_ring *, int);
1782 void (*del_rx_ctx) (struct qlcnic_adapter *);
1783 void (*del_tx_ctx) (struct qlcnic_adapter *,
1784 struct qlcnic_host_tx_ring *);
1785 int (*setup_link_event) (struct qlcnic_adapter *, int);
1786 int (*get_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *, u8);
1787 int (*get_pci_info) (struct qlcnic_adapter *, struct qlcnic_pci_info *);
1788 int (*set_nic_info) (struct qlcnic_adapter *, struct qlcnic_info *);
1789 int (*change_macvlan) (struct qlcnic_adapter *, u8*, u16, u8);
1790 void (*napi_enable) (struct qlcnic_adapter *);
1791 void (*napi_disable) (struct qlcnic_adapter *);
1792 int (*config_intr_coal) (struct qlcnic_adapter *,
1793 struct ethtool_coalesce *);
1794 int (*config_rss) (struct qlcnic_adapter *, int);
1795 int (*config_hw_lro) (struct qlcnic_adapter *, int);
1796 int (*config_loopback) (struct qlcnic_adapter *, u8);
1797 int (*clear_loopback) (struct qlcnic_adapter *, u8);
1798 int (*config_promisc_mode) (struct qlcnic_adapter *, u32);
1799 void (*change_l2_filter)(struct qlcnic_adapter *adapter, u64 *addr,
1800 u16 vlan, struct qlcnic_host_tx_ring *tx_ring);
1801 int (*get_board_info) (struct qlcnic_adapter *);
1802 void (*set_mac_filter_count) (struct qlcnic_adapter *);
1803 void (*free_mac_list) (struct qlcnic_adapter *);
1804 int (*read_phys_port_id) (struct qlcnic_adapter *);
1805 pci_ers_result_t (*io_error_detected) (struct pci_dev *,
1806 pci_channel_state_t);
1807 pci_ers_result_t (*io_slot_reset) (struct pci_dev *);
1808 void (*io_resume) (struct pci_dev *);
1809 void (*get_beacon_state)(struct qlcnic_adapter *);
1810 void (*enable_sds_intr) (struct qlcnic_adapter *,
1811 struct qlcnic_host_sds_ring *);
1812 void (*disable_sds_intr) (struct qlcnic_adapter *,
1813 struct qlcnic_host_sds_ring *);
1814 void (*enable_tx_intr) (struct qlcnic_adapter *,
1815 struct qlcnic_host_tx_ring *);
1816 void (*disable_tx_intr) (struct qlcnic_adapter *,
1817 struct qlcnic_host_tx_ring *);
1818 u32 (*get_saved_state)(void *, u32);
1819 void (*set_saved_state)(void *, u32, u32);
1820 void (*cache_tmpl_hdr_values)(struct qlcnic_fw_dump *);
1821 u32 (*get_cap_size)(void *, int);
1822 void (*set_sys_info)(void *, int, u32);
1823 void (*store_cap_mask)(void *, u32);
1824 bool (*encap_rx_offload) (struct qlcnic_adapter *adapter);
1825 bool (*encap_tx_offload) (struct qlcnic_adapter *adapter);
1826 };
1827
1828 extern struct qlcnic_nic_template qlcnic_vf_ops;
1829
qlcnic_83xx_encap_tx_offload(struct qlcnic_adapter * adapter)1830 static inline bool qlcnic_83xx_encap_tx_offload(struct qlcnic_adapter *adapter)
1831 {
1832 return adapter->ahw->extra_capability[0] &
1833 QLCNIC_83XX_FW_CAPAB_ENCAP_TX_OFFLOAD;
1834 }
1835
qlcnic_83xx_encap_rx_offload(struct qlcnic_adapter * adapter)1836 static inline bool qlcnic_83xx_encap_rx_offload(struct qlcnic_adapter *adapter)
1837 {
1838 return adapter->ahw->extra_capability[0] &
1839 QLCNIC_83XX_FW_CAPAB_ENCAP_RX_OFFLOAD;
1840 }
1841
qlcnic_82xx_encap_tx_offload(struct qlcnic_adapter * adapter)1842 static inline bool qlcnic_82xx_encap_tx_offload(struct qlcnic_adapter *adapter)
1843 {
1844 return false;
1845 }
1846
qlcnic_82xx_encap_rx_offload(struct qlcnic_adapter * adapter)1847 static inline bool qlcnic_82xx_encap_rx_offload(struct qlcnic_adapter *adapter)
1848 {
1849 return false;
1850 }
1851
qlcnic_encap_rx_offload(struct qlcnic_adapter * adapter)1852 static inline bool qlcnic_encap_rx_offload(struct qlcnic_adapter *adapter)
1853 {
1854 return adapter->ahw->hw_ops->encap_rx_offload(adapter);
1855 }
1856
qlcnic_encap_tx_offload(struct qlcnic_adapter * adapter)1857 static inline bool qlcnic_encap_tx_offload(struct qlcnic_adapter *adapter)
1858 {
1859 return adapter->ahw->hw_ops->encap_tx_offload(adapter);
1860 }
1861
qlcnic_start_firmware(struct qlcnic_adapter * adapter)1862 static inline int qlcnic_start_firmware(struct qlcnic_adapter *adapter)
1863 {
1864 return adapter->nic_ops->start_firmware(adapter);
1865 }
1866
qlcnic_read_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1867 static inline void qlcnic_read_crb(struct qlcnic_adapter *adapter, char *buf,
1868 loff_t offset, size_t size)
1869 {
1870 adapter->ahw->hw_ops->read_crb(adapter, buf, offset, size);
1871 }
1872
qlcnic_write_crb(struct qlcnic_adapter * adapter,char * buf,loff_t offset,size_t size)1873 static inline void qlcnic_write_crb(struct qlcnic_adapter *adapter, char *buf,
1874 loff_t offset, size_t size)
1875 {
1876 adapter->ahw->hw_ops->write_crb(adapter, buf, offset, size);
1877 }
1878
qlcnic_get_mac_address(struct qlcnic_adapter * adapter,u8 * mac,u8 function)1879 static inline int qlcnic_get_mac_address(struct qlcnic_adapter *adapter,
1880 u8 *mac, u8 function)
1881 {
1882 return adapter->ahw->hw_ops->get_mac_address(adapter, mac, function);
1883 }
1884
qlcnic_setup_intr(struct qlcnic_adapter * adapter)1885 static inline int qlcnic_setup_intr(struct qlcnic_adapter *adapter)
1886 {
1887 return adapter->ahw->hw_ops->setup_intr(adapter);
1888 }
1889
qlcnic_alloc_mbx_args(struct qlcnic_cmd_args * mbx,struct qlcnic_adapter * adapter,u32 arg)1890 static inline int qlcnic_alloc_mbx_args(struct qlcnic_cmd_args *mbx,
1891 struct qlcnic_adapter *adapter, u32 arg)
1892 {
1893 return adapter->ahw->hw_ops->alloc_mbx_args(mbx, adapter, arg);
1894 }
1895
qlcnic_issue_cmd(struct qlcnic_adapter * adapter,struct qlcnic_cmd_args * cmd)1896 static inline int qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1897 struct qlcnic_cmd_args *cmd)
1898 {
1899 if (adapter->ahw->hw_ops->mbx_cmd)
1900 return adapter->ahw->hw_ops->mbx_cmd(adapter, cmd);
1901
1902 return -EIO;
1903 }
1904
qlcnic_get_func_no(struct qlcnic_adapter * adapter)1905 static inline void qlcnic_get_func_no(struct qlcnic_adapter *adapter)
1906 {
1907 adapter->ahw->hw_ops->get_func_no(adapter);
1908 }
1909
qlcnic_api_lock(struct qlcnic_adapter * adapter)1910 static inline int qlcnic_api_lock(struct qlcnic_adapter *adapter)
1911 {
1912 return adapter->ahw->hw_ops->api_lock(adapter);
1913 }
1914
qlcnic_api_unlock(struct qlcnic_adapter * adapter)1915 static inline void qlcnic_api_unlock(struct qlcnic_adapter *adapter)
1916 {
1917 adapter->ahw->hw_ops->api_unlock(adapter);
1918 }
1919
qlcnic_add_sysfs(struct qlcnic_adapter * adapter)1920 static inline void qlcnic_add_sysfs(struct qlcnic_adapter *adapter)
1921 {
1922 if (adapter->ahw->hw_ops->add_sysfs)
1923 adapter->ahw->hw_ops->add_sysfs(adapter);
1924 }
1925
qlcnic_remove_sysfs(struct qlcnic_adapter * adapter)1926 static inline void qlcnic_remove_sysfs(struct qlcnic_adapter *adapter)
1927 {
1928 if (adapter->ahw->hw_ops->remove_sysfs)
1929 adapter->ahw->hw_ops->remove_sysfs(adapter);
1930 }
1931
1932 static inline void
qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring * sds_ring)1933 qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring)
1934 {
1935 sds_ring->adapter->ahw->hw_ops->process_lb_rcv_ring_diag(sds_ring);
1936 }
1937
qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter * adapter)1938 static inline int qlcnic_fw_cmd_create_rx_ctx(struct qlcnic_adapter *adapter)
1939 {
1940 return adapter->ahw->hw_ops->create_rx_ctx(adapter);
1941 }
1942
qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * ptr,int ring)1943 static inline int qlcnic_fw_cmd_create_tx_ctx(struct qlcnic_adapter *adapter,
1944 struct qlcnic_host_tx_ring *ptr,
1945 int ring)
1946 {
1947 return adapter->ahw->hw_ops->create_tx_ctx(adapter, ptr, ring);
1948 }
1949
qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter * adapter)1950 static inline void qlcnic_fw_cmd_del_rx_ctx(struct qlcnic_adapter *adapter)
1951 {
1952 return adapter->ahw->hw_ops->del_rx_ctx(adapter);
1953 }
1954
qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * ptr)1955 static inline void qlcnic_fw_cmd_del_tx_ctx(struct qlcnic_adapter *adapter,
1956 struct qlcnic_host_tx_ring *ptr)
1957 {
1958 return adapter->ahw->hw_ops->del_tx_ctx(adapter, ptr);
1959 }
1960
qlcnic_linkevent_request(struct qlcnic_adapter * adapter,int enable)1961 static inline int qlcnic_linkevent_request(struct qlcnic_adapter *adapter,
1962 int enable)
1963 {
1964 return adapter->ahw->hw_ops->setup_link_event(adapter, enable);
1965 }
1966
qlcnic_get_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * info,u8 id)1967 static inline int qlcnic_get_nic_info(struct qlcnic_adapter *adapter,
1968 struct qlcnic_info *info, u8 id)
1969 {
1970 return adapter->ahw->hw_ops->get_nic_info(adapter, info, id);
1971 }
1972
qlcnic_get_pci_info(struct qlcnic_adapter * adapter,struct qlcnic_pci_info * info)1973 static inline int qlcnic_get_pci_info(struct qlcnic_adapter *adapter,
1974 struct qlcnic_pci_info *info)
1975 {
1976 return adapter->ahw->hw_ops->get_pci_info(adapter, info);
1977 }
1978
qlcnic_set_nic_info(struct qlcnic_adapter * adapter,struct qlcnic_info * info)1979 static inline int qlcnic_set_nic_info(struct qlcnic_adapter *adapter,
1980 struct qlcnic_info *info)
1981 {
1982 return adapter->ahw->hw_ops->set_nic_info(adapter, info);
1983 }
1984
qlcnic_sre_macaddr_change(struct qlcnic_adapter * adapter,u8 * addr,u16 id,u8 cmd)1985 static inline int qlcnic_sre_macaddr_change(struct qlcnic_adapter *adapter,
1986 u8 *addr, u16 id, u8 cmd)
1987 {
1988 return adapter->ahw->hw_ops->change_macvlan(adapter, addr, id, cmd);
1989 }
1990
qlcnic_napi_add(struct qlcnic_adapter * adapter,struct net_device * netdev)1991 static inline int qlcnic_napi_add(struct qlcnic_adapter *adapter,
1992 struct net_device *netdev)
1993 {
1994 return adapter->nic_ops->napi_add(adapter, netdev);
1995 }
1996
qlcnic_napi_del(struct qlcnic_adapter * adapter)1997 static inline void qlcnic_napi_del(struct qlcnic_adapter *adapter)
1998 {
1999 adapter->nic_ops->napi_del(adapter);
2000 }
2001
qlcnic_napi_enable(struct qlcnic_adapter * adapter)2002 static inline void qlcnic_napi_enable(struct qlcnic_adapter *adapter)
2003 {
2004 adapter->ahw->hw_ops->napi_enable(adapter);
2005 }
2006
__qlcnic_shutdown(struct pci_dev * pdev)2007 static inline int __qlcnic_shutdown(struct pci_dev *pdev)
2008 {
2009 struct qlcnic_adapter *adapter = pci_get_drvdata(pdev);
2010
2011 return adapter->nic_ops->shutdown(pdev);
2012 }
2013
__qlcnic_resume(struct qlcnic_adapter * adapter)2014 static inline int __qlcnic_resume(struct qlcnic_adapter *adapter)
2015 {
2016 return adapter->nic_ops->resume(adapter);
2017 }
2018
qlcnic_napi_disable(struct qlcnic_adapter * adapter)2019 static inline void qlcnic_napi_disable(struct qlcnic_adapter *adapter)
2020 {
2021 adapter->ahw->hw_ops->napi_disable(adapter);
2022 }
2023
qlcnic_config_intr_coalesce(struct qlcnic_adapter * adapter,struct ethtool_coalesce * ethcoal)2024 static inline int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter,
2025 struct ethtool_coalesce *ethcoal)
2026 {
2027 return adapter->ahw->hw_ops->config_intr_coal(adapter, ethcoal);
2028 }
2029
qlcnic_config_rss(struct qlcnic_adapter * adapter,int enable)2030 static inline int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable)
2031 {
2032 return adapter->ahw->hw_ops->config_rss(adapter, enable);
2033 }
2034
qlcnic_config_hw_lro(struct qlcnic_adapter * adapter,int enable)2035 static inline int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter,
2036 int enable)
2037 {
2038 return adapter->ahw->hw_ops->config_hw_lro(adapter, enable);
2039 }
2040
qlcnic_set_lb_mode(struct qlcnic_adapter * adapter,u8 mode)2041 static inline int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2042 {
2043 return adapter->ahw->hw_ops->config_loopback(adapter, mode);
2044 }
2045
qlcnic_clear_lb_mode(struct qlcnic_adapter * adapter,u8 mode)2046 static inline int qlcnic_clear_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
2047 {
2048 return adapter->ahw->hw_ops->clear_loopback(adapter, mode);
2049 }
2050
qlcnic_nic_set_promisc(struct qlcnic_adapter * adapter,u32 mode)2051 static inline int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter,
2052 u32 mode)
2053 {
2054 return adapter->ahw->hw_ops->config_promisc_mode(adapter, mode);
2055 }
2056
qlcnic_change_filter(struct qlcnic_adapter * adapter,u64 * addr,u16 vlan,struct qlcnic_host_tx_ring * tx_ring)2057 static inline void qlcnic_change_filter(struct qlcnic_adapter *adapter,
2058 u64 *addr, u16 vlan,
2059 struct qlcnic_host_tx_ring *tx_ring)
2060 {
2061 adapter->ahw->hw_ops->change_l2_filter(adapter, addr, vlan, tx_ring);
2062 }
2063
qlcnic_get_board_info(struct qlcnic_adapter * adapter)2064 static inline int qlcnic_get_board_info(struct qlcnic_adapter *adapter)
2065 {
2066 return adapter->ahw->hw_ops->get_board_info(adapter);
2067 }
2068
qlcnic_free_mac_list(struct qlcnic_adapter * adapter)2069 static inline void qlcnic_free_mac_list(struct qlcnic_adapter *adapter)
2070 {
2071 return adapter->ahw->hw_ops->free_mac_list(adapter);
2072 }
2073
qlcnic_set_mac_filter_count(struct qlcnic_adapter * adapter)2074 static inline void qlcnic_set_mac_filter_count(struct qlcnic_adapter *adapter)
2075 {
2076 if (adapter->ahw->hw_ops->set_mac_filter_count)
2077 adapter->ahw->hw_ops->set_mac_filter_count(adapter);
2078 }
2079
qlcnic_get_beacon_state(struct qlcnic_adapter * adapter)2080 static inline void qlcnic_get_beacon_state(struct qlcnic_adapter *adapter)
2081 {
2082 adapter->ahw->hw_ops->get_beacon_state(adapter);
2083 }
2084
qlcnic_read_phys_port_id(struct qlcnic_adapter * adapter)2085 static inline void qlcnic_read_phys_port_id(struct qlcnic_adapter *adapter)
2086 {
2087 if (adapter->ahw->hw_ops->read_phys_port_id)
2088 adapter->ahw->hw_ops->read_phys_port_id(adapter);
2089 }
2090
qlcnic_get_saved_state(struct qlcnic_adapter * adapter,void * t_hdr,u32 index)2091 static inline u32 qlcnic_get_saved_state(struct qlcnic_adapter *adapter,
2092 void *t_hdr, u32 index)
2093 {
2094 return adapter->ahw->hw_ops->get_saved_state(t_hdr, index);
2095 }
2096
qlcnic_set_saved_state(struct qlcnic_adapter * adapter,void * t_hdr,u32 index,u32 value)2097 static inline void qlcnic_set_saved_state(struct qlcnic_adapter *adapter,
2098 void *t_hdr, u32 index, u32 value)
2099 {
2100 adapter->ahw->hw_ops->set_saved_state(t_hdr, index, value);
2101 }
2102
qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter * adapter,struct qlcnic_fw_dump * fw_dump)2103 static inline void qlcnic_cache_tmpl_hdr_values(struct qlcnic_adapter *adapter,
2104 struct qlcnic_fw_dump *fw_dump)
2105 {
2106 adapter->ahw->hw_ops->cache_tmpl_hdr_values(fw_dump);
2107 }
2108
qlcnic_get_cap_size(struct qlcnic_adapter * adapter,void * tmpl_hdr,int index)2109 static inline u32 qlcnic_get_cap_size(struct qlcnic_adapter *adapter,
2110 void *tmpl_hdr, int index)
2111 {
2112 return adapter->ahw->hw_ops->get_cap_size(tmpl_hdr, index);
2113 }
2114
qlcnic_set_sys_info(struct qlcnic_adapter * adapter,void * tmpl_hdr,int idx,u32 value)2115 static inline void qlcnic_set_sys_info(struct qlcnic_adapter *adapter,
2116 void *tmpl_hdr, int idx, u32 value)
2117 {
2118 adapter->ahw->hw_ops->set_sys_info(tmpl_hdr, idx, value);
2119 }
2120
qlcnic_store_cap_mask(struct qlcnic_adapter * adapter,void * tmpl_hdr,u32 mask)2121 static inline void qlcnic_store_cap_mask(struct qlcnic_adapter *adapter,
2122 void *tmpl_hdr, u32 mask)
2123 {
2124 adapter->ahw->hw_ops->store_cap_mask(tmpl_hdr, mask);
2125 }
2126
qlcnic_dev_request_reset(struct qlcnic_adapter * adapter,u32 key)2127 static inline void qlcnic_dev_request_reset(struct qlcnic_adapter *adapter,
2128 u32 key)
2129 {
2130 if (adapter->nic_ops->request_reset)
2131 adapter->nic_ops->request_reset(adapter, key);
2132 }
2133
qlcnic_cancel_idc_work(struct qlcnic_adapter * adapter)2134 static inline void qlcnic_cancel_idc_work(struct qlcnic_adapter *adapter)
2135 {
2136 if (adapter->nic_ops->cancel_idc_work)
2137 adapter->nic_ops->cancel_idc_work(adapter);
2138 }
2139
2140 static inline irqreturn_t
qlcnic_clear_legacy_intr(struct qlcnic_adapter * adapter)2141 qlcnic_clear_legacy_intr(struct qlcnic_adapter *adapter)
2142 {
2143 return adapter->nic_ops->clear_legacy_intr(adapter);
2144 }
2145
qlcnic_config_led(struct qlcnic_adapter * adapter,u32 state,u32 rate)2146 static inline int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state,
2147 u32 rate)
2148 {
2149 return adapter->nic_ops->config_led(adapter, state, rate);
2150 }
2151
qlcnic_config_ipaddr(struct qlcnic_adapter * adapter,__be32 ip,int cmd)2152 static inline void qlcnic_config_ipaddr(struct qlcnic_adapter *adapter,
2153 __be32 ip, int cmd)
2154 {
2155 adapter->nic_ops->config_ipaddr(adapter, ip, cmd);
2156 }
2157
qlcnic_check_multi_tx(struct qlcnic_adapter * adapter)2158 static inline bool qlcnic_check_multi_tx(struct qlcnic_adapter *adapter)
2159 {
2160 return test_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2161 }
2162
2163 static inline void
qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2164 qlcnic_82xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2165 struct qlcnic_host_tx_ring *tx_ring)
2166 {
2167 if (qlcnic_check_multi_tx(adapter) &&
2168 !adapter->ahw->diag_test)
2169 writel(0x0, tx_ring->crb_intr_mask);
2170 }
2171
2172 static inline void
qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2173 qlcnic_82xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2174 struct qlcnic_host_tx_ring *tx_ring)
2175 {
2176 if (qlcnic_check_multi_tx(adapter) &&
2177 !adapter->ahw->diag_test)
2178 writel(1, tx_ring->crb_intr_mask);
2179 }
2180
2181 static inline void
qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2182 qlcnic_83xx_enable_tx_intr(struct qlcnic_adapter *adapter,
2183 struct qlcnic_host_tx_ring *tx_ring)
2184 {
2185 writel(0, tx_ring->crb_intr_mask);
2186 }
2187
2188 static inline void
qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2189 qlcnic_83xx_disable_tx_intr(struct qlcnic_adapter *adapter,
2190 struct qlcnic_host_tx_ring *tx_ring)
2191 {
2192 writel(1, tx_ring->crb_intr_mask);
2193 }
2194
2195 /* Enable MSI-x and INT-x interrupts */
2196 static inline void
qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2197 qlcnic_83xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2198 struct qlcnic_host_sds_ring *sds_ring)
2199 {
2200 writel(0, sds_ring->crb_intr_mask);
2201 }
2202
2203 /* Disable MSI-x and INT-x interrupts */
2204 static inline void
qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2205 qlcnic_83xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2206 struct qlcnic_host_sds_ring *sds_ring)
2207 {
2208 writel(1, sds_ring->crb_intr_mask);
2209 }
2210
qlcnic_disable_multi_tx(struct qlcnic_adapter * adapter)2211 static inline void qlcnic_disable_multi_tx(struct qlcnic_adapter *adapter)
2212 {
2213 test_and_clear_bit(__QLCNIC_MULTI_TX_UNIQUE, &adapter->state);
2214 adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
2215 }
2216
2217 /* When operating in a muti tx mode, driver needs to write 0x1
2218 * to src register, instead of 0x0 to disable receiving interrupt.
2219 */
2220 static inline void
qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2221 qlcnic_82xx_disable_sds_intr(struct qlcnic_adapter *adapter,
2222 struct qlcnic_host_sds_ring *sds_ring)
2223 {
2224 if (qlcnic_check_multi_tx(adapter) &&
2225 !adapter->ahw->diag_test &&
2226 (adapter->flags & QLCNIC_MSIX_ENABLED))
2227 writel(0x1, sds_ring->crb_intr_mask);
2228 else
2229 writel(0, sds_ring->crb_intr_mask);
2230 }
2231
qlcnic_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2232 static inline void qlcnic_enable_sds_intr(struct qlcnic_adapter *adapter,
2233 struct qlcnic_host_sds_ring *sds_ring)
2234 {
2235 if (adapter->ahw->hw_ops->enable_sds_intr)
2236 adapter->ahw->hw_ops->enable_sds_intr(adapter, sds_ring);
2237 }
2238
2239 static inline void
qlcnic_disable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2240 qlcnic_disable_sds_intr(struct qlcnic_adapter *adapter,
2241 struct qlcnic_host_sds_ring *sds_ring)
2242 {
2243 if (adapter->ahw->hw_ops->disable_sds_intr)
2244 adapter->ahw->hw_ops->disable_sds_intr(adapter, sds_ring);
2245 }
2246
qlcnic_enable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2247 static inline void qlcnic_enable_tx_intr(struct qlcnic_adapter *adapter,
2248 struct qlcnic_host_tx_ring *tx_ring)
2249 {
2250 if (adapter->ahw->hw_ops->enable_tx_intr)
2251 adapter->ahw->hw_ops->enable_tx_intr(adapter, tx_ring);
2252 }
2253
qlcnic_disable_tx_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_tx_ring * tx_ring)2254 static inline void qlcnic_disable_tx_intr(struct qlcnic_adapter *adapter,
2255 struct qlcnic_host_tx_ring *tx_ring)
2256 {
2257 if (adapter->ahw->hw_ops->disable_tx_intr)
2258 adapter->ahw->hw_ops->disable_tx_intr(adapter, tx_ring);
2259 }
2260
2261 /* When operating in a muti tx mode, driver needs to write 0x0
2262 * to src register, instead of 0x1 to enable receiving interrupts.
2263 */
2264 static inline void
qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter * adapter,struct qlcnic_host_sds_ring * sds_ring)2265 qlcnic_82xx_enable_sds_intr(struct qlcnic_adapter *adapter,
2266 struct qlcnic_host_sds_ring *sds_ring)
2267 {
2268 if (qlcnic_check_multi_tx(adapter) &&
2269 !adapter->ahw->diag_test &&
2270 (adapter->flags & QLCNIC_MSIX_ENABLED))
2271 writel(0, sds_ring->crb_intr_mask);
2272 else
2273 writel(0x1, sds_ring->crb_intr_mask);
2274
2275 if (!QLCNIC_IS_MSI_FAMILY(adapter))
2276 writel(0xfbff, adapter->tgt_mask_reg);
2277 }
2278
qlcnic_get_diag_lock(struct qlcnic_adapter * adapter)2279 static inline int qlcnic_get_diag_lock(struct qlcnic_adapter *adapter)
2280 {
2281 return test_and_set_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2282 }
2283
qlcnic_release_diag_lock(struct qlcnic_adapter * adapter)2284 static inline void qlcnic_release_diag_lock(struct qlcnic_adapter *adapter)
2285 {
2286 clear_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2287 }
2288
qlcnic_check_diag_status(struct qlcnic_adapter * adapter)2289 static inline int qlcnic_check_diag_status(struct qlcnic_adapter *adapter)
2290 {
2291 return test_bit(__QLCNIC_DIAG_MODE, &adapter->state);
2292 }
2293
2294 extern const struct ethtool_ops qlcnic_sriov_vf_ethtool_ops;
2295 extern const struct ethtool_ops qlcnic_ethtool_ops;
2296 extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
2297
2298 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
2299 if (NETIF_MSG_##lvl & adapter->ahw->msg_enable) \
2300 printk(KERN_INFO "%s: %s: " _fmt, \
2301 dev_name(&adapter->pdev->dev), \
2302 __func__, ##_args); \
2303 } while (0)
2304
2305 #define PCI_DEVICE_ID_QLOGIC_QLE824X 0x8020
2306 #define PCI_DEVICE_ID_QLOGIC_QLE834X 0x8030
2307 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
2308 #define PCI_DEVICE_ID_QLOGIC_QLE8830 0x8830
2309 #define PCI_DEVICE_ID_QLOGIC_VF_QLE8C30 0x8C30
2310 #define PCI_DEVICE_ID_QLOGIC_QLE844X 0x8040
2311 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
2312
qlcnic_82xx_check(struct qlcnic_adapter * adapter)2313 static inline bool qlcnic_82xx_check(struct qlcnic_adapter *adapter)
2314 {
2315 unsigned short device = adapter->pdev->device;
2316 return (device == PCI_DEVICE_ID_QLOGIC_QLE824X) ? true : false;
2317 }
2318
qlcnic_84xx_check(struct qlcnic_adapter * adapter)2319 static inline bool qlcnic_84xx_check(struct qlcnic_adapter *adapter)
2320 {
2321 unsigned short device = adapter->pdev->device;
2322
2323 return ((device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2324 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X)) ? true : false;
2325 }
2326
qlcnic_83xx_check(struct qlcnic_adapter * adapter)2327 static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
2328 {
2329 unsigned short device = adapter->pdev->device;
2330 bool status;
2331
2332 status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
2333 (device == PCI_DEVICE_ID_QLOGIC_QLE8830) ||
2334 (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
2335 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2336 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2337 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2338
2339 return status;
2340 }
2341
qlcnic_sriov_pf_check(struct qlcnic_adapter * adapter)2342 static inline bool qlcnic_sriov_pf_check(struct qlcnic_adapter *adapter)
2343 {
2344 return (adapter->ahw->op_mode == QLCNIC_SRIOV_PF_FUNC) ? true : false;
2345 }
2346
qlcnic_sriov_vf_check(struct qlcnic_adapter * adapter)2347 static inline bool qlcnic_sriov_vf_check(struct qlcnic_adapter *adapter)
2348 {
2349 unsigned short device = adapter->pdev->device;
2350 bool status;
2351
2352 status = ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2353 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
2354 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2355
2356 return status;
2357 }
2358
qlcnic_83xx_pf_check(struct qlcnic_adapter * adapter)2359 static inline bool qlcnic_83xx_pf_check(struct qlcnic_adapter *adapter)
2360 {
2361 unsigned short device = adapter->pdev->device;
2362
2363 return (device == PCI_DEVICE_ID_QLOGIC_QLE834X) ? true : false;
2364 }
2365
qlcnic_83xx_vf_check(struct qlcnic_adapter * adapter)2366 static inline bool qlcnic_83xx_vf_check(struct qlcnic_adapter *adapter)
2367 {
2368 unsigned short device = adapter->pdev->device;
2369
2370 return ((device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X) ||
2371 (device == PCI_DEVICE_ID_QLOGIC_VF_QLE8C30)) ? true : false;
2372 }
2373
qlcnic_sriov_check(struct qlcnic_adapter * adapter)2374 static inline bool qlcnic_sriov_check(struct qlcnic_adapter *adapter)
2375 {
2376 bool status;
2377
2378 status = (qlcnic_sriov_pf_check(adapter) ||
2379 qlcnic_sriov_vf_check(adapter)) ? true : false;
2380
2381 return status;
2382 }
2383
qlcnic_get_vnic_func_count(struct qlcnic_adapter * adapter)2384 static inline u32 qlcnic_get_vnic_func_count(struct qlcnic_adapter *adapter)
2385 {
2386 if (qlcnic_84xx_check(adapter))
2387 return QLC_84XX_VNIC_COUNT;
2388 else
2389 return QLC_DEFAULT_VNIC_COUNT;
2390 }
2391
qlcnic_swap32_buffer(u32 * buffer,int count)2392 static inline void qlcnic_swap32_buffer(u32 *buffer, int count)
2393 {
2394 #if defined(__BIG_ENDIAN)
2395 u32 *tmp = buffer;
2396 int i;
2397
2398 for (i = 0; i < count; i++) {
2399 *tmp = swab32(*tmp);
2400 tmp++;
2401 }
2402 #endif
2403 }
2404
2405 #ifdef CONFIG_QLCNIC_HWMON
2406 void qlcnic_register_hwmon_dev(struct qlcnic_adapter *);
2407 void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *);
2408 #else
qlcnic_register_hwmon_dev(struct qlcnic_adapter * adapter)2409 static inline void qlcnic_register_hwmon_dev(struct qlcnic_adapter *adapter)
2410 {
2411 return;
2412 }
qlcnic_unregister_hwmon_dev(struct qlcnic_adapter * adapter)2413 static inline void qlcnic_unregister_hwmon_dev(struct qlcnic_adapter *adapter)
2414 {
2415 return;
2416 }
2417 #endif
2418 #endif /* __QLCNIC_H_ */
2419
