1 /*
2 * aQuantia Corporation Network Driver
3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 */
9
10 /* File hw_atl_b0.c: Definition of Atlantic hardware specific functions. */
11
12 #include "../aq_hw.h"
13 #include "../aq_hw_utils.h"
14 #include "../aq_ring.h"
15 #include "../aq_nic.h"
16 #include "hw_atl_b0.h"
17 #include "hw_atl_utils.h"
18 #include "hw_atl_llh.h"
19 #include "hw_atl_b0_internal.h"
20 #include "hw_atl_llh_internal.h"
21
22 #define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
23 .is_64_dma = true, \
24 .msix_irqs = 4U, \
25 .irq_mask = ~0U, \
26 .vecs = HW_ATL_B0_RSS_MAX, \
27 .tcs = HW_ATL_B0_TC_MAX, \
28 .rxd_alignment = 1U, \
29 .rxd_size = HW_ATL_B0_RXD_SIZE, \
30 .rxds_max = HW_ATL_B0_MAX_RXD, \
31 .rxds_min = HW_ATL_B0_MIN_RXD, \
32 .txd_alignment = 1U, \
33 .txd_size = HW_ATL_B0_TXD_SIZE, \
34 .txds_max = HW_ATL_B0_MAX_TXD, \
35 .txds_min = HW_ATL_B0_MIN_TXD, \
36 .txhwb_alignment = 4096U, \
37 .tx_rings = HW_ATL_B0_TX_RINGS, \
38 .rx_rings = HW_ATL_B0_RX_RINGS, \
39 .hw_features = NETIF_F_HW_CSUM | \
40 NETIF_F_RXCSUM | \
41 NETIF_F_RXHASH | \
42 NETIF_F_SG | \
43 NETIF_F_TSO | \
44 NETIF_F_LRO, \
45 .hw_priv_flags = IFF_UNICAST_FLT, \
46 .flow_control = true, \
47 .mtu = HW_ATL_B0_MTU_JUMBO, \
48 .mac_regs_count = 88, \
49 .hw_alive_check_addr = 0x10U
50
51 const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
52 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
53 .media_type = AQ_HW_MEDIA_TYPE_FIBRE,
54 .link_speed_msk = HW_ATL_B0_RATE_10G |
55 HW_ATL_B0_RATE_5G |
56 HW_ATL_B0_RATE_2G5 |
57 HW_ATL_B0_RATE_1G |
58 HW_ATL_B0_RATE_100M,
59 };
60
61 const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
62 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
63 .media_type = AQ_HW_MEDIA_TYPE_TP,
64 .link_speed_msk = HW_ATL_B0_RATE_10G |
65 HW_ATL_B0_RATE_5G |
66 HW_ATL_B0_RATE_2G5 |
67 HW_ATL_B0_RATE_1G |
68 HW_ATL_B0_RATE_100M,
69 };
70
71 const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
72 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
73 .media_type = AQ_HW_MEDIA_TYPE_TP,
74 .link_speed_msk = HW_ATL_B0_RATE_5G |
75 HW_ATL_B0_RATE_2G5 |
76 HW_ATL_B0_RATE_1G |
77 HW_ATL_B0_RATE_100M,
78 };
79
80 const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
81 DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
82 .media_type = AQ_HW_MEDIA_TYPE_TP,
83 .link_speed_msk = HW_ATL_B0_RATE_2G5 |
84 HW_ATL_B0_RATE_1G |
85 HW_ATL_B0_RATE_100M,
86 };
87
hw_atl_b0_hw_reset(struct aq_hw_s * self)88 static int hw_atl_b0_hw_reset(struct aq_hw_s *self)
89 {
90 int err = 0;
91
92 err = hw_atl_utils_soft_reset(self);
93 if (err)
94 return err;
95
96 self->aq_fw_ops->set_state(self, MPI_RESET);
97
98 err = aq_hw_err_from_flags(self);
99
100 return err;
101 }
102
hw_atl_b0_hw_qos_set(struct aq_hw_s * self)103 static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
104 {
105 u32 tc = 0U;
106 u32 buff_size = 0U;
107 unsigned int i_priority = 0U;
108 bool is_rx_flow_control = false;
109
110 /* TPS Descriptor rate init */
111 hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
112 hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
113
114 /* TPS VM init */
115 hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
116
117 /* TPS TC credits init */
118 hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
119 hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
120
121 hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF, 0U);
122 hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, 0x64, 0U);
123 hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, 0x50, 0U);
124 hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, 0x1E, 0U);
125
126 /* Tx buf size */
127 buff_size = HW_ATL_B0_TXBUF_MAX;
128
129 hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, buff_size, tc);
130 hw_atl_tpb_tx_buff_hi_threshold_per_tc_set(self,
131 (buff_size *
132 (1024 / 32U) * 66U) /
133 100U, tc);
134 hw_atl_tpb_tx_buff_lo_threshold_per_tc_set(self,
135 (buff_size *
136 (1024 / 32U) * 50U) /
137 100U, tc);
138
139 /* QoS Rx buf size per TC */
140 tc = 0;
141 is_rx_flow_control = (AQ_NIC_FC_RX & self->aq_nic_cfg->flow_control);
142 buff_size = HW_ATL_B0_RXBUF_MAX;
143
144 hw_atl_rpb_rx_pkt_buff_size_per_tc_set(self, buff_size, tc);
145 hw_atl_rpb_rx_buff_hi_threshold_per_tc_set(self,
146 (buff_size *
147 (1024U / 32U) * 66U) /
148 100U, tc);
149 hw_atl_rpb_rx_buff_lo_threshold_per_tc_set(self,
150 (buff_size *
151 (1024U / 32U) * 50U) /
152 100U, tc);
153 hw_atl_rpb_rx_xoff_en_per_tc_set(self, is_rx_flow_control ? 1U : 0U, tc);
154
155 /* QoS 802.1p priority -> TC mapping */
156 for (i_priority = 8U; i_priority--;)
157 hw_atl_rpf_rpb_user_priority_tc_map_set(self, i_priority, 0U);
158
159 return aq_hw_err_from_flags(self);
160 }
161
hw_atl_b0_hw_rss_hash_set(struct aq_hw_s * self,struct aq_rss_parameters * rss_params)162 static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
163 struct aq_rss_parameters *rss_params)
164 {
165 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
166 int err = 0;
167 unsigned int i = 0U;
168 unsigned int addr = 0U;
169
170 for (i = 10, addr = 0U; i--; ++addr) {
171 u32 key_data = cfg->is_rss ?
172 __swab32(rss_params->hash_secret_key[i]) : 0U;
173 hw_atl_rpf_rss_key_wr_data_set(self, key_data);
174 hw_atl_rpf_rss_key_addr_set(self, addr);
175 hw_atl_rpf_rss_key_wr_en_set(self, 1U);
176 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
177 1000U, 10U);
178 if (err < 0)
179 goto err_exit;
180 }
181
182 err = aq_hw_err_from_flags(self);
183
184 err_exit:
185 return err;
186 }
187
hw_atl_b0_hw_rss_set(struct aq_hw_s * self,struct aq_rss_parameters * rss_params)188 static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
189 struct aq_rss_parameters *rss_params)
190 {
191 u8 *indirection_table = rss_params->indirection_table;
192 u32 i = 0U;
193 u32 num_rss_queues = max(1U, self->aq_nic_cfg->num_rss_queues);
194 int err = 0;
195 u16 bitary[(HW_ATL_B0_RSS_REDIRECTION_MAX *
196 HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
197
198 memset(bitary, 0, sizeof(bitary));
199
200 for (i = HW_ATL_B0_RSS_REDIRECTION_MAX; i--;) {
201 (*(u32 *)(bitary + ((i * 3U) / 16U))) |=
202 ((indirection_table[i] % num_rss_queues) <<
203 ((i * 3U) & 0xFU));
204 }
205
206 for (i = ARRAY_SIZE(bitary); i--;) {
207 hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
208 hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
209 hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
210 AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
211 1000U, 10U);
212 if (err < 0)
213 goto err_exit;
214 }
215
216 err = aq_hw_err_from_flags(self);
217
218 err_exit:
219 return err;
220 }
221
hw_atl_b0_hw_offload_set(struct aq_hw_s * self,struct aq_nic_cfg_s * aq_nic_cfg)222 static int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
223 struct aq_nic_cfg_s *aq_nic_cfg)
224 {
225 unsigned int i;
226
227 /* TX checksums offloads*/
228 hw_atl_tpo_ipv4header_crc_offload_en_set(self, 1);
229 hw_atl_tpo_tcp_udp_crc_offload_en_set(self, 1);
230
231 /* RX checksums offloads*/
232 hw_atl_rpo_ipv4header_crc_offload_en_set(self, 1);
233 hw_atl_rpo_tcp_udp_crc_offload_en_set(self, 1);
234
235 /* LSO offloads*/
236 hw_atl_tdm_large_send_offload_en_set(self, 0xFFFFFFFFU);
237
238 /* LRO offloads */
239 {
240 unsigned int val = (8U < HW_ATL_B0_LRO_RXD_MAX) ? 0x3U :
241 ((4U < HW_ATL_B0_LRO_RXD_MAX) ? 0x2U :
242 ((2U < HW_ATL_B0_LRO_RXD_MAX) ? 0x1U : 0x0));
243
244 for (i = 0; i < HW_ATL_B0_RINGS_MAX; i++)
245 hw_atl_rpo_lro_max_num_of_descriptors_set(self, val, i);
246
247 hw_atl_rpo_lro_time_base_divider_set(self, 0x61AU);
248 hw_atl_rpo_lro_inactive_interval_set(self, 0);
249 hw_atl_rpo_lro_max_coalescing_interval_set(self, 2);
250
251 hw_atl_rpo_lro_qsessions_lim_set(self, 1U);
252
253 hw_atl_rpo_lro_total_desc_lim_set(self, 2U);
254
255 hw_atl_rpo_lro_patch_optimization_en_set(self, 0U);
256
257 hw_atl_rpo_lro_min_pay_of_first_pkt_set(self, 10U);
258
259 hw_atl_rpo_lro_pkt_lim_set(self, 1U);
260
261 hw_atl_rpo_lro_en_set(self,
262 aq_nic_cfg->is_lro ? 0xFFFFFFFFU : 0U);
263 }
264 return aq_hw_err_from_flags(self);
265 }
266
hw_atl_b0_hw_init_tx_path(struct aq_hw_s * self)267 static int hw_atl_b0_hw_init_tx_path(struct aq_hw_s *self)
268 {
269 hw_atl_thm_lso_tcp_flag_of_first_pkt_set(self, 0x0FF6U);
270 hw_atl_thm_lso_tcp_flag_of_middle_pkt_set(self, 0x0FF6U);
271 hw_atl_thm_lso_tcp_flag_of_last_pkt_set(self, 0x0F7FU);
272
273 /* Tx interrupts */
274 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
275
276 /* misc */
277 aq_hw_write_reg(self, 0x00007040U, IS_CHIP_FEATURE(TPO2) ?
278 0x00010000U : 0x00000000U);
279 hw_atl_tdm_tx_dca_en_set(self, 0U);
280 hw_atl_tdm_tx_dca_mode_set(self, 0U);
281
282 hw_atl_tpb_tx_path_scp_ins_en_set(self, 1U);
283
284 return aq_hw_err_from_flags(self);
285 }
286
hw_atl_b0_hw_init_rx_path(struct aq_hw_s * self)287 static int hw_atl_b0_hw_init_rx_path(struct aq_hw_s *self)
288 {
289 struct aq_nic_cfg_s *cfg = self->aq_nic_cfg;
290 int i;
291
292 /* Rx TC/RSS number config */
293 hw_atl_rpb_rpf_rx_traf_class_mode_set(self, 1U);
294
295 /* Rx flow control */
296 hw_atl_rpb_rx_flow_ctl_mode_set(self, 1U);
297
298 /* RSS Ring selection */
299 hw_atl_reg_rx_flr_rss_control1set(self, cfg->is_rss ?
300 0xB3333333U : 0x00000000U);
301
302 /* Multicast filters */
303 for (i = HW_ATL_B0_MAC_MAX; i--;) {
304 hw_atl_rpfl2_uc_flr_en_set(self, (i == 0U) ? 1U : 0U, i);
305 hw_atl_rpfl2unicast_flr_act_set(self, 1U, i);
306 }
307
308 hw_atl_reg_rx_flr_mcst_flr_msk_set(self, 0x00000000U);
309 hw_atl_reg_rx_flr_mcst_flr_set(self, 0x00010FFFU, 0U);
310
311 /* Vlan filters */
312 hw_atl_rpf_vlan_outer_etht_set(self, 0x88A8U);
313 hw_atl_rpf_vlan_inner_etht_set(self, 0x8100U);
314
315 if (cfg->vlan_id) {
316 hw_atl_rpf_vlan_flr_act_set(self, 1U, 0U);
317 hw_atl_rpf_vlan_id_flr_set(self, 0U, 0U);
318 hw_atl_rpf_vlan_flr_en_set(self, 0U, 0U);
319
320 hw_atl_rpf_vlan_accept_untagged_packets_set(self, 1U);
321 hw_atl_rpf_vlan_untagged_act_set(self, 1U);
322
323 hw_atl_rpf_vlan_flr_act_set(self, 1U, 1U);
324 hw_atl_rpf_vlan_id_flr_set(self, cfg->vlan_id, 0U);
325 hw_atl_rpf_vlan_flr_en_set(self, 1U, 1U);
326 } else {
327 hw_atl_rpf_vlan_prom_mode_en_set(self, 1);
328 }
329
330 /* Rx Interrupts */
331 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
332
333 /* misc */
334 aq_hw_write_reg(self, 0x00005040U,
335 IS_CHIP_FEATURE(RPF2) ? 0x000F0000U : 0x00000000U);
336
337 hw_atl_rpfl2broadcast_flr_act_set(self, 1U);
338 hw_atl_rpfl2broadcast_count_threshold_set(self, 0xFFFFU & (~0U / 256U));
339
340 hw_atl_rdm_rx_dca_en_set(self, 0U);
341 hw_atl_rdm_rx_dca_mode_set(self, 0U);
342
343 return aq_hw_err_from_flags(self);
344 }
345
hw_atl_b0_hw_mac_addr_set(struct aq_hw_s * self,u8 * mac_addr)346 static int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr)
347 {
348 int err = 0;
349 unsigned int h = 0U;
350 unsigned int l = 0U;
351
352 if (!mac_addr) {
353 err = -EINVAL;
354 goto err_exit;
355 }
356 h = (mac_addr[0] << 8) | (mac_addr[1]);
357 l = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
358 (mac_addr[4] << 8) | mac_addr[5];
359
360 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC);
361 hw_atl_rpfl2unicast_dest_addresslsw_set(self, l, HW_ATL_B0_MAC);
362 hw_atl_rpfl2unicast_dest_addressmsw_set(self, h, HW_ATL_B0_MAC);
363 hw_atl_rpfl2_uc_flr_en_set(self, 1U, HW_ATL_B0_MAC);
364
365 err = aq_hw_err_from_flags(self);
366
367 err_exit:
368 return err;
369 }
370
hw_atl_b0_hw_init(struct aq_hw_s * self,u8 * mac_addr)371 static int hw_atl_b0_hw_init(struct aq_hw_s *self, u8 *mac_addr)
372 {
373 static u32 aq_hw_atl_igcr_table_[4][2] = {
374 { 0x20000000U, 0x20000000U }, /* AQ_IRQ_INVALID */
375 { 0x20000080U, 0x20000080U }, /* AQ_IRQ_LEGACY */
376 { 0x20000021U, 0x20000025U }, /* AQ_IRQ_MSI */
377 { 0x20000022U, 0x20000026U } /* AQ_IRQ_MSIX */
378 };
379
380 int err = 0;
381 u32 val;
382
383 struct aq_nic_cfg_s *aq_nic_cfg = self->aq_nic_cfg;
384
385 hw_atl_b0_hw_init_tx_path(self);
386 hw_atl_b0_hw_init_rx_path(self);
387
388 hw_atl_b0_hw_mac_addr_set(self, mac_addr);
389
390 self->aq_fw_ops->set_link_speed(self, aq_nic_cfg->link_speed_msk);
391 self->aq_fw_ops->set_state(self, MPI_INIT);
392
393 hw_atl_b0_hw_qos_set(self);
394 hw_atl_b0_hw_rss_set(self, &aq_nic_cfg->aq_rss);
395 hw_atl_b0_hw_rss_hash_set(self, &aq_nic_cfg->aq_rss);
396
397 /* Force limit MRRS on RDM/TDM to 2K */
398 val = aq_hw_read_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR);
399 aq_hw_write_reg(self, HW_ATL_PCI_REG_CONTROL6_ADR,
400 (val & ~0x707) | 0x404);
401
402 /* TX DMA total request limit. B0 hardware is not capable to
403 * handle more than (8K-MRRS) incoming DMA data.
404 * Value 24 in 256byte units
405 */
406 aq_hw_write_reg(self, HW_ATL_TX_DMA_TOTAL_REQ_LIMIT_ADR, 24);
407
408 /* Reset link status and read out initial hardware counters */
409 self->aq_link_status.mbps = 0;
410 self->aq_fw_ops->update_stats(self);
411
412 err = aq_hw_err_from_flags(self);
413 if (err < 0)
414 goto err_exit;
415
416 /* Interrupts */
417 hw_atl_reg_irq_glb_ctl_set(self,
418 aq_hw_atl_igcr_table_[aq_nic_cfg->irq_type]
419 [(aq_nic_cfg->vecs > 1U) ?
420 1 : 0]);
421
422 hw_atl_itr_irq_auto_masklsw_set(self, aq_nic_cfg->aq_hw_caps->irq_mask);
423
424 /* Interrupts */
425 hw_atl_reg_gen_irq_map_set(self,
426 ((HW_ATL_B0_ERR_INT << 0x18) | (1U << 0x1F)) |
427 ((HW_ATL_B0_ERR_INT << 0x10) | (1U << 0x17)), 0U);
428
429 hw_atl_b0_hw_offload_set(self, aq_nic_cfg);
430
431 err_exit:
432 return err;
433 }
434
hw_atl_b0_hw_ring_tx_start(struct aq_hw_s * self,struct aq_ring_s * ring)435 static int hw_atl_b0_hw_ring_tx_start(struct aq_hw_s *self,
436 struct aq_ring_s *ring)
437 {
438 hw_atl_tdm_tx_desc_en_set(self, 1, ring->idx);
439 return aq_hw_err_from_flags(self);
440 }
441
hw_atl_b0_hw_ring_rx_start(struct aq_hw_s * self,struct aq_ring_s * ring)442 static int hw_atl_b0_hw_ring_rx_start(struct aq_hw_s *self,
443 struct aq_ring_s *ring)
444 {
445 hw_atl_rdm_rx_desc_en_set(self, 1, ring->idx);
446 return aq_hw_err_from_flags(self);
447 }
448
hw_atl_b0_hw_start(struct aq_hw_s * self)449 static int hw_atl_b0_hw_start(struct aq_hw_s *self)
450 {
451 hw_atl_tpb_tx_buff_en_set(self, 1);
452 hw_atl_rpb_rx_buff_en_set(self, 1);
453 return aq_hw_err_from_flags(self);
454 }
455
hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s * self,struct aq_ring_s * ring)456 static int hw_atl_b0_hw_tx_ring_tail_update(struct aq_hw_s *self,
457 struct aq_ring_s *ring)
458 {
459 hw_atl_reg_tx_dma_desc_tail_ptr_set(self, ring->sw_tail, ring->idx);
460 return 0;
461 }
462
hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s * self,struct aq_ring_s * ring,unsigned int frags)463 static int hw_atl_b0_hw_ring_tx_xmit(struct aq_hw_s *self,
464 struct aq_ring_s *ring,
465 unsigned int frags)
466 {
467 struct aq_ring_buff_s *buff = NULL;
468 struct hw_atl_txd_s *txd = NULL;
469 unsigned int buff_pa_len = 0U;
470 unsigned int pkt_len = 0U;
471 unsigned int frag_count = 0U;
472 bool is_gso = false;
473
474 buff = &ring->buff_ring[ring->sw_tail];
475 pkt_len = (buff->is_eop && buff->is_sop) ? buff->len : buff->len_pkt;
476
477 for (frag_count = 0; frag_count < frags; frag_count++) {
478 txd = (struct hw_atl_txd_s *)&ring->dx_ring[ring->sw_tail *
479 HW_ATL_B0_TXD_SIZE];
480 txd->ctl = 0;
481 txd->ctl2 = 0;
482 txd->buf_addr = 0;
483
484 buff = &ring->buff_ring[ring->sw_tail];
485
486 if (buff->is_txc) {
487 txd->ctl |= (buff->len_l3 << 31) |
488 (buff->len_l2 << 24) |
489 HW_ATL_B0_TXD_CTL_CMD_TCP |
490 HW_ATL_B0_TXD_CTL_DESC_TYPE_TXC;
491 txd->ctl2 |= (buff->mss << 16) |
492 (buff->len_l4 << 8) |
493 (buff->len_l3 >> 1);
494
495 pkt_len -= (buff->len_l4 +
496 buff->len_l3 +
497 buff->len_l2);
498 is_gso = true;
499
500 if (buff->is_ipv6)
501 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPV6;
502 } else {
503 buff_pa_len = buff->len;
504
505 txd->buf_addr = buff->pa;
506 txd->ctl |= (HW_ATL_B0_TXD_CTL_BLEN &
507 ((u32)buff_pa_len << 4));
508 txd->ctl |= HW_ATL_B0_TXD_CTL_DESC_TYPE_TXD;
509 /* PAY_LEN */
510 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_LEN & (pkt_len << 14);
511
512 if (is_gso) {
513 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_LSO;
514 txd->ctl2 |= HW_ATL_B0_TXD_CTL2_CTX_EN;
515 }
516
517 /* Tx checksum offloads */
518 if (buff->is_ip_cso)
519 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_IPCSO;
520
521 if (buff->is_udp_cso || buff->is_tcp_cso)
522 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_TUCSO;
523
524 if (unlikely(buff->is_eop)) {
525 txd->ctl |= HW_ATL_B0_TXD_CTL_EOP;
526 txd->ctl |= HW_ATL_B0_TXD_CTL_CMD_WB;
527 is_gso = false;
528 }
529 }
530
531 ring->sw_tail = aq_ring_next_dx(ring, ring->sw_tail);
532 }
533
534 hw_atl_b0_hw_tx_ring_tail_update(self, ring);
535 return aq_hw_err_from_flags(self);
536 }
537
hw_atl_b0_hw_ring_rx_init(struct aq_hw_s * self,struct aq_ring_s * aq_ring,struct aq_ring_param_s * aq_ring_param)538 static int hw_atl_b0_hw_ring_rx_init(struct aq_hw_s *self,
539 struct aq_ring_s *aq_ring,
540 struct aq_ring_param_s *aq_ring_param)
541 {
542 u32 dma_desc_addr_lsw = (u32)aq_ring->dx_ring_pa;
543 u32 dma_desc_addr_msw = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
544
545 hw_atl_rdm_rx_desc_en_set(self, false, aq_ring->idx);
546
547 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
548
549 hw_atl_reg_rx_dma_desc_base_addresslswset(self, dma_desc_addr_lsw,
550 aq_ring->idx);
551
552 hw_atl_reg_rx_dma_desc_base_addressmswset(self,
553 dma_desc_addr_msw, aq_ring->idx);
554
555 hw_atl_rdm_rx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
556
557 hw_atl_rdm_rx_desc_data_buff_size_set(self,
558 AQ_CFG_RX_FRAME_MAX / 1024U,
559 aq_ring->idx);
560
561 hw_atl_rdm_rx_desc_head_buff_size_set(self, 0U, aq_ring->idx);
562 hw_atl_rdm_rx_desc_head_splitting_set(self, 0U, aq_ring->idx);
563 hw_atl_rpo_rx_desc_vlan_stripping_set(self, 0U, aq_ring->idx);
564
565 /* Rx ring set mode */
566
567 /* Mapping interrupt vector */
568 hw_atl_itr_irq_map_rx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
569 hw_atl_itr_irq_map_en_rx_set(self, true, aq_ring->idx);
570
571 hw_atl_rdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
572 hw_atl_rdm_rx_desc_dca_en_set(self, 0U, aq_ring->idx);
573 hw_atl_rdm_rx_head_dca_en_set(self, 0U, aq_ring->idx);
574 hw_atl_rdm_rx_pld_dca_en_set(self, 0U, aq_ring->idx);
575
576 return aq_hw_err_from_flags(self);
577 }
578
hw_atl_b0_hw_ring_tx_init(struct aq_hw_s * self,struct aq_ring_s * aq_ring,struct aq_ring_param_s * aq_ring_param)579 static int hw_atl_b0_hw_ring_tx_init(struct aq_hw_s *self,
580 struct aq_ring_s *aq_ring,
581 struct aq_ring_param_s *aq_ring_param)
582 {
583 u32 dma_desc_lsw_addr = (u32)aq_ring->dx_ring_pa;
584 u32 dma_desc_msw_addr = (u32)(((u64)aq_ring->dx_ring_pa) >> 32);
585
586 hw_atl_reg_tx_dma_desc_base_addresslswset(self, dma_desc_lsw_addr,
587 aq_ring->idx);
588
589 hw_atl_reg_tx_dma_desc_base_addressmswset(self, dma_desc_msw_addr,
590 aq_ring->idx);
591
592 hw_atl_tdm_tx_desc_len_set(self, aq_ring->size / 8U, aq_ring->idx);
593
594 hw_atl_b0_hw_tx_ring_tail_update(self, aq_ring);
595
596 /* Set Tx threshold */
597 hw_atl_tdm_tx_desc_wr_wb_threshold_set(self, 0U, aq_ring->idx);
598
599 /* Mapping interrupt vector */
600 hw_atl_itr_irq_map_tx_set(self, aq_ring_param->vec_idx, aq_ring->idx);
601 hw_atl_itr_irq_map_en_tx_set(self, true, aq_ring->idx);
602
603 hw_atl_tdm_cpu_id_set(self, aq_ring_param->cpu, aq_ring->idx);
604 hw_atl_tdm_tx_desc_dca_en_set(self, 0U, aq_ring->idx);
605
606 return aq_hw_err_from_flags(self);
607 }
608
hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s * self,struct aq_ring_s * ring,unsigned int sw_tail_old)609 static int hw_atl_b0_hw_ring_rx_fill(struct aq_hw_s *self,
610 struct aq_ring_s *ring,
611 unsigned int sw_tail_old)
612 {
613 for (; sw_tail_old != ring->sw_tail;
614 sw_tail_old = aq_ring_next_dx(ring, sw_tail_old)) {
615 struct hw_atl_rxd_s *rxd =
616 (struct hw_atl_rxd_s *)&ring->dx_ring[sw_tail_old *
617 HW_ATL_B0_RXD_SIZE];
618
619 struct aq_ring_buff_s *buff = &ring->buff_ring[sw_tail_old];
620
621 rxd->buf_addr = buff->pa;
622 rxd->hdr_addr = 0U;
623 }
624
625 hw_atl_reg_rx_dma_desc_tail_ptr_set(self, sw_tail_old, ring->idx);
626
627 return aq_hw_err_from_flags(self);
628 }
629
hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s * self,struct aq_ring_s * ring)630 static int hw_atl_b0_hw_ring_tx_head_update(struct aq_hw_s *self,
631 struct aq_ring_s *ring)
632 {
633 int err = 0;
634 unsigned int hw_head_ = hw_atl_tdm_tx_desc_head_ptr_get(self, ring->idx);
635
636 if (aq_utils_obj_test(&self->flags, AQ_HW_FLAG_ERR_UNPLUG)) {
637 err = -ENXIO;
638 goto err_exit;
639 }
640 ring->hw_head = hw_head_;
641 err = aq_hw_err_from_flags(self);
642
643 err_exit:
644 return err;
645 }
646
hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s * self,struct aq_ring_s * ring)647 static int hw_atl_b0_hw_ring_rx_receive(struct aq_hw_s *self,
648 struct aq_ring_s *ring)
649 {
650 struct device *ndev = aq_nic_get_dev(ring->aq_nic);
651
652 for (; ring->hw_head != ring->sw_tail;
653 ring->hw_head = aq_ring_next_dx(ring, ring->hw_head)) {
654 struct aq_ring_buff_s *buff = NULL;
655 struct hw_atl_rxd_wb_s *rxd_wb = (struct hw_atl_rxd_wb_s *)
656 &ring->dx_ring[ring->hw_head * HW_ATL_B0_RXD_SIZE];
657
658 unsigned int is_err = 1U;
659 unsigned int is_rx_check_sum_enabled = 0U;
660 unsigned int pkt_type = 0U;
661
662 if (!(rxd_wb->status & 0x1U)) { /* RxD is not done */
663 break;
664 }
665
666 buff = &ring->buff_ring[ring->hw_head];
667
668 is_err = (0x0000003CU & rxd_wb->status);
669
670 is_rx_check_sum_enabled = (rxd_wb->type) & (0x3U << 19);
671 is_err &= ~0x20U; /* exclude validity bit */
672
673 pkt_type = 0xFFU & (rxd_wb->type >> 4);
674
675 if (is_rx_check_sum_enabled) {
676 if (0x0U == (pkt_type & 0x3U))
677 buff->is_ip_cso = (is_err & 0x08U) ? 0U : 1U;
678
679 if (0x4U == (pkt_type & 0x1CU))
680 buff->is_udp_cso = buff->is_cso_err ? 0U : 1U;
681 else if (0x0U == (pkt_type & 0x1CU))
682 buff->is_tcp_cso = buff->is_cso_err ? 0U : 1U;
683
684 /* Checksum offload workaround for small packets */
685 if (rxd_wb->pkt_len <= 60) {
686 buff->is_ip_cso = 0U;
687 buff->is_cso_err = 0U;
688 }
689 }
690
691 is_err &= ~0x18U;
692
693 dma_unmap_page(ndev, buff->pa, buff->len, DMA_FROM_DEVICE);
694
695 if (is_err || rxd_wb->type & 0x1000U) {
696 /* status error or DMA error */
697 buff->is_error = 1U;
698 } else {
699 if (self->aq_nic_cfg->is_rss) {
700 /* last 4 byte */
701 u16 rss_type = rxd_wb->type & 0xFU;
702
703 if (rss_type && rss_type < 0x8U) {
704 buff->is_hash_l4 = (rss_type == 0x4 ||
705 rss_type == 0x5);
706 buff->rss_hash = rxd_wb->rss_hash;
707 }
708 }
709
710 if (HW_ATL_B0_RXD_WB_STAT2_EOP & rxd_wb->status) {
711 buff->len = rxd_wb->pkt_len %
712 AQ_CFG_RX_FRAME_MAX;
713 buff->len = buff->len ?
714 buff->len : AQ_CFG_RX_FRAME_MAX;
715 buff->next = 0U;
716 buff->is_eop = 1U;
717 } else {
718 if (HW_ATL_B0_RXD_WB_STAT2_RSCCNT &
719 rxd_wb->status) {
720 /* LRO */
721 buff->next = rxd_wb->next_desc_ptr;
722 ++ring->stats.rx.lro_packets;
723 } else {
724 /* jumbo */
725 buff->next =
726 aq_ring_next_dx(ring,
727 ring->hw_head);
728 ++ring->stats.rx.jumbo_packets;
729 }
730 }
731 }
732 }
733
734 return aq_hw_err_from_flags(self);
735 }
736
hw_atl_b0_hw_irq_enable(struct aq_hw_s * self,u64 mask)737 static int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask)
738 {
739 hw_atl_itr_irq_msk_setlsw_set(self, LODWORD(mask));
740 return aq_hw_err_from_flags(self);
741 }
742
hw_atl_b0_hw_irq_disable(struct aq_hw_s * self,u64 mask)743 static int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask)
744 {
745 hw_atl_itr_irq_msk_clearlsw_set(self, LODWORD(mask));
746 hw_atl_itr_irq_status_clearlsw_set(self, LODWORD(mask));
747
748 atomic_inc(&self->dpc);
749 return aq_hw_err_from_flags(self);
750 }
751
hw_atl_b0_hw_irq_read(struct aq_hw_s * self,u64 * mask)752 static int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask)
753 {
754 *mask = hw_atl_itr_irq_statuslsw_get(self);
755 return aq_hw_err_from_flags(self);
756 }
757
758 #define IS_FILTER_ENABLED(_F_) ((packet_filter & (_F_)) ? 1U : 0U)
759
hw_atl_b0_hw_packet_filter_set(struct aq_hw_s * self,unsigned int packet_filter)760 static int hw_atl_b0_hw_packet_filter_set(struct aq_hw_s *self,
761 unsigned int packet_filter)
762 {
763 unsigned int i = 0U;
764
765 hw_atl_rpfl2promiscuous_mode_en_set(self, IS_FILTER_ENABLED(IFF_PROMISC));
766 hw_atl_rpfl2multicast_flr_en_set(self,
767 IS_FILTER_ENABLED(IFF_ALLMULTI), 0);
768
769 hw_atl_rpfl2_accept_all_mc_packets_set(self,
770 IS_FILTER_ENABLED(IFF_ALLMULTI));
771
772 hw_atl_rpfl2broadcast_en_set(self, IS_FILTER_ENABLED(IFF_BROADCAST));
773
774 self->aq_nic_cfg->is_mc_list_enabled = IS_FILTER_ENABLED(IFF_MULTICAST);
775
776 for (i = HW_ATL_B0_MAC_MIN; i < HW_ATL_B0_MAC_MAX; ++i)
777 hw_atl_rpfl2_uc_flr_en_set(self,
778 (self->aq_nic_cfg->is_mc_list_enabled &&
779 (i <= self->aq_nic_cfg->mc_list_count)) ?
780 1U : 0U, i);
781
782 return aq_hw_err_from_flags(self);
783 }
784
785 #undef IS_FILTER_ENABLED
786
hw_atl_b0_hw_multicast_list_set(struct aq_hw_s * self,u8 ar_mac[AQ_HW_MULTICAST_ADDRESS_MAX][ETH_ALEN],u32 count)787 static int hw_atl_b0_hw_multicast_list_set(struct aq_hw_s *self,
788 u8 ar_mac
789 [AQ_HW_MULTICAST_ADDRESS_MAX]
790 [ETH_ALEN],
791 u32 count)
792 {
793 int err = 0;
794
795 if (count > (HW_ATL_B0_MAC_MAX - HW_ATL_B0_MAC_MIN)) {
796 err = -EBADRQC;
797 goto err_exit;
798 }
799 for (self->aq_nic_cfg->mc_list_count = 0U;
800 self->aq_nic_cfg->mc_list_count < count;
801 ++self->aq_nic_cfg->mc_list_count) {
802 u32 i = self->aq_nic_cfg->mc_list_count;
803 u32 h = (ar_mac[i][0] << 8) | (ar_mac[i][1]);
804 u32 l = (ar_mac[i][2] << 24) | (ar_mac[i][3] << 16) |
805 (ar_mac[i][4] << 8) | ar_mac[i][5];
806
807 hw_atl_rpfl2_uc_flr_en_set(self, 0U, HW_ATL_B0_MAC_MIN + i);
808
809 hw_atl_rpfl2unicast_dest_addresslsw_set(self,
810 l, HW_ATL_B0_MAC_MIN + i);
811
812 hw_atl_rpfl2unicast_dest_addressmsw_set(self,
813 h, HW_ATL_B0_MAC_MIN + i);
814
815 hw_atl_rpfl2_uc_flr_en_set(self,
816 (self->aq_nic_cfg->is_mc_list_enabled),
817 HW_ATL_B0_MAC_MIN + i);
818 }
819
820 err = aq_hw_err_from_flags(self);
821
822 err_exit:
823 return err;
824 }
825
hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s * self)826 static int hw_atl_b0_hw_interrupt_moderation_set(struct aq_hw_s *self)
827 {
828 unsigned int i = 0U;
829 u32 itr_tx = 2U;
830 u32 itr_rx = 2U;
831
832 switch (self->aq_nic_cfg->itr) {
833 case AQ_CFG_INTERRUPT_MODERATION_ON:
834 case AQ_CFG_INTERRUPT_MODERATION_AUTO:
835 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 0U);
836 hw_atl_tdm_tdm_intr_moder_en_set(self, 1U);
837 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 0U);
838 hw_atl_rdm_rdm_intr_moder_en_set(self, 1U);
839
840 if (self->aq_nic_cfg->itr == AQ_CFG_INTERRUPT_MODERATION_ON) {
841 /* HW timers are in 2us units */
842 int tx_max_timer = self->aq_nic_cfg->tx_itr / 2;
843 int tx_min_timer = tx_max_timer / 2;
844
845 int rx_max_timer = self->aq_nic_cfg->rx_itr / 2;
846 int rx_min_timer = rx_max_timer / 2;
847
848 tx_max_timer = min(HW_ATL_INTR_MODER_MAX, tx_max_timer);
849 tx_min_timer = min(HW_ATL_INTR_MODER_MIN, tx_min_timer);
850 rx_max_timer = min(HW_ATL_INTR_MODER_MAX, rx_max_timer);
851 rx_min_timer = min(HW_ATL_INTR_MODER_MIN, rx_min_timer);
852
853 itr_tx |= tx_min_timer << 0x8U;
854 itr_tx |= tx_max_timer << 0x10U;
855 itr_rx |= rx_min_timer << 0x8U;
856 itr_rx |= rx_max_timer << 0x10U;
857 } else {
858 static unsigned int hw_atl_b0_timers_table_tx_[][2] = {
859 {0xfU, 0xffU}, /* 10Gbit */
860 {0xfU, 0x1ffU}, /* 5Gbit */
861 {0xfU, 0x1ffU}, /* 5Gbit 5GS */
862 {0xfU, 0x1ffU}, /* 2.5Gbit */
863 {0xfU, 0x1ffU}, /* 1Gbit */
864 {0xfU, 0x1ffU}, /* 100Mbit */
865 };
866
867 static unsigned int hw_atl_b0_timers_table_rx_[][2] = {
868 {0x6U, 0x38U},/* 10Gbit */
869 {0xCU, 0x70U},/* 5Gbit */
870 {0xCU, 0x70U},/* 5Gbit 5GS */
871 {0x18U, 0xE0U},/* 2.5Gbit */
872 {0x30U, 0x80U},/* 1Gbit */
873 {0x4U, 0x50U},/* 100Mbit */
874 };
875
876 unsigned int speed_index =
877 hw_atl_utils_mbps_2_speed_index(
878 self->aq_link_status.mbps);
879
880 /* Update user visible ITR settings */
881 self->aq_nic_cfg->tx_itr = hw_atl_b0_timers_table_tx_
882 [speed_index][1] * 2;
883 self->aq_nic_cfg->rx_itr = hw_atl_b0_timers_table_rx_
884 [speed_index][1] * 2;
885
886 itr_tx |= hw_atl_b0_timers_table_tx_
887 [speed_index][0] << 0x8U;
888 itr_tx |= hw_atl_b0_timers_table_tx_
889 [speed_index][1] << 0x10U;
890
891 itr_rx |= hw_atl_b0_timers_table_rx_
892 [speed_index][0] << 0x8U;
893 itr_rx |= hw_atl_b0_timers_table_rx_
894 [speed_index][1] << 0x10U;
895 }
896 break;
897 case AQ_CFG_INTERRUPT_MODERATION_OFF:
898 hw_atl_tdm_tx_desc_wr_wb_irq_en_set(self, 1U);
899 hw_atl_tdm_tdm_intr_moder_en_set(self, 0U);
900 hw_atl_rdm_rx_desc_wr_wb_irq_en_set(self, 1U);
901 hw_atl_rdm_rdm_intr_moder_en_set(self, 0U);
902 itr_tx = 0U;
903 itr_rx = 0U;
904 break;
905 }
906
907 for (i = HW_ATL_B0_RINGS_MAX; i--;) {
908 hw_atl_reg_tx_intr_moder_ctrl_set(self, itr_tx, i);
909 hw_atl_reg_rx_intr_moder_ctrl_set(self, itr_rx, i);
910 }
911
912 return aq_hw_err_from_flags(self);
913 }
914
hw_atl_b0_hw_stop(struct aq_hw_s * self)915 static int hw_atl_b0_hw_stop(struct aq_hw_s *self)
916 {
917 hw_atl_b0_hw_irq_disable(self, HW_ATL_B0_INT_MASK);
918 return aq_hw_err_from_flags(self);
919 }
920
hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s * self,struct aq_ring_s * ring)921 static int hw_atl_b0_hw_ring_tx_stop(struct aq_hw_s *self,
922 struct aq_ring_s *ring)
923 {
924 hw_atl_tdm_tx_desc_en_set(self, 0U, ring->idx);
925 return aq_hw_err_from_flags(self);
926 }
927
hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s * self,struct aq_ring_s * ring)928 static int hw_atl_b0_hw_ring_rx_stop(struct aq_hw_s *self,
929 struct aq_ring_s *ring)
930 {
931 hw_atl_rdm_rx_desc_en_set(self, 0U, ring->idx);
932 return aq_hw_err_from_flags(self);
933 }
934
935 const struct aq_hw_ops hw_atl_ops_b0 = {
936 .hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
937 .hw_init = hw_atl_b0_hw_init,
938 .hw_set_power = hw_atl_utils_hw_set_power,
939 .hw_reset = hw_atl_b0_hw_reset,
940 .hw_start = hw_atl_b0_hw_start,
941 .hw_ring_tx_start = hw_atl_b0_hw_ring_tx_start,
942 .hw_ring_tx_stop = hw_atl_b0_hw_ring_tx_stop,
943 .hw_ring_rx_start = hw_atl_b0_hw_ring_rx_start,
944 .hw_ring_rx_stop = hw_atl_b0_hw_ring_rx_stop,
945 .hw_stop = hw_atl_b0_hw_stop,
946
947 .hw_ring_tx_xmit = hw_atl_b0_hw_ring_tx_xmit,
948 .hw_ring_tx_head_update = hw_atl_b0_hw_ring_tx_head_update,
949
950 .hw_ring_rx_receive = hw_atl_b0_hw_ring_rx_receive,
951 .hw_ring_rx_fill = hw_atl_b0_hw_ring_rx_fill,
952
953 .hw_irq_enable = hw_atl_b0_hw_irq_enable,
954 .hw_irq_disable = hw_atl_b0_hw_irq_disable,
955 .hw_irq_read = hw_atl_b0_hw_irq_read,
956
957 .hw_ring_rx_init = hw_atl_b0_hw_ring_rx_init,
958 .hw_ring_tx_init = hw_atl_b0_hw_ring_tx_init,
959 .hw_packet_filter_set = hw_atl_b0_hw_packet_filter_set,
960 .hw_multicast_list_set = hw_atl_b0_hw_multicast_list_set,
961 .hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
962 .hw_rss_set = hw_atl_b0_hw_rss_set,
963 .hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
964 .hw_get_regs = hw_atl_utils_hw_get_regs,
965 .hw_get_hw_stats = hw_atl_utils_get_hw_stats,
966 .hw_get_fw_version = hw_atl_utils_get_fw_version,
967 };
968
