1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __KVM_X86_VMX_H
3 #define __KVM_X86_VMX_H
4
5 #include <linux/kvm_host.h>
6
7 #include <asm/kvm.h>
8 #include <asm/intel_pt.h>
9 #include <asm/perf_event.h>
10
11 #include "capabilities.h"
12 #include "../kvm_cache_regs.h"
13 #include "posted_intr.h"
14 #include "vmcs.h"
15 #include "vmx_ops.h"
16 #include "../cpuid.h"
17 #include "run_flags.h"
18
19 #define MSR_TYPE_R 1
20 #define MSR_TYPE_W 2
21 #define MSR_TYPE_RW 3
22
23 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
24
25 #ifdef CONFIG_X86_64
26 #define MAX_NR_USER_RETURN_MSRS 7
27 #else
28 #define MAX_NR_USER_RETURN_MSRS 4
29 #endif
30
31 #define MAX_NR_LOADSTORE_MSRS 8
32
33 struct vmx_msrs {
34 unsigned int nr;
35 struct vmx_msr_entry val[MAX_NR_LOADSTORE_MSRS];
36 };
37
38 struct vmx_uret_msr {
39 bool load_into_hardware;
40 u64 data;
41 u64 mask;
42 };
43
44 enum segment_cache_field {
45 SEG_FIELD_SEL = 0,
46 SEG_FIELD_BASE = 1,
47 SEG_FIELD_LIMIT = 2,
48 SEG_FIELD_AR = 3,
49
50 SEG_FIELD_NR = 4
51 };
52
53 #define RTIT_ADDR_RANGE 4
54
55 struct pt_ctx {
56 u64 ctl;
57 u64 status;
58 u64 output_base;
59 u64 output_mask;
60 u64 cr3_match;
61 u64 addr_a[RTIT_ADDR_RANGE];
62 u64 addr_b[RTIT_ADDR_RANGE];
63 };
64
65 struct pt_desc {
66 u64 ctl_bitmask;
67 u32 num_address_ranges;
68 u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
69 struct pt_ctx host;
70 struct pt_ctx guest;
71 };
72
73 union vmx_exit_reason {
74 struct {
75 u32 basic : 16;
76 u32 reserved16 : 1;
77 u32 reserved17 : 1;
78 u32 reserved18 : 1;
79 u32 reserved19 : 1;
80 u32 reserved20 : 1;
81 u32 reserved21 : 1;
82 u32 reserved22 : 1;
83 u32 reserved23 : 1;
84 u32 reserved24 : 1;
85 u32 reserved25 : 1;
86 u32 bus_lock_detected : 1;
87 u32 enclave_mode : 1;
88 u32 smi_pending_mtf : 1;
89 u32 smi_from_vmx_root : 1;
90 u32 reserved30 : 1;
91 u32 failed_vmentry : 1;
92 };
93 u32 full;
94 };
95
intel_pmu_has_perf_global_ctrl(struct kvm_pmu * pmu)96 static inline bool intel_pmu_has_perf_global_ctrl(struct kvm_pmu *pmu)
97 {
98 /*
99 * Architecturally, Intel's SDM states that IA32_PERF_GLOBAL_CTRL is
100 * supported if "CPUID.0AH: EAX[7:0] > 0", i.e. if the PMU version is
101 * greater than zero. However, KVM only exposes and emulates the MSR
102 * to/for the guest if the guest PMU supports at least "Architectural
103 * Performance Monitoring Version 2".
104 */
105 return pmu->version > 1;
106 }
107
108 struct lbr_desc {
109 /* Basic info about guest LBR records. */
110 struct x86_pmu_lbr records;
111
112 /*
113 * Emulate LBR feature via passthrough LBR registers when the
114 * per-vcpu guest LBR event is scheduled on the current pcpu.
115 *
116 * The records may be inaccurate if the host reclaims the LBR.
117 */
118 struct perf_event *event;
119
120 /* True if LBRs are marked as not intercepted in the MSR bitmap */
121 bool msr_passthrough;
122 };
123
124 /*
125 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
126 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
127 */
128 struct nested_vmx {
129 /* Has the level1 guest done vmxon? */
130 bool vmxon;
131 gpa_t vmxon_ptr;
132 bool pml_full;
133
134 /* The guest-physical address of the current VMCS L1 keeps for L2 */
135 gpa_t current_vmptr;
136 /*
137 * Cache of the guest's VMCS, existing outside of guest memory.
138 * Loaded from guest memory during VMPTRLD. Flushed to guest
139 * memory during VMCLEAR and VMPTRLD.
140 */
141 struct vmcs12 *cached_vmcs12;
142 /*
143 * Cache of the guest's shadow VMCS, existing outside of guest
144 * memory. Loaded from guest memory during VM entry. Flushed
145 * to guest memory during VM exit.
146 */
147 struct vmcs12 *cached_shadow_vmcs12;
148
149 /*
150 * GPA to HVA cache for accessing vmcs12->vmcs_link_pointer
151 */
152 struct gfn_to_hva_cache shadow_vmcs12_cache;
153
154 /*
155 * GPA to HVA cache for VMCS12
156 */
157 struct gfn_to_hva_cache vmcs12_cache;
158
159 /*
160 * Indicates if the shadow vmcs or enlightened vmcs must be updated
161 * with the data held by struct vmcs12.
162 */
163 bool need_vmcs12_to_shadow_sync;
164 bool dirty_vmcs12;
165
166 /*
167 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
168 * changes in MSR bitmap for L1 or switching to a different L2. Note,
169 * this flag can only be used reliably in conjunction with a paravirt L1
170 * which informs L0 whether any changes to MSR bitmap for L2 were done
171 * on its side.
172 */
173 bool force_msr_bitmap_recalc;
174
175 /*
176 * Indicates lazily loaded guest state has not yet been decached from
177 * vmcs02.
178 */
179 bool need_sync_vmcs02_to_vmcs12_rare;
180
181 /*
182 * vmcs02 has been initialized, i.e. state that is constant for
183 * vmcs02 has been written to the backing VMCS. Initialization
184 * is delayed until L1 actually attempts to run a nested VM.
185 */
186 bool vmcs02_initialized;
187
188 bool change_vmcs01_virtual_apic_mode;
189 bool reload_vmcs01_apic_access_page;
190 bool update_vmcs01_cpu_dirty_logging;
191 bool update_vmcs01_apicv_status;
192
193 /*
194 * Enlightened VMCS has been enabled. It does not mean that L1 has to
195 * use it. However, VMX features available to L1 will be limited based
196 * on what the enlightened VMCS supports.
197 */
198 bool enlightened_vmcs_enabled;
199
200 /* L2 must run next, and mustn't decide to exit to L1. */
201 bool nested_run_pending;
202
203 /* Pending MTF VM-exit into L1. */
204 bool mtf_pending;
205
206 struct loaded_vmcs vmcs02;
207
208 /*
209 * Guest pages referred to in the vmcs02 with host-physical
210 * pointers, so we must keep them pinned while L2 runs.
211 */
212 struct kvm_host_map apic_access_page_map;
213 struct kvm_host_map virtual_apic_map;
214 struct kvm_host_map pi_desc_map;
215
216 struct kvm_host_map msr_bitmap_map;
217
218 struct pi_desc *pi_desc;
219 bool pi_pending;
220 u16 posted_intr_nv;
221
222 struct hrtimer preemption_timer;
223 u64 preemption_timer_deadline;
224 bool has_preemption_timer_deadline;
225 bool preemption_timer_expired;
226
227 /*
228 * Used to snapshot MSRs that are conditionally loaded on VM-Enter in
229 * order to propagate the guest's pre-VM-Enter value into vmcs02. For
230 * emulation of VMLAUNCH/VMRESUME, the snapshot will be of L1's value.
231 * For KVM_SET_NESTED_STATE, the snapshot is of L2's value, _if_
232 * userspace restores MSRs before nested state. If userspace restores
233 * MSRs after nested state, the snapshot holds garbage, but KVM can't
234 * detect that, and the garbage value in vmcs02 will be overwritten by
235 * MSR restoration in any case.
236 */
237 u64 pre_vmenter_debugctl;
238 u64 pre_vmenter_bndcfgs;
239
240 /* to migrate it to L1 if L2 writes to L1's CR8 directly */
241 int l1_tpr_threshold;
242
243 u16 vpid02;
244 u16 last_vpid;
245
246 struct nested_vmx_msrs msrs;
247
248 /* SMM related state */
249 struct {
250 /* in VMX operation on SMM entry? */
251 bool vmxon;
252 /* in guest mode on SMM entry? */
253 bool guest_mode;
254 } smm;
255
256 gpa_t hv_evmcs_vmptr;
257 struct kvm_host_map hv_evmcs_map;
258 struct hv_enlightened_vmcs *hv_evmcs;
259 };
260
261 struct vcpu_vmx {
262 struct kvm_vcpu vcpu;
263 u8 fail;
264 u8 x2apic_msr_bitmap_mode;
265
266 /*
267 * If true, host state has been stored in vmx->loaded_vmcs for
268 * the CPU registers that only need to be switched when transitioning
269 * to/from the kernel, and the registers have been loaded with guest
270 * values. If false, host state is loaded in the CPU registers
271 * and vmx->loaded_vmcs->host_state is invalid.
272 */
273 bool guest_state_loaded;
274
275 unsigned long exit_qualification;
276 u32 exit_intr_info;
277 u32 idt_vectoring_info;
278 ulong rflags;
279
280 /*
281 * User return MSRs are always emulated when enabled in the guest, but
282 * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
283 * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
284 * be loaded into hardware if those conditions aren't met.
285 */
286 struct vmx_uret_msr guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
287 bool guest_uret_msrs_loaded;
288 #ifdef CONFIG_X86_64
289 u64 msr_host_kernel_gs_base;
290 u64 msr_guest_kernel_gs_base;
291 #endif
292
293 u64 spec_ctrl;
294 u32 msr_ia32_umwait_control;
295
296 /*
297 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
298 * non-nested (L1) guest, it always points to vmcs01. For a nested
299 * guest (L2), it points to a different VMCS.
300 */
301 struct loaded_vmcs vmcs01;
302 struct loaded_vmcs *loaded_vmcs;
303
304 struct msr_autoload {
305 struct vmx_msrs guest;
306 struct vmx_msrs host;
307 } msr_autoload;
308
309 struct msr_autostore {
310 struct vmx_msrs guest;
311 } msr_autostore;
312
313 struct {
314 int vm86_active;
315 ulong save_rflags;
316 struct kvm_segment segs[8];
317 } rmode;
318 struct {
319 u32 bitmask; /* 4 bits per segment (1 bit per field) */
320 struct kvm_save_segment {
321 u16 selector;
322 unsigned long base;
323 u32 limit;
324 u32 ar;
325 } seg[8];
326 } segment_cache;
327 int vpid;
328 bool emulation_required;
329
330 union vmx_exit_reason exit_reason;
331
332 /* Posted interrupt descriptor */
333 struct pi_desc pi_desc;
334
335 /* Used if this vCPU is waiting for PI notification wakeup. */
336 struct list_head pi_wakeup_list;
337
338 /* Support for a guest hypervisor (nested VMX) */
339 struct nested_vmx nested;
340
341 /* Dynamic PLE window. */
342 unsigned int ple_window;
343 bool ple_window_dirty;
344
345 bool req_immediate_exit;
346
347 /* Support for PML */
348 #define PML_ENTITY_NUM 512
349 struct page *pml_pg;
350
351 /* apic deadline value in host tsc */
352 u64 hv_deadline_tsc;
353
354 unsigned long host_debugctlmsr;
355
356 /*
357 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
358 * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
359 * in msr_ia32_feature_control_valid_bits.
360 */
361 u64 msr_ia32_feature_control;
362 u64 msr_ia32_feature_control_valid_bits;
363 /* SGX Launch Control public key hash */
364 u64 msr_ia32_sgxlepubkeyhash[4];
365 u64 msr_ia32_mcu_opt_ctrl;
366 bool disable_fb_clear;
367
368 struct pt_desc pt_desc;
369 struct lbr_desc lbr_desc;
370
371 /* Save desired MSR intercept (read: pass-through) state */
372 #define MAX_POSSIBLE_PASSTHROUGH_MSRS 15
373 struct {
374 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
375 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
376 } shadow_msr_intercept;
377 };
378
379 struct kvm_vmx {
380 struct kvm kvm;
381
382 unsigned int tss_addr;
383 bool ept_identity_pagetable_done;
384 gpa_t ept_identity_map_addr;
385 /* Posted Interrupt Descriptor (PID) table for IPI virtualization */
386 u64 *pid_table;
387 };
388
389 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
390 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
391 struct loaded_vmcs *buddy);
392 int allocate_vpid(void);
393 void free_vpid(int vpid);
394 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
395 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
396 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
397 unsigned long fs_base, unsigned long gs_base);
398 int vmx_get_cpl(struct kvm_vcpu *vcpu);
399 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
400 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
401 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
402 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
403 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
404 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
405 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
406 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
407 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
408 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
409 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
410 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
411 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
412
413 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
414 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
415 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
416 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
417 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
418 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
419 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
420 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
421 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
422 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
423 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
424 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
425 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
426 unsigned int flags);
427 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
428 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
429
430 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
431 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
432
433 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
434 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
435
vmx_set_intercept_for_msr(struct kvm_vcpu * vcpu,u32 msr,int type,bool value)436 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
437 int type, bool value)
438 {
439 if (value)
440 vmx_enable_intercept_for_msr(vcpu, msr, type);
441 else
442 vmx_disable_intercept_for_msr(vcpu, msr, type);
443 }
444
445 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
446
447 /*
448 * Note, early Intel manuals have the write-low and read-high bitmap offsets
449 * the wrong way round. The bitmaps control MSRs 0x00000000-0x00001fff and
450 * 0xc0000000-0xc0001fff. The former (low) uses bytes 0-0x3ff for reads and
451 * 0x800-0xbff for writes. The latter (high) uses 0x400-0x7ff for reads and
452 * 0xc00-0xfff for writes. MSRs not covered by either of the ranges always
453 * VM-Exit.
454 */
455 #define __BUILD_VMX_MSR_BITMAP_HELPER(rtype, action, bitop, access, base) \
456 static inline rtype vmx_##action##_msr_bitmap_##access(unsigned long *bitmap, \
457 u32 msr) \
458 { \
459 int f = sizeof(unsigned long); \
460 \
461 if (msr <= 0x1fff) \
462 return bitop##_bit(msr, bitmap + base / f); \
463 else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) \
464 return bitop##_bit(msr & 0x1fff, bitmap + (base + 0x400) / f); \
465 return (rtype)true; \
466 }
467 #define BUILD_VMX_MSR_BITMAP_HELPERS(ret_type, action, bitop) \
468 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, read, 0x0) \
469 __BUILD_VMX_MSR_BITMAP_HELPER(ret_type, action, bitop, write, 0x800)
470
BUILD_VMX_MSR_BITMAP_HELPERS(bool,test,test)471 BUILD_VMX_MSR_BITMAP_HELPERS(bool, test, test)
472 BUILD_VMX_MSR_BITMAP_HELPERS(void, clear, __clear)
473 BUILD_VMX_MSR_BITMAP_HELPERS(void, set, __set)
474
475 static inline u8 vmx_get_rvi(void)
476 {
477 return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
478 }
479
480 #define __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
481 (VM_ENTRY_LOAD_DEBUG_CONTROLS)
482 #ifdef CONFIG_X86_64
483 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
484 (__KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS | \
485 VM_ENTRY_IA32E_MODE)
486 #else
487 #define KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS \
488 __KVM_REQUIRED_VMX_VM_ENTRY_CONTROLS
489 #endif
490 #define KVM_OPTIONAL_VMX_VM_ENTRY_CONTROLS \
491 (VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | \
492 VM_ENTRY_LOAD_IA32_PAT | \
493 VM_ENTRY_LOAD_IA32_EFER | \
494 VM_ENTRY_LOAD_BNDCFGS | \
495 VM_ENTRY_PT_CONCEAL_PIP | \
496 VM_ENTRY_LOAD_IA32_RTIT_CTL)
497
498 #define __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
499 (VM_EXIT_SAVE_DEBUG_CONTROLS | \
500 VM_EXIT_ACK_INTR_ON_EXIT)
501 #ifdef CONFIG_X86_64
502 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
503 (__KVM_REQUIRED_VMX_VM_EXIT_CONTROLS | \
504 VM_EXIT_HOST_ADDR_SPACE_SIZE)
505 #else
506 #define KVM_REQUIRED_VMX_VM_EXIT_CONTROLS \
507 __KVM_REQUIRED_VMX_VM_EXIT_CONTROLS
508 #endif
509 #define KVM_OPTIONAL_VMX_VM_EXIT_CONTROLS \
510 (VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | \
511 VM_EXIT_SAVE_IA32_PAT | \
512 VM_EXIT_LOAD_IA32_PAT | \
513 VM_EXIT_SAVE_IA32_EFER | \
514 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | \
515 VM_EXIT_LOAD_IA32_EFER | \
516 VM_EXIT_CLEAR_BNDCFGS | \
517 VM_EXIT_PT_CONCEAL_PIP | \
518 VM_EXIT_CLEAR_IA32_RTIT_CTL)
519
520 #define KVM_REQUIRED_VMX_PIN_BASED_VM_EXEC_CONTROL \
521 (PIN_BASED_EXT_INTR_MASK | \
522 PIN_BASED_NMI_EXITING)
523 #define KVM_OPTIONAL_VMX_PIN_BASED_VM_EXEC_CONTROL \
524 (PIN_BASED_VIRTUAL_NMIS | \
525 PIN_BASED_POSTED_INTR | \
526 PIN_BASED_VMX_PREEMPTION_TIMER)
527
528 #define __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
529 (CPU_BASED_HLT_EXITING | \
530 CPU_BASED_CR3_LOAD_EXITING | \
531 CPU_BASED_CR3_STORE_EXITING | \
532 CPU_BASED_UNCOND_IO_EXITING | \
533 CPU_BASED_MOV_DR_EXITING | \
534 CPU_BASED_USE_TSC_OFFSETTING | \
535 CPU_BASED_MWAIT_EXITING | \
536 CPU_BASED_MONITOR_EXITING | \
537 CPU_BASED_INVLPG_EXITING | \
538 CPU_BASED_RDPMC_EXITING | \
539 CPU_BASED_INTR_WINDOW_EXITING)
540
541 #ifdef CONFIG_X86_64
542 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
543 (__KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL | \
544 CPU_BASED_CR8_LOAD_EXITING | \
545 CPU_BASED_CR8_STORE_EXITING)
546 #else
547 #define KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL \
548 __KVM_REQUIRED_VMX_CPU_BASED_VM_EXEC_CONTROL
549 #endif
550
551 #define KVM_OPTIONAL_VMX_CPU_BASED_VM_EXEC_CONTROL \
552 (CPU_BASED_RDTSC_EXITING | \
553 CPU_BASED_TPR_SHADOW | \
554 CPU_BASED_USE_IO_BITMAPS | \
555 CPU_BASED_MONITOR_TRAP_FLAG | \
556 CPU_BASED_USE_MSR_BITMAPS | \
557 CPU_BASED_NMI_WINDOW_EXITING | \
558 CPU_BASED_PAUSE_EXITING | \
559 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS | \
560 CPU_BASED_ACTIVATE_TERTIARY_CONTROLS)
561
562 #define KVM_REQUIRED_VMX_SECONDARY_VM_EXEC_CONTROL 0
563 #define KVM_OPTIONAL_VMX_SECONDARY_VM_EXEC_CONTROL \
564 (SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | \
565 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | \
566 SECONDARY_EXEC_WBINVD_EXITING | \
567 SECONDARY_EXEC_ENABLE_VPID | \
568 SECONDARY_EXEC_ENABLE_EPT | \
569 SECONDARY_EXEC_UNRESTRICTED_GUEST | \
570 SECONDARY_EXEC_PAUSE_LOOP_EXITING | \
571 SECONDARY_EXEC_DESC | \
572 SECONDARY_EXEC_ENABLE_RDTSCP | \
573 SECONDARY_EXEC_ENABLE_INVPCID | \
574 SECONDARY_EXEC_APIC_REGISTER_VIRT | \
575 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | \
576 SECONDARY_EXEC_SHADOW_VMCS | \
577 SECONDARY_EXEC_XSAVES | \
578 SECONDARY_EXEC_RDSEED_EXITING | \
579 SECONDARY_EXEC_RDRAND_EXITING | \
580 SECONDARY_EXEC_ENABLE_PML | \
581 SECONDARY_EXEC_TSC_SCALING | \
582 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | \
583 SECONDARY_EXEC_PT_USE_GPA | \
584 SECONDARY_EXEC_PT_CONCEAL_VMX | \
585 SECONDARY_EXEC_ENABLE_VMFUNC | \
586 SECONDARY_EXEC_BUS_LOCK_DETECTION | \
587 SECONDARY_EXEC_NOTIFY_VM_EXITING | \
588 SECONDARY_EXEC_ENCLS_EXITING)
589
590 #define KVM_REQUIRED_VMX_TERTIARY_VM_EXEC_CONTROL 0
591 #define KVM_OPTIONAL_VMX_TERTIARY_VM_EXEC_CONTROL \
592 (TERTIARY_EXEC_IPI_VIRT)
593
594 #define BUILD_CONTROLS_SHADOW(lname, uname, bits) \
595 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u##bits val) \
596 { \
597 if (vmx->loaded_vmcs->controls_shadow.lname != val) { \
598 vmcs_write##bits(uname, val); \
599 vmx->loaded_vmcs->controls_shadow.lname = val; \
600 } \
601 } \
602 static inline u##bits __##lname##_controls_get(struct loaded_vmcs *vmcs) \
603 { \
604 return vmcs->controls_shadow.lname; \
605 } \
606 static inline u##bits lname##_controls_get(struct vcpu_vmx *vmx) \
607 { \
608 return __##lname##_controls_get(vmx->loaded_vmcs); \
609 } \
610 static __always_inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u##bits val) \
611 { \
612 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
613 lname##_controls_set(vmx, lname##_controls_get(vmx) | val); \
614 } \
615 static __always_inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u##bits val) \
616 { \
617 BUILD_BUG_ON(!(val & (KVM_REQUIRED_VMX_##uname | KVM_OPTIONAL_VMX_##uname))); \
618 lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val); \
619 }
620 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS, 32)
621 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS, 32)
622 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL, 32)
623 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL, 32)
624 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL, 32)
625 BUILD_CONTROLS_SHADOW(tertiary_exec, TERTIARY_VM_EXEC_CONTROL, 64)
626
627 /*
628 * VMX_REGS_LAZY_LOAD_SET - The set of registers that will be updated in the
629 * cache on demand. Other registers not listed here are synced to
630 * the cache immediately after VM-Exit.
631 */
632 #define VMX_REGS_LAZY_LOAD_SET ((1 << VCPU_REGS_RIP) | \
633 (1 << VCPU_REGS_RSP) | \
634 (1 << VCPU_EXREG_RFLAGS) | \
635 (1 << VCPU_EXREG_PDPTR) | \
636 (1 << VCPU_EXREG_SEGMENTS) | \
637 (1 << VCPU_EXREG_CR0) | \
638 (1 << VCPU_EXREG_CR3) | \
639 (1 << VCPU_EXREG_CR4) | \
640 (1 << VCPU_EXREG_EXIT_INFO_1) | \
641 (1 << VCPU_EXREG_EXIT_INFO_2))
642
to_kvm_vmx(struct kvm * kvm)643 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
644 {
645 return container_of(kvm, struct kvm_vmx, kvm);
646 }
647
to_vmx(struct kvm_vcpu * vcpu)648 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
649 {
650 return container_of(vcpu, struct vcpu_vmx, vcpu);
651 }
652
vcpu_to_lbr_desc(struct kvm_vcpu * vcpu)653 static inline struct lbr_desc *vcpu_to_lbr_desc(struct kvm_vcpu *vcpu)
654 {
655 return &to_vmx(vcpu)->lbr_desc;
656 }
657
vcpu_to_lbr_records(struct kvm_vcpu * vcpu)658 static inline struct x86_pmu_lbr *vcpu_to_lbr_records(struct kvm_vcpu *vcpu)
659 {
660 return &vcpu_to_lbr_desc(vcpu)->records;
661 }
662
intel_pmu_lbr_is_enabled(struct kvm_vcpu * vcpu)663 static inline bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu)
664 {
665 return !!vcpu_to_lbr_records(vcpu)->nr;
666 }
667
668 void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu);
669 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
670 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
671
vmx_get_exit_qual(struct kvm_vcpu * vcpu)672 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
673 {
674 struct vcpu_vmx *vmx = to_vmx(vcpu);
675
676 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
677 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
678 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
679 }
680 return vmx->exit_qualification;
681 }
682
vmx_get_intr_info(struct kvm_vcpu * vcpu)683 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
684 {
685 struct vcpu_vmx *vmx = to_vmx(vcpu);
686
687 if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
688 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
689 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
690 }
691 return vmx->exit_intr_info;
692 }
693
694 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
695 void free_vmcs(struct vmcs *vmcs);
696 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
697 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
698 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
699
alloc_vmcs(bool shadow)700 static inline struct vmcs *alloc_vmcs(bool shadow)
701 {
702 return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
703 GFP_KERNEL_ACCOUNT);
704 }
705
vmx_has_waitpkg(struct vcpu_vmx * vmx)706 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
707 {
708 return secondary_exec_controls_get(vmx) &
709 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
710 }
711
vmx_need_pf_intercept(struct kvm_vcpu * vcpu)712 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
713 {
714 if (!enable_ept)
715 return true;
716
717 return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
718 }
719
is_unrestricted_guest(struct kvm_vcpu * vcpu)720 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
721 {
722 return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
723 (secondary_exec_controls_get(to_vmx(vcpu)) &
724 SECONDARY_EXEC_UNRESTRICTED_GUEST));
725 }
726
727 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
vmx_guest_state_valid(struct kvm_vcpu * vcpu)728 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
729 {
730 return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
731 }
732
733 void dump_vmcs(struct kvm_vcpu *vcpu);
734
vmx_get_instr_info_reg2(u32 vmx_instr_info)735 static inline int vmx_get_instr_info_reg2(u32 vmx_instr_info)
736 {
737 return (vmx_instr_info >> 28) & 0xf;
738 }
739
vmx_can_use_ipiv(struct kvm_vcpu * vcpu)740 static inline bool vmx_can_use_ipiv(struct kvm_vcpu *vcpu)
741 {
742 return lapic_in_kernel(vcpu) && enable_ipiv;
743 }
744
guest_cpuid_has_evmcs(struct kvm_vcpu * vcpu)745 static inline bool guest_cpuid_has_evmcs(struct kvm_vcpu *vcpu)
746 {
747 /*
748 * eVMCS is exposed to the guest if Hyper-V is enabled in CPUID and
749 * eVMCS has been explicitly enabled by userspace.
750 */
751 return vcpu->arch.hyperv_enabled &&
752 to_vmx(vcpu)->nested.enlightened_vmcs_enabled;
753 }
754
755 #endif /* __KVM_X86_VMX_H */
756
