1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "dcn20_hubbub.h"
28 #include "reg_helper.h"
29 #include "clk_mgr.h"
30
31 #define REG(reg)\
32 hubbub1->regs->reg
33
34 #define CTX \
35 hubbub1->base.ctx
36
37 #undef FN
38 #define FN(reg_name, field_name) \
39 hubbub1->shifts->field_name, hubbub1->masks->field_name
40
41 #define REG(reg)\
42 hubbub1->regs->reg
43
44 #define CTX \
45 hubbub1->base.ctx
46
47 #undef FN
48 #define FN(reg_name, field_name) \
49 hubbub1->shifts->field_name, hubbub1->masks->field_name
50
51 #ifdef NUM_VMID
52 #undef NUM_VMID
53 #endif
54 #define NUM_VMID 16
55
hubbub2_dcc_support_swizzle(enum swizzle_mode_values swizzle,unsigned int bytes_per_element,enum segment_order * segment_order_horz,enum segment_order * segment_order_vert)56 bool hubbub2_dcc_support_swizzle(
57 enum swizzle_mode_values swizzle,
58 unsigned int bytes_per_element,
59 enum segment_order *segment_order_horz,
60 enum segment_order *segment_order_vert)
61 {
62 bool standard_swizzle = false;
63 bool display_swizzle = false;
64 bool render_swizzle = false;
65
66 switch (swizzle) {
67 case DC_SW_4KB_S:
68 case DC_SW_64KB_S:
69 case DC_SW_VAR_S:
70 case DC_SW_4KB_S_X:
71 case DC_SW_64KB_S_X:
72 case DC_SW_VAR_S_X:
73 standard_swizzle = true;
74 break;
75 case DC_SW_64KB_R_X:
76 render_swizzle = true;
77 break;
78 case DC_SW_4KB_D:
79 case DC_SW_64KB_D:
80 case DC_SW_VAR_D:
81 case DC_SW_4KB_D_X:
82 case DC_SW_64KB_D_X:
83 case DC_SW_VAR_D_X:
84 display_swizzle = true;
85 break;
86 default:
87 break;
88 }
89
90 if (standard_swizzle) {
91 if (bytes_per_element == 1) {
92 *segment_order_horz = segment_order__contiguous;
93 *segment_order_vert = segment_order__na;
94 return true;
95 }
96 if (bytes_per_element == 2) {
97 *segment_order_horz = segment_order__non_contiguous;
98 *segment_order_vert = segment_order__contiguous;
99 return true;
100 }
101 if (bytes_per_element == 4) {
102 *segment_order_horz = segment_order__non_contiguous;
103 *segment_order_vert = segment_order__contiguous;
104 return true;
105 }
106 if (bytes_per_element == 8) {
107 *segment_order_horz = segment_order__na;
108 *segment_order_vert = segment_order__contiguous;
109 return true;
110 }
111 }
112 if (render_swizzle) {
113 if (bytes_per_element == 2) {
114 *segment_order_horz = segment_order__contiguous;
115 *segment_order_vert = segment_order__contiguous;
116 return true;
117 }
118 if (bytes_per_element == 4) {
119 *segment_order_horz = segment_order__non_contiguous;
120 *segment_order_vert = segment_order__contiguous;
121 return true;
122 }
123 if (bytes_per_element == 8) {
124 *segment_order_horz = segment_order__contiguous;
125 *segment_order_vert = segment_order__non_contiguous;
126 return true;
127 }
128 }
129 if (display_swizzle && bytes_per_element == 8) {
130 *segment_order_horz = segment_order__contiguous;
131 *segment_order_vert = segment_order__non_contiguous;
132 return true;
133 }
134
135 return false;
136 }
137
hubbub2_dcc_support_pixel_format(enum surface_pixel_format format,unsigned int * bytes_per_element)138 bool hubbub2_dcc_support_pixel_format(
139 enum surface_pixel_format format,
140 unsigned int *bytes_per_element)
141 {
142 /* DML: get_bytes_per_element */
143 switch (format) {
144 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
145 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
146 *bytes_per_element = 2;
147 return true;
148 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
149 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
150 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
151 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
152 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
153 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
154 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
155 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
156 *bytes_per_element = 4;
157 return true;
158 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
159 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
160 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
161 *bytes_per_element = 8;
162 return true;
163 default:
164 return false;
165 }
166 }
167
hubbub2_get_blk256_size(unsigned int * blk256_width,unsigned int * blk256_height,unsigned int bytes_per_element)168 static void hubbub2_get_blk256_size(unsigned int *blk256_width, unsigned int *blk256_height,
169 unsigned int bytes_per_element)
170 {
171 /* copied from DML. might want to refactor DML to leverage from DML */
172 /* DML : get_blk256_size */
173 if (bytes_per_element == 1) {
174 *blk256_width = 16;
175 *blk256_height = 16;
176 } else if (bytes_per_element == 2) {
177 *blk256_width = 16;
178 *blk256_height = 8;
179 } else if (bytes_per_element == 4) {
180 *blk256_width = 8;
181 *blk256_height = 8;
182 } else if (bytes_per_element == 8) {
183 *blk256_width = 8;
184 *blk256_height = 4;
185 }
186 }
187
hubbub2_det_request_size(unsigned int height,unsigned int width,unsigned int bpe,bool * req128_horz_wc,bool * req128_vert_wc)188 static void hubbub2_det_request_size(
189 unsigned int height,
190 unsigned int width,
191 unsigned int bpe,
192 bool *req128_horz_wc,
193 bool *req128_vert_wc)
194 {
195 unsigned int detile_buf_size = 164 * 1024; /* 164KB for DCN1.0 */
196
197 unsigned int blk256_height = 0;
198 unsigned int blk256_width = 0;
199 unsigned int swath_bytes_horz_wc, swath_bytes_vert_wc;
200
201 hubbub2_get_blk256_size(&blk256_width, &blk256_height, bpe);
202
203 swath_bytes_horz_wc = width * blk256_height * bpe;
204 swath_bytes_vert_wc = height * blk256_width * bpe;
205
206 *req128_horz_wc = (2 * swath_bytes_horz_wc <= detile_buf_size) ?
207 false : /* full 256B request */
208 true; /* half 128b request */
209
210 *req128_vert_wc = (2 * swath_bytes_vert_wc <= detile_buf_size) ?
211 false : /* full 256B request */
212 true; /* half 128b request */
213 }
214
hubbub2_get_dcc_compression_cap(struct hubbub * hubbub,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)215 bool hubbub2_get_dcc_compression_cap(struct hubbub *hubbub,
216 const struct dc_dcc_surface_param *input,
217 struct dc_surface_dcc_cap *output)
218 {
219 struct dc *dc = hubbub->ctx->dc;
220 /* implement section 1.6.2.1 of DCN1_Programming_Guide.docx */
221 enum dcc_control dcc_control;
222 unsigned int bpe;
223 enum segment_order segment_order_horz, segment_order_vert;
224 bool req128_horz_wc, req128_vert_wc;
225
226 memset(output, 0, sizeof(*output));
227
228 if (dc->debug.disable_dcc == DCC_DISABLE)
229 return false;
230
231 if (!hubbub->funcs->dcc_support_pixel_format(input->format,
232 &bpe))
233 return false;
234
235 if (!hubbub->funcs->dcc_support_swizzle(input->swizzle_mode, bpe,
236 &segment_order_horz, &segment_order_vert))
237 return false;
238
239 hubbub2_det_request_size(input->surface_size.height, input->surface_size.width,
240 bpe, &req128_horz_wc, &req128_vert_wc);
241
242 if (!req128_horz_wc && !req128_vert_wc) {
243 dcc_control = dcc_control__256_256_xxx;
244 } else if (input->scan == SCAN_DIRECTION_HORIZONTAL) {
245 if (!req128_horz_wc)
246 dcc_control = dcc_control__256_256_xxx;
247 else if (segment_order_horz == segment_order__contiguous)
248 dcc_control = dcc_control__128_128_xxx;
249 else
250 dcc_control = dcc_control__256_64_64;
251 } else if (input->scan == SCAN_DIRECTION_VERTICAL) {
252 if (!req128_vert_wc)
253 dcc_control = dcc_control__256_256_xxx;
254 else if (segment_order_vert == segment_order__contiguous)
255 dcc_control = dcc_control__128_128_xxx;
256 else
257 dcc_control = dcc_control__256_64_64;
258 } else {
259 if ((req128_horz_wc &&
260 segment_order_horz == segment_order__non_contiguous) ||
261 (req128_vert_wc &&
262 segment_order_vert == segment_order__non_contiguous))
263 /* access_dir not known, must use most constraining */
264 dcc_control = dcc_control__256_64_64;
265 else
266 /* reg128 is true for either horz and vert
267 * but segment_order is contiguous
268 */
269 dcc_control = dcc_control__128_128_xxx;
270 }
271
272 /* Exception for 64KB_R_X */
273 if ((bpe == 2) && (input->swizzle_mode == DC_SW_64KB_R_X))
274 dcc_control = dcc_control__128_128_xxx;
275
276 if (dc->debug.disable_dcc == DCC_HALF_REQ_DISALBE &&
277 dcc_control != dcc_control__256_256_xxx)
278 return false;
279
280 switch (dcc_control) {
281 case dcc_control__256_256_xxx:
282 output->grph.rgb.max_uncompressed_blk_size = 256;
283 output->grph.rgb.max_compressed_blk_size = 256;
284 output->grph.rgb.independent_64b_blks = false;
285 break;
286 case dcc_control__128_128_xxx:
287 output->grph.rgb.max_uncompressed_blk_size = 128;
288 output->grph.rgb.max_compressed_blk_size = 128;
289 output->grph.rgb.independent_64b_blks = false;
290 break;
291 case dcc_control__256_64_64:
292 output->grph.rgb.max_uncompressed_blk_size = 256;
293 output->grph.rgb.max_compressed_blk_size = 64;
294 output->grph.rgb.independent_64b_blks = true;
295 break;
296 }
297 output->capable = true;
298 output->const_color_support = true;
299
300 return true;
301 }
302
page_table_depth_to_hw(unsigned int page_table_depth)303 static enum dcn_hubbub_page_table_depth page_table_depth_to_hw(unsigned int page_table_depth)
304 {
305 enum dcn_hubbub_page_table_depth depth = 0;
306
307 switch (page_table_depth) {
308 case 1:
309 depth = DCN_PAGE_TABLE_DEPTH_1_LEVEL;
310 break;
311 case 2:
312 depth = DCN_PAGE_TABLE_DEPTH_2_LEVEL;
313 break;
314 case 3:
315 depth = DCN_PAGE_TABLE_DEPTH_3_LEVEL;
316 break;
317 case 4:
318 depth = DCN_PAGE_TABLE_DEPTH_4_LEVEL;
319 break;
320 default:
321 ASSERT(false);
322 break;
323 }
324
325 return depth;
326 }
327
page_table_block_size_to_hw(unsigned int page_table_block_size)328 static enum dcn_hubbub_page_table_block_size page_table_block_size_to_hw(unsigned int page_table_block_size)
329 {
330 enum dcn_hubbub_page_table_block_size block_size = 0;
331
332 switch (page_table_block_size) {
333 case 4096:
334 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_4KB;
335 break;
336 case 65536:
337 block_size = DCN_PAGE_TABLE_BLOCK_SIZE_64KB;
338 break;
339 default:
340 ASSERT(false);
341 block_size = page_table_block_size;
342 break;
343 }
344
345 return block_size;
346 }
347
hubbub2_init_vm_ctx(struct hubbub * hubbub,struct dcn_hubbub_virt_addr_config * va_config,int vmid)348 void hubbub2_init_vm_ctx(struct hubbub *hubbub,
349 struct dcn_hubbub_virt_addr_config *va_config,
350 int vmid)
351 {
352 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
353 struct dcn_vmid_page_table_config virt_config;
354
355 virt_config.page_table_start_addr = va_config->page_table_start_addr >> 12;
356 virt_config.page_table_end_addr = va_config->page_table_end_addr >> 12;
357 virt_config.depth = page_table_depth_to_hw(va_config->page_table_depth);
358 virt_config.block_size = page_table_block_size_to_hw(va_config->page_table_block_size);
359 virt_config.page_table_base_addr = va_config->page_table_base_addr;
360
361 dcn20_vmid_setup(&hubbub1->vmid[vmid], &virt_config);
362 }
363
hubbub2_init_dchub_sys_ctx(struct hubbub * hubbub,struct dcn_hubbub_phys_addr_config * pa_config)364 int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
365 struct dcn_hubbub_phys_addr_config *pa_config)
366 {
367 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
368 struct dcn_vmid_page_table_config phys_config;
369
370 REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
371 FB_BASE, pa_config->system_aperture.fb_base >> 24);
372 REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
373 FB_TOP, pa_config->system_aperture.fb_top >> 24);
374 REG_SET(DCN_VM_FB_OFFSET, 0,
375 FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
376 REG_SET(DCN_VM_AGP_BOT, 0,
377 AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
378 REG_SET(DCN_VM_AGP_TOP, 0,
379 AGP_TOP, pa_config->system_aperture.agp_top >> 24);
380 REG_SET(DCN_VM_AGP_BASE, 0,
381 AGP_BASE, pa_config->system_aperture.agp_base >> 24);
382
383 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
384 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
385 REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, 0,
386 DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_LSB, (pa_config->page_table_default_page_addr >> 12) & 0xFFFFFFFF);
387
388 if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
389 phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
390 phys_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr >> 12;
391 phys_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
392 phys_config.depth = 0;
393 phys_config.block_size = 0;
394 // Init VMID 0 based on PA config
395 dcn20_vmid_setup(&hubbub1->vmid[0], &phys_config);
396 }
397
398 return NUM_VMID;
399 }
400
hubbub2_update_dchub(struct hubbub * hubbub,struct dchub_init_data * dh_data)401 void hubbub2_update_dchub(struct hubbub *hubbub,
402 struct dchub_init_data *dh_data)
403 {
404 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
405
406 if (REG(DCN_VM_FB_LOCATION_TOP) == 0)
407 return;
408
409 switch (dh_data->fb_mode) {
410 case FRAME_BUFFER_MODE_ZFB_ONLY:
411 /*For ZFB case need to put DCHUB FB BASE and TOP upside down to indicate ZFB mode*/
412 REG_UPDATE(DCN_VM_FB_LOCATION_TOP,
413 FB_TOP, 0);
414
415 REG_UPDATE(DCN_VM_FB_LOCATION_BASE,
416 FB_BASE, 0xFFFFFF);
417
418 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
419 REG_UPDATE(DCN_VM_AGP_BASE,
420 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
421
422 /*This field defines the bottom range of the AGP aperture and represents the 24*/
423 /*MSBs, bits [47:24] of the 48 address bits*/
424 REG_UPDATE(DCN_VM_AGP_BOT,
425 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
426
427 /*This field defines the top range of the AGP aperture and represents the 24*/
428 /*MSBs, bits [47:24] of the 48 address bits*/
429 REG_UPDATE(DCN_VM_AGP_TOP,
430 AGP_TOP, (dh_data->zfb_mc_base_addr +
431 dh_data->zfb_size_in_byte - 1) >> 24);
432 break;
433 case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
434 /*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
435
436 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
437 REG_UPDATE(DCN_VM_AGP_BASE,
438 AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
439
440 /*This field defines the bottom range of the AGP aperture and represents the 24*/
441 /*MSBs, bits [47:24] of the 48 address bits*/
442 REG_UPDATE(DCN_VM_AGP_BOT,
443 AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
444
445 /*This field defines the top range of the AGP aperture and represents the 24*/
446 /*MSBs, bits [47:24] of the 48 address bits*/
447 REG_UPDATE(DCN_VM_AGP_TOP,
448 AGP_TOP, (dh_data->zfb_mc_base_addr +
449 dh_data->zfb_size_in_byte - 1) >> 24);
450 break;
451 case FRAME_BUFFER_MODE_LOCAL_ONLY:
452 /*Should not touch FB LOCATION (should be done by VBIOS)*/
453
454 /*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
455 REG_UPDATE(DCN_VM_AGP_BASE,
456 AGP_BASE, 0);
457
458 /*This field defines the bottom range of the AGP aperture and represents the 24*/
459 /*MSBs, bits [47:24] of the 48 address bits*/
460 REG_UPDATE(DCN_VM_AGP_BOT,
461 AGP_BOT, 0xFFFFFF);
462
463 /*This field defines the top range of the AGP aperture and represents the 24*/
464 /*MSBs, bits [47:24] of the 48 address bits*/
465 REG_UPDATE(DCN_VM_AGP_TOP,
466 AGP_TOP, 0);
467 break;
468 default:
469 break;
470 }
471
472 dh_data->dchub_initialzied = true;
473 dh_data->dchub_info_valid = false;
474 }
475
hubbub2_wm_read_state(struct hubbub * hubbub,struct dcn_hubbub_wm * wm)476 void hubbub2_wm_read_state(struct hubbub *hubbub,
477 struct dcn_hubbub_wm *wm)
478 {
479 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
480
481 struct dcn_hubbub_wm_set *s;
482
483 memset(wm, 0, sizeof(struct dcn_hubbub_wm));
484
485 s = &wm->sets[0];
486 s->wm_set = 0;
487 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
488 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A))
489 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A);
490 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
491 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
492 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
493 }
494 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
495
496 s = &wm->sets[1];
497 s->wm_set = 1;
498 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B);
499 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B))
500 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B);
501 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
502 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B);
503 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B);
504 }
505 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B);
506
507 s = &wm->sets[2];
508 s->wm_set = 2;
509 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C);
510 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C))
511 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C);
512 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
513 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C);
514 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C);
515 }
516 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C);
517
518 s = &wm->sets[3];
519 s->wm_set = 3;
520 s->data_urgent = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D);
521 if (REG(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D))
522 s->pte_meta_urgent = REG_READ(DCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D);
523 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
524 s->sr_enter = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D);
525 s->sr_exit = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D);
526 }
527 s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
528 }
529
hubbub2_get_dchub_ref_freq(struct hubbub * hubbub,unsigned int dccg_ref_freq_inKhz,unsigned int * dchub_ref_freq_inKhz)530 void hubbub2_get_dchub_ref_freq(struct hubbub *hubbub,
531 unsigned int dccg_ref_freq_inKhz,
532 unsigned int *dchub_ref_freq_inKhz)
533 {
534 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
535 uint32_t ref_div = 0;
536 uint32_t ref_en = 0;
537
538 REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div,
539 DCHUBBUB_GLOBAL_TIMER_ENABLE, &ref_en);
540
541 if (ref_en) {
542 if (ref_div == 2)
543 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz / 2;
544 else
545 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
546
547 // DC hub reference frequency must be around 50Mhz, otherwise there may be
548 // overflow/underflow issues when doing HUBBUB programming
549 if (*dchub_ref_freq_inKhz < 40000 || *dchub_ref_freq_inKhz > 60000)
550 ASSERT_CRITICAL(false);
551
552 return;
553 } else {
554 *dchub_ref_freq_inKhz = dccg_ref_freq_inKhz;
555
556 // HUBBUB global timer must be enabled.
557 ASSERT_CRITICAL(false);
558 return;
559 }
560 }
561
hubbub2_program_watermarks(struct hubbub * hubbub,struct dcn_watermark_set * watermarks,unsigned int refclk_mhz,bool safe_to_lower)562 static void hubbub2_program_watermarks(
563 struct hubbub *hubbub,
564 struct dcn_watermark_set *watermarks,
565 unsigned int refclk_mhz,
566 bool safe_to_lower)
567 {
568 struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
569 /*
570 * Need to clamp to max of the register values (i.e. no wrap)
571 * for dcn1, all wm registers are 21-bit wide
572 */
573 hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
574 hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
575
576 /*
577 * There's a special case when going from p-state support to p-state unsupported
578 * here we are going to LOWER watermarks to go to dummy p-state only, but this has
579 * to be done prepare_bandwidth, not optimize
580 */
581 if (hubbub1->base.ctx->dc->clk_mgr->clks.prev_p_state_change_support == true &&
582 hubbub1->base.ctx->dc->clk_mgr->clks.p_state_change_support == false)
583 safe_to_lower = true;
584
585 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower);
586
587 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0,
588 DCHUBBUB_ARB_SAT_LEVEL, 60 * refclk_mhz);
589 REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 180);
590
591 hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
592 }
593
594 static const struct hubbub_funcs hubbub2_funcs = {
595 .update_dchub = hubbub2_update_dchub,
596 .init_dchub_sys_ctx = hubbub2_init_dchub_sys_ctx,
597 .init_vm_ctx = hubbub2_init_vm_ctx,
598 .dcc_support_swizzle = hubbub2_dcc_support_swizzle,
599 .dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
600 .get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
601 .wm_read_state = hubbub2_wm_read_state,
602 .get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
603 .program_watermarks = hubbub2_program_watermarks
604 };
605
hubbub2_construct(struct dcn20_hubbub * hubbub,struct dc_context * ctx,const struct dcn_hubbub_registers * hubbub_regs,const struct dcn_hubbub_shift * hubbub_shift,const struct dcn_hubbub_mask * hubbub_mask)606 void hubbub2_construct(struct dcn20_hubbub *hubbub,
607 struct dc_context *ctx,
608 const struct dcn_hubbub_registers *hubbub_regs,
609 const struct dcn_hubbub_shift *hubbub_shift,
610 const struct dcn_hubbub_mask *hubbub_mask)
611 {
612 hubbub->base.ctx = ctx;
613
614 hubbub->base.funcs = &hubbub2_funcs;
615
616 hubbub->regs = hubbub_regs;
617 hubbub->shifts = hubbub_shift;
618 hubbub->masks = hubbub_mask;
619
620 hubbub->debug_test_index_pstate = 0xB;
621 }
622
