1 /*
2 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
3 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
4 * Portions Copyright (C) 2003 Red Hat Inc
5 * Portions Copyright (C) 2007 Bartlomiej Zolnierkiewicz
6 * Portions Copyright (C) 2005-2009 MontaVista Software, Inc.
7 *
8 * Thanks to HighPoint Technologies for their assistance, and hardware.
9 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
10 * donation of an ABit BP6 mainboard, processor, and memory acellerated
11 * development and support.
12 *
13 *
14 * HighPoint has its own drivers (open source except for the RAID part)
15 * available from http://www.highpoint-tech.com/USA_new/service_support.htm
16 * This may be useful to anyone wanting to work on this driver, however do not
17 * trust them too much since the code tends to become less and less meaningful
18 * as the time passes... :-/
19 *
20 * Note that final HPT370 support was done by force extraction of GPL.
21 *
22 * - add function for getting/setting power status of drive
23 * - the HPT370's state machine can get confused. reset it before each dma
24 * xfer to prevent that from happening.
25 * - reset state engine whenever we get an error.
26 * - check for busmaster state at end of dma.
27 * - use new highpoint timings.
28 * - detect bus speed using highpoint register.
29 * - use pll if we don't have a clock table. added a 66MHz table that's
30 * just 2x the 33MHz table.
31 * - removed turnaround. NOTE: we never want to switch between pll and
32 * pci clocks as the chip can glitch in those cases. the highpoint
33 * approved workaround slows everything down too much to be useful. in
34 * addition, we would have to serialize access to each chip.
35 * Adrian Sun <a.sun@sun.com>
36 *
37 * add drive timings for 66MHz PCI bus,
38 * fix ATA Cable signal detection, fix incorrect /proc info
39 * add /proc display for per-drive PIO/DMA/UDMA mode and
40 * per-channel ATA-33/66 Cable detect.
41 * Duncan Laurie <void@sun.com>
42 *
43 * fixup /proc output for multiple controllers
44 * Tim Hockin <thockin@sun.com>
45 *
46 * On hpt366:
47 * Reset the hpt366 on error, reset on dma
48 * Fix disabling Fast Interrupt hpt366.
49 * Mike Waychison <crlf@sun.com>
50 *
51 * Added support for 372N clocking and clock switching. The 372N needs
52 * different clocks on read/write. This requires overloading rw_disk and
53 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
54 * keeping me sane.
55 * Alan Cox <alan@lxorguk.ukuu.org.uk>
56 *
57 * - fix the clock turnaround code: it was writing to the wrong ports when
58 * called for the secondary channel, caching the current clock mode per-
59 * channel caused the cached register value to get out of sync with the
60 * actual one, the channels weren't serialized, the turnaround shouldn't
61 * be done on 66 MHz PCI bus
62 * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
63 * does not allow for this speed anyway
64 * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
65 * their primary channel is kind of virtual, it isn't tied to any pins)
66 * - fix/remove bad/unused timing tables and use one set of tables for the whole
67 * HPT37x chip family; save space by introducing the separate transfer mode
68 * table in which the mode lookup is done
69 * - use f_CNT value saved by the HighPoint BIOS as reading it directly gives
70 * the wrong PCI frequency since DPLL has already been calibrated by BIOS;
71 * read it only from the function 0 of HPT374 chips
72 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
73 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
74 * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
75 * they tamper with its fields
76 * - pass to the init_setup handlers a copy of the ide_pci_device_t structure
77 * since they may tamper with its fields
78 * - prefix the driver startup messages with the real chip name
79 * - claim the extra 240 bytes of I/O space for all chips
80 * - optimize the UltraDMA filtering and the drive list lookup code
81 * - use pci_get_slot() to get to the function 1 of HPT36x/374
82 * - cache offset of the channel's misc. control registers (MCRs) being used
83 * throughout the driver
84 * - only touch the relevant MCR when detecting the cable type on HPT374's
85 * function 1
86 * - rename all the register related variables consistently
87 * - move all the interrupt twiddling code from the speedproc handlers into
88 * init_hwif_hpt366(), also grouping all the DMA related code together there
89 * - merge HPT36x/HPT37x speedproc handlers, fix PIO timing register mask and
90 * separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
91 * when setting an UltraDMA mode
92 * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
93 * the best possible one
94 * - clean up DMA timeout handling for HPT370
95 * - switch to using the enumeration type to differ between the numerous chip
96 * variants, matching PCI device/revision ID with the chip type early, at the
97 * init_setup stage
98 * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
99 * stop duplicating it for each channel by storing the pointer in the pci_dev
100 * structure: first, at the init_setup stage, point it to a static "template"
101 * with only the chip type and its specific base DPLL frequency, the highest
102 * UltraDMA mode, and the chip settings table pointer filled, then, at the
103 * init_chipset stage, allocate per-chip instance and fill it with the rest
104 * of the necessary information
105 * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
106 * switch to calculating PCI clock frequency based on the chip's base DPLL
107 * frequency
108 * - switch to using the DPLL clock and enable UltraATA/133 mode by default on
109 * anything newer than HPT370/A (except HPT374 that is not capable of this
110 * mode according to the manual)
111 * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
112 * also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
113 * unify HPT36x/37x timing setup code and the speedproc handlers by joining
114 * the register setting lists into the table indexed by the clock selected
115 * - set the correct hwif->ultra_mask for each individual chip
116 * - add Ultra and MW DMA mode filtering for the HPT37[24] based SATA cards
117 * - stop resetting HPT370's state machine before each DMA transfer as that has
118 * caused more harm than good
119 * Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
120 */
121
122 #include <linux/types.h>
123 #include <linux/module.h>
124 #include <linux/kernel.h>
125 #include <linux/delay.h>
126 #include <linux/blkdev.h>
127 #include <linux/interrupt.h>
128 #include <linux/pci.h>
129 #include <linux/init.h>
130 #include <linux/ide.h>
131 #include <linux/slab.h>
132
133 #include <linux/uaccess.h>
134 #include <asm/io.h>
135
136 #define DRV_NAME "hpt366"
137
138 /* various tuning parameters */
139 #undef HPT_RESET_STATE_ENGINE
140 #undef HPT_DELAY_INTERRUPT
141
142 static const char *bad_ata100_5[] = {
143 "IBM-DTLA-307075",
144 "IBM-DTLA-307060",
145 "IBM-DTLA-307045",
146 "IBM-DTLA-307030",
147 "IBM-DTLA-307020",
148 "IBM-DTLA-307015",
149 "IBM-DTLA-305040",
150 "IBM-DTLA-305030",
151 "IBM-DTLA-305020",
152 "IC35L010AVER07-0",
153 "IC35L020AVER07-0",
154 "IC35L030AVER07-0",
155 "IC35L040AVER07-0",
156 "IC35L060AVER07-0",
157 "WDC AC310200R",
158 NULL
159 };
160
161 static const char *bad_ata66_4[] = {
162 "IBM-DTLA-307075",
163 "IBM-DTLA-307060",
164 "IBM-DTLA-307045",
165 "IBM-DTLA-307030",
166 "IBM-DTLA-307020",
167 "IBM-DTLA-307015",
168 "IBM-DTLA-305040",
169 "IBM-DTLA-305030",
170 "IBM-DTLA-305020",
171 "IC35L010AVER07-0",
172 "IC35L020AVER07-0",
173 "IC35L030AVER07-0",
174 "IC35L040AVER07-0",
175 "IC35L060AVER07-0",
176 "WDC AC310200R",
177 "MAXTOR STM3320620A",
178 NULL
179 };
180
181 static const char *bad_ata66_3[] = {
182 "WDC AC310200R",
183 NULL
184 };
185
186 static const char *bad_ata33[] = {
187 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
188 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
189 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
190 "Maxtor 90510D4",
191 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
192 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
193 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
194 NULL
195 };
196
197 static u8 xfer_speeds[] = {
198 XFER_UDMA_6,
199 XFER_UDMA_5,
200 XFER_UDMA_4,
201 XFER_UDMA_3,
202 XFER_UDMA_2,
203 XFER_UDMA_1,
204 XFER_UDMA_0,
205
206 XFER_MW_DMA_2,
207 XFER_MW_DMA_1,
208 XFER_MW_DMA_0,
209
210 XFER_PIO_4,
211 XFER_PIO_3,
212 XFER_PIO_2,
213 XFER_PIO_1,
214 XFER_PIO_0
215 };
216
217 /* Key for bus clock timings
218 * 36x 37x
219 * bits bits
220 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
221 * cycles = value + 1
222 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
223 * cycles = value + 1
224 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
225 * register access.
226 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
227 * register access.
228 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
229 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
230 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
231 * MW DMA xfer.
232 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
233 * task file register access.
234 * 28 28 UDMA enable.
235 * 29 29 DMA enable.
236 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
237 * PIO xfer.
238 * 31 31 FIFO enable.
239 */
240
241 static u32 forty_base_hpt36x[] = {
242 /* XFER_UDMA_6 */ 0x900fd943,
243 /* XFER_UDMA_5 */ 0x900fd943,
244 /* XFER_UDMA_4 */ 0x900fd943,
245 /* XFER_UDMA_3 */ 0x900ad943,
246 /* XFER_UDMA_2 */ 0x900bd943,
247 /* XFER_UDMA_1 */ 0x9008d943,
248 /* XFER_UDMA_0 */ 0x9008d943,
249
250 /* XFER_MW_DMA_2 */ 0xa008d943,
251 /* XFER_MW_DMA_1 */ 0xa010d955,
252 /* XFER_MW_DMA_0 */ 0xa010d9fc,
253
254 /* XFER_PIO_4 */ 0xc008d963,
255 /* XFER_PIO_3 */ 0xc010d974,
256 /* XFER_PIO_2 */ 0xc010d997,
257 /* XFER_PIO_1 */ 0xc010d9c7,
258 /* XFER_PIO_0 */ 0xc018d9d9
259 };
260
261 static u32 thirty_three_base_hpt36x[] = {
262 /* XFER_UDMA_6 */ 0x90c9a731,
263 /* XFER_UDMA_5 */ 0x90c9a731,
264 /* XFER_UDMA_4 */ 0x90c9a731,
265 /* XFER_UDMA_3 */ 0x90cfa731,
266 /* XFER_UDMA_2 */ 0x90caa731,
267 /* XFER_UDMA_1 */ 0x90cba731,
268 /* XFER_UDMA_0 */ 0x90c8a731,
269
270 /* XFER_MW_DMA_2 */ 0xa0c8a731,
271 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
272 /* XFER_MW_DMA_0 */ 0xa0c8a797,
273
274 /* XFER_PIO_4 */ 0xc0c8a731,
275 /* XFER_PIO_3 */ 0xc0c8a742,
276 /* XFER_PIO_2 */ 0xc0d0a753,
277 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
278 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
279 };
280
281 static u32 twenty_five_base_hpt36x[] = {
282 /* XFER_UDMA_6 */ 0x90c98521,
283 /* XFER_UDMA_5 */ 0x90c98521,
284 /* XFER_UDMA_4 */ 0x90c98521,
285 /* XFER_UDMA_3 */ 0x90cf8521,
286 /* XFER_UDMA_2 */ 0x90cf8521,
287 /* XFER_UDMA_1 */ 0x90cb8521,
288 /* XFER_UDMA_0 */ 0x90cb8521,
289
290 /* XFER_MW_DMA_2 */ 0xa0ca8521,
291 /* XFER_MW_DMA_1 */ 0xa0ca8532,
292 /* XFER_MW_DMA_0 */ 0xa0ca8575,
293
294 /* XFER_PIO_4 */ 0xc0ca8521,
295 /* XFER_PIO_3 */ 0xc0ca8532,
296 /* XFER_PIO_2 */ 0xc0ca8542,
297 /* XFER_PIO_1 */ 0xc0d08572,
298 /* XFER_PIO_0 */ 0xc0d08585
299 };
300
301 /*
302 * The following are the new timing tables with PIO mode data/taskfile transfer
303 * overclocking fixed...
304 */
305
306 /* This table is taken from the HPT370 data manual rev. 1.02 */
307 static u32 thirty_three_base_hpt37x[] = {
308 /* XFER_UDMA_6 */ 0x16455031, /* 0x16655031 ?? */
309 /* XFER_UDMA_5 */ 0x16455031,
310 /* XFER_UDMA_4 */ 0x16455031,
311 /* XFER_UDMA_3 */ 0x166d5031,
312 /* XFER_UDMA_2 */ 0x16495031,
313 /* XFER_UDMA_1 */ 0x164d5033,
314 /* XFER_UDMA_0 */ 0x16515097,
315
316 /* XFER_MW_DMA_2 */ 0x26515031,
317 /* XFER_MW_DMA_1 */ 0x26515033,
318 /* XFER_MW_DMA_0 */ 0x26515097,
319
320 /* XFER_PIO_4 */ 0x06515021,
321 /* XFER_PIO_3 */ 0x06515022,
322 /* XFER_PIO_2 */ 0x06515033,
323 /* XFER_PIO_1 */ 0x06915065,
324 /* XFER_PIO_0 */ 0x06d1508a
325 };
326
327 static u32 fifty_base_hpt37x[] = {
328 /* XFER_UDMA_6 */ 0x1a861842,
329 /* XFER_UDMA_5 */ 0x1a861842,
330 /* XFER_UDMA_4 */ 0x1aae1842,
331 /* XFER_UDMA_3 */ 0x1a8e1842,
332 /* XFER_UDMA_2 */ 0x1a0e1842,
333 /* XFER_UDMA_1 */ 0x1a161854,
334 /* XFER_UDMA_0 */ 0x1a1a18ea,
335
336 /* XFER_MW_DMA_2 */ 0x2a821842,
337 /* XFER_MW_DMA_1 */ 0x2a821854,
338 /* XFER_MW_DMA_0 */ 0x2a8218ea,
339
340 /* XFER_PIO_4 */ 0x0a821842,
341 /* XFER_PIO_3 */ 0x0a821843,
342 /* XFER_PIO_2 */ 0x0a821855,
343 /* XFER_PIO_1 */ 0x0ac218a8,
344 /* XFER_PIO_0 */ 0x0b02190c
345 };
346
347 static u32 sixty_six_base_hpt37x[] = {
348 /* XFER_UDMA_6 */ 0x1c86fe62,
349 /* XFER_UDMA_5 */ 0x1caefe62, /* 0x1c8afe62 */
350 /* XFER_UDMA_4 */ 0x1c8afe62,
351 /* XFER_UDMA_3 */ 0x1c8efe62,
352 /* XFER_UDMA_2 */ 0x1c92fe62,
353 /* XFER_UDMA_1 */ 0x1c9afe62,
354 /* XFER_UDMA_0 */ 0x1c82fe62,
355
356 /* XFER_MW_DMA_2 */ 0x2c82fe62,
357 /* XFER_MW_DMA_1 */ 0x2c82fe66,
358 /* XFER_MW_DMA_0 */ 0x2c82ff2e,
359
360 /* XFER_PIO_4 */ 0x0c82fe62,
361 /* XFER_PIO_3 */ 0x0c82fe84,
362 /* XFER_PIO_2 */ 0x0c82fea6,
363 /* XFER_PIO_1 */ 0x0d02ff26,
364 /* XFER_PIO_0 */ 0x0d42ff7f
365 };
366
367 #define HPT371_ALLOW_ATA133_6 1
368 #define HPT302_ALLOW_ATA133_6 1
369 #define HPT372_ALLOW_ATA133_6 1
370 #define HPT370_ALLOW_ATA100_5 0
371 #define HPT366_ALLOW_ATA66_4 1
372 #define HPT366_ALLOW_ATA66_3 1
373
374 /* Supported ATA clock frequencies */
375 enum ata_clock {
376 ATA_CLOCK_25MHZ,
377 ATA_CLOCK_33MHZ,
378 ATA_CLOCK_40MHZ,
379 ATA_CLOCK_50MHZ,
380 ATA_CLOCK_66MHZ,
381 NUM_ATA_CLOCKS
382 };
383
384 struct hpt_timings {
385 u32 pio_mask;
386 u32 dma_mask;
387 u32 ultra_mask;
388 u32 *clock_table[NUM_ATA_CLOCKS];
389 };
390
391 /*
392 * Hold all the HighPoint chip information in one place.
393 */
394
395 struct hpt_info {
396 char *chip_name; /* Chip name */
397 u8 chip_type; /* Chip type */
398 u8 udma_mask; /* Allowed UltraDMA modes mask. */
399 u8 dpll_clk; /* DPLL clock in MHz */
400 u8 pci_clk; /* PCI clock in MHz */
401 struct hpt_timings *timings; /* Chipset timing data */
402 u8 clock; /* ATA clock selected */
403 };
404
405 /* Supported HighPoint chips */
406 enum {
407 HPT36x,
408 HPT370,
409 HPT370A,
410 HPT374,
411 HPT372,
412 HPT372A,
413 HPT302,
414 HPT371,
415 HPT372N,
416 HPT302N,
417 HPT371N
418 };
419
420 static struct hpt_timings hpt36x_timings = {
421 .pio_mask = 0xc1f8ffff,
422 .dma_mask = 0x303800ff,
423 .ultra_mask = 0x30070000,
424 .clock_table = {
425 [ATA_CLOCK_25MHZ] = twenty_five_base_hpt36x,
426 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt36x,
427 [ATA_CLOCK_40MHZ] = forty_base_hpt36x,
428 [ATA_CLOCK_50MHZ] = NULL,
429 [ATA_CLOCK_66MHZ] = NULL
430 }
431 };
432
433 static struct hpt_timings hpt37x_timings = {
434 .pio_mask = 0xcfc3ffff,
435 .dma_mask = 0x31c001ff,
436 .ultra_mask = 0x303c0000,
437 .clock_table = {
438 [ATA_CLOCK_25MHZ] = NULL,
439 [ATA_CLOCK_33MHZ] = thirty_three_base_hpt37x,
440 [ATA_CLOCK_40MHZ] = NULL,
441 [ATA_CLOCK_50MHZ] = fifty_base_hpt37x,
442 [ATA_CLOCK_66MHZ] = sixty_six_base_hpt37x
443 }
444 };
445
446 static const struct hpt_info hpt36x = {
447 .chip_name = "HPT36x",
448 .chip_type = HPT36x,
449 .udma_mask = HPT366_ALLOW_ATA66_3 ? (HPT366_ALLOW_ATA66_4 ? ATA_UDMA4 : ATA_UDMA3) : ATA_UDMA2,
450 .dpll_clk = 0, /* no DPLL */
451 .timings = &hpt36x_timings
452 };
453
454 static const struct hpt_info hpt370 = {
455 .chip_name = "HPT370",
456 .chip_type = HPT370,
457 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
458 .dpll_clk = 48,
459 .timings = &hpt37x_timings
460 };
461
462 static const struct hpt_info hpt370a = {
463 .chip_name = "HPT370A",
464 .chip_type = HPT370A,
465 .udma_mask = HPT370_ALLOW_ATA100_5 ? ATA_UDMA5 : ATA_UDMA4,
466 .dpll_clk = 48,
467 .timings = &hpt37x_timings
468 };
469
470 static const struct hpt_info hpt374 = {
471 .chip_name = "HPT374",
472 .chip_type = HPT374,
473 .udma_mask = ATA_UDMA5,
474 .dpll_clk = 48,
475 .timings = &hpt37x_timings
476 };
477
478 static const struct hpt_info hpt372 = {
479 .chip_name = "HPT372",
480 .chip_type = HPT372,
481 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
482 .dpll_clk = 55,
483 .timings = &hpt37x_timings
484 };
485
486 static const struct hpt_info hpt372a = {
487 .chip_name = "HPT372A",
488 .chip_type = HPT372A,
489 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
490 .dpll_clk = 66,
491 .timings = &hpt37x_timings
492 };
493
494 static const struct hpt_info hpt302 = {
495 .chip_name = "HPT302",
496 .chip_type = HPT302,
497 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
498 .dpll_clk = 66,
499 .timings = &hpt37x_timings
500 };
501
502 static const struct hpt_info hpt371 = {
503 .chip_name = "HPT371",
504 .chip_type = HPT371,
505 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
506 .dpll_clk = 66,
507 .timings = &hpt37x_timings
508 };
509
510 static const struct hpt_info hpt372n = {
511 .chip_name = "HPT372N",
512 .chip_type = HPT372N,
513 .udma_mask = HPT372_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
514 .dpll_clk = 77,
515 .timings = &hpt37x_timings
516 };
517
518 static const struct hpt_info hpt302n = {
519 .chip_name = "HPT302N",
520 .chip_type = HPT302N,
521 .udma_mask = HPT302_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
522 .dpll_clk = 77,
523 .timings = &hpt37x_timings
524 };
525
526 static const struct hpt_info hpt371n = {
527 .chip_name = "HPT371N",
528 .chip_type = HPT371N,
529 .udma_mask = HPT371_ALLOW_ATA133_6 ? ATA_UDMA6 : ATA_UDMA5,
530 .dpll_clk = 77,
531 .timings = &hpt37x_timings
532 };
533
check_in_drive_list(ide_drive_t * drive,const char ** list)534 static bool check_in_drive_list(ide_drive_t *drive, const char **list)
535 {
536 return match_string(list, -1, (char *)&drive->id[ATA_ID_PROD]) >= 0;
537 }
538
hpt3xx_get_info(struct device * dev)539 static struct hpt_info *hpt3xx_get_info(struct device *dev)
540 {
541 struct ide_host *host = dev_get_drvdata(dev);
542 struct hpt_info *info = (struct hpt_info *)host->host_priv;
543
544 return dev == host->dev[1] ? info + 1 : info;
545 }
546
547 /*
548 * The Marvell bridge chips used on the HighPoint SATA cards do not seem
549 * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
550 */
551
hpt3xx_udma_filter(ide_drive_t * drive)552 static u8 hpt3xx_udma_filter(ide_drive_t *drive)
553 {
554 ide_hwif_t *hwif = drive->hwif;
555 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
556 u8 mask = hwif->ultra_mask;
557
558 switch (info->chip_type) {
559 case HPT36x:
560 if (!HPT366_ALLOW_ATA66_4 ||
561 check_in_drive_list(drive, bad_ata66_4))
562 mask = ATA_UDMA3;
563
564 if (!HPT366_ALLOW_ATA66_3 ||
565 check_in_drive_list(drive, bad_ata66_3))
566 mask = ATA_UDMA2;
567 break;
568 case HPT370:
569 if (!HPT370_ALLOW_ATA100_5 ||
570 check_in_drive_list(drive, bad_ata100_5))
571 mask = ATA_UDMA4;
572 break;
573 case HPT370A:
574 if (!HPT370_ALLOW_ATA100_5 ||
575 check_in_drive_list(drive, bad_ata100_5))
576 return ATA_UDMA4;
577 /* else: fall through */
578 case HPT372 :
579 case HPT372A:
580 case HPT372N:
581 case HPT374 :
582 if (ata_id_is_sata(drive->id))
583 mask &= ~0x0e;
584 /* fall through */
585 default:
586 return mask;
587 }
588
589 return check_in_drive_list(drive, bad_ata33) ? 0x00 : mask;
590 }
591
hpt3xx_mdma_filter(ide_drive_t * drive)592 static u8 hpt3xx_mdma_filter(ide_drive_t *drive)
593 {
594 ide_hwif_t *hwif = drive->hwif;
595 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
596
597 switch (info->chip_type) {
598 case HPT372 :
599 case HPT372A:
600 case HPT372N:
601 case HPT374 :
602 if (ata_id_is_sata(drive->id))
603 return 0x00;
604 /* else: fall through */
605 default:
606 return 0x07;
607 }
608 }
609
get_speed_setting(u8 speed,struct hpt_info * info)610 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
611 {
612 int i;
613
614 /*
615 * Lookup the transfer mode table to get the index into
616 * the timing table.
617 *
618 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
619 */
620 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
621 if (xfer_speeds[i] == speed)
622 break;
623
624 return info->timings->clock_table[info->clock][i];
625 }
626
hpt3xx_set_mode(ide_hwif_t * hwif,ide_drive_t * drive)627 static void hpt3xx_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
628 {
629 struct pci_dev *dev = to_pci_dev(hwif->dev);
630 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
631 struct hpt_timings *t = info->timings;
632 u8 itr_addr = 0x40 + (drive->dn * 4);
633 u32 old_itr = 0;
634 const u8 speed = drive->dma_mode;
635 u32 new_itr = get_speed_setting(speed, info);
636 u32 itr_mask = speed < XFER_MW_DMA_0 ? t->pio_mask :
637 (speed < XFER_UDMA_0 ? t->dma_mask :
638 t->ultra_mask);
639
640 pci_read_config_dword(dev, itr_addr, &old_itr);
641 new_itr = (old_itr & ~itr_mask) | (new_itr & itr_mask);
642 /*
643 * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
644 * to avoid problems handling I/O errors later
645 */
646 new_itr &= ~0xc0000000;
647
648 pci_write_config_dword(dev, itr_addr, new_itr);
649 }
650
hpt3xx_set_pio_mode(ide_hwif_t * hwif,ide_drive_t * drive)651 static void hpt3xx_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
652 {
653 drive->dma_mode = drive->pio_mode;
654 hpt3xx_set_mode(hwif, drive);
655 }
656
hpt3xx_maskproc(ide_drive_t * drive,int mask)657 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
658 {
659 ide_hwif_t *hwif = drive->hwif;
660 struct pci_dev *dev = to_pci_dev(hwif->dev);
661 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
662
663 if ((drive->dev_flags & IDE_DFLAG_NIEN_QUIRK) == 0)
664 return;
665
666 if (info->chip_type >= HPT370) {
667 u8 scr1 = 0;
668
669 pci_read_config_byte(dev, 0x5a, &scr1);
670 if (((scr1 & 0x10) >> 4) != mask) {
671 if (mask)
672 scr1 |= 0x10;
673 else
674 scr1 &= ~0x10;
675 pci_write_config_byte(dev, 0x5a, scr1);
676 }
677 } else if (mask)
678 disable_irq(hwif->irq);
679 else
680 enable_irq(hwif->irq);
681 }
682
683 /*
684 * This is specific to the HPT366 UDMA chipset
685 * by HighPoint|Triones Technologies, Inc.
686 */
hpt366_dma_lost_irq(ide_drive_t * drive)687 static void hpt366_dma_lost_irq(ide_drive_t *drive)
688 {
689 struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
690 u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
691
692 pci_read_config_byte(dev, 0x50, &mcr1);
693 pci_read_config_byte(dev, 0x52, &mcr3);
694 pci_read_config_byte(dev, 0x5a, &scr1);
695 printk("%s: (%s) mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
696 drive->name, __func__, mcr1, mcr3, scr1);
697 if (scr1 & 0x10)
698 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
699 ide_dma_lost_irq(drive);
700 }
701
hpt370_clear_engine(ide_drive_t * drive)702 static void hpt370_clear_engine(ide_drive_t *drive)
703 {
704 ide_hwif_t *hwif = drive->hwif;
705 struct pci_dev *dev = to_pci_dev(hwif->dev);
706
707 pci_write_config_byte(dev, hwif->select_data, 0x37);
708 udelay(10);
709 }
710
hpt370_irq_timeout(ide_drive_t * drive)711 static void hpt370_irq_timeout(ide_drive_t *drive)
712 {
713 ide_hwif_t *hwif = drive->hwif;
714 struct pci_dev *dev = to_pci_dev(hwif->dev);
715 u16 bfifo = 0;
716 u8 dma_cmd;
717
718 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
719 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
720
721 /* get DMA command mode */
722 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
723 /* stop DMA */
724 outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
725 hpt370_clear_engine(drive);
726 }
727
hpt370_dma_start(ide_drive_t * drive)728 static void hpt370_dma_start(ide_drive_t *drive)
729 {
730 #ifdef HPT_RESET_STATE_ENGINE
731 hpt370_clear_engine(drive);
732 #endif
733 ide_dma_start(drive);
734 }
735
hpt370_dma_end(ide_drive_t * drive)736 static int hpt370_dma_end(ide_drive_t *drive)
737 {
738 ide_hwif_t *hwif = drive->hwif;
739 u8 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
740
741 if (dma_stat & ATA_DMA_ACTIVE) {
742 /* wait a little */
743 udelay(20);
744 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
745 if (dma_stat & ATA_DMA_ACTIVE)
746 hpt370_irq_timeout(drive);
747 }
748 return ide_dma_end(drive);
749 }
750
751 /* returns 1 if DMA IRQ issued, 0 otherwise */
hpt374_dma_test_irq(ide_drive_t * drive)752 static int hpt374_dma_test_irq(ide_drive_t *drive)
753 {
754 ide_hwif_t *hwif = drive->hwif;
755 struct pci_dev *dev = to_pci_dev(hwif->dev);
756 u16 bfifo = 0;
757 u8 dma_stat;
758
759 pci_read_config_word(dev, hwif->select_data + 2, &bfifo);
760 if (bfifo & 0x1FF) {
761 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
762 return 0;
763 }
764
765 dma_stat = inb(hwif->dma_base + ATA_DMA_STATUS);
766 /* return 1 if INTR asserted */
767 if (dma_stat & ATA_DMA_INTR)
768 return 1;
769
770 return 0;
771 }
772
hpt374_dma_end(ide_drive_t * drive)773 static int hpt374_dma_end(ide_drive_t *drive)
774 {
775 ide_hwif_t *hwif = drive->hwif;
776 struct pci_dev *dev = to_pci_dev(hwif->dev);
777 u8 mcr = 0, mcr_addr = hwif->select_data;
778 u8 bwsr = 0, mask = hwif->channel ? 0x02 : 0x01;
779
780 pci_read_config_byte(dev, 0x6a, &bwsr);
781 pci_read_config_byte(dev, mcr_addr, &mcr);
782 if (bwsr & mask)
783 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
784 return ide_dma_end(drive);
785 }
786
787 /**
788 * hpt3xxn_set_clock - perform clock switching dance
789 * @hwif: hwif to switch
790 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
791 *
792 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
793 */
794
hpt3xxn_set_clock(ide_hwif_t * hwif,u8 mode)795 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
796 {
797 unsigned long base = hwif->extra_base;
798 u8 scr2 = inb(base + 0x6b);
799
800 if ((scr2 & 0x7f) == mode)
801 return;
802
803 /* Tristate the bus */
804 outb(0x80, base + 0x63);
805 outb(0x80, base + 0x67);
806
807 /* Switch clock and reset channels */
808 outb(mode, base + 0x6b);
809 outb(0xc0, base + 0x69);
810
811 /*
812 * Reset the state machines.
813 * NOTE: avoid accidentally enabling the disabled channels.
814 */
815 outb(inb(base + 0x60) | 0x32, base + 0x60);
816 outb(inb(base + 0x64) | 0x32, base + 0x64);
817
818 /* Complete reset */
819 outb(0x00, base + 0x69);
820
821 /* Reconnect channels to bus */
822 outb(0x00, base + 0x63);
823 outb(0x00, base + 0x67);
824 }
825
826 /**
827 * hpt3xxn_rw_disk - prepare for I/O
828 * @drive: drive for command
829 * @rq: block request structure
830 *
831 * This is called when a disk I/O is issued to HPT3xxN.
832 * We need it because of the clock switching.
833 */
834
hpt3xxn_rw_disk(ide_drive_t * drive,struct request * rq)835 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
836 {
837 hpt3xxn_set_clock(drive->hwif, rq_data_dir(rq) ? 0x21 : 0x23);
838 }
839
840 /**
841 * hpt37x_calibrate_dpll - calibrate the DPLL
842 * @dev: PCI device
843 *
844 * Perform a calibration cycle on the DPLL.
845 * Returns 1 if this succeeds
846 */
hpt37x_calibrate_dpll(struct pci_dev * dev,u16 f_low,u16 f_high)847 static int hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
848 {
849 u32 dpll = (f_high << 16) | f_low | 0x100;
850 u8 scr2;
851 int i;
852
853 pci_write_config_dword(dev, 0x5c, dpll);
854
855 /* Wait for oscillator ready */
856 for(i = 0; i < 0x5000; ++i) {
857 udelay(50);
858 pci_read_config_byte(dev, 0x5b, &scr2);
859 if (scr2 & 0x80)
860 break;
861 }
862 /* See if it stays ready (we'll just bail out if it's not yet) */
863 for(i = 0; i < 0x1000; ++i) {
864 pci_read_config_byte(dev, 0x5b, &scr2);
865 /* DPLL destabilized? */
866 if(!(scr2 & 0x80))
867 return 0;
868 }
869 /* Turn off tuning, we have the DPLL set */
870 pci_read_config_dword (dev, 0x5c, &dpll);
871 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
872 return 1;
873 }
874
hpt3xx_disable_fast_irq(struct pci_dev * dev,u8 mcr_addr)875 static void hpt3xx_disable_fast_irq(struct pci_dev *dev, u8 mcr_addr)
876 {
877 struct ide_host *host = pci_get_drvdata(dev);
878 struct hpt_info *info = host->host_priv + (&dev->dev == host->dev[1]);
879 u8 chip_type = info->chip_type;
880 u8 new_mcr, old_mcr = 0;
881
882 /*
883 * Disable the "fast interrupt" prediction. Don't hold off
884 * on interrupts. (== 0x01 despite what the docs say)
885 */
886 pci_read_config_byte(dev, mcr_addr + 1, &old_mcr);
887
888 if (chip_type >= HPT374)
889 new_mcr = old_mcr & ~0x07;
890 else if (chip_type >= HPT370) {
891 new_mcr = old_mcr;
892 new_mcr &= ~0x02;
893 #ifdef HPT_DELAY_INTERRUPT
894 new_mcr &= ~0x01;
895 #else
896 new_mcr |= 0x01;
897 #endif
898 } else /* HPT366 and HPT368 */
899 new_mcr = old_mcr & ~0x80;
900
901 if (new_mcr != old_mcr)
902 pci_write_config_byte(dev, mcr_addr + 1, new_mcr);
903 }
904
init_chipset_hpt366(struct pci_dev * dev)905 static int init_chipset_hpt366(struct pci_dev *dev)
906 {
907 unsigned long io_base = pci_resource_start(dev, 4);
908 struct hpt_info *info = hpt3xx_get_info(&dev->dev);
909 const char *name = DRV_NAME;
910 u8 pci_clk, dpll_clk = 0; /* PCI and DPLL clock in MHz */
911 u8 chip_type;
912 enum ata_clock clock;
913
914 chip_type = info->chip_type;
915
916 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
917 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
918 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
919 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
920
921 /*
922 * First, try to estimate the PCI clock frequency...
923 */
924 if (chip_type >= HPT370) {
925 u8 scr1 = 0;
926 u16 f_cnt = 0;
927 u32 temp = 0;
928
929 /* Interrupt force enable. */
930 pci_read_config_byte(dev, 0x5a, &scr1);
931 if (scr1 & 0x10)
932 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
933
934 /*
935 * HighPoint does this for HPT372A.
936 * NOTE: This register is only writeable via I/O space.
937 */
938 if (chip_type == HPT372A)
939 outb(0x0e, io_base + 0x9c);
940
941 /*
942 * Default to PCI clock. Make sure MA15/16 are set to output
943 * to prevent drives having problems with 40-pin cables.
944 */
945 pci_write_config_byte(dev, 0x5b, 0x23);
946
947 /*
948 * We'll have to read f_CNT value in order to determine
949 * the PCI clock frequency according to the following ratio:
950 *
951 * f_CNT = Fpci * 192 / Fdpll
952 *
953 * First try reading the register in which the HighPoint BIOS
954 * saves f_CNT value before reprogramming the DPLL from its
955 * default setting (which differs for the various chips).
956 *
957 * NOTE: This register is only accessible via I/O space;
958 * HPT374 BIOS only saves it for the function 0, so we have to
959 * always read it from there -- no need to check the result of
960 * pci_get_slot() for the function 0 as the whole device has
961 * been already "pinned" (via function 1) in init_setup_hpt374()
962 */
963 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
964 struct pci_dev *dev1 = pci_get_slot(dev->bus,
965 dev->devfn - 1);
966 unsigned long io_base = pci_resource_start(dev1, 4);
967
968 temp = inl(io_base + 0x90);
969 pci_dev_put(dev1);
970 } else
971 temp = inl(io_base + 0x90);
972
973 /*
974 * In case the signature check fails, we'll have to
975 * resort to reading the f_CNT register itself in hopes
976 * that nobody has touched the DPLL yet...
977 */
978 if ((temp & 0xFFFFF000) != 0xABCDE000) {
979 int i;
980
981 printk(KERN_WARNING "%s %s: no clock data saved by "
982 "BIOS\n", name, pci_name(dev));
983
984 /* Calculate the average value of f_CNT. */
985 for (temp = i = 0; i < 128; i++) {
986 pci_read_config_word(dev, 0x78, &f_cnt);
987 temp += f_cnt & 0x1ff;
988 mdelay(1);
989 }
990 f_cnt = temp / 128;
991 } else
992 f_cnt = temp & 0x1ff;
993
994 dpll_clk = info->dpll_clk;
995 pci_clk = (f_cnt * dpll_clk) / 192;
996
997 /* Clamp PCI clock to bands. */
998 if (pci_clk < 40)
999 pci_clk = 33;
1000 else if(pci_clk < 45)
1001 pci_clk = 40;
1002 else if(pci_clk < 55)
1003 pci_clk = 50;
1004 else
1005 pci_clk = 66;
1006
1007 printk(KERN_INFO "%s %s: DPLL base: %d MHz, f_CNT: %d, "
1008 "assuming %d MHz PCI\n", name, pci_name(dev),
1009 dpll_clk, f_cnt, pci_clk);
1010 } else {
1011 u32 itr1 = 0;
1012
1013 pci_read_config_dword(dev, 0x40, &itr1);
1014
1015 /* Detect PCI clock by looking at cmd_high_time. */
1016 switch ((itr1 >> 8) & 0x0f) {
1017 case 0x09:
1018 pci_clk = 40;
1019 break;
1020 case 0x05:
1021 pci_clk = 25;
1022 break;
1023 case 0x07:
1024 default:
1025 pci_clk = 33;
1026 break;
1027 }
1028 }
1029
1030 /* Let's assume we'll use PCI clock for the ATA clock... */
1031 switch (pci_clk) {
1032 case 25:
1033 clock = ATA_CLOCK_25MHZ;
1034 break;
1035 case 33:
1036 default:
1037 clock = ATA_CLOCK_33MHZ;
1038 break;
1039 case 40:
1040 clock = ATA_CLOCK_40MHZ;
1041 break;
1042 case 50:
1043 clock = ATA_CLOCK_50MHZ;
1044 break;
1045 case 66:
1046 clock = ATA_CLOCK_66MHZ;
1047 break;
1048 }
1049
1050 /*
1051 * Only try the DPLL if we don't have a table for the PCI clock that
1052 * we are running at for HPT370/A, always use it for anything newer...
1053 *
1054 * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1055 * We also don't like using the DPLL because this causes glitches
1056 * on PRST-/SRST- when the state engine gets reset...
1057 */
1058 if (chip_type >= HPT374 || info->timings->clock_table[clock] == NULL) {
1059 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1060 int adjust;
1061
1062 /*
1063 * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1064 * supported/enabled, use 50 MHz DPLL clock otherwise...
1065 */
1066 if (info->udma_mask == ATA_UDMA6) {
1067 dpll_clk = 66;
1068 clock = ATA_CLOCK_66MHZ;
1069 } else if (dpll_clk) { /* HPT36x chips don't have DPLL */
1070 dpll_clk = 50;
1071 clock = ATA_CLOCK_50MHZ;
1072 }
1073
1074 if (info->timings->clock_table[clock] == NULL) {
1075 printk(KERN_ERR "%s %s: unknown bus timing!\n",
1076 name, pci_name(dev));
1077 return -EIO;
1078 }
1079
1080 /* Select the DPLL clock. */
1081 pci_write_config_byte(dev, 0x5b, 0x21);
1082
1083 /*
1084 * Adjust the DPLL based upon PCI clock, enable it,
1085 * and wait for stabilization...
1086 */
1087 f_low = (pci_clk * 48) / dpll_clk;
1088
1089 for (adjust = 0; adjust < 8; adjust++) {
1090 if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1091 break;
1092
1093 /*
1094 * See if it'll settle at a fractionally different clock
1095 */
1096 if (adjust & 1)
1097 f_low -= adjust >> 1;
1098 else
1099 f_low += adjust >> 1;
1100 }
1101 if (adjust == 8) {
1102 printk(KERN_ERR "%s %s: DPLL did not stabilize!\n",
1103 name, pci_name(dev));
1104 return -EIO;
1105 }
1106
1107 printk(KERN_INFO "%s %s: using %d MHz DPLL clock\n",
1108 name, pci_name(dev), dpll_clk);
1109 } else {
1110 /* Mark the fact that we're not using the DPLL. */
1111 dpll_clk = 0;
1112
1113 printk(KERN_INFO "%s %s: using %d MHz PCI clock\n",
1114 name, pci_name(dev), pci_clk);
1115 }
1116
1117 /* Store the clock frequencies. */
1118 info->dpll_clk = dpll_clk;
1119 info->pci_clk = pci_clk;
1120 info->clock = clock;
1121
1122 if (chip_type >= HPT370) {
1123 u8 mcr1, mcr4;
1124
1125 /*
1126 * Reset the state engines.
1127 * NOTE: Avoid accidentally enabling the disabled channels.
1128 */
1129 pci_read_config_byte (dev, 0x50, &mcr1);
1130 pci_read_config_byte (dev, 0x54, &mcr4);
1131 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1132 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1133 udelay(100);
1134 }
1135
1136 /*
1137 * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1138 * the MISC. register to stretch the UltraDMA Tss timing.
1139 * NOTE: This register is only writeable via I/O space.
1140 */
1141 if (chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1142 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1143
1144 hpt3xx_disable_fast_irq(dev, 0x50);
1145 hpt3xx_disable_fast_irq(dev, 0x54);
1146
1147 return 0;
1148 }
1149
hpt3xx_cable_detect(ide_hwif_t * hwif)1150 static u8 hpt3xx_cable_detect(ide_hwif_t *hwif)
1151 {
1152 struct pci_dev *dev = to_pci_dev(hwif->dev);
1153 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1154 u8 chip_type = info->chip_type;
1155 u8 scr1 = 0, ata66 = hwif->channel ? 0x01 : 0x02;
1156
1157 /*
1158 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1159 * address lines to access an external EEPROM. To read valid
1160 * cable detect state the pins must be enabled as inputs.
1161 */
1162 if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1163 /*
1164 * HPT374 PCI function 1
1165 * - set bit 15 of reg 0x52 to enable TCBLID as input
1166 * - set bit 15 of reg 0x56 to enable FCBLID as input
1167 */
1168 u8 mcr_addr = hwif->select_data + 2;
1169 u16 mcr;
1170
1171 pci_read_config_word(dev, mcr_addr, &mcr);
1172 pci_write_config_word(dev, mcr_addr, mcr | 0x8000);
1173 /* Debounce, then read cable ID register */
1174 udelay(10);
1175 pci_read_config_byte(dev, 0x5a, &scr1);
1176 pci_write_config_word(dev, mcr_addr, mcr);
1177 } else if (chip_type >= HPT370) {
1178 /*
1179 * HPT370/372 and 374 pcifn 0
1180 * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1181 */
1182 u8 scr2 = 0;
1183
1184 pci_read_config_byte(dev, 0x5b, &scr2);
1185 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1186 /* Debounce, then read cable ID register */
1187 udelay(10);
1188 pci_read_config_byte(dev, 0x5a, &scr1);
1189 pci_write_config_byte(dev, 0x5b, scr2);
1190 } else
1191 pci_read_config_byte(dev, 0x5a, &scr1);
1192
1193 return (scr1 & ata66) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
1194 }
1195
init_hwif_hpt366(ide_hwif_t * hwif)1196 static void init_hwif_hpt366(ide_hwif_t *hwif)
1197 {
1198 struct hpt_info *info = hpt3xx_get_info(hwif->dev);
1199 u8 chip_type = info->chip_type;
1200
1201 /* Cache the channel's MISC. control registers' offset */
1202 hwif->select_data = hwif->channel ? 0x54 : 0x50;
1203
1204 /*
1205 * HPT3xxN chips have some complications:
1206 *
1207 * - on 33 MHz PCI we must clock switch
1208 * - on 66 MHz PCI we must NOT use the PCI clock
1209 */
1210 if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1211 /*
1212 * Clock is shared between the channels,
1213 * so we'll have to serialize them... :-(
1214 */
1215 hwif->host->host_flags |= IDE_HFLAG_SERIALIZE;
1216 hwif->rw_disk = &hpt3xxn_rw_disk;
1217 }
1218 }
1219
init_dma_hpt366(ide_hwif_t * hwif,const struct ide_port_info * d)1220 static int init_dma_hpt366(ide_hwif_t *hwif,
1221 const struct ide_port_info *d)
1222 {
1223 struct pci_dev *dev = to_pci_dev(hwif->dev);
1224 unsigned long flags, base = ide_pci_dma_base(hwif, d);
1225 u8 dma_old, dma_new, masterdma = 0, slavedma = 0;
1226
1227 if (base == 0)
1228 return -1;
1229
1230 hwif->dma_base = base;
1231
1232 if (ide_pci_check_simplex(hwif, d) < 0)
1233 return -1;
1234
1235 if (ide_pci_set_master(dev, d->name) < 0)
1236 return -1;
1237
1238 dma_old = inb(base + 2);
1239
1240 local_irq_save(flags);
1241
1242 dma_new = dma_old;
1243 pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1244 pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47, &slavedma);
1245
1246 if (masterdma & 0x30) dma_new |= 0x20;
1247 if ( slavedma & 0x30) dma_new |= 0x40;
1248 if (dma_new != dma_old)
1249 outb(dma_new, base + 2);
1250
1251 local_irq_restore(flags);
1252
1253 printk(KERN_INFO " %s: BM-DMA at 0x%04lx-0x%04lx\n",
1254 hwif->name, base, base + 7);
1255
1256 hwif->extra_base = base + (hwif->channel ? 8 : 16);
1257
1258 if (ide_allocate_dma_engine(hwif))
1259 return -1;
1260
1261 return 0;
1262 }
1263
hpt374_init(struct pci_dev * dev,struct pci_dev * dev2)1264 static void hpt374_init(struct pci_dev *dev, struct pci_dev *dev2)
1265 {
1266 if (dev2->irq != dev->irq) {
1267 /* FIXME: we need a core pci_set_interrupt() */
1268 dev2->irq = dev->irq;
1269 printk(KERN_INFO DRV_NAME " %s: PCI config space interrupt "
1270 "fixed\n", pci_name(dev2));
1271 }
1272 }
1273
hpt371_init(struct pci_dev * dev)1274 static void hpt371_init(struct pci_dev *dev)
1275 {
1276 u8 mcr1 = 0;
1277
1278 /*
1279 * HPT371 chips physically have only one channel, the secondary one,
1280 * but the primary channel registers do exist! Go figure...
1281 * So, we manually disable the non-existing channel here
1282 * (if the BIOS hasn't done this already).
1283 */
1284 pci_read_config_byte(dev, 0x50, &mcr1);
1285 if (mcr1 & 0x04)
1286 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1287 }
1288
hpt36x_init(struct pci_dev * dev,struct pci_dev * dev2)1289 static int hpt36x_init(struct pci_dev *dev, struct pci_dev *dev2)
1290 {
1291 u8 mcr1 = 0, pin1 = 0, pin2 = 0;
1292
1293 /*
1294 * Now we'll have to force both channels enabled if
1295 * at least one of them has been enabled by BIOS...
1296 */
1297 pci_read_config_byte(dev, 0x50, &mcr1);
1298 if (mcr1 & 0x30)
1299 pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
1300
1301 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1302 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1303
1304 if (pin1 != pin2 && dev->irq == dev2->irq) {
1305 printk(KERN_INFO DRV_NAME " %s: onboard version of chipset, "
1306 "pin1=%d pin2=%d\n", pci_name(dev), pin1, pin2);
1307 return 1;
1308 }
1309
1310 return 0;
1311 }
1312
1313 #define IDE_HFLAGS_HPT3XX \
1314 (IDE_HFLAG_NO_ATAPI_DMA | \
1315 IDE_HFLAG_OFF_BOARD)
1316
1317 static const struct ide_port_ops hpt3xx_port_ops = {
1318 .set_pio_mode = hpt3xx_set_pio_mode,
1319 .set_dma_mode = hpt3xx_set_mode,
1320 .maskproc = hpt3xx_maskproc,
1321 .mdma_filter = hpt3xx_mdma_filter,
1322 .udma_filter = hpt3xx_udma_filter,
1323 .cable_detect = hpt3xx_cable_detect,
1324 };
1325
1326 static const struct ide_dma_ops hpt37x_dma_ops = {
1327 .dma_host_set = ide_dma_host_set,
1328 .dma_setup = ide_dma_setup,
1329 .dma_start = ide_dma_start,
1330 .dma_end = hpt374_dma_end,
1331 .dma_test_irq = hpt374_dma_test_irq,
1332 .dma_lost_irq = ide_dma_lost_irq,
1333 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1334 .dma_sff_read_status = ide_dma_sff_read_status,
1335 };
1336
1337 static const struct ide_dma_ops hpt370_dma_ops = {
1338 .dma_host_set = ide_dma_host_set,
1339 .dma_setup = ide_dma_setup,
1340 .dma_start = hpt370_dma_start,
1341 .dma_end = hpt370_dma_end,
1342 .dma_test_irq = ide_dma_test_irq,
1343 .dma_lost_irq = ide_dma_lost_irq,
1344 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1345 .dma_clear = hpt370_irq_timeout,
1346 .dma_sff_read_status = ide_dma_sff_read_status,
1347 };
1348
1349 static const struct ide_dma_ops hpt36x_dma_ops = {
1350 .dma_host_set = ide_dma_host_set,
1351 .dma_setup = ide_dma_setup,
1352 .dma_start = ide_dma_start,
1353 .dma_end = ide_dma_end,
1354 .dma_test_irq = ide_dma_test_irq,
1355 .dma_lost_irq = hpt366_dma_lost_irq,
1356 .dma_timer_expiry = ide_dma_sff_timer_expiry,
1357 .dma_sff_read_status = ide_dma_sff_read_status,
1358 };
1359
1360 static const struct ide_port_info hpt366_chipsets[] = {
1361 { /* 0: HPT36x */
1362 .name = DRV_NAME,
1363 .init_chipset = init_chipset_hpt366,
1364 .init_hwif = init_hwif_hpt366,
1365 .init_dma = init_dma_hpt366,
1366 /*
1367 * HPT36x chips have one channel per function and have
1368 * both channel enable bits located differently and visible
1369 * to both functions -- really stupid design decision... :-(
1370 * Bit 4 is for the primary channel, bit 5 for the secondary.
1371 */
1372 .enablebits = {{0x50,0x10,0x10}, {0x54,0x04,0x04}},
1373 .port_ops = &hpt3xx_port_ops,
1374 .dma_ops = &hpt36x_dma_ops,
1375 .host_flags = IDE_HFLAGS_HPT3XX | IDE_HFLAG_SINGLE,
1376 .pio_mask = ATA_PIO4,
1377 .mwdma_mask = ATA_MWDMA2,
1378 },
1379 { /* 1: HPT3xx */
1380 .name = DRV_NAME,
1381 .init_chipset = init_chipset_hpt366,
1382 .init_hwif = init_hwif_hpt366,
1383 .init_dma = init_dma_hpt366,
1384 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1385 .port_ops = &hpt3xx_port_ops,
1386 .dma_ops = &hpt37x_dma_ops,
1387 .host_flags = IDE_HFLAGS_HPT3XX,
1388 .pio_mask = ATA_PIO4,
1389 .mwdma_mask = ATA_MWDMA2,
1390 }
1391 };
1392
1393 /**
1394 * hpt366_init_one - called when an HPT366 is found
1395 * @dev: the hpt366 device
1396 * @id: the matching pci id
1397 *
1398 * Called when the PCI registration layer (or the IDE initialization)
1399 * finds a device matching our IDE device tables.
1400 */
hpt366_init_one(struct pci_dev * dev,const struct pci_device_id * id)1401 static int hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1402 {
1403 const struct hpt_info *info = NULL;
1404 struct hpt_info *dyn_info;
1405 struct pci_dev *dev2 = NULL;
1406 struct ide_port_info d;
1407 u8 idx = id->driver_data;
1408 u8 rev = dev->revision;
1409 int ret;
1410
1411 if ((idx == 0 || idx == 4) && (PCI_FUNC(dev->devfn) & 1))
1412 return -ENODEV;
1413
1414 switch (idx) {
1415 case 0:
1416 if (rev < 3)
1417 info = &hpt36x;
1418 else {
1419 switch (min_t(u8, rev, 6)) {
1420 case 3: info = &hpt370; break;
1421 case 4: info = &hpt370a; break;
1422 case 5: info = &hpt372; break;
1423 case 6: info = &hpt372n; break;
1424 }
1425 idx++;
1426 }
1427 break;
1428 case 1:
1429 info = (rev > 1) ? &hpt372n : &hpt372a;
1430 break;
1431 case 2:
1432 info = (rev > 1) ? &hpt302n : &hpt302;
1433 break;
1434 case 3:
1435 hpt371_init(dev);
1436 info = (rev > 1) ? &hpt371n : &hpt371;
1437 break;
1438 case 4:
1439 info = &hpt374;
1440 break;
1441 case 5:
1442 info = &hpt372n;
1443 break;
1444 }
1445
1446 printk(KERN_INFO DRV_NAME ": %s chipset detected\n", info->chip_name);
1447
1448 d = hpt366_chipsets[min_t(u8, idx, 1)];
1449
1450 d.udma_mask = info->udma_mask;
1451
1452 /* fixup ->dma_ops for HPT370/HPT370A */
1453 if (info == &hpt370 || info == &hpt370a)
1454 d.dma_ops = &hpt370_dma_ops;
1455
1456 if (info == &hpt36x || info == &hpt374)
1457 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
1458
1459 dyn_info = kcalloc(dev2 ? 2 : 1, sizeof(*dyn_info), GFP_KERNEL);
1460 if (dyn_info == NULL) {
1461 printk(KERN_ERR "%s %s: out of memory!\n",
1462 d.name, pci_name(dev));
1463 pci_dev_put(dev2);
1464 return -ENOMEM;
1465 }
1466
1467 /*
1468 * Copy everything from a static "template" structure
1469 * to just allocated per-chip hpt_info structure.
1470 */
1471 memcpy(dyn_info, info, sizeof(*dyn_info));
1472
1473 if (dev2) {
1474 memcpy(dyn_info + 1, info, sizeof(*dyn_info));
1475
1476 if (info == &hpt374)
1477 hpt374_init(dev, dev2);
1478 else {
1479 if (hpt36x_init(dev, dev2))
1480 d.host_flags &= ~IDE_HFLAG_NON_BOOTABLE;
1481 }
1482
1483 ret = ide_pci_init_two(dev, dev2, &d, dyn_info);
1484 if (ret < 0) {
1485 pci_dev_put(dev2);
1486 kfree(dyn_info);
1487 }
1488 return ret;
1489 }
1490
1491 ret = ide_pci_init_one(dev, &d, dyn_info);
1492 if (ret < 0)
1493 kfree(dyn_info);
1494
1495 return ret;
1496 }
1497
hpt366_remove(struct pci_dev * dev)1498 static void hpt366_remove(struct pci_dev *dev)
1499 {
1500 struct ide_host *host = pci_get_drvdata(dev);
1501 struct ide_info *info = host->host_priv;
1502 struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
1503
1504 ide_pci_remove(dev);
1505 pci_dev_put(dev2);
1506 kfree(info);
1507 }
1508
1509 static const struct pci_device_id hpt366_pci_tbl[] = {
1510 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), 0 },
1511 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), 1 },
1512 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), 2 },
1513 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), 3 },
1514 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT374), 4 },
1515 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), 5 },
1516 { 0, },
1517 };
1518 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1519
1520 static struct pci_driver hpt366_pci_driver = {
1521 .name = "HPT366_IDE",
1522 .id_table = hpt366_pci_tbl,
1523 .probe = hpt366_init_one,
1524 .remove = hpt366_remove,
1525 .suspend = ide_pci_suspend,
1526 .resume = ide_pci_resume,
1527 };
1528
hpt366_ide_init(void)1529 static int __init hpt366_ide_init(void)
1530 {
1531 return ide_pci_register_driver(&hpt366_pci_driver);
1532 }
1533
hpt366_ide_exit(void)1534 static void __exit hpt366_ide_exit(void)
1535 {
1536 pci_unregister_driver(&hpt366_pci_driver);
1537 }
1538
1539 module_init(hpt366_ide_init);
1540 module_exit(hpt366_ide_exit);
1541
1542 MODULE_AUTHOR("Andre Hedrick");
1543 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1544 MODULE_LICENSE("GPL");
1545
