1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include "hns_roce_hem.h"
43
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,const u8 * addr)44 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
45 const u8 *addr)
46 {
47 u8 phy_port;
48 u32 i;
49
50 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
51 return 0;
52
53 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
54 return 0;
55
56 for (i = 0; i < ETH_ALEN; i++)
57 hr_dev->dev_addr[port][i] = addr[i];
58
59 phy_port = hr_dev->iboe.phy_port[port];
60 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
61 }
62
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)63 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
64 {
65 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
66 u32 port = attr->port_num - 1;
67 int ret;
68
69 if (port >= hr_dev->caps.num_ports)
70 return -EINVAL;
71
72 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
73
74 return ret;
75 }
76
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)77 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
78 {
79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
80 u32 port = attr->port_num - 1;
81 int ret;
82
83 if (port >= hr_dev->caps.num_ports)
84 return -EINVAL;
85
86 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
87
88 return ret;
89 }
90
handle_en_event(struct hns_roce_dev * hr_dev,u32 port,unsigned long event)91 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
92 unsigned long event)
93 {
94 struct device *dev = hr_dev->dev;
95 struct net_device *netdev;
96 int ret = 0;
97
98 netdev = hr_dev->iboe.netdevs[port];
99 if (!netdev) {
100 dev_err(dev, "can't find netdev on port(%u)!\n", port);
101 return -ENODEV;
102 }
103
104 switch (event) {
105 case NETDEV_UP:
106 case NETDEV_CHANGE:
107 case NETDEV_REGISTER:
108 case NETDEV_CHANGEADDR:
109 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
110 break;
111 case NETDEV_DOWN:
112 /*
113 * In v1 engine, only support all ports closed together.
114 */
115 break;
116 default:
117 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
118 break;
119 }
120
121 return ret;
122 }
123
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)124 static int hns_roce_netdev_event(struct notifier_block *self,
125 unsigned long event, void *ptr)
126 {
127 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
128 struct hns_roce_ib_iboe *iboe = NULL;
129 struct hns_roce_dev *hr_dev = NULL;
130 int ret;
131 u32 port;
132
133 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
134 iboe = &hr_dev->iboe;
135
136 for (port = 0; port < hr_dev->caps.num_ports; port++) {
137 if (dev == iboe->netdevs[port]) {
138 ret = handle_en_event(hr_dev, port, event);
139 if (ret)
140 return NOTIFY_DONE;
141 break;
142 }
143 }
144
145 return NOTIFY_DONE;
146 }
147
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)148 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
149 {
150 int ret;
151 u8 i;
152
153 for (i = 0; i < hr_dev->caps.num_ports; i++) {
154 ret = hns_roce_set_mac(hr_dev, i,
155 hr_dev->iboe.netdevs[i]->dev_addr);
156 if (ret)
157 return ret;
158 }
159
160 return 0;
161 }
162
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)163 static int hns_roce_query_device(struct ib_device *ib_dev,
164 struct ib_device_attr *props,
165 struct ib_udata *uhw)
166 {
167 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
168
169 memset(props, 0, sizeof(*props));
170
171 props->fw_ver = hr_dev->caps.fw_ver;
172 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
173 props->max_mr_size = (u64)(~(0ULL));
174 props->page_size_cap = hr_dev->caps.page_size_cap;
175 props->vendor_id = hr_dev->vendor_id;
176 props->vendor_part_id = hr_dev->vendor_part_id;
177 props->hw_ver = hr_dev->hw_rev;
178 props->max_qp = hr_dev->caps.num_qps;
179 props->max_qp_wr = hr_dev->caps.max_wqes;
180 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
181 IB_DEVICE_RC_RNR_NAK_GEN;
182 props->max_send_sge = hr_dev->caps.max_sq_sg;
183 props->max_recv_sge = hr_dev->caps.max_rq_sg;
184 props->max_sge_rd = 1;
185 props->max_cq = hr_dev->caps.num_cqs;
186 props->max_cqe = hr_dev->caps.max_cqes;
187 props->max_mr = hr_dev->caps.num_mtpts;
188 props->max_pd = hr_dev->caps.num_pds;
189 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
190 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
191 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
192 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
193 props->max_pkeys = 1;
194 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
195 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
196 props->max_srq = hr_dev->caps.num_srqs;
197 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
198 props->max_srq_sge = hr_dev->caps.max_srq_sges;
199 }
200
201 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
202 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
203 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
204 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
205 }
206
207 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
208 props->device_cap_flags |= IB_DEVICE_XRC;
209
210 return 0;
211 }
212
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)213 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
214 struct ib_port_attr *props)
215 {
216 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
217 struct device *dev = hr_dev->dev;
218 struct net_device *net_dev;
219 unsigned long flags;
220 enum ib_mtu mtu;
221 u32 port;
222
223 port = port_num - 1;
224
225 /* props being zeroed by the caller, avoid zeroing it here */
226
227 props->max_mtu = hr_dev->caps.max_mtu;
228 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
229 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
230 IB_PORT_VENDOR_CLASS_SUP |
231 IB_PORT_BOOT_MGMT_SUP;
232 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
233 props->pkey_tbl_len = 1;
234 props->active_width = IB_WIDTH_4X;
235 props->active_speed = 1;
236
237 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
238
239 net_dev = hr_dev->iboe.netdevs[port];
240 if (!net_dev) {
241 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
242 dev_err(dev, "find netdev %u failed!\n", port);
243 return -EINVAL;
244 }
245
246 mtu = iboe_get_mtu(net_dev->mtu);
247 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
248 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
249 IB_PORT_ACTIVE :
250 IB_PORT_DOWN;
251 props->phys_state = props->state == IB_PORT_ACTIVE ?
252 IB_PORT_PHYS_STATE_LINK_UP :
253 IB_PORT_PHYS_STATE_DISABLED;
254
255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
256
257 return 0;
258 }
259
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)260 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
261 u32 port_num)
262 {
263 return IB_LINK_LAYER_ETHERNET;
264 }
265
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)266 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
267 u16 *pkey)
268 {
269 if (index > 0)
270 return -EINVAL;
271
272 *pkey = PKEY_ID;
273
274 return 0;
275 }
276
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)277 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
278 struct ib_device_modify *props)
279 {
280 unsigned long flags;
281
282 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
283 return -EOPNOTSUPP;
284
285 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
286 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
287 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
288 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
289 }
290
291 return 0;
292 }
293
294 struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext * ucontext,u64 address,size_t length,enum hns_roce_mmap_type mmap_type)295 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
296 size_t length,
297 enum hns_roce_mmap_type mmap_type)
298 {
299 struct hns_user_mmap_entry *entry;
300 int ret;
301
302 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
303 if (!entry)
304 return NULL;
305
306 entry->address = address;
307 entry->mmap_type = mmap_type;
308
309 switch (mmap_type) {
310 /* pgoff 0 must be used by DB for compatibility */
311 case HNS_ROCE_MMAP_TYPE_DB:
312 ret = rdma_user_mmap_entry_insert_exact(
313 ucontext, &entry->rdma_entry, length, 0);
314 break;
315 case HNS_ROCE_MMAP_TYPE_DWQE:
316 ret = rdma_user_mmap_entry_insert_range(
317 ucontext, &entry->rdma_entry, length, 1,
318 U32_MAX);
319 break;
320 default:
321 ret = -EINVAL;
322 break;
323 }
324
325 if (ret) {
326 kfree(entry);
327 return NULL;
328 }
329
330 return entry;
331 }
332
hns_roce_dealloc_uar_entry(struct hns_roce_ucontext * context)333 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
334 {
335 if (context->db_mmap_entry)
336 rdma_user_mmap_entry_remove(
337 &context->db_mmap_entry->rdma_entry);
338 }
339
hns_roce_alloc_uar_entry(struct ib_ucontext * uctx)340 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
341 {
342 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
343 u64 address;
344
345 address = context->uar.pfn << PAGE_SHIFT;
346 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
347 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
348 if (!context->db_mmap_entry)
349 return -ENOMEM;
350
351 return 0;
352 }
353
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)354 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
355 struct ib_udata *udata)
356 {
357 int ret;
358 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
359 struct hns_roce_ib_alloc_ucontext_resp resp = {};
360 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
361
362 if (!hr_dev->active)
363 return -EAGAIN;
364
365 resp.qp_tab_size = hr_dev->caps.num_qps;
366 resp.srq_tab_size = hr_dev->caps.num_srqs;
367
368 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
369 if (ret)
370 goto error_fail_uar_alloc;
371
372 ret = hns_roce_alloc_uar_entry(uctx);
373 if (ret)
374 goto error_fail_uar_entry;
375
376 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
377 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
378 INIT_LIST_HEAD(&context->page_list);
379 mutex_init(&context->page_mutex);
380 }
381
382 resp.cqe_size = hr_dev->caps.cqe_sz;
383
384 ret = ib_copy_to_udata(udata, &resp,
385 min(udata->outlen, sizeof(resp)));
386 if (ret)
387 goto error_fail_copy_to_udata;
388
389 return 0;
390
391 error_fail_copy_to_udata:
392 hns_roce_dealloc_uar_entry(context);
393
394 error_fail_uar_entry:
395 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
396
397 error_fail_uar_alloc:
398 return ret;
399 }
400
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)401 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
402 {
403 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
404 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
405
406 hns_roce_dealloc_uar_entry(context);
407
408 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
409 }
410
hns_roce_mmap(struct ib_ucontext * uctx,struct vm_area_struct * vma)411 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
412 {
413 struct rdma_user_mmap_entry *rdma_entry;
414 struct hns_user_mmap_entry *entry;
415 phys_addr_t pfn;
416 pgprot_t prot;
417 int ret;
418
419 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
420 if (!rdma_entry)
421 return -EINVAL;
422
423 entry = to_hns_mmap(rdma_entry);
424 pfn = entry->address >> PAGE_SHIFT;
425
426 switch (entry->mmap_type) {
427 case HNS_ROCE_MMAP_TYPE_DB:
428 case HNS_ROCE_MMAP_TYPE_DWQE:
429 prot = pgprot_device(vma->vm_page_prot);
430 break;
431 default:
432 return -EINVAL;
433 }
434
435 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
436 prot, rdma_entry);
437
438 rdma_user_mmap_entry_put(rdma_entry);
439
440 return ret;
441 }
442
hns_roce_free_mmap(struct rdma_user_mmap_entry * rdma_entry)443 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
444 {
445 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
446
447 kfree(entry);
448 }
449
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)450 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
451 struct ib_port_immutable *immutable)
452 {
453 struct ib_port_attr attr;
454 int ret;
455
456 ret = ib_query_port(ib_dev, port_num, &attr);
457 if (ret)
458 return ret;
459
460 immutable->pkey_tbl_len = attr.pkey_tbl_len;
461 immutable->gid_tbl_len = attr.gid_tbl_len;
462
463 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
464 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
465 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
466 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
467
468 return 0;
469 }
470
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)471 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
472 {
473 }
474
hns_roce_get_fw_ver(struct ib_device * device,char * str)475 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
476 {
477 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
478 unsigned int major, minor, sub_minor;
479
480 major = upper_32_bits(fw_ver);
481 minor = high_16_bits(lower_32_bits(fw_ver));
482 sub_minor = low_16_bits(fw_ver);
483
484 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
485 sub_minor);
486 }
487
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)488 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
489 {
490 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
491
492 hr_dev->active = false;
493 unregister_netdevice_notifier(&iboe->nb);
494 ib_unregister_device(&hr_dev->ib_dev);
495 }
496
497 static const struct ib_device_ops hns_roce_dev_ops = {
498 .owner = THIS_MODULE,
499 .driver_id = RDMA_DRIVER_HNS,
500 .uverbs_abi_ver = 1,
501 .uverbs_no_driver_id_binding = 1,
502
503 .get_dev_fw_str = hns_roce_get_fw_ver,
504 .add_gid = hns_roce_add_gid,
505 .alloc_pd = hns_roce_alloc_pd,
506 .alloc_ucontext = hns_roce_alloc_ucontext,
507 .create_ah = hns_roce_create_ah,
508 .create_user_ah = hns_roce_create_ah,
509 .create_cq = hns_roce_create_cq,
510 .create_qp = hns_roce_create_qp,
511 .dealloc_pd = hns_roce_dealloc_pd,
512 .dealloc_ucontext = hns_roce_dealloc_ucontext,
513 .del_gid = hns_roce_del_gid,
514 .dereg_mr = hns_roce_dereg_mr,
515 .destroy_ah = hns_roce_destroy_ah,
516 .destroy_cq = hns_roce_destroy_cq,
517 .disassociate_ucontext = hns_roce_disassociate_ucontext,
518 .get_dma_mr = hns_roce_get_dma_mr,
519 .get_link_layer = hns_roce_get_link_layer,
520 .get_port_immutable = hns_roce_port_immutable,
521 .mmap = hns_roce_mmap,
522 .mmap_free = hns_roce_free_mmap,
523 .modify_device = hns_roce_modify_device,
524 .modify_qp = hns_roce_modify_qp,
525 .query_ah = hns_roce_query_ah,
526 .query_device = hns_roce_query_device,
527 .query_pkey = hns_roce_query_pkey,
528 .query_port = hns_roce_query_port,
529 .reg_user_mr = hns_roce_reg_user_mr,
530
531 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
532 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
533 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
534 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
535 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
536 };
537
538 static const struct ib_device_ops hns_roce_dev_mr_ops = {
539 .rereg_user_mr = hns_roce_rereg_user_mr,
540 };
541
542 static const struct ib_device_ops hns_roce_dev_mw_ops = {
543 .alloc_mw = hns_roce_alloc_mw,
544 .dealloc_mw = hns_roce_dealloc_mw,
545
546 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
547 };
548
549 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
550 .alloc_mr = hns_roce_alloc_mr,
551 .map_mr_sg = hns_roce_map_mr_sg,
552 };
553
554 static const struct ib_device_ops hns_roce_dev_srq_ops = {
555 .create_srq = hns_roce_create_srq,
556 .destroy_srq = hns_roce_destroy_srq,
557
558 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
559 };
560
561 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
562 .alloc_xrcd = hns_roce_alloc_xrcd,
563 .dealloc_xrcd = hns_roce_dealloc_xrcd,
564
565 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
566 };
567
568 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
569 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
570 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
571 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
572 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
573 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
574 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
575 };
576
hns_roce_register_device(struct hns_roce_dev * hr_dev)577 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
578 {
579 int ret;
580 struct hns_roce_ib_iboe *iboe = NULL;
581 struct ib_device *ib_dev = NULL;
582 struct device *dev = hr_dev->dev;
583 unsigned int i;
584
585 iboe = &hr_dev->iboe;
586 spin_lock_init(&iboe->lock);
587
588 ib_dev = &hr_dev->ib_dev;
589
590 ib_dev->node_type = RDMA_NODE_IB_CA;
591 ib_dev->dev.parent = dev;
592
593 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
594 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
595 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
596
597 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
598 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
599
600 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
601 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
602
603 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
604 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
605
606 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
607 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
608 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
609 }
610
611 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
612 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
613
614 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
615 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
616 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
617 for (i = 0; i < hr_dev->caps.num_ports; i++) {
618 if (!hr_dev->iboe.netdevs[i])
619 continue;
620
621 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
622 i + 1);
623 if (ret)
624 return ret;
625 }
626 dma_set_max_seg_size(dev, UINT_MAX);
627 ret = ib_register_device(ib_dev, "hns_%d", dev);
628 if (ret) {
629 dev_err(dev, "ib_register_device failed!\n");
630 return ret;
631 }
632
633 ret = hns_roce_setup_mtu_mac(hr_dev);
634 if (ret) {
635 dev_err(dev, "setup_mtu_mac failed!\n");
636 goto error_failed_setup_mtu_mac;
637 }
638
639 iboe->nb.notifier_call = hns_roce_netdev_event;
640 ret = register_netdevice_notifier(&iboe->nb);
641 if (ret) {
642 dev_err(dev, "register_netdevice_notifier failed!\n");
643 goto error_failed_setup_mtu_mac;
644 }
645
646 hr_dev->active = true;
647 return 0;
648
649 error_failed_setup_mtu_mac:
650 ib_unregister_device(ib_dev);
651
652 return ret;
653 }
654
hns_roce_init_hem(struct hns_roce_dev * hr_dev)655 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
656 {
657 struct device *dev = hr_dev->dev;
658 int ret;
659
660 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
661 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
662 hr_dev->caps.num_mtpts);
663 if (ret) {
664 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
665 return ret;
666 }
667
668 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
669 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
670 hr_dev->caps.num_qps);
671 if (ret) {
672 dev_err(dev, "failed to init QP context memory, aborting.\n");
673 goto err_unmap_dmpt;
674 }
675
676 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
677 HEM_TYPE_IRRL,
678 hr_dev->caps.irrl_entry_sz *
679 hr_dev->caps.max_qp_init_rdma,
680 hr_dev->caps.num_qps);
681 if (ret) {
682 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
683 goto err_unmap_qp;
684 }
685
686 if (hr_dev->caps.trrl_entry_sz) {
687 ret = hns_roce_init_hem_table(hr_dev,
688 &hr_dev->qp_table.trrl_table,
689 HEM_TYPE_TRRL,
690 hr_dev->caps.trrl_entry_sz *
691 hr_dev->caps.max_qp_dest_rdma,
692 hr_dev->caps.num_qps);
693 if (ret) {
694 dev_err(dev,
695 "failed to init trrl_table memory, aborting.\n");
696 goto err_unmap_irrl;
697 }
698 }
699
700 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
701 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
702 hr_dev->caps.num_cqs);
703 if (ret) {
704 dev_err(dev, "failed to init CQ context memory, aborting.\n");
705 goto err_unmap_trrl;
706 }
707
708 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
709 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
710 HEM_TYPE_SRQC,
711 hr_dev->caps.srqc_entry_sz,
712 hr_dev->caps.num_srqs);
713 if (ret) {
714 dev_err(dev,
715 "failed to init SRQ context memory, aborting.\n");
716 goto err_unmap_cq;
717 }
718 }
719
720 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
721 ret = hns_roce_init_hem_table(hr_dev,
722 &hr_dev->qp_table.sccc_table,
723 HEM_TYPE_SCCC,
724 hr_dev->caps.sccc_sz,
725 hr_dev->caps.num_qps);
726 if (ret) {
727 dev_err(dev,
728 "failed to init SCC context memory, aborting.\n");
729 goto err_unmap_srq;
730 }
731 }
732
733 if (hr_dev->caps.qpc_timer_entry_sz) {
734 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
735 HEM_TYPE_QPC_TIMER,
736 hr_dev->caps.qpc_timer_entry_sz,
737 hr_dev->caps.qpc_timer_bt_num);
738 if (ret) {
739 dev_err(dev,
740 "failed to init QPC timer memory, aborting.\n");
741 goto err_unmap_ctx;
742 }
743 }
744
745 if (hr_dev->caps.cqc_timer_entry_sz) {
746 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
747 HEM_TYPE_CQC_TIMER,
748 hr_dev->caps.cqc_timer_entry_sz,
749 hr_dev->caps.cqc_timer_bt_num);
750 if (ret) {
751 dev_err(dev,
752 "failed to init CQC timer memory, aborting.\n");
753 goto err_unmap_qpc_timer;
754 }
755 }
756
757 if (hr_dev->caps.gmv_entry_sz) {
758 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
759 HEM_TYPE_GMV,
760 hr_dev->caps.gmv_entry_sz,
761 hr_dev->caps.gmv_entry_num);
762 if (ret) {
763 dev_err(dev,
764 "failed to init gmv table memory, ret = %d\n",
765 ret);
766 goto err_unmap_cqc_timer;
767 }
768 }
769
770 return 0;
771
772 err_unmap_cqc_timer:
773 if (hr_dev->caps.cqc_timer_entry_sz)
774 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
775
776 err_unmap_qpc_timer:
777 if (hr_dev->caps.qpc_timer_entry_sz)
778 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
779
780 err_unmap_ctx:
781 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
782 hns_roce_cleanup_hem_table(hr_dev,
783 &hr_dev->qp_table.sccc_table);
784 err_unmap_srq:
785 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
786 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
787
788 err_unmap_cq:
789 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
790
791 err_unmap_trrl:
792 if (hr_dev->caps.trrl_entry_sz)
793 hns_roce_cleanup_hem_table(hr_dev,
794 &hr_dev->qp_table.trrl_table);
795
796 err_unmap_irrl:
797 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
798
799 err_unmap_qp:
800 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
801
802 err_unmap_dmpt:
803 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
804
805 return ret;
806 }
807
808 /**
809 * hns_roce_setup_hca - setup host channel adapter
810 * @hr_dev: pointer to hns roce device
811 * Return : int
812 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)813 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
814 {
815 struct device *dev = hr_dev->dev;
816 int ret;
817
818 spin_lock_init(&hr_dev->sm_lock);
819
820 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
821 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
822 INIT_LIST_HEAD(&hr_dev->pgdir_list);
823 mutex_init(&hr_dev->pgdir_mutex);
824 }
825
826 hns_roce_init_uar_table(hr_dev);
827
828 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
829 if (ret) {
830 dev_err(dev, "failed to allocate priv_uar.\n");
831 goto err_uar_table_free;
832 }
833
834 ret = hns_roce_init_qp_table(hr_dev);
835 if (ret) {
836 dev_err(dev, "failed to init qp_table.\n");
837 goto err_uar_table_free;
838 }
839
840 hns_roce_init_pd_table(hr_dev);
841
842 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
843 hns_roce_init_xrcd_table(hr_dev);
844
845 hns_roce_init_mr_table(hr_dev);
846
847 hns_roce_init_cq_table(hr_dev);
848
849 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
850 hns_roce_init_srq_table(hr_dev);
851
852 return 0;
853
854 err_uar_table_free:
855 ida_destroy(&hr_dev->uar_ida.ida);
856 return ret;
857 }
858
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)859 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
860 {
861 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
862 unsigned long flags;
863
864 spin_lock_irqsave(&hr_cq->lock, flags);
865 if (cq->comp_handler) {
866 if (!hr_cq->is_armed) {
867 hr_cq->is_armed = 1;
868 list_add_tail(&hr_cq->node, cq_list);
869 }
870 }
871 spin_unlock_irqrestore(&hr_cq->lock, flags);
872 }
873
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)874 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
875 {
876 struct hns_roce_qp *hr_qp;
877 struct hns_roce_cq *hr_cq;
878 struct list_head cq_list;
879 unsigned long flags_qp;
880 unsigned long flags;
881
882 INIT_LIST_HEAD(&cq_list);
883
884 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
885 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
886 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
887 if (hr_qp->sq.tail != hr_qp->sq.head)
888 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
889 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
890
891 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
892 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
893 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
894 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
895 }
896
897 list_for_each_entry(hr_cq, &cq_list, node)
898 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
899
900 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
901 }
902
hns_roce_init(struct hns_roce_dev * hr_dev)903 int hns_roce_init(struct hns_roce_dev *hr_dev)
904 {
905 struct device *dev = hr_dev->dev;
906 int ret;
907
908 hr_dev->is_reset = false;
909
910 if (hr_dev->hw->cmq_init) {
911 ret = hr_dev->hw->cmq_init(hr_dev);
912 if (ret) {
913 dev_err(dev, "init RoCE Command Queue failed!\n");
914 return ret;
915 }
916 }
917
918 ret = hr_dev->hw->hw_profile(hr_dev);
919 if (ret) {
920 dev_err(dev, "get RoCE engine profile failed!\n");
921 goto error_failed_cmd_init;
922 }
923
924 ret = hns_roce_cmd_init(hr_dev);
925 if (ret) {
926 dev_err(dev, "cmd init failed!\n");
927 goto error_failed_cmd_init;
928 }
929
930 /* EQ depends on poll mode, event mode depends on EQ */
931 ret = hr_dev->hw->init_eq(hr_dev);
932 if (ret) {
933 dev_err(dev, "eq init failed!\n");
934 goto error_failed_eq_table;
935 }
936
937 if (hr_dev->cmd_mod) {
938 ret = hns_roce_cmd_use_events(hr_dev);
939 if (ret)
940 dev_warn(dev,
941 "Cmd event mode failed, set back to poll!\n");
942 }
943
944 ret = hns_roce_init_hem(hr_dev);
945 if (ret) {
946 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
947 goto error_failed_init_hem;
948 }
949
950 ret = hns_roce_setup_hca(hr_dev);
951 if (ret) {
952 dev_err(dev, "setup hca failed!\n");
953 goto error_failed_setup_hca;
954 }
955
956 if (hr_dev->hw->hw_init) {
957 ret = hr_dev->hw->hw_init(hr_dev);
958 if (ret) {
959 dev_err(dev, "hw_init failed!\n");
960 goto error_failed_engine_init;
961 }
962 }
963
964 INIT_LIST_HEAD(&hr_dev->qp_list);
965 spin_lock_init(&hr_dev->qp_list_lock);
966 INIT_LIST_HEAD(&hr_dev->dip_list);
967 spin_lock_init(&hr_dev->dip_list_lock);
968
969 ret = hns_roce_register_device(hr_dev);
970 if (ret)
971 goto error_failed_register_device;
972
973 return 0;
974
975 error_failed_register_device:
976 if (hr_dev->hw->hw_exit)
977 hr_dev->hw->hw_exit(hr_dev);
978
979 error_failed_engine_init:
980 hns_roce_cleanup_bitmap(hr_dev);
981
982 error_failed_setup_hca:
983 hns_roce_cleanup_hem(hr_dev);
984
985 error_failed_init_hem:
986 if (hr_dev->cmd_mod)
987 hns_roce_cmd_use_polling(hr_dev);
988 hr_dev->hw->cleanup_eq(hr_dev);
989
990 error_failed_eq_table:
991 hns_roce_cmd_cleanup(hr_dev);
992
993 error_failed_cmd_init:
994 if (hr_dev->hw->cmq_exit)
995 hr_dev->hw->cmq_exit(hr_dev);
996
997 return ret;
998 }
999
hns_roce_exit(struct hns_roce_dev * hr_dev)1000 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1001 {
1002 hns_roce_unregister_device(hr_dev);
1003
1004 if (hr_dev->hw->hw_exit)
1005 hr_dev->hw->hw_exit(hr_dev);
1006 hns_roce_cleanup_bitmap(hr_dev);
1007 hns_roce_cleanup_hem(hr_dev);
1008
1009 if (hr_dev->cmd_mod)
1010 hns_roce_cmd_use_polling(hr_dev);
1011
1012 hr_dev->hw->cleanup_eq(hr_dev);
1013 hns_roce_cmd_cleanup(hr_dev);
1014 if (hr_dev->hw->cmq_exit)
1015 hr_dev->hw->cmq_exit(hr_dev);
1016 }
1017
1018 MODULE_LICENSE("Dual BSD/GPL");
1019 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1020 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1021 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1022 MODULE_DESCRIPTION("HNS RoCE Driver");
1023
