1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include <rdma/hns-abi.h>
43 #include "hns_roce_hem.h"
44
45 /**
46 * hns_get_gid_index - Get gid index.
47 * @hr_dev: pointer to structure hns_roce_dev.
48 * @port: port, value range: 0 ~ MAX
49 * @gid_index: gid_index, value range: 0 ~ MAX
50 * Description:
51 * N ports shared gids, allocation method as follow:
52 * GID[0][0], GID[1][0],.....GID[N - 1][0],
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * And so on
55 */
hns_get_gid_index(struct hns_roce_dev * hr_dev,u8 port,int gid_index)56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57 {
58 return gid_index * hr_dev->caps.num_ports + port;
59 }
60
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u8 port,u8 * addr)61 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
62 {
63 u8 phy_port;
64 u32 i = 0;
65
66 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
67 return 0;
68
69 for (i = 0; i < ETH_ALEN; i++)
70 hr_dev->dev_addr[port][i] = addr[i];
71
72 phy_port = hr_dev->iboe.phy_port[port];
73 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
74 }
75
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)76 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
77 {
78 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
79 u8 port = attr->port_num - 1;
80 int ret;
81
82 if (port >= hr_dev->caps.num_ports)
83 return -EINVAL;
84
85 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
86
87 return ret;
88 }
89
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)90 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
91 {
92 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
93 struct ib_gid_attr zattr = { };
94 u8 port = attr->port_num - 1;
95 int ret;
96
97 if (port >= hr_dev->caps.num_ports)
98 return -EINVAL;
99
100 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
101
102 return ret;
103 }
104
handle_en_event(struct hns_roce_dev * hr_dev,u8 port,unsigned long event)105 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
106 unsigned long event)
107 {
108 struct device *dev = hr_dev->dev;
109 struct net_device *netdev;
110 int ret = 0;
111
112 netdev = hr_dev->iboe.netdevs[port];
113 if (!netdev) {
114 dev_err(dev, "port(%d) can't find netdev\n", port);
115 return -ENODEV;
116 }
117
118 switch (event) {
119 case NETDEV_UP:
120 case NETDEV_CHANGE:
121 case NETDEV_REGISTER:
122 case NETDEV_CHANGEADDR:
123 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
124 break;
125 case NETDEV_DOWN:
126 /*
127 * In v1 engine, only support all ports closed together.
128 */
129 break;
130 default:
131 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
132 break;
133 }
134
135 return ret;
136 }
137
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)138 static int hns_roce_netdev_event(struct notifier_block *self,
139 unsigned long event, void *ptr)
140 {
141 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
142 struct hns_roce_ib_iboe *iboe = NULL;
143 struct hns_roce_dev *hr_dev = NULL;
144 u8 port = 0;
145 int ret = 0;
146
147 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
148 iboe = &hr_dev->iboe;
149
150 for (port = 0; port < hr_dev->caps.num_ports; port++) {
151 if (dev == iboe->netdevs[port]) {
152 ret = handle_en_event(hr_dev, port, event);
153 if (ret)
154 return NOTIFY_DONE;
155 break;
156 }
157 }
158
159 return NOTIFY_DONE;
160 }
161
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)162 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
163 {
164 int ret;
165 u8 i;
166
167 for (i = 0; i < hr_dev->caps.num_ports; i++) {
168 if (hr_dev->hw->set_mtu)
169 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
170 hr_dev->caps.max_mtu);
171 ret = hns_roce_set_mac(hr_dev, i,
172 hr_dev->iboe.netdevs[i]->dev_addr);
173 if (ret)
174 return ret;
175 }
176
177 return 0;
178 }
179
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)180 static int hns_roce_query_device(struct ib_device *ib_dev,
181 struct ib_device_attr *props,
182 struct ib_udata *uhw)
183 {
184 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
185
186 memset(props, 0, sizeof(*props));
187
188 props->fw_ver = hr_dev->caps.fw_ver;
189 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
190 props->max_mr_size = (u64)(~(0ULL));
191 props->page_size_cap = hr_dev->caps.page_size_cap;
192 props->vendor_id = hr_dev->vendor_id;
193 props->vendor_part_id = hr_dev->vendor_part_id;
194 props->hw_ver = hr_dev->hw_rev;
195 props->max_qp = hr_dev->caps.num_qps;
196 props->max_qp_wr = hr_dev->caps.max_wqes;
197 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
198 IB_DEVICE_RC_RNR_NAK_GEN;
199 props->max_send_sge = hr_dev->caps.max_sq_sg;
200 props->max_recv_sge = hr_dev->caps.max_rq_sg;
201 props->max_sge_rd = 1;
202 props->max_cq = hr_dev->caps.num_cqs;
203 props->max_cqe = hr_dev->caps.max_cqes;
204 props->max_mr = hr_dev->caps.num_mtpts;
205 props->max_pd = hr_dev->caps.num_pds;
206 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
207 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
208 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
209 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
210 props->max_pkeys = 1;
211 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
212 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
213 props->max_srq = hr_dev->caps.max_srqs;
214 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
215 props->max_srq_sge = hr_dev->caps.max_srq_sges;
216 }
217
218 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
219 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
220 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
221 }
222
223 return 0;
224 }
225
hns_roce_query_port(struct ib_device * ib_dev,u8 port_num,struct ib_port_attr * props)226 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
227 struct ib_port_attr *props)
228 {
229 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
230 struct device *dev = hr_dev->dev;
231 struct net_device *net_dev;
232 unsigned long flags;
233 enum ib_mtu mtu;
234 u8 port;
235
236 assert(port_num > 0);
237 port = port_num - 1;
238
239 /* props being zeroed by the caller, avoid zeroing it here */
240
241 props->max_mtu = hr_dev->caps.max_mtu;
242 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
243 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
244 IB_PORT_VENDOR_CLASS_SUP |
245 IB_PORT_BOOT_MGMT_SUP;
246 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
247 props->pkey_tbl_len = 1;
248 props->active_width = IB_WIDTH_4X;
249 props->active_speed = 1;
250
251 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
252
253 net_dev = hr_dev->iboe.netdevs[port];
254 if (!net_dev) {
255 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
256 dev_err(dev, "find netdev %d failed!\r\n", port);
257 return -EINVAL;
258 }
259
260 mtu = iboe_get_mtu(net_dev->mtu);
261 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
262 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
263 IB_PORT_ACTIVE : IB_PORT_DOWN;
264 props->phys_state = (props->state == IB_PORT_ACTIVE) ?
265 IB_PORT_PHYS_STATE_LINK_UP :
266 IB_PORT_PHYS_STATE_DISABLED;
267
268 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
269
270 return 0;
271 }
272
hns_roce_get_link_layer(struct ib_device * device,u8 port_num)273 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
274 u8 port_num)
275 {
276 return IB_LINK_LAYER_ETHERNET;
277 }
278
hns_roce_query_pkey(struct ib_device * ib_dev,u8 port,u16 index,u16 * pkey)279 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
280 u16 *pkey)
281 {
282 *pkey = PKEY_ID;
283
284 return 0;
285 }
286
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)287 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
288 struct ib_device_modify *props)
289 {
290 unsigned long flags;
291
292 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
293 return -EOPNOTSUPP;
294
295 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
296 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
297 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
298 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
299 }
300
301 return 0;
302 }
303
hns_roce_modify_port(struct ib_device * ib_dev,u8 port_num,int mask,struct ib_port_modify * props)304 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
305 struct ib_port_modify *props)
306 {
307 return 0;
308 }
309
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)310 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
311 struct ib_udata *udata)
312 {
313 int ret;
314 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
315 struct hns_roce_ib_alloc_ucontext_resp resp = {};
316 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
317
318 if (!hr_dev->active)
319 return -EAGAIN;
320
321 resp.qp_tab_size = hr_dev->caps.num_qps;
322
323 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
324 if (ret)
325 goto error_fail_uar_alloc;
326
327 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
328 INIT_LIST_HEAD(&context->page_list);
329 mutex_init(&context->page_mutex);
330 }
331
332 ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
333 if (ret)
334 goto error_fail_copy_to_udata;
335
336 return 0;
337
338 error_fail_copy_to_udata:
339 hns_roce_uar_free(hr_dev, &context->uar);
340
341 error_fail_uar_alloc:
342 return ret;
343 }
344
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)345 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
346 {
347 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
348
349 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
350 }
351
hns_roce_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)352 static int hns_roce_mmap(struct ib_ucontext *context,
353 struct vm_area_struct *vma)
354 {
355 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
356
357 switch (vma->vm_pgoff) {
358 case 0:
359 return rdma_user_mmap_io(context, vma,
360 to_hr_ucontext(context)->uar.pfn,
361 PAGE_SIZE,
362 pgprot_noncached(vma->vm_page_prot));
363
364 /* vm_pgoff: 1 -- TPTR */
365 case 1:
366 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
367 return -EINVAL;
368 /*
369 * FIXME: using io_remap_pfn_range on the dma address returned
370 * by dma_alloc_coherent is totally wrong.
371 */
372 return rdma_user_mmap_io(context, vma,
373 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
374 hr_dev->tptr_size,
375 vma->vm_page_prot);
376
377 default:
378 return -EINVAL;
379 }
380 }
381
hns_roce_port_immutable(struct ib_device * ib_dev,u8 port_num,struct ib_port_immutable * immutable)382 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
383 struct ib_port_immutable *immutable)
384 {
385 struct ib_port_attr attr;
386 int ret;
387
388 ret = ib_query_port(ib_dev, port_num, &attr);
389 if (ret)
390 return ret;
391
392 immutable->pkey_tbl_len = attr.pkey_tbl_len;
393 immutable->gid_tbl_len = attr.gid_tbl_len;
394
395 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
396 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
397 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
398 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
399
400 return 0;
401 }
402
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)403 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
404 {
405 }
406
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)407 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
408 {
409 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
410
411 hr_dev->active = false;
412 unregister_netdevice_notifier(&iboe->nb);
413 ib_unregister_device(&hr_dev->ib_dev);
414 }
415
416 static const struct ib_device_ops hns_roce_dev_ops = {
417 .owner = THIS_MODULE,
418 .driver_id = RDMA_DRIVER_HNS,
419 .uverbs_abi_ver = 1,
420 .uverbs_no_driver_id_binding = 1,
421
422 .add_gid = hns_roce_add_gid,
423 .alloc_pd = hns_roce_alloc_pd,
424 .alloc_ucontext = hns_roce_alloc_ucontext,
425 .create_ah = hns_roce_create_ah,
426 .create_cq = hns_roce_ib_create_cq,
427 .create_qp = hns_roce_create_qp,
428 .dealloc_pd = hns_roce_dealloc_pd,
429 .dealloc_ucontext = hns_roce_dealloc_ucontext,
430 .del_gid = hns_roce_del_gid,
431 .dereg_mr = hns_roce_dereg_mr,
432 .destroy_ah = hns_roce_destroy_ah,
433 .destroy_cq = hns_roce_ib_destroy_cq,
434 .disassociate_ucontext = hns_roce_disassociate_ucontext,
435 .fill_res_entry = hns_roce_fill_res_entry,
436 .get_dma_mr = hns_roce_get_dma_mr,
437 .get_link_layer = hns_roce_get_link_layer,
438 .get_port_immutable = hns_roce_port_immutable,
439 .mmap = hns_roce_mmap,
440 .modify_device = hns_roce_modify_device,
441 .modify_port = hns_roce_modify_port,
442 .modify_qp = hns_roce_modify_qp,
443 .query_ah = hns_roce_query_ah,
444 .query_device = hns_roce_query_device,
445 .query_pkey = hns_roce_query_pkey,
446 .query_port = hns_roce_query_port,
447 .reg_user_mr = hns_roce_reg_user_mr,
448
449 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
450 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
451 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
452 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
453 };
454
455 static const struct ib_device_ops hns_roce_dev_mr_ops = {
456 .rereg_user_mr = hns_roce_rereg_user_mr,
457 };
458
459 static const struct ib_device_ops hns_roce_dev_mw_ops = {
460 .alloc_mw = hns_roce_alloc_mw,
461 .dealloc_mw = hns_roce_dealloc_mw,
462 };
463
464 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
465 .alloc_mr = hns_roce_alloc_mr,
466 .map_mr_sg = hns_roce_map_mr_sg,
467 };
468
469 static const struct ib_device_ops hns_roce_dev_srq_ops = {
470 .create_srq = hns_roce_create_srq,
471 .destroy_srq = hns_roce_destroy_srq,
472
473 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
474 };
475
hns_roce_register_device(struct hns_roce_dev * hr_dev)476 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
477 {
478 int ret;
479 struct hns_roce_ib_iboe *iboe = NULL;
480 struct ib_device *ib_dev = NULL;
481 struct device *dev = hr_dev->dev;
482 unsigned int i;
483
484 iboe = &hr_dev->iboe;
485 spin_lock_init(&iboe->lock);
486
487 ib_dev = &hr_dev->ib_dev;
488
489 ib_dev->node_type = RDMA_NODE_IB_CA;
490 ib_dev->dev.parent = dev;
491
492 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
493 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
494 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
495 ib_dev->uverbs_cmd_mask =
496 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
497 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
498 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
499 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
500 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
501 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
502 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
503 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
504 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
505 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
506 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
507 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
508 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
509 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
510
511 ib_dev->uverbs_ex_cmd_mask |=
512 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
513
514 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
515 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
516 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
517 }
518
519 /* MW */
520 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) {
521 ib_dev->uverbs_cmd_mask |=
522 (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) |
523 (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
524 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
525 }
526
527 /* FRMR */
528 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
529 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
530
531 /* SRQ */
532 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
533 ib_dev->uverbs_cmd_mask |=
534 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) |
535 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) |
536 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) |
537 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) |
538 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV);
539 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
540 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
541 }
542
543 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
544 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
545 for (i = 0; i < hr_dev->caps.num_ports; i++) {
546 if (!hr_dev->iboe.netdevs[i])
547 continue;
548
549 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
550 i + 1);
551 if (ret)
552 return ret;
553 }
554 ret = ib_register_device(ib_dev, "hns_%d");
555 if (ret) {
556 dev_err(dev, "ib_register_device failed!\n");
557 return ret;
558 }
559
560 ret = hns_roce_setup_mtu_mac(hr_dev);
561 if (ret) {
562 dev_err(dev, "setup_mtu_mac failed!\n");
563 goto error_failed_setup_mtu_mac;
564 }
565
566 iboe->nb.notifier_call = hns_roce_netdev_event;
567 ret = register_netdevice_notifier(&iboe->nb);
568 if (ret) {
569 dev_err(dev, "register_netdevice_notifier failed!\n");
570 goto error_failed_setup_mtu_mac;
571 }
572
573 hr_dev->active = true;
574 return 0;
575
576 error_failed_setup_mtu_mac:
577 ib_unregister_device(ib_dev);
578
579 return ret;
580 }
581
hns_roce_init_hem(struct hns_roce_dev * hr_dev)582 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
583 {
584 int ret;
585 struct device *dev = hr_dev->dev;
586
587 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
588 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
589 hr_dev->caps.num_mtt_segs, 1);
590 if (ret) {
591 dev_err(dev, "Failed to init MTT context memory, aborting.\n");
592 return ret;
593 }
594
595 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
596 ret = hns_roce_init_hem_table(hr_dev,
597 &hr_dev->mr_table.mtt_cqe_table,
598 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
599 hr_dev->caps.num_cqe_segs, 1);
600 if (ret) {
601 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
602 goto err_unmap_cqe;
603 }
604 }
605
606 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
607 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
608 hr_dev->caps.num_mtpts, 1);
609 if (ret) {
610 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
611 goto err_unmap_mtt;
612 }
613
614 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
615 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
616 hr_dev->caps.num_qps, 1);
617 if (ret) {
618 dev_err(dev, "Failed to init QP context memory, aborting.\n");
619 goto err_unmap_dmpt;
620 }
621
622 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
623 HEM_TYPE_IRRL,
624 hr_dev->caps.irrl_entry_sz *
625 hr_dev->caps.max_qp_init_rdma,
626 hr_dev->caps.num_qps, 1);
627 if (ret) {
628 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
629 goto err_unmap_qp;
630 }
631
632 if (hr_dev->caps.trrl_entry_sz) {
633 ret = hns_roce_init_hem_table(hr_dev,
634 &hr_dev->qp_table.trrl_table,
635 HEM_TYPE_TRRL,
636 hr_dev->caps.trrl_entry_sz *
637 hr_dev->caps.max_qp_dest_rdma,
638 hr_dev->caps.num_qps, 1);
639 if (ret) {
640 dev_err(dev,
641 "Failed to init trrl_table memory, aborting.\n");
642 goto err_unmap_irrl;
643 }
644 }
645
646 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
647 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
648 hr_dev->caps.num_cqs, 1);
649 if (ret) {
650 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
651 goto err_unmap_trrl;
652 }
653
654 if (hr_dev->caps.srqc_entry_sz) {
655 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
656 HEM_TYPE_SRQC,
657 hr_dev->caps.srqc_entry_sz,
658 hr_dev->caps.num_srqs, 1);
659 if (ret) {
660 dev_err(dev,
661 "Failed to init SRQ context memory, aborting.\n");
662 goto err_unmap_cq;
663 }
664 }
665
666 if (hr_dev->caps.num_srqwqe_segs) {
667 ret = hns_roce_init_hem_table(hr_dev,
668 &hr_dev->mr_table.mtt_srqwqe_table,
669 HEM_TYPE_SRQWQE,
670 hr_dev->caps.mtt_entry_sz,
671 hr_dev->caps.num_srqwqe_segs, 1);
672 if (ret) {
673 dev_err(dev,
674 "Failed to init MTT srqwqe memory, aborting.\n");
675 goto err_unmap_srq;
676 }
677 }
678
679 if (hr_dev->caps.num_idx_segs) {
680 ret = hns_roce_init_hem_table(hr_dev,
681 &hr_dev->mr_table.mtt_idx_table,
682 HEM_TYPE_IDX,
683 hr_dev->caps.idx_entry_sz,
684 hr_dev->caps.num_idx_segs, 1);
685 if (ret) {
686 dev_err(dev,
687 "Failed to init MTT idx memory, aborting.\n");
688 goto err_unmap_srqwqe;
689 }
690 }
691
692 if (hr_dev->caps.sccc_entry_sz) {
693 ret = hns_roce_init_hem_table(hr_dev,
694 &hr_dev->qp_table.sccc_table,
695 HEM_TYPE_SCCC,
696 hr_dev->caps.sccc_entry_sz,
697 hr_dev->caps.num_qps, 1);
698 if (ret) {
699 dev_err(dev,
700 "Failed to init SCC context memory, aborting.\n");
701 goto err_unmap_idx;
702 }
703 }
704
705 if (hr_dev->caps.qpc_timer_entry_sz) {
706 ret = hns_roce_init_hem_table(hr_dev,
707 &hr_dev->qpc_timer_table,
708 HEM_TYPE_QPC_TIMER,
709 hr_dev->caps.qpc_timer_entry_sz,
710 hr_dev->caps.num_qpc_timer, 1);
711 if (ret) {
712 dev_err(dev,
713 "Failed to init QPC timer memory, aborting.\n");
714 goto err_unmap_ctx;
715 }
716 }
717
718 if (hr_dev->caps.cqc_timer_entry_sz) {
719 ret = hns_roce_init_hem_table(hr_dev,
720 &hr_dev->cqc_timer_table,
721 HEM_TYPE_CQC_TIMER,
722 hr_dev->caps.cqc_timer_entry_sz,
723 hr_dev->caps.num_cqc_timer, 1);
724 if (ret) {
725 dev_err(dev,
726 "Failed to init CQC timer memory, aborting.\n");
727 goto err_unmap_qpc_timer;
728 }
729 }
730
731 return 0;
732
733 err_unmap_qpc_timer:
734 if (hr_dev->caps.qpc_timer_entry_sz)
735 hns_roce_cleanup_hem_table(hr_dev,
736 &hr_dev->qpc_timer_table);
737
738 err_unmap_ctx:
739 if (hr_dev->caps.sccc_entry_sz)
740 hns_roce_cleanup_hem_table(hr_dev,
741 &hr_dev->qp_table.sccc_table);
742
743 err_unmap_idx:
744 if (hr_dev->caps.num_idx_segs)
745 hns_roce_cleanup_hem_table(hr_dev,
746 &hr_dev->mr_table.mtt_idx_table);
747
748 err_unmap_srqwqe:
749 if (hr_dev->caps.num_srqwqe_segs)
750 hns_roce_cleanup_hem_table(hr_dev,
751 &hr_dev->mr_table.mtt_srqwqe_table);
752
753 err_unmap_srq:
754 if (hr_dev->caps.srqc_entry_sz)
755 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
756
757 err_unmap_cq:
758 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
759
760 err_unmap_trrl:
761 if (hr_dev->caps.trrl_entry_sz)
762 hns_roce_cleanup_hem_table(hr_dev,
763 &hr_dev->qp_table.trrl_table);
764
765 err_unmap_irrl:
766 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
767
768 err_unmap_qp:
769 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
770
771 err_unmap_dmpt:
772 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
773
774 err_unmap_mtt:
775 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
776 hns_roce_cleanup_hem_table(hr_dev,
777 &hr_dev->mr_table.mtt_cqe_table);
778
779 err_unmap_cqe:
780 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
781
782 return ret;
783 }
784
785 /**
786 * hns_roce_setup_hca - setup host channel adapter
787 * @hr_dev: pointer to hns roce device
788 * Return : int
789 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)790 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
791 {
792 int ret;
793 struct device *dev = hr_dev->dev;
794
795 spin_lock_init(&hr_dev->sm_lock);
796 spin_lock_init(&hr_dev->bt_cmd_lock);
797
798 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
799 INIT_LIST_HEAD(&hr_dev->pgdir_list);
800 mutex_init(&hr_dev->pgdir_mutex);
801 }
802
803 ret = hns_roce_init_uar_table(hr_dev);
804 if (ret) {
805 dev_err(dev, "Failed to initialize uar table. aborting\n");
806 return ret;
807 }
808
809 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
810 if (ret) {
811 dev_err(dev, "Failed to allocate priv_uar.\n");
812 goto err_uar_table_free;
813 }
814
815 ret = hns_roce_init_pd_table(hr_dev);
816 if (ret) {
817 dev_err(dev, "Failed to init protected domain table.\n");
818 goto err_uar_alloc_free;
819 }
820
821 ret = hns_roce_init_mr_table(hr_dev);
822 if (ret) {
823 dev_err(dev, "Failed to init memory region table.\n");
824 goto err_pd_table_free;
825 }
826
827 ret = hns_roce_init_cq_table(hr_dev);
828 if (ret) {
829 dev_err(dev, "Failed to init completion queue table.\n");
830 goto err_mr_table_free;
831 }
832
833 ret = hns_roce_init_qp_table(hr_dev);
834 if (ret) {
835 dev_err(dev, "Failed to init queue pair table.\n");
836 goto err_cq_table_free;
837 }
838
839 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
840 ret = hns_roce_init_srq_table(hr_dev);
841 if (ret) {
842 dev_err(dev,
843 "Failed to init share receive queue table.\n");
844 goto err_qp_table_free;
845 }
846 }
847
848 return 0;
849
850 err_qp_table_free:
851 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
852 hns_roce_cleanup_qp_table(hr_dev);
853
854 err_cq_table_free:
855 hns_roce_cleanup_cq_table(hr_dev);
856
857 err_mr_table_free:
858 hns_roce_cleanup_mr_table(hr_dev);
859
860 err_pd_table_free:
861 hns_roce_cleanup_pd_table(hr_dev);
862
863 err_uar_alloc_free:
864 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
865
866 err_uar_table_free:
867 hns_roce_cleanup_uar_table(hr_dev);
868 return ret;
869 }
870
hns_roce_init(struct hns_roce_dev * hr_dev)871 int hns_roce_init(struct hns_roce_dev *hr_dev)
872 {
873 int ret;
874 struct device *dev = hr_dev->dev;
875
876 if (hr_dev->hw->reset) {
877 ret = hr_dev->hw->reset(hr_dev, true);
878 if (ret) {
879 dev_err(dev, "Reset RoCE engine failed!\n");
880 return ret;
881 }
882 }
883 hr_dev->is_reset = false;
884
885 if (hr_dev->hw->cmq_init) {
886 ret = hr_dev->hw->cmq_init(hr_dev);
887 if (ret) {
888 dev_err(dev, "Init RoCE Command Queue failed!\n");
889 goto error_failed_cmq_init;
890 }
891 }
892
893 ret = hr_dev->hw->hw_profile(hr_dev);
894 if (ret) {
895 dev_err(dev, "Get RoCE engine profile failed!\n");
896 goto error_failed_cmd_init;
897 }
898
899 ret = hns_roce_cmd_init(hr_dev);
900 if (ret) {
901 dev_err(dev, "cmd init failed!\n");
902 goto error_failed_cmd_init;
903 }
904
905 /* EQ depends on poll mode, event mode depends on EQ */
906 ret = hr_dev->hw->init_eq(hr_dev);
907 if (ret) {
908 dev_err(dev, "eq init failed!\n");
909 goto error_failed_eq_table;
910 }
911
912 if (hr_dev->cmd_mod) {
913 ret = hns_roce_cmd_use_events(hr_dev);
914 if (ret) {
915 dev_warn(dev,
916 "Cmd event mode failed, set back to poll!\n");
917 hns_roce_cmd_use_polling(hr_dev);
918 }
919 }
920
921 ret = hns_roce_init_hem(hr_dev);
922 if (ret) {
923 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
924 goto error_failed_init_hem;
925 }
926
927 ret = hns_roce_setup_hca(hr_dev);
928 if (ret) {
929 dev_err(dev, "setup hca failed!\n");
930 goto error_failed_setup_hca;
931 }
932
933 if (hr_dev->hw->hw_init) {
934 ret = hr_dev->hw->hw_init(hr_dev);
935 if (ret) {
936 dev_err(dev, "hw_init failed!\n");
937 goto error_failed_engine_init;
938 }
939 }
940
941 ret = hns_roce_register_device(hr_dev);
942 if (ret)
943 goto error_failed_register_device;
944
945 return 0;
946
947 error_failed_register_device:
948 if (hr_dev->hw->hw_exit)
949 hr_dev->hw->hw_exit(hr_dev);
950
951 error_failed_engine_init:
952 hns_roce_cleanup_bitmap(hr_dev);
953
954 error_failed_setup_hca:
955 hns_roce_cleanup_hem(hr_dev);
956
957 error_failed_init_hem:
958 if (hr_dev->cmd_mod)
959 hns_roce_cmd_use_polling(hr_dev);
960 hr_dev->hw->cleanup_eq(hr_dev);
961
962 error_failed_eq_table:
963 hns_roce_cmd_cleanup(hr_dev);
964
965 error_failed_cmd_init:
966 if (hr_dev->hw->cmq_exit)
967 hr_dev->hw->cmq_exit(hr_dev);
968
969 error_failed_cmq_init:
970 if (hr_dev->hw->reset) {
971 if (hr_dev->hw->reset(hr_dev, false))
972 dev_err(dev, "Dereset RoCE engine failed!\n");
973 }
974
975 return ret;
976 }
977
hns_roce_exit(struct hns_roce_dev * hr_dev)978 void hns_roce_exit(struct hns_roce_dev *hr_dev)
979 {
980 hns_roce_unregister_device(hr_dev);
981
982 if (hr_dev->hw->hw_exit)
983 hr_dev->hw->hw_exit(hr_dev);
984 hns_roce_cleanup_bitmap(hr_dev);
985 hns_roce_cleanup_hem(hr_dev);
986
987 if (hr_dev->cmd_mod)
988 hns_roce_cmd_use_polling(hr_dev);
989
990 hr_dev->hw->cleanup_eq(hr_dev);
991 hns_roce_cmd_cleanup(hr_dev);
992 if (hr_dev->hw->cmq_exit)
993 hr_dev->hw->cmq_exit(hr_dev);
994 if (hr_dev->hw->reset)
995 hr_dev->hw->reset(hr_dev, false);
996 }
997
998 MODULE_LICENSE("Dual BSD/GPL");
999 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1000 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1001 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1002 MODULE_DESCRIPTION("HNS RoCE Driver");
1003
