Searched defs:hdmi_8996_phy_pll_reg_cfg (Results 1 – 1 of 1) sorted by relevance
41 struct hdmi_8996_phy_pll_reg_cfg { struct42 u32 tx_lx_lane_mode[HDMI_NUM_TX_CHANNEL];43 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];44 u32 com_svs_mode_clk_sel;45 u32 com_hsclk_sel;46 u32 com_pll_cctrl_mode0;47 u32 com_pll_rctrl_mode0;48 u32 com_cp_ctrl_mode0;49 u32 com_dec_start_mode0;50 u32 com_div_frac_start1_mode0;[all …]
