Searched defs:hdmi_8996_phy_pll_reg_cfg (Results 1 – 1 of 1) sorted by relevance
48 struct hdmi_8996_phy_pll_reg_cfg { struct49 u32 tx_lx_lane_mode[HDMI_NUM_TX_CHANNEL];50 u32 tx_lx_tx_band[HDMI_NUM_TX_CHANNEL];51 u32 com_svs_mode_clk_sel;52 u32 com_hsclk_sel;53 u32 com_pll_cctrl_mode0;54 u32 com_pll_rctrl_mode0;55 u32 com_cp_ctrl_mode0;56 u32 com_dec_start_mode0;57 u32 com_div_frac_start1_mode0;[all …]
