1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #include "hclge_err.h"
5
6 static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
7 {
8 .int_msk = BIT(1),
9 .msg = "imp_itcm0_ecc_mbit_err",
10 .reset_level = HNAE3_NONE_RESET
11 }, {
12 .int_msk = BIT(3),
13 .msg = "imp_itcm1_ecc_mbit_err",
14 .reset_level = HNAE3_NONE_RESET
15 }, {
16 .int_msk = BIT(5),
17 .msg = "imp_itcm2_ecc_mbit_err",
18 .reset_level = HNAE3_NONE_RESET
19 }, {
20 .int_msk = BIT(7),
21 .msg = "imp_itcm3_ecc_mbit_err",
22 .reset_level = HNAE3_NONE_RESET
23 }, {
24 .int_msk = BIT(9),
25 .msg = "imp_dtcm0_mem0_ecc_mbit_err",
26 .reset_level = HNAE3_NONE_RESET
27 }, {
28 .int_msk = BIT(11),
29 .msg = "imp_dtcm0_mem1_ecc_mbit_err",
30 .reset_level = HNAE3_NONE_RESET
31 }, {
32 .int_msk = BIT(13),
33 .msg = "imp_dtcm1_mem0_ecc_mbit_err",
34 .reset_level = HNAE3_NONE_RESET
35 }, {
36 .int_msk = BIT(15),
37 .msg = "imp_dtcm1_mem1_ecc_mbit_err",
38 .reset_level = HNAE3_NONE_RESET
39 }, {
40 .int_msk = BIT(17),
41 .msg = "imp_itcm4_ecc_mbit_err",
42 .reset_level = HNAE3_NONE_RESET
43 }, {
44 /* sentinel */
45 }
46 };
47
48 static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
49 {
50 .int_msk = BIT(1),
51 .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
52 .reset_level = HNAE3_NONE_RESET
53 }, {
54 .int_msk = BIT(3),
55 .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
56 .reset_level = HNAE3_NONE_RESET
57 }, {
58 .int_msk = BIT(5),
59 .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
60 .reset_level = HNAE3_NONE_RESET
61 }, {
62 .int_msk = BIT(7),
63 .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
64 .reset_level = HNAE3_NONE_RESET
65 }, {
66 .int_msk = BIT(9),
67 .msg = "cmdq_nic_rx_head_ecc_mbit_err",
68 .reset_level = HNAE3_NONE_RESET
69 }, {
70 .int_msk = BIT(11),
71 .msg = "cmdq_nic_tx_head_ecc_mbit_err",
72 .reset_level = HNAE3_NONE_RESET
73 }, {
74 .int_msk = BIT(13),
75 .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
76 .reset_level = HNAE3_NONE_RESET
77 }, {
78 .int_msk = BIT(15),
79 .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
80 .reset_level = HNAE3_NONE_RESET
81 }, {
82 .int_msk = BIT(17),
83 .msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
84 .reset_level = HNAE3_NONE_RESET
85 }, {
86 .int_msk = BIT(19),
87 .msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
88 .reset_level = HNAE3_NONE_RESET
89 }, {
90 .int_msk = BIT(21),
91 .msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
92 .reset_level = HNAE3_NONE_RESET
93 }, {
94 .int_msk = BIT(23),
95 .msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
96 .reset_level = HNAE3_NONE_RESET
97 }, {
98 .int_msk = BIT(25),
99 .msg = "cmdq_rocee_rx_head_ecc_mbit_err",
100 .reset_level = HNAE3_NONE_RESET
101 }, {
102 .int_msk = BIT(27),
103 .msg = "cmdq_rocee_tx_head_ecc_mbit_err",
104 .reset_level = HNAE3_NONE_RESET
105 }, {
106 .int_msk = BIT(29),
107 .msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
108 .reset_level = HNAE3_NONE_RESET
109 }, {
110 .int_msk = BIT(31),
111 .msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
112 .reset_level = HNAE3_NONE_RESET
113 }, {
114 /* sentinel */
115 }
116 };
117
118 static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
119 {
120 .int_msk = BIT(6),
121 .msg = "tqp_int_cfg_even_ecc_mbit_err",
122 .reset_level = HNAE3_NONE_RESET
123 }, {
124 .int_msk = BIT(7),
125 .msg = "tqp_int_cfg_odd_ecc_mbit_err",
126 .reset_level = HNAE3_NONE_RESET
127 }, {
128 .int_msk = BIT(8),
129 .msg = "tqp_int_ctrl_even_ecc_mbit_err",
130 .reset_level = HNAE3_NONE_RESET
131 }, {
132 .int_msk = BIT(9),
133 .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
134 .reset_level = HNAE3_NONE_RESET
135 }, {
136 .int_msk = BIT(10),
137 .msg = "tx_que_scan_int_ecc_mbit_err",
138 .reset_level = HNAE3_NONE_RESET
139 }, {
140 .int_msk = BIT(11),
141 .msg = "rx_que_scan_int_ecc_mbit_err",
142 .reset_level = HNAE3_NONE_RESET
143 }, {
144 /* sentinel */
145 }
146 };
147
148 static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
149 {
150 .int_msk = BIT(1),
151 .msg = "msix_nic_ecc_mbit_err",
152 .reset_level = HNAE3_NONE_RESET
153 }, {
154 .int_msk = BIT(3),
155 .msg = "msix_rocee_ecc_mbit_err",
156 .reset_level = HNAE3_NONE_RESET
157 }, {
158 /* sentinel */
159 }
160 };
161
162 static const struct hclge_hw_error hclge_igu_int[] = {
163 {
164 .int_msk = BIT(0),
165 .msg = "igu_rx_buf0_ecc_mbit_err",
166 .reset_level = HNAE3_GLOBAL_RESET
167 }, {
168 .int_msk = BIT(2),
169 .msg = "igu_rx_buf1_ecc_mbit_err",
170 .reset_level = HNAE3_GLOBAL_RESET
171 }, {
172 /* sentinel */
173 }
174 };
175
176 static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
177 {
178 .int_msk = BIT(0),
179 .msg = "rx_buf_overflow",
180 .reset_level = HNAE3_GLOBAL_RESET
181 }, {
182 .int_msk = BIT(1),
183 .msg = "rx_stp_fifo_overflow",
184 .reset_level = HNAE3_GLOBAL_RESET
185 }, {
186 .int_msk = BIT(2),
187 .msg = "rx_stp_fifo_underflow",
188 .reset_level = HNAE3_GLOBAL_RESET
189 }, {
190 .int_msk = BIT(3),
191 .msg = "tx_buf_overflow",
192 .reset_level = HNAE3_GLOBAL_RESET
193 }, {
194 .int_msk = BIT(4),
195 .msg = "tx_buf_underrun",
196 .reset_level = HNAE3_GLOBAL_RESET
197 }, {
198 .int_msk = BIT(5),
199 .msg = "rx_stp_buf_overflow",
200 .reset_level = HNAE3_GLOBAL_RESET
201 }, {
202 /* sentinel */
203 }
204 };
205
206 static const struct hclge_hw_error hclge_ncsi_err_int[] = {
207 {
208 .int_msk = BIT(1),
209 .msg = "ncsi_tx_ecc_mbit_err",
210 .reset_level = HNAE3_NONE_RESET
211 }, {
212 /* sentinel */
213 }
214 };
215
216 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
217 {
218 .int_msk = BIT(0),
219 .msg = "vf_vlan_ad_mem_ecc_mbit_err",
220 .reset_level = HNAE3_GLOBAL_RESET
221 }, {
222 .int_msk = BIT(1),
223 .msg = "umv_mcast_group_mem_ecc_mbit_err",
224 .reset_level = HNAE3_GLOBAL_RESET
225 }, {
226 .int_msk = BIT(2),
227 .msg = "umv_key_mem0_ecc_mbit_err",
228 .reset_level = HNAE3_GLOBAL_RESET
229 }, {
230 .int_msk = BIT(3),
231 .msg = "umv_key_mem1_ecc_mbit_err",
232 .reset_level = HNAE3_GLOBAL_RESET
233 }, {
234 .int_msk = BIT(4),
235 .msg = "umv_key_mem2_ecc_mbit_err",
236 .reset_level = HNAE3_GLOBAL_RESET
237 }, {
238 .int_msk = BIT(5),
239 .msg = "umv_key_mem3_ecc_mbit_err",
240 .reset_level = HNAE3_GLOBAL_RESET
241 }, {
242 .int_msk = BIT(6),
243 .msg = "umv_ad_mem_ecc_mbit_err",
244 .reset_level = HNAE3_GLOBAL_RESET
245 }, {
246 .int_msk = BIT(7),
247 .msg = "rss_tc_mode_mem_ecc_mbit_err",
248 .reset_level = HNAE3_GLOBAL_RESET
249 }, {
250 .int_msk = BIT(8),
251 .msg = "rss_idt_mem0_ecc_mbit_err",
252 .reset_level = HNAE3_GLOBAL_RESET
253 }, {
254 .int_msk = BIT(9),
255 .msg = "rss_idt_mem1_ecc_mbit_err",
256 .reset_level = HNAE3_GLOBAL_RESET
257 }, {
258 .int_msk = BIT(10),
259 .msg = "rss_idt_mem2_ecc_mbit_err",
260 .reset_level = HNAE3_GLOBAL_RESET
261 }, {
262 .int_msk = BIT(11),
263 .msg = "rss_idt_mem3_ecc_mbit_err",
264 .reset_level = HNAE3_GLOBAL_RESET
265 }, {
266 .int_msk = BIT(12),
267 .msg = "rss_idt_mem4_ecc_mbit_err",
268 .reset_level = HNAE3_GLOBAL_RESET
269 }, {
270 .int_msk = BIT(13),
271 .msg = "rss_idt_mem5_ecc_mbit_err",
272 .reset_level = HNAE3_GLOBAL_RESET
273 }, {
274 .int_msk = BIT(14),
275 .msg = "rss_idt_mem6_ecc_mbit_err",
276 .reset_level = HNAE3_GLOBAL_RESET
277 }, {
278 .int_msk = BIT(15),
279 .msg = "rss_idt_mem7_ecc_mbit_err",
280 .reset_level = HNAE3_GLOBAL_RESET
281 }, {
282 .int_msk = BIT(16),
283 .msg = "rss_idt_mem8_ecc_mbit_err",
284 .reset_level = HNAE3_GLOBAL_RESET
285 }, {
286 .int_msk = BIT(17),
287 .msg = "rss_idt_mem9_ecc_mbit_err",
288 .reset_level = HNAE3_GLOBAL_RESET
289 }, {
290 .int_msk = BIT(18),
291 .msg = "rss_idt_mem10_ecc_mbit_err",
292 .reset_level = HNAE3_GLOBAL_RESET
293 }, {
294 .int_msk = BIT(19),
295 .msg = "rss_idt_mem11_ecc_mbit_err",
296 .reset_level = HNAE3_GLOBAL_RESET
297 }, {
298 .int_msk = BIT(20),
299 .msg = "rss_idt_mem12_ecc_mbit_err",
300 .reset_level = HNAE3_GLOBAL_RESET
301 }, {
302 .int_msk = BIT(21),
303 .msg = "rss_idt_mem13_ecc_mbit_err",
304 .reset_level = HNAE3_GLOBAL_RESET
305 }, {
306 .int_msk = BIT(22),
307 .msg = "rss_idt_mem14_ecc_mbit_err",
308 .reset_level = HNAE3_GLOBAL_RESET
309 }, {
310 .int_msk = BIT(23),
311 .msg = "rss_idt_mem15_ecc_mbit_err",
312 .reset_level = HNAE3_GLOBAL_RESET
313 }, {
314 .int_msk = BIT(24),
315 .msg = "port_vlan_mem_ecc_mbit_err",
316 .reset_level = HNAE3_GLOBAL_RESET
317 }, {
318 .int_msk = BIT(25),
319 .msg = "mcast_linear_table_mem_ecc_mbit_err",
320 .reset_level = HNAE3_GLOBAL_RESET
321 }, {
322 .int_msk = BIT(26),
323 .msg = "mcast_result_mem_ecc_mbit_err",
324 .reset_level = HNAE3_GLOBAL_RESET
325 }, {
326 .int_msk = BIT(27),
327 .msg = "flow_director_ad_mem0_ecc_mbit_err",
328 .reset_level = HNAE3_GLOBAL_RESET
329 }, {
330 .int_msk = BIT(28),
331 .msg = "flow_director_ad_mem1_ecc_mbit_err",
332 .reset_level = HNAE3_GLOBAL_RESET
333 }, {
334 .int_msk = BIT(29),
335 .msg = "rx_vlan_tag_memory_ecc_mbit_err",
336 .reset_level = HNAE3_GLOBAL_RESET
337 }, {
338 .int_msk = BIT(30),
339 .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
340 .reset_level = HNAE3_GLOBAL_RESET
341 }, {
342 /* sentinel */
343 }
344 };
345
346 static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
347 {
348 .int_msk = BIT(0),
349 .msg = "tx_vlan_tag_err",
350 .reset_level = HNAE3_NONE_RESET
351 }, {
352 .int_msk = BIT(1),
353 .msg = "rss_list_tc_unassigned_queue_err",
354 .reset_level = HNAE3_NONE_RESET
355 }, {
356 /* sentinel */
357 }
358 };
359
360 static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
361 {
362 .int_msk = BIT(0),
363 .msg = "hfs_fifo_mem_ecc_mbit_err",
364 .reset_level = HNAE3_GLOBAL_RESET
365 }, {
366 .int_msk = BIT(1),
367 .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
368 .reset_level = HNAE3_GLOBAL_RESET
369 }, {
370 .int_msk = BIT(2),
371 .msg = "tx_vlan_tag_mem_ecc_mbit_err",
372 .reset_level = HNAE3_GLOBAL_RESET
373 }, {
374 .int_msk = BIT(3),
375 .msg = "FD_CN0_memory_ecc_mbit_err",
376 .reset_level = HNAE3_GLOBAL_RESET
377 }, {
378 .int_msk = BIT(4),
379 .msg = "FD_CN1_memory_ecc_mbit_err",
380 .reset_level = HNAE3_GLOBAL_RESET
381 }, {
382 .int_msk = BIT(5),
383 .msg = "GRO_AD_memory_ecc_mbit_err",
384 .reset_level = HNAE3_GLOBAL_RESET
385 }, {
386 /* sentinel */
387 }
388 };
389
390 static const struct hclge_hw_error hclge_tm_sch_rint[] = {
391 {
392 .int_msk = BIT(1),
393 .msg = "tm_sch_ecc_mbit_err",
394 .reset_level = HNAE3_GLOBAL_RESET
395 }, {
396 .int_msk = BIT(2),
397 .msg = "tm_sch_port_shap_sub_fifo_wr_err",
398 .reset_level = HNAE3_GLOBAL_RESET
399 }, {
400 .int_msk = BIT(3),
401 .msg = "tm_sch_port_shap_sub_fifo_rd_err",
402 .reset_level = HNAE3_GLOBAL_RESET
403 }, {
404 .int_msk = BIT(4),
405 .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
406 .reset_level = HNAE3_GLOBAL_RESET
407 }, {
408 .int_msk = BIT(5),
409 .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
410 .reset_level = HNAE3_GLOBAL_RESET
411 }, {
412 .int_msk = BIT(6),
413 .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
414 .reset_level = HNAE3_GLOBAL_RESET
415 }, {
416 .int_msk = BIT(7),
417 .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
418 .reset_level = HNAE3_GLOBAL_RESET
419 }, {
420 .int_msk = BIT(8),
421 .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
422 .reset_level = HNAE3_GLOBAL_RESET
423 }, {
424 .int_msk = BIT(9),
425 .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
426 .reset_level = HNAE3_GLOBAL_RESET
427 }, {
428 .int_msk = BIT(10),
429 .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
430 .reset_level = HNAE3_GLOBAL_RESET
431 }, {
432 .int_msk = BIT(11),
433 .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
434 .reset_level = HNAE3_GLOBAL_RESET
435 }, {
436 .int_msk = BIT(12),
437 .msg = "tm_sch_port_shap_offset_fifo_wr_err",
438 .reset_level = HNAE3_GLOBAL_RESET
439 }, {
440 .int_msk = BIT(13),
441 .msg = "tm_sch_port_shap_offset_fifo_rd_err",
442 .reset_level = HNAE3_GLOBAL_RESET
443 }, {
444 .int_msk = BIT(14),
445 .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
446 .reset_level = HNAE3_GLOBAL_RESET
447 }, {
448 .int_msk = BIT(15),
449 .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
450 .reset_level = HNAE3_GLOBAL_RESET
451 }, {
452 .int_msk = BIT(16),
453 .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
454 .reset_level = HNAE3_GLOBAL_RESET
455 }, {
456 .int_msk = BIT(17),
457 .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
458 .reset_level = HNAE3_GLOBAL_RESET
459 }, {
460 .int_msk = BIT(18),
461 .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
462 .reset_level = HNAE3_GLOBAL_RESET
463 }, {
464 .int_msk = BIT(19),
465 .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
466 .reset_level = HNAE3_GLOBAL_RESET
467 }, {
468 .int_msk = BIT(20),
469 .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
470 .reset_level = HNAE3_GLOBAL_RESET
471 }, {
472 .int_msk = BIT(21),
473 .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
474 .reset_level = HNAE3_GLOBAL_RESET
475 }, {
476 .int_msk = BIT(22),
477 .msg = "tm_sch_rq_fifo_wr_err",
478 .reset_level = HNAE3_GLOBAL_RESET
479 }, {
480 .int_msk = BIT(23),
481 .msg = "tm_sch_rq_fifo_rd_err",
482 .reset_level = HNAE3_GLOBAL_RESET
483 }, {
484 .int_msk = BIT(24),
485 .msg = "tm_sch_nq_fifo_wr_err",
486 .reset_level = HNAE3_GLOBAL_RESET
487 }, {
488 .int_msk = BIT(25),
489 .msg = "tm_sch_nq_fifo_rd_err",
490 .reset_level = HNAE3_GLOBAL_RESET
491 }, {
492 .int_msk = BIT(26),
493 .msg = "tm_sch_roce_up_fifo_wr_err",
494 .reset_level = HNAE3_GLOBAL_RESET
495 }, {
496 .int_msk = BIT(27),
497 .msg = "tm_sch_roce_up_fifo_rd_err",
498 .reset_level = HNAE3_GLOBAL_RESET
499 }, {
500 .int_msk = BIT(28),
501 .msg = "tm_sch_rcb_byte_fifo_wr_err",
502 .reset_level = HNAE3_GLOBAL_RESET
503 }, {
504 .int_msk = BIT(29),
505 .msg = "tm_sch_rcb_byte_fifo_rd_err",
506 .reset_level = HNAE3_GLOBAL_RESET
507 }, {
508 .int_msk = BIT(30),
509 .msg = "tm_sch_ssu_byte_fifo_wr_err",
510 .reset_level = HNAE3_GLOBAL_RESET
511 }, {
512 .int_msk = BIT(31),
513 .msg = "tm_sch_ssu_byte_fifo_rd_err",
514 .reset_level = HNAE3_GLOBAL_RESET
515 }, {
516 /* sentinel */
517 }
518 };
519
520 static const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
521 {
522 .int_msk = BIT(0),
523 .msg = "qcn_shap_gp0_sch_fifo_rd_err",
524 .reset_level = HNAE3_GLOBAL_RESET
525 }, {
526 .int_msk = BIT(1),
527 .msg = "qcn_shap_gp0_sch_fifo_wr_err",
528 .reset_level = HNAE3_GLOBAL_RESET
529 }, {
530 .int_msk = BIT(2),
531 .msg = "qcn_shap_gp1_sch_fifo_rd_err",
532 .reset_level = HNAE3_GLOBAL_RESET
533 }, {
534 .int_msk = BIT(3),
535 .msg = "qcn_shap_gp1_sch_fifo_wr_err",
536 .reset_level = HNAE3_GLOBAL_RESET
537 }, {
538 .int_msk = BIT(4),
539 .msg = "qcn_shap_gp2_sch_fifo_rd_err",
540 .reset_level = HNAE3_GLOBAL_RESET
541 }, {
542 .int_msk = BIT(5),
543 .msg = "qcn_shap_gp2_sch_fifo_wr_err",
544 .reset_level = HNAE3_GLOBAL_RESET
545 }, {
546 .int_msk = BIT(6),
547 .msg = "qcn_shap_gp3_sch_fifo_rd_err",
548 .reset_level = HNAE3_GLOBAL_RESET
549 }, {
550 .int_msk = BIT(7),
551 .msg = "qcn_shap_gp3_sch_fifo_wr_err",
552 .reset_level = HNAE3_GLOBAL_RESET
553 }, {
554 .int_msk = BIT(8),
555 .msg = "qcn_shap_gp0_offset_fifo_rd_err",
556 .reset_level = HNAE3_GLOBAL_RESET
557 }, {
558 .int_msk = BIT(9),
559 .msg = "qcn_shap_gp0_offset_fifo_wr_err",
560 .reset_level = HNAE3_GLOBAL_RESET
561 }, {
562 .int_msk = BIT(10),
563 .msg = "qcn_shap_gp1_offset_fifo_rd_err",
564 .reset_level = HNAE3_GLOBAL_RESET
565 }, {
566 .int_msk = BIT(11),
567 .msg = "qcn_shap_gp1_offset_fifo_wr_err",
568 .reset_level = HNAE3_GLOBAL_RESET
569 }, {
570 .int_msk = BIT(12),
571 .msg = "qcn_shap_gp2_offset_fifo_rd_err",
572 .reset_level = HNAE3_GLOBAL_RESET
573 }, {
574 .int_msk = BIT(13),
575 .msg = "qcn_shap_gp2_offset_fifo_wr_err",
576 .reset_level = HNAE3_GLOBAL_RESET
577 }, {
578 .int_msk = BIT(14),
579 .msg = "qcn_shap_gp3_offset_fifo_rd_err",
580 .reset_level = HNAE3_GLOBAL_RESET
581 }, {
582 .int_msk = BIT(15),
583 .msg = "qcn_shap_gp3_offset_fifo_wr_err",
584 .reset_level = HNAE3_GLOBAL_RESET
585 }, {
586 .int_msk = BIT(16),
587 .msg = "qcn_byte_info_fifo_rd_err",
588 .reset_level = HNAE3_GLOBAL_RESET
589 }, {
590 .int_msk = BIT(17),
591 .msg = "qcn_byte_info_fifo_wr_err",
592 .reset_level = HNAE3_GLOBAL_RESET
593 }, {
594 /* sentinel */
595 }
596 };
597
598 static const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
599 {
600 .int_msk = BIT(1),
601 .msg = "qcn_byte_mem_ecc_mbit_err",
602 .reset_level = HNAE3_GLOBAL_RESET
603 }, {
604 .int_msk = BIT(3),
605 .msg = "qcn_time_mem_ecc_mbit_err",
606 .reset_level = HNAE3_GLOBAL_RESET
607 }, {
608 .int_msk = BIT(5),
609 .msg = "qcn_fb_mem_ecc_mbit_err",
610 .reset_level = HNAE3_GLOBAL_RESET
611 }, {
612 .int_msk = BIT(7),
613 .msg = "qcn_link_mem_ecc_mbit_err",
614 .reset_level = HNAE3_GLOBAL_RESET
615 }, {
616 .int_msk = BIT(9),
617 .msg = "qcn_rate_mem_ecc_mbit_err",
618 .reset_level = HNAE3_GLOBAL_RESET
619 }, {
620 .int_msk = BIT(11),
621 .msg = "qcn_tmplt_mem_ecc_mbit_err",
622 .reset_level = HNAE3_GLOBAL_RESET
623 }, {
624 .int_msk = BIT(13),
625 .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
626 .reset_level = HNAE3_GLOBAL_RESET
627 }, {
628 .int_msk = BIT(15),
629 .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
630 .reset_level = HNAE3_GLOBAL_RESET
631 }, {
632 .int_msk = BIT(17),
633 .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
634 .reset_level = HNAE3_GLOBAL_RESET
635 }, {
636 .int_msk = BIT(19),
637 .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
638 .reset_level = HNAE3_GLOBAL_RESET
639 }, {
640 .int_msk = BIT(21),
641 .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
642 .reset_level = HNAE3_GLOBAL_RESET
643 }, {
644 /* sentinel */
645 }
646 };
647
648 static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
649 {
650 .int_msk = BIT(0),
651 .msg = "egu_cge_afifo_ecc_1bit_err",
652 .reset_level = HNAE3_NONE_RESET
653 }, {
654 .int_msk = BIT(1),
655 .msg = "egu_cge_afifo_ecc_mbit_err",
656 .reset_level = HNAE3_GLOBAL_RESET
657 }, {
658 .int_msk = BIT(2),
659 .msg = "egu_lge_afifo_ecc_1bit_err",
660 .reset_level = HNAE3_NONE_RESET
661 }, {
662 .int_msk = BIT(3),
663 .msg = "egu_lge_afifo_ecc_mbit_err",
664 .reset_level = HNAE3_GLOBAL_RESET
665 }, {
666 .int_msk = BIT(4),
667 .msg = "cge_igu_afifo_ecc_1bit_err",
668 .reset_level = HNAE3_NONE_RESET
669 }, {
670 .int_msk = BIT(5),
671 .msg = "cge_igu_afifo_ecc_mbit_err",
672 .reset_level = HNAE3_GLOBAL_RESET
673 }, {
674 .int_msk = BIT(6),
675 .msg = "lge_igu_afifo_ecc_1bit_err",
676 .reset_level = HNAE3_NONE_RESET
677 }, {
678 .int_msk = BIT(7),
679 .msg = "lge_igu_afifo_ecc_mbit_err",
680 .reset_level = HNAE3_GLOBAL_RESET
681 }, {
682 .int_msk = BIT(8),
683 .msg = "cge_igu_afifo_overflow_err",
684 .reset_level = HNAE3_GLOBAL_RESET
685 }, {
686 .int_msk = BIT(9),
687 .msg = "lge_igu_afifo_overflow_err",
688 .reset_level = HNAE3_GLOBAL_RESET
689 }, {
690 .int_msk = BIT(10),
691 .msg = "egu_cge_afifo_underrun_err",
692 .reset_level = HNAE3_GLOBAL_RESET
693 }, {
694 .int_msk = BIT(11),
695 .msg = "egu_lge_afifo_underrun_err",
696 .reset_level = HNAE3_GLOBAL_RESET
697 }, {
698 .int_msk = BIT(12),
699 .msg = "egu_ge_afifo_underrun_err",
700 .reset_level = HNAE3_GLOBAL_RESET
701 }, {
702 .int_msk = BIT(13),
703 .msg = "ge_igu_afifo_overflow_err",
704 .reset_level = HNAE3_GLOBAL_RESET
705 }, {
706 /* sentinel */
707 }
708 };
709
710 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
711 {
712 .int_msk = BIT(13),
713 .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
714 .reset_level = HNAE3_GLOBAL_RESET
715 }, {
716 .int_msk = BIT(14),
717 .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
718 .reset_level = HNAE3_GLOBAL_RESET
719 }, {
720 .int_msk = BIT(15),
721 .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
722 .reset_level = HNAE3_GLOBAL_RESET
723 }, {
724 .int_msk = BIT(16),
725 .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
726 .reset_level = HNAE3_GLOBAL_RESET
727 }, {
728 .int_msk = BIT(17),
729 .msg = "rcb_tx_ring_ecc_mbit_err",
730 .reset_level = HNAE3_GLOBAL_RESET
731 }, {
732 .int_msk = BIT(18),
733 .msg = "rcb_rx_ring_ecc_mbit_err",
734 .reset_level = HNAE3_GLOBAL_RESET
735 }, {
736 .int_msk = BIT(19),
737 .msg = "rcb_tx_fbd_ecc_mbit_err",
738 .reset_level = HNAE3_GLOBAL_RESET
739 }, {
740 .int_msk = BIT(20),
741 .msg = "rcb_rx_ebd_ecc_mbit_err",
742 .reset_level = HNAE3_GLOBAL_RESET
743 }, {
744 .int_msk = BIT(21),
745 .msg = "rcb_tso_info_ecc_mbit_err",
746 .reset_level = HNAE3_GLOBAL_RESET
747 }, {
748 .int_msk = BIT(22),
749 .msg = "rcb_tx_int_info_ecc_mbit_err",
750 .reset_level = HNAE3_GLOBAL_RESET
751 }, {
752 .int_msk = BIT(23),
753 .msg = "rcb_rx_int_info_ecc_mbit_err",
754 .reset_level = HNAE3_GLOBAL_RESET
755 }, {
756 .int_msk = BIT(24),
757 .msg = "tpu_tx_pkt_0_ecc_mbit_err",
758 .reset_level = HNAE3_GLOBAL_RESET
759 }, {
760 .int_msk = BIT(25),
761 .msg = "tpu_tx_pkt_1_ecc_mbit_err",
762 .reset_level = HNAE3_GLOBAL_RESET
763 }, {
764 .int_msk = BIT(26),
765 .msg = "rd_bus_err",
766 .reset_level = HNAE3_GLOBAL_RESET
767 }, {
768 .int_msk = BIT(27),
769 .msg = "wr_bus_err",
770 .reset_level = HNAE3_GLOBAL_RESET
771 }, {
772 .int_msk = BIT(28),
773 .msg = "reg_search_miss",
774 .reset_level = HNAE3_GLOBAL_RESET
775 }, {
776 .int_msk = BIT(29),
777 .msg = "rx_q_search_miss",
778 .reset_level = HNAE3_NONE_RESET
779 }, {
780 .int_msk = BIT(30),
781 .msg = "ooo_ecc_err_detect",
782 .reset_level = HNAE3_NONE_RESET
783 }, {
784 .int_msk = BIT(31),
785 .msg = "ooo_ecc_err_multpl",
786 .reset_level = HNAE3_GLOBAL_RESET
787 }, {
788 /* sentinel */
789 }
790 };
791
792 static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
793 {
794 .int_msk = BIT(4),
795 .msg = "gro_bd_ecc_mbit_err",
796 .reset_level = HNAE3_GLOBAL_RESET
797 }, {
798 .int_msk = BIT(5),
799 .msg = "gro_context_ecc_mbit_err",
800 .reset_level = HNAE3_GLOBAL_RESET
801 }, {
802 .int_msk = BIT(6),
803 .msg = "rx_stash_cfg_ecc_mbit_err",
804 .reset_level = HNAE3_GLOBAL_RESET
805 }, {
806 .int_msk = BIT(7),
807 .msg = "axi_rd_fbd_ecc_mbit_err",
808 .reset_level = HNAE3_GLOBAL_RESET
809 }, {
810 /* sentinel */
811 }
812 };
813
814 static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
815 {
816 .int_msk = BIT(0),
817 .msg = "over_8bd_no_fe",
818 .reset_level = HNAE3_FUNC_RESET
819 }, {
820 .int_msk = BIT(1),
821 .msg = "tso_mss_cmp_min_err",
822 .reset_level = HNAE3_NONE_RESET
823 }, {
824 .int_msk = BIT(2),
825 .msg = "tso_mss_cmp_max_err",
826 .reset_level = HNAE3_NONE_RESET
827 }, {
828 .int_msk = BIT(3),
829 .msg = "tx_rd_fbd_poison",
830 .reset_level = HNAE3_FUNC_RESET
831 }, {
832 .int_msk = BIT(4),
833 .msg = "rx_rd_ebd_poison",
834 .reset_level = HNAE3_FUNC_RESET
835 }, {
836 .int_msk = BIT(5),
837 .msg = "buf_wait_timeout",
838 .reset_level = HNAE3_NONE_RESET
839 }, {
840 /* sentinel */
841 }
842 };
843
844 static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
845 {
846 .int_msk = BIT(0),
847 .msg = "buf_sum_err",
848 .reset_level = HNAE3_NONE_RESET
849 }, {
850 .int_msk = BIT(1),
851 .msg = "ppp_mb_num_err",
852 .reset_level = HNAE3_NONE_RESET
853 }, {
854 .int_msk = BIT(2),
855 .msg = "ppp_mbid_err",
856 .reset_level = HNAE3_GLOBAL_RESET
857 }, {
858 .int_msk = BIT(3),
859 .msg = "ppp_rlt_mac_err",
860 .reset_level = HNAE3_GLOBAL_RESET
861 }, {
862 .int_msk = BIT(4),
863 .msg = "ppp_rlt_host_err",
864 .reset_level = HNAE3_GLOBAL_RESET
865 }, {
866 .int_msk = BIT(5),
867 .msg = "cks_edit_position_err",
868 .reset_level = HNAE3_GLOBAL_RESET
869 }, {
870 .int_msk = BIT(6),
871 .msg = "cks_edit_condition_err",
872 .reset_level = HNAE3_GLOBAL_RESET
873 }, {
874 .int_msk = BIT(7),
875 .msg = "vlan_edit_condition_err",
876 .reset_level = HNAE3_GLOBAL_RESET
877 }, {
878 .int_msk = BIT(8),
879 .msg = "vlan_num_ot_err",
880 .reset_level = HNAE3_GLOBAL_RESET
881 }, {
882 .int_msk = BIT(9),
883 .msg = "vlan_num_in_err",
884 .reset_level = HNAE3_GLOBAL_RESET
885 }, {
886 /* sentinel */
887 }
888 };
889
890 #define HCLGE_SSU_MEM_ECC_ERR(x) \
891 { \
892 .int_msk = BIT(x), \
893 .msg = "ssu_mem" #x "_ecc_mbit_err", \
894 .reset_level = HNAE3_GLOBAL_RESET \
895 }
896
897 static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
898 HCLGE_SSU_MEM_ECC_ERR(0),
899 HCLGE_SSU_MEM_ECC_ERR(1),
900 HCLGE_SSU_MEM_ECC_ERR(2),
901 HCLGE_SSU_MEM_ECC_ERR(3),
902 HCLGE_SSU_MEM_ECC_ERR(4),
903 HCLGE_SSU_MEM_ECC_ERR(5),
904 HCLGE_SSU_MEM_ECC_ERR(6),
905 HCLGE_SSU_MEM_ECC_ERR(7),
906 HCLGE_SSU_MEM_ECC_ERR(8),
907 HCLGE_SSU_MEM_ECC_ERR(9),
908 HCLGE_SSU_MEM_ECC_ERR(10),
909 HCLGE_SSU_MEM_ECC_ERR(11),
910 HCLGE_SSU_MEM_ECC_ERR(12),
911 HCLGE_SSU_MEM_ECC_ERR(13),
912 HCLGE_SSU_MEM_ECC_ERR(14),
913 HCLGE_SSU_MEM_ECC_ERR(15),
914 HCLGE_SSU_MEM_ECC_ERR(16),
915 HCLGE_SSU_MEM_ECC_ERR(17),
916 HCLGE_SSU_MEM_ECC_ERR(18),
917 HCLGE_SSU_MEM_ECC_ERR(19),
918 HCLGE_SSU_MEM_ECC_ERR(20),
919 HCLGE_SSU_MEM_ECC_ERR(21),
920 HCLGE_SSU_MEM_ECC_ERR(22),
921 HCLGE_SSU_MEM_ECC_ERR(23),
922 HCLGE_SSU_MEM_ECC_ERR(24),
923 HCLGE_SSU_MEM_ECC_ERR(25),
924 HCLGE_SSU_MEM_ECC_ERR(26),
925 HCLGE_SSU_MEM_ECC_ERR(27),
926 HCLGE_SSU_MEM_ECC_ERR(28),
927 HCLGE_SSU_MEM_ECC_ERR(29),
928 HCLGE_SSU_MEM_ECC_ERR(30),
929 HCLGE_SSU_MEM_ECC_ERR(31),
930 { /* sentinel */ }
931 };
932
933 static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
934 {
935 .int_msk = BIT(0),
936 .msg = "roc_pkt_without_key_port",
937 .reset_level = HNAE3_FUNC_RESET
938 }, {
939 .int_msk = BIT(1),
940 .msg = "tpu_pkt_without_key_port",
941 .reset_level = HNAE3_GLOBAL_RESET
942 }, {
943 .int_msk = BIT(2),
944 .msg = "igu_pkt_without_key_port",
945 .reset_level = HNAE3_GLOBAL_RESET
946 }, {
947 .int_msk = BIT(3),
948 .msg = "roc_eof_mis_match_port",
949 .reset_level = HNAE3_GLOBAL_RESET
950 }, {
951 .int_msk = BIT(4),
952 .msg = "tpu_eof_mis_match_port",
953 .reset_level = HNAE3_GLOBAL_RESET
954 }, {
955 .int_msk = BIT(5),
956 .msg = "igu_eof_mis_match_port",
957 .reset_level = HNAE3_GLOBAL_RESET
958 }, {
959 .int_msk = BIT(6),
960 .msg = "roc_sof_mis_match_port",
961 .reset_level = HNAE3_GLOBAL_RESET
962 }, {
963 .int_msk = BIT(7),
964 .msg = "tpu_sof_mis_match_port",
965 .reset_level = HNAE3_GLOBAL_RESET
966 }, {
967 .int_msk = BIT(8),
968 .msg = "igu_sof_mis_match_port",
969 .reset_level = HNAE3_GLOBAL_RESET
970 }, {
971 .int_msk = BIT(11),
972 .msg = "ets_rd_int_rx_port",
973 .reset_level = HNAE3_GLOBAL_RESET
974 }, {
975 .int_msk = BIT(12),
976 .msg = "ets_wr_int_rx_port",
977 .reset_level = HNAE3_GLOBAL_RESET
978 }, {
979 .int_msk = BIT(13),
980 .msg = "ets_rd_int_tx_port",
981 .reset_level = HNAE3_GLOBAL_RESET
982 }, {
983 .int_msk = BIT(14),
984 .msg = "ets_wr_int_tx_port",
985 .reset_level = HNAE3_GLOBAL_RESET
986 }, {
987 /* sentinel */
988 }
989 };
990
991 static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
992 {
993 .int_msk = BIT(0),
994 .msg = "ig_mac_inf_int",
995 .reset_level = HNAE3_GLOBAL_RESET
996 }, {
997 .int_msk = BIT(1),
998 .msg = "ig_host_inf_int",
999 .reset_level = HNAE3_GLOBAL_RESET
1000 }, {
1001 .int_msk = BIT(2),
1002 .msg = "ig_roc_buf_int",
1003 .reset_level = HNAE3_GLOBAL_RESET
1004 }, {
1005 .int_msk = BIT(3),
1006 .msg = "ig_host_data_fifo_int",
1007 .reset_level = HNAE3_GLOBAL_RESET
1008 }, {
1009 .int_msk = BIT(4),
1010 .msg = "ig_host_key_fifo_int",
1011 .reset_level = HNAE3_GLOBAL_RESET
1012 }, {
1013 .int_msk = BIT(5),
1014 .msg = "tx_qcn_fifo_int",
1015 .reset_level = HNAE3_GLOBAL_RESET
1016 }, {
1017 .int_msk = BIT(6),
1018 .msg = "rx_qcn_fifo_int",
1019 .reset_level = HNAE3_GLOBAL_RESET
1020 }, {
1021 .int_msk = BIT(7),
1022 .msg = "tx_pf_rd_fifo_int",
1023 .reset_level = HNAE3_GLOBAL_RESET
1024 }, {
1025 .int_msk = BIT(8),
1026 .msg = "rx_pf_rd_fifo_int",
1027 .reset_level = HNAE3_GLOBAL_RESET
1028 }, {
1029 .int_msk = BIT(9),
1030 .msg = "qm_eof_fifo_int",
1031 .reset_level = HNAE3_GLOBAL_RESET
1032 }, {
1033 .int_msk = BIT(10),
1034 .msg = "mb_rlt_fifo_int",
1035 .reset_level = HNAE3_GLOBAL_RESET
1036 }, {
1037 .int_msk = BIT(11),
1038 .msg = "dup_uncopy_fifo_int",
1039 .reset_level = HNAE3_GLOBAL_RESET
1040 }, {
1041 .int_msk = BIT(12),
1042 .msg = "dup_cnt_rd_fifo_int",
1043 .reset_level = HNAE3_GLOBAL_RESET
1044 }, {
1045 .int_msk = BIT(13),
1046 .msg = "dup_cnt_drop_fifo_int",
1047 .reset_level = HNAE3_GLOBAL_RESET
1048 }, {
1049 .int_msk = BIT(14),
1050 .msg = "dup_cnt_wrb_fifo_int",
1051 .reset_level = HNAE3_GLOBAL_RESET
1052 }, {
1053 .int_msk = BIT(15),
1054 .msg = "host_cmd_fifo_int",
1055 .reset_level = HNAE3_GLOBAL_RESET
1056 }, {
1057 .int_msk = BIT(16),
1058 .msg = "mac_cmd_fifo_int",
1059 .reset_level = HNAE3_GLOBAL_RESET
1060 }, {
1061 .int_msk = BIT(17),
1062 .msg = "host_cmd_bitmap_empty_int",
1063 .reset_level = HNAE3_GLOBAL_RESET
1064 }, {
1065 .int_msk = BIT(18),
1066 .msg = "mac_cmd_bitmap_empty_int",
1067 .reset_level = HNAE3_GLOBAL_RESET
1068 }, {
1069 .int_msk = BIT(19),
1070 .msg = "dup_bitmap_empty_int",
1071 .reset_level = HNAE3_GLOBAL_RESET
1072 }, {
1073 .int_msk = BIT(20),
1074 .msg = "out_queue_bitmap_empty_int",
1075 .reset_level = HNAE3_GLOBAL_RESET
1076 }, {
1077 .int_msk = BIT(21),
1078 .msg = "bank2_bitmap_empty_int",
1079 .reset_level = HNAE3_GLOBAL_RESET
1080 }, {
1081 .int_msk = BIT(22),
1082 .msg = "bank1_bitmap_empty_int",
1083 .reset_level = HNAE3_GLOBAL_RESET
1084 }, {
1085 .int_msk = BIT(23),
1086 .msg = "bank0_bitmap_empty_int",
1087 .reset_level = HNAE3_GLOBAL_RESET
1088 }, {
1089 /* sentinel */
1090 }
1091 };
1092
1093 static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
1094 {
1095 .int_msk = BIT(0),
1096 .msg = "ets_rd_int_rx_tcg",
1097 .reset_level = HNAE3_GLOBAL_RESET
1098 }, {
1099 .int_msk = BIT(1),
1100 .msg = "ets_wr_int_rx_tcg",
1101 .reset_level = HNAE3_GLOBAL_RESET
1102 }, {
1103 .int_msk = BIT(2),
1104 .msg = "ets_rd_int_tx_tcg",
1105 .reset_level = HNAE3_GLOBAL_RESET
1106 }, {
1107 .int_msk = BIT(3),
1108 .msg = "ets_wr_int_tx_tcg",
1109 .reset_level = HNAE3_GLOBAL_RESET
1110 }, {
1111 /* sentinel */
1112 }
1113 };
1114
1115 static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
1116 {
1117 .int_msk = BIT(0),
1118 .msg = "roc_pkt_without_key_port",
1119 .reset_level = HNAE3_FUNC_RESET
1120 }, {
1121 .int_msk = BIT(9),
1122 .msg = "low_water_line_err_port",
1123 .reset_level = HNAE3_NONE_RESET
1124 }, {
1125 .int_msk = BIT(10),
1126 .msg = "hi_water_line_err_port",
1127 .reset_level = HNAE3_GLOBAL_RESET
1128 }, {
1129 /* sentinel */
1130 }
1131 };
1132
1133 static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
1134 {
1135 .int_msk = 0,
1136 .msg = "rocee qmm ovf: sgid invalid err"
1137 }, {
1138 .int_msk = 0x4,
1139 .msg = "rocee qmm ovf: sgid ovf err"
1140 }, {
1141 .int_msk = 0x8,
1142 .msg = "rocee qmm ovf: smac invalid err"
1143 }, {
1144 .int_msk = 0xC,
1145 .msg = "rocee qmm ovf: smac ovf err"
1146 }, {
1147 .int_msk = 0x10,
1148 .msg = "rocee qmm ovf: cqc invalid err"
1149 }, {
1150 .int_msk = 0x11,
1151 .msg = "rocee qmm ovf: cqc ovf err"
1152 }, {
1153 .int_msk = 0x12,
1154 .msg = "rocee qmm ovf: cqc hopnum err"
1155 }, {
1156 .int_msk = 0x13,
1157 .msg = "rocee qmm ovf: cqc ba0 err"
1158 }, {
1159 .int_msk = 0x14,
1160 .msg = "rocee qmm ovf: srqc invalid err"
1161 }, {
1162 .int_msk = 0x15,
1163 .msg = "rocee qmm ovf: srqc ovf err"
1164 }, {
1165 .int_msk = 0x16,
1166 .msg = "rocee qmm ovf: srqc hopnum err"
1167 }, {
1168 .int_msk = 0x17,
1169 .msg = "rocee qmm ovf: srqc ba0 err"
1170 }, {
1171 .int_msk = 0x18,
1172 .msg = "rocee qmm ovf: mpt invalid err"
1173 }, {
1174 .int_msk = 0x19,
1175 .msg = "rocee qmm ovf: mpt ovf err"
1176 }, {
1177 .int_msk = 0x1A,
1178 .msg = "rocee qmm ovf: mpt hopnum err"
1179 }, {
1180 .int_msk = 0x1B,
1181 .msg = "rocee qmm ovf: mpt ba0 err"
1182 }, {
1183 .int_msk = 0x1C,
1184 .msg = "rocee qmm ovf: qpc invalid err"
1185 }, {
1186 .int_msk = 0x1D,
1187 .msg = "rocee qmm ovf: qpc ovf err"
1188 }, {
1189 .int_msk = 0x1E,
1190 .msg = "rocee qmm ovf: qpc hopnum err"
1191 }, {
1192 .int_msk = 0x1F,
1193 .msg = "rocee qmm ovf: qpc ba0 err"
1194 }, {
1195 /* sentinel */
1196 }
1197 };
1198
1199 static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
1200 {
1201 .module_id = MODULE_NONE,
1202 .msg = "MODULE_NONE"
1203 }, {
1204 .module_id = MODULE_BIOS_COMMON,
1205 .msg = "MODULE_BIOS_COMMON"
1206 }, {
1207 .module_id = MODULE_GE,
1208 .msg = "MODULE_GE"
1209 }, {
1210 .module_id = MODULE_IGU_EGU,
1211 .msg = "MODULE_IGU_EGU"
1212 }, {
1213 .module_id = MODULE_LGE,
1214 .msg = "MODULE_LGE"
1215 }, {
1216 .module_id = MODULE_NCSI,
1217 .msg = "MODULE_NCSI"
1218 }, {
1219 .module_id = MODULE_PPP,
1220 .msg = "MODULE_PPP"
1221 }, {
1222 .module_id = MODULE_QCN,
1223 .msg = "MODULE_QCN"
1224 }, {
1225 .module_id = MODULE_RCB_RX,
1226 .msg = "MODULE_RCB_RX"
1227 }, {
1228 .module_id = MODULE_RTC,
1229 .msg = "MODULE_RTC"
1230 }, {
1231 .module_id = MODULE_SSU,
1232 .msg = "MODULE_SSU"
1233 }, {
1234 .module_id = MODULE_TM,
1235 .msg = "MODULE_TM"
1236 }, {
1237 .module_id = MODULE_RCB_TX,
1238 .msg = "MODULE_RCB_TX"
1239 }, {
1240 .module_id = MODULE_TXDMA,
1241 .msg = "MODULE_TXDMA"
1242 }, {
1243 .module_id = MODULE_MASTER,
1244 .msg = "MODULE_MASTER"
1245 }, {
1246 .module_id = MODULE_ROCEE_TOP,
1247 .msg = "MODULE_ROCEE_TOP"
1248 }, {
1249 .module_id = MODULE_ROCEE_TIMER,
1250 .msg = "MODULE_ROCEE_TIMER"
1251 }, {
1252 .module_id = MODULE_ROCEE_MDB,
1253 .msg = "MODULE_ROCEE_MDB"
1254 }, {
1255 .module_id = MODULE_ROCEE_TSP,
1256 .msg = "MODULE_ROCEE_TSP"
1257 }, {
1258 .module_id = MODULE_ROCEE_TRP,
1259 .msg = "MODULE_ROCEE_TRP"
1260 }, {
1261 .module_id = MODULE_ROCEE_SCC,
1262 .msg = "MODULE_ROCEE_SCC"
1263 }, {
1264 .module_id = MODULE_ROCEE_CAEP,
1265 .msg = "MODULE_ROCEE_CAEP"
1266 }, {
1267 .module_id = MODULE_ROCEE_GEN_AC,
1268 .msg = "MODULE_ROCEE_GEN_AC"
1269 }, {
1270 .module_id = MODULE_ROCEE_QMM,
1271 .msg = "MODULE_ROCEE_QMM"
1272 }, {
1273 .module_id = MODULE_ROCEE_LSAN,
1274 .msg = "MODULE_ROCEE_LSAN"
1275 }
1276 };
1277
1278 static const struct hclge_hw_type_id hclge_hw_type_id_st[] = {
1279 {
1280 .type_id = NONE_ERROR,
1281 .msg = "none_error"
1282 }, {
1283 .type_id = FIFO_ERROR,
1284 .msg = "fifo_error"
1285 }, {
1286 .type_id = MEMORY_ERROR,
1287 .msg = "memory_error"
1288 }, {
1289 .type_id = POISON_ERROR,
1290 .msg = "poison_error"
1291 }, {
1292 .type_id = MSIX_ECC_ERROR,
1293 .msg = "msix_ecc_error"
1294 }, {
1295 .type_id = TQP_INT_ECC_ERROR,
1296 .msg = "tqp_int_ecc_error"
1297 }, {
1298 .type_id = PF_ABNORMAL_INT_ERROR,
1299 .msg = "pf_abnormal_int_error"
1300 }, {
1301 .type_id = MPF_ABNORMAL_INT_ERROR,
1302 .msg = "mpf_abnormal_int_error"
1303 }, {
1304 .type_id = COMMON_ERROR,
1305 .msg = "common_error"
1306 }, {
1307 .type_id = PORT_ERROR,
1308 .msg = "port_error"
1309 }, {
1310 .type_id = ETS_ERROR,
1311 .msg = "ets_error"
1312 }, {
1313 .type_id = NCSI_ERROR,
1314 .msg = "ncsi_error"
1315 }, {
1316 .type_id = GLB_ERROR,
1317 .msg = "glb_error"
1318 }, {
1319 .type_id = ROCEE_NORMAL_ERR,
1320 .msg = "rocee_normal_error"
1321 }, {
1322 .type_id = ROCEE_OVF_ERR,
1323 .msg = "rocee_ovf_error"
1324 }
1325 };
1326
hclge_log_error(struct device * dev,char * reg,const struct hclge_hw_error * err,u32 err_sts,unsigned long * reset_requests)1327 static void hclge_log_error(struct device *dev, char *reg,
1328 const struct hclge_hw_error *err,
1329 u32 err_sts, unsigned long *reset_requests)
1330 {
1331 while (err->msg) {
1332 if (err->int_msk & err_sts) {
1333 dev_err(dev, "%s %s found [error status=0x%x]\n",
1334 reg, err->msg, err_sts);
1335 if (err->reset_level &&
1336 err->reset_level != HNAE3_NONE_RESET)
1337 set_bit(err->reset_level, reset_requests);
1338 }
1339 err++;
1340 }
1341 }
1342
1343 /* hclge_cmd_query_error: read the error information
1344 * @hdev: pointer to struct hclge_dev
1345 * @desc: descriptor for describing the command
1346 * @cmd: command opcode
1347 * @flag: flag for extended command structure
1348 *
1349 * This function query the error info from hw register/s using command
1350 */
hclge_cmd_query_error(struct hclge_dev * hdev,struct hclge_desc * desc,u32 cmd,u16 flag)1351 static int hclge_cmd_query_error(struct hclge_dev *hdev,
1352 struct hclge_desc *desc, u32 cmd, u16 flag)
1353 {
1354 struct device *dev = &hdev->pdev->dev;
1355 int desc_num = 1;
1356 int ret;
1357
1358 hclge_cmd_setup_basic_desc(&desc[0], cmd, true);
1359 if (flag) {
1360 desc[0].flag |= cpu_to_le16(flag);
1361 hclge_cmd_setup_basic_desc(&desc[1], cmd, true);
1362 desc_num = 2;
1363 }
1364
1365 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num);
1366 if (ret)
1367 dev_err(dev, "query error cmd failed (%d)\n", ret);
1368
1369 return ret;
1370 }
1371
hclge_clear_mac_tnl_int(struct hclge_dev * hdev)1372 static int hclge_clear_mac_tnl_int(struct hclge_dev *hdev)
1373 {
1374 struct hclge_desc desc;
1375
1376 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CLEAR_MAC_TNL_INT, false);
1377 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_CLR);
1378
1379 return hclge_cmd_send(&hdev->hw, &desc, 1);
1380 }
1381
hclge_config_common_hw_err_int(struct hclge_dev * hdev,bool en)1382 static int hclge_config_common_hw_err_int(struct hclge_dev *hdev, bool en)
1383 {
1384 struct device *dev = &hdev->pdev->dev;
1385 struct hclge_desc desc[2];
1386 int ret;
1387
1388 /* configure common error interrupts */
1389 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_COMMON_ECC_INT_CFG, false);
1390 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1391 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_COMMON_ECC_INT_CFG, false);
1392
1393 if (en) {
1394 desc[0].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN);
1395 desc[0].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN |
1396 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN);
1397 desc[0].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN);
1398 desc[0].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN |
1399 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN);
1400 desc[0].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN);
1401 }
1402
1403 desc[1].data[0] = cpu_to_le32(HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK);
1404 desc[1].data[2] = cpu_to_le32(HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK |
1405 HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK);
1406 desc[1].data[3] = cpu_to_le32(HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK);
1407 desc[1].data[4] = cpu_to_le32(HCLGE_TQP_ECC_ERR_INT_EN_MASK |
1408 HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK);
1409 desc[1].data[5] = cpu_to_le32(HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK);
1410
1411 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1412 if (ret)
1413 dev_err(dev,
1414 "fail(%d) to configure common err interrupts\n", ret);
1415
1416 return ret;
1417 }
1418
hclge_config_ncsi_hw_err_int(struct hclge_dev * hdev,bool en)1419 static int hclge_config_ncsi_hw_err_int(struct hclge_dev *hdev, bool en)
1420 {
1421 struct device *dev = &hdev->pdev->dev;
1422 struct hclge_desc desc;
1423 int ret;
1424
1425 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2)
1426 return 0;
1427
1428 /* configure NCSI error interrupts */
1429 hclge_cmd_setup_basic_desc(&desc, HCLGE_NCSI_INT_EN, false);
1430 if (en)
1431 desc.data[0] = cpu_to_le32(HCLGE_NCSI_ERR_INT_EN);
1432
1433 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1434 if (ret)
1435 dev_err(dev,
1436 "fail(%d) to configure NCSI error interrupts\n", ret);
1437
1438 return ret;
1439 }
1440
hclge_config_igu_egu_hw_err_int(struct hclge_dev * hdev,bool en)1441 static int hclge_config_igu_egu_hw_err_int(struct hclge_dev *hdev, bool en)
1442 {
1443 struct device *dev = &hdev->pdev->dev;
1444 struct hclge_desc desc;
1445 int ret;
1446
1447 /* configure IGU,EGU error interrupts */
1448 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_COMMON_INT_EN, false);
1449 desc.data[0] = cpu_to_le32(HCLGE_IGU_ERR_INT_TYPE);
1450 if (en)
1451 desc.data[0] |= cpu_to_le32(HCLGE_IGU_ERR_INT_EN);
1452
1453 desc.data[1] = cpu_to_le32(HCLGE_IGU_ERR_INT_EN_MASK);
1454
1455 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1456 if (ret) {
1457 dev_err(dev,
1458 "fail(%d) to configure IGU common interrupts\n", ret);
1459 return ret;
1460 }
1461
1462 hclge_cmd_setup_basic_desc(&desc, HCLGE_IGU_EGU_TNL_INT_EN, false);
1463 if (en)
1464 desc.data[0] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN);
1465
1466 desc.data[1] = cpu_to_le32(HCLGE_IGU_TNL_ERR_INT_EN_MASK);
1467
1468 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1469 if (ret) {
1470 dev_err(dev,
1471 "fail(%d) to configure IGU-EGU TNL interrupts\n", ret);
1472 return ret;
1473 }
1474
1475 ret = hclge_config_ncsi_hw_err_int(hdev, en);
1476
1477 return ret;
1478 }
1479
hclge_config_ppp_error_interrupt(struct hclge_dev * hdev,u32 cmd,bool en)1480 static int hclge_config_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd,
1481 bool en)
1482 {
1483 struct device *dev = &hdev->pdev->dev;
1484 struct hclge_desc desc[2];
1485 int ret;
1486
1487 /* configure PPP error interrupts */
1488 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
1489 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1490 hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
1491
1492 if (cmd == HCLGE_PPP_CMD0_INT_CMD) {
1493 if (en) {
1494 desc[0].data[0] =
1495 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN);
1496 desc[0].data[1] =
1497 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN);
1498 desc[0].data[4] = cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN);
1499 }
1500
1501 desc[1].data[0] =
1502 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK);
1503 desc[1].data[1] =
1504 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK);
1505 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
1506 desc[1].data[2] =
1507 cpu_to_le32(HCLGE_PPP_PF_ERR_INT_EN_MASK);
1508 } else if (cmd == HCLGE_PPP_CMD1_INT_CMD) {
1509 if (en) {
1510 desc[0].data[0] =
1511 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN);
1512 desc[0].data[1] =
1513 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN);
1514 }
1515
1516 desc[1].data[0] =
1517 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK);
1518 desc[1].data[1] =
1519 cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK);
1520 }
1521
1522 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1523 if (ret)
1524 dev_err(dev, "fail(%d) to configure PPP error intr\n", ret);
1525
1526 return ret;
1527 }
1528
hclge_config_ppp_hw_err_int(struct hclge_dev * hdev,bool en)1529 static int hclge_config_ppp_hw_err_int(struct hclge_dev *hdev, bool en)
1530 {
1531 int ret;
1532
1533 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD0_INT_CMD,
1534 en);
1535 if (ret)
1536 return ret;
1537
1538 ret = hclge_config_ppp_error_interrupt(hdev, HCLGE_PPP_CMD1_INT_CMD,
1539 en);
1540
1541 return ret;
1542 }
1543
hclge_config_tm_hw_err_int(struct hclge_dev * hdev,bool en)1544 static int hclge_config_tm_hw_err_int(struct hclge_dev *hdev, bool en)
1545 {
1546 struct device *dev = &hdev->pdev->dev;
1547 struct hclge_desc desc;
1548 int ret;
1549
1550 /* configure TM SCH hw errors */
1551 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false);
1552 if (en)
1553 desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN);
1554
1555 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1556 if (ret) {
1557 dev_err(dev, "fail(%d) to configure TM SCH errors\n", ret);
1558 return ret;
1559 }
1560
1561 /* configure TM QCN hw errors */
1562 hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_QCN_MEM_INT_CFG, false);
1563 desc.data[0] = cpu_to_le32(HCLGE_TM_QCN_ERR_INT_TYPE);
1564 if (en) {
1565 desc.data[0] |= cpu_to_le32(HCLGE_TM_QCN_FIFO_INT_EN);
1566 desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
1567 }
1568
1569 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1570 if (ret)
1571 dev_err(dev,
1572 "fail(%d) to configure TM QCN mem errors\n", ret);
1573
1574 return ret;
1575 }
1576
hclge_config_mac_err_int(struct hclge_dev * hdev,bool en)1577 static int hclge_config_mac_err_int(struct hclge_dev *hdev, bool en)
1578 {
1579 struct device *dev = &hdev->pdev->dev;
1580 struct hclge_desc desc;
1581 int ret;
1582
1583 /* configure MAC common error interrupts */
1584 hclge_cmd_setup_basic_desc(&desc, HCLGE_MAC_COMMON_INT_EN, false);
1585 if (en)
1586 desc.data[0] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN);
1587
1588 desc.data[1] = cpu_to_le32(HCLGE_MAC_COMMON_ERR_INT_EN_MASK);
1589
1590 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1591 if (ret)
1592 dev_err(dev,
1593 "fail(%d) to configure MAC COMMON error intr\n", ret);
1594
1595 return ret;
1596 }
1597
hclge_config_mac_tnl_int(struct hclge_dev * hdev,bool en)1598 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en)
1599 {
1600 struct hclge_desc desc;
1601
1602 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_TNL_INT_EN, false);
1603 if (en)
1604 desc.data[0] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN);
1605 else
1606 desc.data[0] = 0;
1607
1608 desc.data[1] = cpu_to_le32(HCLGE_MAC_TNL_INT_EN_MASK);
1609
1610 return hclge_cmd_send(&hdev->hw, &desc, 1);
1611 }
1612
hclge_config_ppu_error_interrupts(struct hclge_dev * hdev,u32 cmd,bool en)1613 static int hclge_config_ppu_error_interrupts(struct hclge_dev *hdev, u32 cmd,
1614 bool en)
1615 {
1616 struct device *dev = &hdev->pdev->dev;
1617 struct hclge_desc desc[2];
1618 int desc_num = 1;
1619 int ret;
1620
1621 /* configure PPU error interrupts */
1622 if (cmd == HCLGE_PPU_MPF_ECC_INT_CMD) {
1623 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
1624 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1625 hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
1626 if (en) {
1627 desc[0].data[0] =
1628 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN);
1629 desc[0].data[1] =
1630 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN);
1631 desc[1].data[3] =
1632 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN);
1633 desc[1].data[4] =
1634 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN);
1635 }
1636
1637 desc[1].data[0] =
1638 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK);
1639 desc[1].data[1] =
1640 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK);
1641 desc[1].data[2] =
1642 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK);
1643 desc[1].data[3] |=
1644 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK);
1645 desc_num = 2;
1646 } else if (cmd == HCLGE_PPU_MPF_OTHER_INT_CMD) {
1647 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
1648 if (en)
1649 desc[0].data[0] =
1650 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2);
1651
1652 desc[0].data[2] =
1653 cpu_to_le32(HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK);
1654 } else if (cmd == HCLGE_PPU_PF_OTHER_INT_CMD) {
1655 hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
1656 if (en)
1657 desc[0].data[0] =
1658 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN);
1659
1660 desc[0].data[2] =
1661 cpu_to_le32(HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK);
1662 } else {
1663 dev_err(dev, "Invalid cmd to configure PPU error interrupts\n");
1664 return -EINVAL;
1665 }
1666
1667 ret = hclge_cmd_send(&hdev->hw, &desc[0], desc_num);
1668
1669 return ret;
1670 }
1671
hclge_config_ppu_hw_err_int(struct hclge_dev * hdev,bool en)1672 static int hclge_config_ppu_hw_err_int(struct hclge_dev *hdev, bool en)
1673 {
1674 struct device *dev = &hdev->pdev->dev;
1675 int ret;
1676
1677 ret = hclge_config_ppu_error_interrupts(hdev, HCLGE_PPU_MPF_ECC_INT_CMD,
1678 en);
1679 if (ret) {
1680 dev_err(dev, "fail(%d) to configure PPU MPF ECC error intr\n",
1681 ret);
1682 return ret;
1683 }
1684
1685 ret = hclge_config_ppu_error_interrupts(hdev,
1686 HCLGE_PPU_MPF_OTHER_INT_CMD,
1687 en);
1688 if (ret) {
1689 dev_err(dev, "fail(%d) to configure PPU MPF other intr\n", ret);
1690 return ret;
1691 }
1692
1693 ret = hclge_config_ppu_error_interrupts(hdev,
1694 HCLGE_PPU_PF_OTHER_INT_CMD, en);
1695 if (ret)
1696 dev_err(dev, "fail(%d) to configure PPU PF error interrupts\n",
1697 ret);
1698 return ret;
1699 }
1700
hclge_config_ssu_hw_err_int(struct hclge_dev * hdev,bool en)1701 static int hclge_config_ssu_hw_err_int(struct hclge_dev *hdev, bool en)
1702 {
1703 struct device *dev = &hdev->pdev->dev;
1704 struct hclge_desc desc[2];
1705 int ret;
1706
1707 /* configure SSU ecc error interrupts */
1708 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_ECC_INT_CMD, false);
1709 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1710 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_ECC_INT_CMD, false);
1711 if (en) {
1712 desc[0].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN);
1713 desc[0].data[1] =
1714 cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN);
1715 desc[0].data[4] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN);
1716 }
1717
1718 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK);
1719 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK);
1720 desc[1].data[2] = cpu_to_le32(HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK);
1721
1722 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1723 if (ret) {
1724 dev_err(dev,
1725 "fail(%d) to configure SSU ECC error interrupt\n", ret);
1726 return ret;
1727 }
1728
1729 /* configure SSU common error interrupts */
1730 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_SSU_COMMON_INT_CMD, false);
1731 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1732 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_SSU_COMMON_INT_CMD, false);
1733
1734 if (en) {
1735 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2)
1736 desc[0].data[0] =
1737 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN);
1738 else
1739 desc[0].data[0] =
1740 cpu_to_le32(HCLGE_SSU_COMMON_INT_EN & ~BIT(5));
1741 desc[0].data[1] = cpu_to_le32(HCLGE_SSU_PORT_BASED_ERR_INT_EN);
1742 desc[0].data[2] =
1743 cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN);
1744 }
1745
1746 desc[1].data[0] = cpu_to_le32(HCLGE_SSU_COMMON_INT_EN_MASK |
1747 HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK);
1748 desc[1].data[1] = cpu_to_le32(HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK);
1749
1750 ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
1751 if (ret)
1752 dev_err(dev,
1753 "fail(%d) to configure SSU COMMON error intr\n", ret);
1754
1755 return ret;
1756 }
1757
1758 /* hclge_query_bd_num: query number of buffer descriptors
1759 * @hdev: pointer to struct hclge_dev
1760 * @is_ras: true for ras, false for msix
1761 * @mpf_bd_num: number of main PF interrupt buffer descriptors
1762 * @pf_bd_num: number of not main PF interrupt buffer descriptors
1763 *
1764 * This function querys number of mpf and pf buffer descriptors.
1765 */
hclge_query_bd_num(struct hclge_dev * hdev,bool is_ras,u32 * mpf_bd_num,u32 * pf_bd_num)1766 static int hclge_query_bd_num(struct hclge_dev *hdev, bool is_ras,
1767 u32 *mpf_bd_num, u32 *pf_bd_num)
1768 {
1769 struct device *dev = &hdev->pdev->dev;
1770 u32 mpf_min_bd_num, pf_min_bd_num;
1771 enum hclge_opcode_type opcode;
1772 struct hclge_desc desc_bd;
1773 int ret;
1774
1775 if (is_ras) {
1776 opcode = HCLGE_QUERY_RAS_INT_STS_BD_NUM;
1777 mpf_min_bd_num = HCLGE_MPF_RAS_INT_MIN_BD_NUM;
1778 pf_min_bd_num = HCLGE_PF_RAS_INT_MIN_BD_NUM;
1779 } else {
1780 opcode = HCLGE_QUERY_MSIX_INT_STS_BD_NUM;
1781 mpf_min_bd_num = HCLGE_MPF_MSIX_INT_MIN_BD_NUM;
1782 pf_min_bd_num = HCLGE_PF_MSIX_INT_MIN_BD_NUM;
1783 }
1784
1785 hclge_cmd_setup_basic_desc(&desc_bd, opcode, true);
1786 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1);
1787 if (ret) {
1788 dev_err(dev, "fail(%d) to query msix int status bd num\n",
1789 ret);
1790 return ret;
1791 }
1792
1793 *mpf_bd_num = le32_to_cpu(desc_bd.data[0]);
1794 *pf_bd_num = le32_to_cpu(desc_bd.data[1]);
1795 if (*mpf_bd_num < mpf_min_bd_num || *pf_bd_num < pf_min_bd_num) {
1796 dev_err(dev, "Invalid bd num: mpf(%u), pf(%u)\n",
1797 *mpf_bd_num, *pf_bd_num);
1798 return -EINVAL;
1799 }
1800
1801 return 0;
1802 }
1803
1804 /* hclge_handle_mpf_ras_error: handle all main PF RAS errors
1805 * @hdev: pointer to struct hclge_dev
1806 * @desc: descriptor for describing the command
1807 * @num: number of extended command structures
1808 *
1809 * This function handles all the main PF RAS errors in the
1810 * hw register/s using command.
1811 */
hclge_handle_mpf_ras_error(struct hclge_dev * hdev,struct hclge_desc * desc,int num)1812 static int hclge_handle_mpf_ras_error(struct hclge_dev *hdev,
1813 struct hclge_desc *desc,
1814 int num)
1815 {
1816 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1817 struct device *dev = &hdev->pdev->dev;
1818 __le32 *desc_data;
1819 u32 status;
1820 int ret;
1821
1822 /* query all main PF RAS errors */
1823 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_MPF_RAS_INT,
1824 true);
1825 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
1826 if (ret) {
1827 dev_err(dev, "query all mpf ras int cmd failed (%d)\n", ret);
1828 return ret;
1829 }
1830
1831 /* log HNS common errors */
1832 status = le32_to_cpu(desc[0].data[0]);
1833 if (status)
1834 hclge_log_error(dev, "IMP_TCM_ECC_INT_STS",
1835 &hclge_imp_tcm_ecc_int[0], status,
1836 &ae_dev->hw_err_reset_req);
1837
1838 status = le32_to_cpu(desc[0].data[1]);
1839 if (status)
1840 hclge_log_error(dev, "CMDQ_MEM_ECC_INT_STS",
1841 &hclge_cmdq_nic_mem_ecc_int[0], status,
1842 &ae_dev->hw_err_reset_req);
1843
1844 if ((le32_to_cpu(desc[0].data[2])) & BIT(0))
1845 dev_warn(dev, "imp_rd_data_poison_err found\n");
1846
1847 status = le32_to_cpu(desc[0].data[3]);
1848 if (status)
1849 hclge_log_error(dev, "TQP_INT_ECC_INT_STS",
1850 &hclge_tqp_int_ecc_int[0], status,
1851 &ae_dev->hw_err_reset_req);
1852
1853 status = le32_to_cpu(desc[0].data[4]);
1854 if (status)
1855 hclge_log_error(dev, "MSIX_ECC_INT_STS",
1856 &hclge_msix_sram_ecc_int[0], status,
1857 &ae_dev->hw_err_reset_req);
1858
1859 /* log SSU(Storage Switch Unit) errors */
1860 desc_data = (__le32 *)&desc[2];
1861 status = le32_to_cpu(*(desc_data + 2));
1862 if (status)
1863 hclge_log_error(dev, "SSU_ECC_MULTI_BIT_INT_0",
1864 &hclge_ssu_mem_ecc_err_int[0], status,
1865 &ae_dev->hw_err_reset_req);
1866
1867 status = le32_to_cpu(*(desc_data + 3)) & BIT(0);
1868 if (status) {
1869 dev_err(dev, "SSU_ECC_MULTI_BIT_INT_1 ssu_mem32_ecc_mbit_err found [error status=0x%x]\n",
1870 status);
1871 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
1872 }
1873
1874 status = le32_to_cpu(*(desc_data + 4)) & HCLGE_SSU_COMMON_ERR_INT_MASK;
1875 if (status)
1876 hclge_log_error(dev, "SSU_COMMON_ERR_INT",
1877 &hclge_ssu_com_err_int[0], status,
1878 &ae_dev->hw_err_reset_req);
1879
1880 /* log IGU(Ingress Unit) errors */
1881 desc_data = (__le32 *)&desc[3];
1882 status = le32_to_cpu(*desc_data) & HCLGE_IGU_INT_MASK;
1883 if (status)
1884 hclge_log_error(dev, "IGU_INT_STS",
1885 &hclge_igu_int[0], status,
1886 &ae_dev->hw_err_reset_req);
1887
1888 /* log PPP(Programmable Packet Process) errors */
1889 desc_data = (__le32 *)&desc[4];
1890 status = le32_to_cpu(*(desc_data + 1));
1891 if (status)
1892 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST1",
1893 &hclge_ppp_mpf_abnormal_int_st1[0], status,
1894 &ae_dev->hw_err_reset_req);
1895
1896 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPP_MPF_INT_ST3_MASK;
1897 if (status)
1898 hclge_log_error(dev, "PPP_MPF_ABNORMAL_INT_ST3",
1899 &hclge_ppp_mpf_abnormal_int_st3[0], status,
1900 &ae_dev->hw_err_reset_req);
1901
1902 /* log PPU(RCB) errors */
1903 desc_data = (__le32 *)&desc[5];
1904 status = le32_to_cpu(*(desc_data + 1));
1905 if (status) {
1906 dev_err(dev,
1907 "PPU_MPF_ABNORMAL_INT_ST1 rpu_rx_pkt_ecc_mbit_err found\n");
1908 set_bit(HNAE3_GLOBAL_RESET, &ae_dev->hw_err_reset_req);
1909 }
1910
1911 status = le32_to_cpu(*(desc_data + 2));
1912 if (status)
1913 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST2",
1914 &hclge_ppu_mpf_abnormal_int_st2[0], status,
1915 &ae_dev->hw_err_reset_req);
1916
1917 status = le32_to_cpu(*(desc_data + 3)) & HCLGE_PPU_MPF_INT_ST3_MASK;
1918 if (status)
1919 hclge_log_error(dev, "PPU_MPF_ABNORMAL_INT_ST3",
1920 &hclge_ppu_mpf_abnormal_int_st3[0], status,
1921 &ae_dev->hw_err_reset_req);
1922
1923 /* log TM(Traffic Manager) errors */
1924 desc_data = (__le32 *)&desc[6];
1925 status = le32_to_cpu(*desc_data);
1926 if (status)
1927 hclge_log_error(dev, "TM_SCH_RINT",
1928 &hclge_tm_sch_rint[0], status,
1929 &ae_dev->hw_err_reset_req);
1930
1931 /* log QCN(Quantized Congestion Control) errors */
1932 desc_data = (__le32 *)&desc[7];
1933 status = le32_to_cpu(*desc_data) & HCLGE_QCN_FIFO_INT_MASK;
1934 if (status)
1935 hclge_log_error(dev, "QCN_FIFO_RINT",
1936 &hclge_qcn_fifo_rint[0], status,
1937 &ae_dev->hw_err_reset_req);
1938
1939 status = le32_to_cpu(*(desc_data + 1)) & HCLGE_QCN_ECC_INT_MASK;
1940 if (status)
1941 hclge_log_error(dev, "QCN_ECC_RINT",
1942 &hclge_qcn_ecc_rint[0], status,
1943 &ae_dev->hw_err_reset_req);
1944
1945 /* log NCSI errors */
1946 desc_data = (__le32 *)&desc[9];
1947 status = le32_to_cpu(*desc_data) & HCLGE_NCSI_ECC_INT_MASK;
1948 if (status)
1949 hclge_log_error(dev, "NCSI_ECC_INT_RPT",
1950 &hclge_ncsi_err_int[0], status,
1951 &ae_dev->hw_err_reset_req);
1952
1953 /* clear all main PF RAS errors */
1954 hclge_cmd_reuse_desc(&desc[0], false);
1955 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
1956 if (ret)
1957 dev_err(dev, "clear all mpf ras int cmd failed (%d)\n", ret);
1958
1959 return ret;
1960 }
1961
1962 /* hclge_handle_pf_ras_error: handle all PF RAS errors
1963 * @hdev: pointer to struct hclge_dev
1964 * @desc: descriptor for describing the command
1965 * @num: number of extended command structures
1966 *
1967 * This function handles all the PF RAS errors in the
1968 * hw register/s using command.
1969 */
hclge_handle_pf_ras_error(struct hclge_dev * hdev,struct hclge_desc * desc,int num)1970 static int hclge_handle_pf_ras_error(struct hclge_dev *hdev,
1971 struct hclge_desc *desc,
1972 int num)
1973 {
1974 struct hnae3_ae_dev *ae_dev = hdev->ae_dev;
1975 struct device *dev = &hdev->pdev->dev;
1976 __le32 *desc_data;
1977 u32 status;
1978 int ret;
1979
1980 /* query all PF RAS errors */
1981 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_PF_RAS_INT,
1982 true);
1983 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
1984 if (ret) {
1985 dev_err(dev, "query all pf ras int cmd failed (%d)\n", ret);
1986 return ret;
1987 }
1988
1989 /* log SSU(Storage Switch Unit) errors */
1990 status = le32_to_cpu(desc[0].data[0]);
1991 if (status)
1992 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
1993 &hclge_ssu_port_based_err_int[0], status,
1994 &ae_dev->hw_err_reset_req);
1995
1996 status = le32_to_cpu(desc[0].data[1]);
1997 if (status)
1998 hclge_log_error(dev, "SSU_FIFO_OVERFLOW_INT",
1999 &hclge_ssu_fifo_overflow_int[0], status,
2000 &ae_dev->hw_err_reset_req);
2001
2002 status = le32_to_cpu(desc[0].data[2]);
2003 if (status)
2004 hclge_log_error(dev, "SSU_ETS_TCG_INT",
2005 &hclge_ssu_ets_tcg_int[0], status,
2006 &ae_dev->hw_err_reset_req);
2007
2008 /* log IGU(Ingress Unit) EGU(Egress Unit) TNL errors */
2009 desc_data = (__le32 *)&desc[1];
2010 status = le32_to_cpu(*desc_data) & HCLGE_IGU_EGU_TNL_INT_MASK;
2011 if (status)
2012 hclge_log_error(dev, "IGU_EGU_TNL_INT_STS",
2013 &hclge_igu_egu_tnl_int[0], status,
2014 &ae_dev->hw_err_reset_req);
2015
2016 /* log PPU(RCB) errors */
2017 desc_data = (__le32 *)&desc[3];
2018 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_RAS_MASK;
2019 if (status) {
2020 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST0",
2021 &hclge_ppu_pf_abnormal_int[0], status,
2022 &ae_dev->hw_err_reset_req);
2023 hclge_report_hw_error(hdev, HNAE3_PPU_POISON_ERROR);
2024 }
2025
2026 /* clear all PF RAS errors */
2027 hclge_cmd_reuse_desc(&desc[0], false);
2028 ret = hclge_cmd_send(&hdev->hw, &desc[0], num);
2029 if (ret)
2030 dev_err(dev, "clear all pf ras int cmd failed (%d)\n", ret);
2031
2032 return ret;
2033 }
2034
hclge_handle_all_ras_errors(struct hclge_dev * hdev)2035 static int hclge_handle_all_ras_errors(struct hclge_dev *hdev)
2036 {
2037 u32 mpf_bd_num, pf_bd_num, bd_num;
2038 struct hclge_desc *desc;
2039 int ret;
2040
2041 /* query the number of registers in the RAS int status */
2042 ret = hclge_query_bd_num(hdev, true, &mpf_bd_num, &pf_bd_num);
2043 if (ret)
2044 return ret;
2045
2046 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
2047 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
2048 if (!desc)
2049 return -ENOMEM;
2050
2051 /* handle all main PF RAS errors */
2052 ret = hclge_handle_mpf_ras_error(hdev, desc, mpf_bd_num);
2053 if (ret) {
2054 kfree(desc);
2055 return ret;
2056 }
2057 memset(desc, 0, bd_num * sizeof(struct hclge_desc));
2058
2059 /* handle all PF RAS errors */
2060 ret = hclge_handle_pf_ras_error(hdev, desc, pf_bd_num);
2061 kfree(desc);
2062
2063 return ret;
2064 }
2065
hclge_log_rocee_axi_error(struct hclge_dev * hdev)2066 static int hclge_log_rocee_axi_error(struct hclge_dev *hdev)
2067 {
2068 struct device *dev = &hdev->pdev->dev;
2069 struct hclge_desc desc[3];
2070 int ret;
2071
2072 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2073 true);
2074 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2075 true);
2076 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD,
2077 true);
2078 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
2079 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
2080
2081 ret = hclge_cmd_send(&hdev->hw, &desc[0], 3);
2082 if (ret) {
2083 dev_err(dev, "failed(%d) to query ROCEE AXI error sts\n", ret);
2084 return ret;
2085 }
2086
2087 dev_err(dev, "AXI1: %08X %08X %08X %08X %08X %08X\n",
2088 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
2089 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
2090 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
2091 dev_err(dev, "AXI2: %08X %08X %08X %08X %08X %08X\n",
2092 le32_to_cpu(desc[1].data[0]), le32_to_cpu(desc[1].data[1]),
2093 le32_to_cpu(desc[1].data[2]), le32_to_cpu(desc[1].data[3]),
2094 le32_to_cpu(desc[1].data[4]), le32_to_cpu(desc[1].data[5]));
2095 dev_err(dev, "AXI3: %08X %08X %08X %08X\n",
2096 le32_to_cpu(desc[2].data[0]), le32_to_cpu(desc[2].data[1]),
2097 le32_to_cpu(desc[2].data[2]), le32_to_cpu(desc[2].data[3]));
2098
2099 return 0;
2100 }
2101
hclge_log_rocee_ecc_error(struct hclge_dev * hdev)2102 static int hclge_log_rocee_ecc_error(struct hclge_dev *hdev)
2103 {
2104 struct device *dev = &hdev->pdev->dev;
2105 struct hclge_desc desc[2];
2106 int ret;
2107
2108 ret = hclge_cmd_query_error(hdev, &desc[0],
2109 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD,
2110 HCLGE_CMD_FLAG_NEXT);
2111 if (ret) {
2112 dev_err(dev, "failed(%d) to query ROCEE ECC error sts\n", ret);
2113 return ret;
2114 }
2115
2116 dev_err(dev, "ECC1: %08X %08X %08X %08X %08X %08X\n",
2117 le32_to_cpu(desc[0].data[0]), le32_to_cpu(desc[0].data[1]),
2118 le32_to_cpu(desc[0].data[2]), le32_to_cpu(desc[0].data[3]),
2119 le32_to_cpu(desc[0].data[4]), le32_to_cpu(desc[0].data[5]));
2120 dev_err(dev, "ECC2: %08X %08X %08X\n", le32_to_cpu(desc[1].data[0]),
2121 le32_to_cpu(desc[1].data[1]), le32_to_cpu(desc[1].data[2]));
2122
2123 return 0;
2124 }
2125
hclge_log_rocee_ovf_error(struct hclge_dev * hdev)2126 static int hclge_log_rocee_ovf_error(struct hclge_dev *hdev)
2127 {
2128 struct device *dev = &hdev->pdev->dev;
2129 struct hclge_desc desc[2];
2130 int ret;
2131
2132 /* read overflow error status */
2133 ret = hclge_cmd_query_error(hdev, &desc[0], HCLGE_ROCEE_PF_RAS_INT_CMD,
2134 0);
2135 if (ret) {
2136 dev_err(dev, "failed(%d) to query ROCEE OVF error sts\n", ret);
2137 return ret;
2138 }
2139
2140 /* log overflow error */
2141 if (le32_to_cpu(desc[0].data[0]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2142 const struct hclge_hw_error *err;
2143 u32 err_sts;
2144
2145 err = &hclge_rocee_qmm_ovf_err_int[0];
2146 err_sts = HCLGE_ROCEE_OVF_ERR_TYPE_MASK &
2147 le32_to_cpu(desc[0].data[0]);
2148 while (err->msg) {
2149 if (err->int_msk == err_sts) {
2150 dev_err(dev, "%s [error status=0x%x] found\n",
2151 err->msg,
2152 le32_to_cpu(desc[0].data[0]));
2153 break;
2154 }
2155 err++;
2156 }
2157 }
2158
2159 if (le32_to_cpu(desc[0].data[1]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2160 dev_err(dev, "ROCEE TSP OVF [error status=0x%x] found\n",
2161 le32_to_cpu(desc[0].data[1]));
2162 }
2163
2164 if (le32_to_cpu(desc[0].data[2]) & HCLGE_ROCEE_OVF_ERR_INT_MASK) {
2165 dev_err(dev, "ROCEE SCC OVF [error status=0x%x] found\n",
2166 le32_to_cpu(desc[0].data[2]));
2167 }
2168
2169 return 0;
2170 }
2171
2172 static enum hnae3_reset_type
hclge_log_and_clear_rocee_ras_error(struct hclge_dev * hdev)2173 hclge_log_and_clear_rocee_ras_error(struct hclge_dev *hdev)
2174 {
2175 enum hnae3_reset_type reset_type = HNAE3_NONE_RESET;
2176 struct device *dev = &hdev->pdev->dev;
2177 struct hclge_desc desc[2];
2178 unsigned int status;
2179 int ret;
2180
2181 /* read RAS error interrupt status */
2182 ret = hclge_cmd_query_error(hdev, &desc[0],
2183 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT, 0);
2184 if (ret) {
2185 dev_err(dev, "failed(%d) to query ROCEE RAS INT SRC\n", ret);
2186 /* reset everything for now */
2187 return HNAE3_GLOBAL_RESET;
2188 }
2189
2190 status = le32_to_cpu(desc[0].data[0]);
2191 if (status & HCLGE_ROCEE_AXI_ERR_INT_MASK) {
2192 if (status & HCLGE_ROCEE_RERR_INT_MASK)
2193 dev_err(dev, "ROCEE RAS AXI rresp error\n");
2194
2195 if (status & HCLGE_ROCEE_BERR_INT_MASK)
2196 dev_err(dev, "ROCEE RAS AXI bresp error\n");
2197
2198 reset_type = HNAE3_FUNC_RESET;
2199
2200 hclge_report_hw_error(hdev, HNAE3_ROCEE_AXI_RESP_ERROR);
2201
2202 ret = hclge_log_rocee_axi_error(hdev);
2203 if (ret)
2204 return HNAE3_GLOBAL_RESET;
2205 }
2206
2207 if (status & HCLGE_ROCEE_ECC_INT_MASK) {
2208 dev_err(dev, "ROCEE RAS 2bit ECC error\n");
2209 reset_type = HNAE3_GLOBAL_RESET;
2210
2211 ret = hclge_log_rocee_ecc_error(hdev);
2212 if (ret)
2213 return HNAE3_GLOBAL_RESET;
2214 }
2215
2216 if (status & HCLGE_ROCEE_OVF_INT_MASK) {
2217 ret = hclge_log_rocee_ovf_error(hdev);
2218 if (ret) {
2219 dev_err(dev, "failed(%d) to process ovf error\n", ret);
2220 /* reset everything for now */
2221 return HNAE3_GLOBAL_RESET;
2222 }
2223 }
2224
2225 /* clear error status */
2226 hclge_cmd_reuse_desc(&desc[0], false);
2227 ret = hclge_cmd_send(&hdev->hw, &desc[0], 1);
2228 if (ret) {
2229 dev_err(dev, "failed(%d) to clear ROCEE RAS error\n", ret);
2230 /* reset everything for now */
2231 return HNAE3_GLOBAL_RESET;
2232 }
2233
2234 return reset_type;
2235 }
2236
hclge_config_rocee_ras_interrupt(struct hclge_dev * hdev,bool en)2237 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en)
2238 {
2239 struct device *dev = &hdev->pdev->dev;
2240 struct hclge_desc desc;
2241 int ret;
2242
2243 if (hdev->ae_dev->dev_version < HNAE3_DEVICE_VERSION_V2 ||
2244 !hnae3_dev_roce_supported(hdev))
2245 return 0;
2246
2247 hclge_cmd_setup_basic_desc(&desc, HCLGE_CONFIG_ROCEE_RAS_INT_EN, false);
2248 if (en) {
2249 /* enable ROCEE hw error interrupts */
2250 desc.data[0] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN);
2251 desc.data[1] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN);
2252
2253 hclge_log_and_clear_rocee_ras_error(hdev);
2254 }
2255 desc.data[2] = cpu_to_le32(HCLGE_ROCEE_RAS_NFE_INT_EN_MASK);
2256 desc.data[3] = cpu_to_le32(HCLGE_ROCEE_RAS_CE_INT_EN_MASK);
2257
2258 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2259 if (ret)
2260 dev_err(dev, "failed(%d) to config ROCEE RAS interrupt\n", ret);
2261
2262 return ret;
2263 }
2264
hclge_handle_rocee_ras_error(struct hnae3_ae_dev * ae_dev)2265 static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
2266 {
2267 struct hclge_dev *hdev = ae_dev->priv;
2268 enum hnae3_reset_type reset_type;
2269
2270 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2271 return;
2272
2273 reset_type = hclge_log_and_clear_rocee_ras_error(hdev);
2274 if (reset_type != HNAE3_NONE_RESET)
2275 set_bit(reset_type, &ae_dev->hw_err_reset_req);
2276 }
2277
2278 static const struct hclge_hw_blk hw_blk[] = {
2279 {
2280 .msk = BIT(0),
2281 .name = "IGU_EGU",
2282 .config_err_int = hclge_config_igu_egu_hw_err_int,
2283 }, {
2284 .msk = BIT(1),
2285 .name = "PPP",
2286 .config_err_int = hclge_config_ppp_hw_err_int,
2287 }, {
2288 .msk = BIT(2),
2289 .name = "SSU",
2290 .config_err_int = hclge_config_ssu_hw_err_int,
2291 }, {
2292 .msk = BIT(3),
2293 .name = "PPU",
2294 .config_err_int = hclge_config_ppu_hw_err_int,
2295 }, {
2296 .msk = BIT(4),
2297 .name = "TM",
2298 .config_err_int = hclge_config_tm_hw_err_int,
2299 }, {
2300 .msk = BIT(5),
2301 .name = "COMMON",
2302 .config_err_int = hclge_config_common_hw_err_int,
2303 }, {
2304 .msk = BIT(8),
2305 .name = "MAC",
2306 .config_err_int = hclge_config_mac_err_int,
2307 }, {
2308 /* sentinel */
2309 }
2310 };
2311
hclge_config_all_msix_error(struct hclge_dev * hdev,bool enable)2312 static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
2313 {
2314 u32 reg_val;
2315
2316 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2317
2318 if (enable)
2319 reg_val |= BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
2320 else
2321 reg_val &= ~BIT(HCLGE_VECTOR0_ALL_MSIX_ERR_B);
2322
2323 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG, reg_val);
2324 }
2325
hclge_config_nic_hw_error(struct hclge_dev * hdev,bool state)2326 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state)
2327 {
2328 const struct hclge_hw_blk *module = hw_blk;
2329 int ret = 0;
2330
2331 hclge_config_all_msix_error(hdev, state);
2332
2333 while (module->name) {
2334 if (module->config_err_int) {
2335 ret = module->config_err_int(hdev, state);
2336 if (ret)
2337 return ret;
2338 }
2339 module++;
2340 }
2341
2342 return ret;
2343 }
2344
hclge_handle_hw_ras_error(struct hnae3_ae_dev * ae_dev)2345 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev)
2346 {
2347 struct hclge_dev *hdev = ae_dev->priv;
2348 struct device *dev = &hdev->pdev->dev;
2349 u32 status;
2350
2351 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) {
2352 dev_err(dev,
2353 "Can't recover - RAS error reported during dev init\n");
2354 return PCI_ERS_RESULT_NONE;
2355 }
2356
2357 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
2358 if (status & HCLGE_RAS_REG_NFE_MASK ||
2359 status & HCLGE_RAS_REG_ROCEE_ERR_MASK)
2360 ae_dev->hw_err_reset_req = 0;
2361 else
2362 goto out;
2363
2364 /* Handling Non-fatal HNS RAS errors */
2365 if (status & HCLGE_RAS_REG_NFE_MASK) {
2366 dev_err(dev,
2367 "HNS Non-Fatal RAS error(status=0x%x) identified\n",
2368 status);
2369 hclge_handle_all_ras_errors(hdev);
2370 }
2371
2372 /* Handling Non-fatal Rocee RAS errors */
2373 if (hdev->ae_dev->dev_version >= HNAE3_DEVICE_VERSION_V2 &&
2374 status & HCLGE_RAS_REG_ROCEE_ERR_MASK) {
2375 dev_err(dev, "ROCEE Non-Fatal RAS error identified\n");
2376 hclge_handle_rocee_ras_error(ae_dev);
2377 }
2378
2379 if (ae_dev->hw_err_reset_req)
2380 return PCI_ERS_RESULT_NEED_RESET;
2381
2382 out:
2383 return PCI_ERS_RESULT_RECOVERED;
2384 }
2385
hclge_clear_hw_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,bool is_mpf,u32 bd_num)2386 static int hclge_clear_hw_msix_error(struct hclge_dev *hdev,
2387 struct hclge_desc *desc, bool is_mpf,
2388 u32 bd_num)
2389 {
2390 if (is_mpf)
2391 desc[0].opcode =
2392 cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT);
2393 else
2394 desc[0].opcode = cpu_to_le16(HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT);
2395
2396 desc[0].flag = cpu_to_le16(HCLGE_CMD_FLAG_NO_INTR | HCLGE_CMD_FLAG_IN);
2397
2398 return hclge_cmd_send(&hdev->hw, &desc[0], bd_num);
2399 }
2400
2401 /* hclge_query_8bd_info: query information about over_8bd_nfe_err
2402 * @hdev: pointer to struct hclge_dev
2403 * @vf_id: Index of the virtual function with error
2404 * @q_id: Physical index of the queue with error
2405 *
2406 * This function get specific index of queue and function which causes
2407 * over_8bd_nfe_err by using command. If vf_id is 0, it means error is
2408 * caused by PF instead of VF.
2409 */
hclge_query_over_8bd_err_info(struct hclge_dev * hdev,u16 * vf_id,u16 * q_id)2410 static int hclge_query_over_8bd_err_info(struct hclge_dev *hdev, u16 *vf_id,
2411 u16 *q_id)
2412 {
2413 struct hclge_query_ppu_pf_other_int_dfx_cmd *req;
2414 struct hclge_desc desc;
2415 int ret;
2416
2417 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PPU_PF_OTHER_INT_DFX, true);
2418 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2419 if (ret)
2420 return ret;
2421
2422 req = (struct hclge_query_ppu_pf_other_int_dfx_cmd *)desc.data;
2423 *vf_id = le16_to_cpu(req->over_8bd_no_fe_vf_id);
2424 *q_id = le16_to_cpu(req->over_8bd_no_fe_qid);
2425
2426 return 0;
2427 }
2428
2429 /* hclge_handle_over_8bd_err: handle MSI-X error named over_8bd_nfe_err
2430 * @hdev: pointer to struct hclge_dev
2431 * @reset_requests: reset level that we need to trigger later
2432 *
2433 * over_8bd_nfe_err is a special MSI-X because it may caused by a VF, in
2434 * that case, we need to trigger VF reset. Otherwise, a PF reset is needed.
2435 */
hclge_handle_over_8bd_err(struct hclge_dev * hdev,unsigned long * reset_requests)2436 static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
2437 unsigned long *reset_requests)
2438 {
2439 struct device *dev = &hdev->pdev->dev;
2440 u16 vf_id;
2441 u16 q_id;
2442 int ret;
2443
2444 ret = hclge_query_over_8bd_err_info(hdev, &vf_id, &q_id);
2445 if (ret) {
2446 dev_err(dev, "fail(%d) to query over_8bd_no_fe info\n",
2447 ret);
2448 return;
2449 }
2450
2451 dev_err(dev, "PPU_PF_ABNORMAL_INT_ST over_8bd_no_fe found, vport(%u), queue_id(%u)\n",
2452 vf_id, q_id);
2453
2454 if (vf_id) {
2455 if (vf_id >= hdev->num_alloc_vport) {
2456 dev_err(dev, "invalid vport(%u)\n", vf_id);
2457 return;
2458 }
2459
2460 /* If we need to trigger other reset whose level is higher
2461 * than HNAE3_VF_FUNC_RESET, no need to trigger a VF reset
2462 * here.
2463 */
2464 if (*reset_requests != 0)
2465 return;
2466
2467 ret = hclge_inform_reset_assert_to_vf(&hdev->vport[vf_id]);
2468 if (ret)
2469 dev_err(dev, "inform reset to vport(%u) failed %d!\n",
2470 vf_id, ret);
2471 } else {
2472 set_bit(HNAE3_FUNC_RESET, reset_requests);
2473 }
2474 }
2475
2476 /* hclge_handle_mpf_msix_error: handle all main PF MSI-X errors
2477 * @hdev: pointer to struct hclge_dev
2478 * @desc: descriptor for describing the command
2479 * @mpf_bd_num: number of extended command structures
2480 * @reset_requests: record of the reset level that we need
2481 *
2482 * This function handles all the main PF MSI-X errors in the hw register/s
2483 * using command.
2484 */
hclge_handle_mpf_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,int mpf_bd_num,unsigned long * reset_requests)2485 static int hclge_handle_mpf_msix_error(struct hclge_dev *hdev,
2486 struct hclge_desc *desc,
2487 int mpf_bd_num,
2488 unsigned long *reset_requests)
2489 {
2490 struct device *dev = &hdev->pdev->dev;
2491 __le32 *desc_data;
2492 u32 status;
2493 int ret;
2494 /* query all main PF MSIx errors */
2495 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
2496 true);
2497 ret = hclge_cmd_send(&hdev->hw, &desc[0], mpf_bd_num);
2498 if (ret) {
2499 dev_err(dev, "query all mpf msix int cmd failed (%d)\n", ret);
2500 return ret;
2501 }
2502
2503 /* log MAC errors */
2504 desc_data = (__le32 *)&desc[1];
2505 status = le32_to_cpu(*desc_data);
2506 if (status)
2507 hclge_log_error(dev, "MAC_AFIFO_TNL_INT_R",
2508 &hclge_mac_afifo_tnl_int[0], status,
2509 reset_requests);
2510
2511 /* log PPU(RCB) MPF errors */
2512 desc_data = (__le32 *)&desc[5];
2513 status = le32_to_cpu(*(desc_data + 2)) &
2514 HCLGE_PPU_MPF_INT_ST2_MSIX_MASK;
2515 if (status)
2516 dev_err(dev, "PPU_MPF_ABNORMAL_INT_ST2 rx_q_search_miss found [dfx status=0x%x\n]",
2517 status);
2518
2519 /* clear all main PF MSIx errors */
2520 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);
2521 if (ret)
2522 dev_err(dev, "clear all mpf msix int cmd failed (%d)\n", ret);
2523
2524 return ret;
2525 }
2526
2527 /* hclge_handle_pf_msix_error: handle all PF MSI-X errors
2528 * @hdev: pointer to struct hclge_dev
2529 * @desc: descriptor for describing the command
2530 * @mpf_bd_num: number of extended command structures
2531 * @reset_requests: record of the reset level that we need
2532 *
2533 * This function handles all the PF MSI-X errors in the hw register/s using
2534 * command.
2535 */
hclge_handle_pf_msix_error(struct hclge_dev * hdev,struct hclge_desc * desc,int pf_bd_num,unsigned long * reset_requests)2536 static int hclge_handle_pf_msix_error(struct hclge_dev *hdev,
2537 struct hclge_desc *desc,
2538 int pf_bd_num,
2539 unsigned long *reset_requests)
2540 {
2541 struct device *dev = &hdev->pdev->dev;
2542 __le32 *desc_data;
2543 u32 status;
2544 int ret;
2545
2546 /* query all PF MSIx errors */
2547 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
2548 true);
2549 ret = hclge_cmd_send(&hdev->hw, &desc[0], pf_bd_num);
2550 if (ret) {
2551 dev_err(dev, "query all pf msix int cmd failed (%d)\n", ret);
2552 return ret;
2553 }
2554
2555 /* log SSU PF errors */
2556 status = le32_to_cpu(desc[0].data[0]) & HCLGE_SSU_PORT_INT_MSIX_MASK;
2557 if (status)
2558 hclge_log_error(dev, "SSU_PORT_BASED_ERR_INT",
2559 &hclge_ssu_port_based_pf_int[0],
2560 status, reset_requests);
2561
2562 /* read and log PPP PF errors */
2563 desc_data = (__le32 *)&desc[2];
2564 status = le32_to_cpu(*desc_data);
2565 if (status)
2566 hclge_log_error(dev, "PPP_PF_ABNORMAL_INT_ST0",
2567 &hclge_ppp_pf_abnormal_int[0],
2568 status, reset_requests);
2569
2570 /* log PPU(RCB) PF errors */
2571 desc_data = (__le32 *)&desc[3];
2572 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_INT_MSIX_MASK;
2573 if (status)
2574 hclge_log_error(dev, "PPU_PF_ABNORMAL_INT_ST",
2575 &hclge_ppu_pf_abnormal_int[0],
2576 status, reset_requests);
2577
2578 status = le32_to_cpu(*desc_data) & HCLGE_PPU_PF_OVER_8BD_ERR_MASK;
2579 if (status)
2580 hclge_handle_over_8bd_err(hdev, reset_requests);
2581
2582 /* clear all PF MSIx errors */
2583 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num);
2584 if (ret)
2585 dev_err(dev, "clear all pf msix int cmd failed (%d)\n", ret);
2586
2587 return ret;
2588 }
2589
hclge_handle_all_hw_msix_error(struct hclge_dev * hdev,unsigned long * reset_requests)2590 static int hclge_handle_all_hw_msix_error(struct hclge_dev *hdev,
2591 unsigned long *reset_requests)
2592 {
2593 u32 mpf_bd_num, pf_bd_num, bd_num;
2594 struct hclge_desc *desc;
2595 int ret;
2596
2597 /* query the number of bds for the MSIx int status */
2598 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num);
2599 if (ret)
2600 goto out;
2601
2602 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
2603 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
2604 if (!desc)
2605 return -ENOMEM;
2606
2607 ret = hclge_handle_mpf_msix_error(hdev, desc, mpf_bd_num,
2608 reset_requests);
2609 if (ret)
2610 goto msi_error;
2611
2612 memset(desc, 0, bd_num * sizeof(struct hclge_desc));
2613 ret = hclge_handle_pf_msix_error(hdev, desc, pf_bd_num, reset_requests);
2614 if (ret)
2615 goto msi_error;
2616
2617 ret = hclge_handle_mac_tnl(hdev);
2618
2619 msi_error:
2620 kfree(desc);
2621 out:
2622 return ret;
2623 }
2624
hclge_handle_hw_msix_error(struct hclge_dev * hdev,unsigned long * reset_requests)2625 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
2626 unsigned long *reset_requests)
2627 {
2628 struct device *dev = &hdev->pdev->dev;
2629
2630 if (!test_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state)) {
2631 dev_err(dev,
2632 "failed to handle msix error during dev init\n");
2633 return -EAGAIN;
2634 }
2635
2636 return hclge_handle_all_hw_msix_error(hdev, reset_requests);
2637 }
2638
hclge_handle_mac_tnl(struct hclge_dev * hdev)2639 int hclge_handle_mac_tnl(struct hclge_dev *hdev)
2640 {
2641 struct hclge_mac_tnl_stats mac_tnl_stats;
2642 struct device *dev = &hdev->pdev->dev;
2643 struct hclge_desc desc;
2644 u32 status;
2645 int ret;
2646
2647 /* query and clear mac tnl interruptions */
2648 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_MAC_TNL_INT, true);
2649 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2650 if (ret) {
2651 dev_err(dev, "failed to query mac tnl int, ret = %d.\n", ret);
2652 return ret;
2653 }
2654
2655 status = le32_to_cpu(desc.data[0]);
2656 if (status) {
2657 /* When mac tnl interrupt occurs, we record current time and
2658 * register status here in a fifo, then clear the status. So
2659 * that if link status changes suddenly at some time, we can
2660 * query them by debugfs.
2661 */
2662 mac_tnl_stats.time = local_clock();
2663 mac_tnl_stats.status = status;
2664 kfifo_put(&hdev->mac_tnl_log, mac_tnl_stats);
2665 ret = hclge_clear_mac_tnl_int(hdev);
2666 if (ret)
2667 dev_err(dev, "failed to clear mac tnl int, ret = %d.\n",
2668 ret);
2669 }
2670
2671 return ret;
2672 }
2673
hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev * ae_dev)2674 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev)
2675 {
2676 struct hclge_dev *hdev = ae_dev->priv;
2677 struct device *dev = &hdev->pdev->dev;
2678 u32 mpf_bd_num, pf_bd_num, bd_num;
2679 struct hclge_desc *desc;
2680 u32 status;
2681 int ret;
2682
2683 ae_dev->hw_err_reset_req = 0;
2684 status = hclge_read_dev(&hdev->hw, HCLGE_RAS_PF_OTHER_INT_STS_REG);
2685
2686 /* query the number of bds for the MSIx int status */
2687 ret = hclge_query_bd_num(hdev, false, &mpf_bd_num, &pf_bd_num);
2688 if (ret)
2689 return;
2690
2691 bd_num = max_t(u32, mpf_bd_num, pf_bd_num);
2692 desc = kcalloc(bd_num, sizeof(struct hclge_desc), GFP_KERNEL);
2693 if (!desc)
2694 return;
2695
2696 /* Clear HNS hw errors reported through msix */
2697 memset(&desc[0].data[0], 0xFF, mpf_bd_num * sizeof(struct hclge_desc) -
2698 HCLGE_DESC_NO_DATA_LEN);
2699 ret = hclge_clear_hw_msix_error(hdev, desc, true, mpf_bd_num);
2700 if (ret) {
2701 dev_err(dev, "fail(%d) to clear mpf msix int during init\n",
2702 ret);
2703 goto msi_error;
2704 }
2705
2706 memset(&desc[0].data[0], 0xFF, pf_bd_num * sizeof(struct hclge_desc) -
2707 HCLGE_DESC_NO_DATA_LEN);
2708 ret = hclge_clear_hw_msix_error(hdev, desc, false, pf_bd_num);
2709 if (ret) {
2710 dev_err(dev, "fail(%d) to clear pf msix int during init\n",
2711 ret);
2712 goto msi_error;
2713 }
2714
2715 /* Handle Non-fatal HNS RAS errors */
2716 if (status & HCLGE_RAS_REG_NFE_MASK) {
2717 dev_err(dev, "HNS hw error(RAS) identified during init\n");
2718 hclge_handle_all_ras_errors(hdev);
2719 }
2720
2721 msi_error:
2722 kfree(desc);
2723 }
2724
hclge_find_error_source(struct hclge_dev * hdev)2725 bool hclge_find_error_source(struct hclge_dev *hdev)
2726 {
2727 u32 msix_src_flag, hw_err_src_flag;
2728
2729 msix_src_flag = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
2730 HCLGE_VECTOR0_REG_MSIX_MASK;
2731
2732 hw_err_src_flag = hclge_read_dev(&hdev->hw,
2733 HCLGE_RAS_PF_OTHER_INT_STS_REG) &
2734 HCLGE_RAS_REG_ERR_MASK;
2735
2736 return msix_src_flag || hw_err_src_flag;
2737 }
2738
hclge_handle_occurred_error(struct hclge_dev * hdev)2739 void hclge_handle_occurred_error(struct hclge_dev *hdev)
2740 {
2741 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
2742
2743 if (hclge_find_error_source(hdev))
2744 hclge_handle_error_info_log(ae_dev);
2745 }
2746
2747 static void
hclge_handle_error_type_reg_log(struct device * dev,struct hclge_mod_err_info * mod_info,struct hclge_type_reg_err_info * type_reg_info)2748 hclge_handle_error_type_reg_log(struct device *dev,
2749 struct hclge_mod_err_info *mod_info,
2750 struct hclge_type_reg_err_info *type_reg_info)
2751 {
2752 #define HCLGE_ERR_TYPE_MASK 0x7F
2753 #define HCLGE_ERR_TYPE_IS_RAS_OFFSET 7
2754
2755 u8 mod_id, total_module, type_id, total_type, i, is_ras;
2756 u8 index_module = MODULE_NONE;
2757 u8 index_type = NONE_ERROR;
2758
2759 mod_id = mod_info->mod_id;
2760 type_id = type_reg_info->type_id & HCLGE_ERR_TYPE_MASK;
2761 is_ras = type_reg_info->type_id >> HCLGE_ERR_TYPE_IS_RAS_OFFSET;
2762
2763 total_module = ARRAY_SIZE(hclge_hw_module_id_st);
2764 total_type = ARRAY_SIZE(hclge_hw_type_id_st);
2765
2766 for (i = 0; i < total_module; i++) {
2767 if (mod_id == hclge_hw_module_id_st[i].module_id) {
2768 index_module = i;
2769 break;
2770 }
2771 }
2772
2773 for (i = 0; i < total_type; i++) {
2774 if (type_id == hclge_hw_type_id_st[i].type_id) {
2775 index_type = i;
2776 break;
2777 }
2778 }
2779
2780 if (index_module != MODULE_NONE && index_type != NONE_ERROR)
2781 dev_err(dev,
2782 "found %s %s, is %s error.\n",
2783 hclge_hw_module_id_st[index_module].msg,
2784 hclge_hw_type_id_st[index_type].msg,
2785 is_ras ? "ras" : "msix");
2786 else
2787 dev_err(dev,
2788 "unknown module[%u] or type[%u].\n", mod_id, type_id);
2789
2790 dev_err(dev, "reg_value:\n");
2791 for (i = 0; i < type_reg_info->reg_num; i++)
2792 dev_err(dev, "0x%08x\n", type_reg_info->hclge_reg[i]);
2793 }
2794
hclge_handle_error_module_log(struct hnae3_ae_dev * ae_dev,const u32 * buf,u32 buf_size)2795 static void hclge_handle_error_module_log(struct hnae3_ae_dev *ae_dev,
2796 const u32 *buf, u32 buf_size)
2797 {
2798 struct hclge_type_reg_err_info *type_reg_info;
2799 struct hclge_dev *hdev = ae_dev->priv;
2800 struct device *dev = &hdev->pdev->dev;
2801 struct hclge_mod_err_info *mod_info;
2802 struct hclge_sum_err_info *sum_info;
2803 u8 mod_num, err_num, i;
2804 u32 offset = 0;
2805
2806 sum_info = (struct hclge_sum_err_info *)&buf[offset++];
2807 if (sum_info->reset_type &&
2808 sum_info->reset_type != HNAE3_NONE_RESET)
2809 set_bit(sum_info->reset_type, &ae_dev->hw_err_reset_req);
2810 mod_num = sum_info->mod_num;
2811
2812 while (mod_num--) {
2813 if (offset >= buf_size) {
2814 dev_err(dev, "The offset(%u) exceeds buf's size(%u).\n",
2815 offset, buf_size);
2816 return;
2817 }
2818 mod_info = (struct hclge_mod_err_info *)&buf[offset++];
2819 err_num = mod_info->err_num;
2820
2821 for (i = 0; i < err_num; i++) {
2822 if (offset >= buf_size) {
2823 dev_err(dev,
2824 "The offset(%u) exceeds buf size(%u).\n",
2825 offset, buf_size);
2826 return;
2827 }
2828
2829 type_reg_info = (struct hclge_type_reg_err_info *)
2830 &buf[offset++];
2831 hclge_handle_error_type_reg_log(dev, mod_info,
2832 type_reg_info);
2833
2834 offset += type_reg_info->reg_num;
2835 }
2836 }
2837 }
2838
hclge_query_all_err_bd_num(struct hclge_dev * hdev,u32 * bd_num)2839 static int hclge_query_all_err_bd_num(struct hclge_dev *hdev, u32 *bd_num)
2840 {
2841 struct device *dev = &hdev->pdev->dev;
2842 struct hclge_desc desc_bd;
2843 int ret;
2844
2845 hclge_cmd_setup_basic_desc(&desc_bd, HCLGE_QUERY_ALL_ERR_BD_NUM, true);
2846 ret = hclge_cmd_send(&hdev->hw, &desc_bd, 1);
2847 if (ret) {
2848 dev_err(dev, "failed to query error bd_num, ret = %d.\n", ret);
2849 return ret;
2850 }
2851
2852 *bd_num = le32_to_cpu(desc_bd.data[0]);
2853 if (!(*bd_num)) {
2854 dev_err(dev, "The value of bd_num is 0!\n");
2855 return -EINVAL;
2856 }
2857
2858 return 0;
2859 }
2860
hclge_query_all_err_info(struct hclge_dev * hdev,struct hclge_desc * desc,u32 bd_num)2861 static int hclge_query_all_err_info(struct hclge_dev *hdev,
2862 struct hclge_desc *desc, u32 bd_num)
2863 {
2864 struct device *dev = &hdev->pdev->dev;
2865 int ret;
2866
2867 hclge_cmd_setup_basic_desc(desc, HCLGE_QUERY_ALL_ERR_INFO, true);
2868 ret = hclge_cmd_send(&hdev->hw, desc, bd_num);
2869 if (ret)
2870 dev_err(dev, "failed to query error info, ret = %d.\n", ret);
2871
2872 return ret;
2873 }
2874
hclge_handle_error_info_log(struct hnae3_ae_dev * ae_dev)2875 int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev)
2876 {
2877 u32 bd_num, desc_len, buf_len, buf_size, i;
2878 struct hclge_dev *hdev = ae_dev->priv;
2879 struct hclge_desc *desc;
2880 __le32 *desc_data;
2881 u32 *buf;
2882 int ret;
2883
2884 ret = hclge_query_all_err_bd_num(hdev, &bd_num);
2885 if (ret)
2886 goto out;
2887
2888 desc_len = bd_num * sizeof(struct hclge_desc);
2889 desc = kzalloc(desc_len, GFP_KERNEL);
2890 if (!desc) {
2891 ret = -ENOMEM;
2892 goto out;
2893 }
2894
2895 ret = hclge_query_all_err_info(hdev, desc, bd_num);
2896 if (ret)
2897 goto err_desc;
2898
2899 buf_len = bd_num * sizeof(struct hclge_desc) - HCLGE_DESC_NO_DATA_LEN;
2900 buf_size = buf_len / sizeof(u32);
2901
2902 desc_data = kzalloc(buf_len, GFP_KERNEL);
2903 if (!desc_data) {
2904 ret = -ENOMEM;
2905 goto err_desc;
2906 }
2907
2908 buf = kzalloc(buf_len, GFP_KERNEL);
2909 if (!buf) {
2910 ret = -ENOMEM;
2911 goto err_buf_alloc;
2912 }
2913
2914 memcpy(desc_data, &desc[0].data[0], buf_len);
2915 for (i = 0; i < buf_size; i++)
2916 buf[i] = le32_to_cpu(desc_data[i]);
2917
2918 hclge_handle_error_module_log(ae_dev, buf, buf_size);
2919 kfree(buf);
2920
2921 err_buf_alloc:
2922 kfree(desc_data);
2923 err_desc:
2924 kfree(desc);
2925 out:
2926 return ret;
2927 }
2928
