1 /*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25 #ifndef __INTEL_DRV_H__
26 #define __INTEL_DRV_H__
27
28 #include <linux/async.h>
29 #include <linux/i2c.h>
30 #include <linux/hdmi.h>
31 #include <linux/sched/clock.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_encoder.h>
37 #include <drm/drm_fb_helper.h>
38 #include <drm/drm_dp_dual_mode_helper.h>
39 #include <drm/drm_dp_mst_helper.h>
40 #include <drm/drm_rect.h>
41 #include <drm/drm_atomic.h>
42 #include <media/cec-notifier.h>
43
44 /**
45 * __wait_for - magic wait macro
46 *
47 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
48 * important that we check the condition again after having timed out, since the
49 * timeout could be due to preemption or similar and we've never had a chance to
50 * check the condition before the timeout.
51 */
52 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
53 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
54 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
55 int ret__; \
56 might_sleep(); \
57 for (;;) { \
58 const bool expired__ = ktime_after(ktime_get_raw(), end__); \
59 OP; \
60 /* Guarantee COND check prior to timeout */ \
61 barrier(); \
62 if (COND) { \
63 ret__ = 0; \
64 break; \
65 } \
66 if (expired__) { \
67 ret__ = -ETIMEDOUT; \
68 break; \
69 } \
70 usleep_range(wait__, wait__ * 2); \
71 if (wait__ < (Wmax)) \
72 wait__ <<= 1; \
73 } \
74 ret__; \
75 })
76
77 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
78 (Wmax))
79 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000)
80
81 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
82 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
84 #else
85 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
86 #endif
87
88 #define _wait_for_atomic(COND, US, ATOMIC) \
89 ({ \
90 int cpu, ret, timeout = (US) * 1000; \
91 u64 base; \
92 _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
93 if (!(ATOMIC)) { \
94 preempt_disable(); \
95 cpu = smp_processor_id(); \
96 } \
97 base = local_clock(); \
98 for (;;) { \
99 u64 now = local_clock(); \
100 if (!(ATOMIC)) \
101 preempt_enable(); \
102 /* Guarantee COND check prior to timeout */ \
103 barrier(); \
104 if (COND) { \
105 ret = 0; \
106 break; \
107 } \
108 if (now - base >= timeout) { \
109 ret = -ETIMEDOUT; \
110 break; \
111 } \
112 cpu_relax(); \
113 if (!(ATOMIC)) { \
114 preempt_disable(); \
115 if (unlikely(cpu != smp_processor_id())) { \
116 timeout -= now - base; \
117 cpu = smp_processor_id(); \
118 base = local_clock(); \
119 } \
120 } \
121 } \
122 ret; \
123 })
124
125 #define wait_for_us(COND, US) \
126 ({ \
127 int ret__; \
128 BUILD_BUG_ON(!__builtin_constant_p(US)); \
129 if ((US) > 10) \
130 ret__ = _wait_for((COND), (US), 10, 10); \
131 else \
132 ret__ = _wait_for_atomic((COND), (US), 0); \
133 ret__; \
134 })
135
136 #define wait_for_atomic_us(COND, US) \
137 ({ \
138 BUILD_BUG_ON(!__builtin_constant_p(US)); \
139 BUILD_BUG_ON((US) > 50000); \
140 _wait_for_atomic((COND), (US), 1); \
141 })
142
143 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
144
145 #define KHz(x) (1000 * (x))
146 #define MHz(x) KHz(1000 * (x))
147
148 #define KBps(x) (1000 * (x))
149 #define MBps(x) KBps(1000 * (x))
150 #define GBps(x) ((u64)1000 * MBps((x)))
151
152 /*
153 * Display related stuff
154 */
155
156 /* store information about an Ixxx DVO */
157 /* The i830->i865 use multiple DVOs with multiple i2cs */
158 /* the i915, i945 have a single sDVO i2c bus - which is different */
159 #define MAX_OUTPUTS 6
160 /* maximum connectors per crtcs in the mode set */
161
162 #define INTEL_I2C_BUS_DVO 1
163 #define INTEL_I2C_BUS_SDVO 2
164
165 /* these are outputs from the chip - integrated only
166 external chips are via DVO or SDVO output */
167 enum intel_output_type {
168 INTEL_OUTPUT_UNUSED = 0,
169 INTEL_OUTPUT_ANALOG = 1,
170 INTEL_OUTPUT_DVO = 2,
171 INTEL_OUTPUT_SDVO = 3,
172 INTEL_OUTPUT_LVDS = 4,
173 INTEL_OUTPUT_TVOUT = 5,
174 INTEL_OUTPUT_HDMI = 6,
175 INTEL_OUTPUT_DP = 7,
176 INTEL_OUTPUT_EDP = 8,
177 INTEL_OUTPUT_DSI = 9,
178 INTEL_OUTPUT_DDI = 10,
179 INTEL_OUTPUT_DP_MST = 11,
180 };
181
182 #define INTEL_DVO_CHIP_NONE 0
183 #define INTEL_DVO_CHIP_LVDS 1
184 #define INTEL_DVO_CHIP_TMDS 2
185 #define INTEL_DVO_CHIP_TVOUT 4
186
187 #define INTEL_DSI_VIDEO_MODE 0
188 #define INTEL_DSI_COMMAND_MODE 1
189
190 struct intel_framebuffer {
191 struct drm_framebuffer base;
192 struct intel_rotation_info rot_info;
193
194 /* for each plane in the normal GTT view */
195 struct {
196 unsigned int x, y;
197 } normal[2];
198 /* for each plane in the rotated GTT view */
199 struct {
200 unsigned int x, y;
201 unsigned int pitch; /* pixels */
202 } rotated[2];
203 };
204
205 struct intel_fbdev {
206 struct drm_fb_helper helper;
207 struct intel_framebuffer *fb;
208 struct i915_vma *vma;
209 unsigned long vma_flags;
210 async_cookie_t cookie;
211 int preferred_bpp;
212 };
213
214 struct intel_encoder {
215 struct drm_encoder base;
216
217 enum intel_output_type type;
218 enum port port;
219 unsigned int cloneable;
220 bool (*hotplug)(struct intel_encoder *encoder,
221 struct intel_connector *connector);
222 enum intel_output_type (*compute_output_type)(struct intel_encoder *,
223 struct intel_crtc_state *,
224 struct drm_connector_state *);
225 bool (*compute_config)(struct intel_encoder *,
226 struct intel_crtc_state *,
227 struct drm_connector_state *);
228 void (*pre_pll_enable)(struct intel_encoder *,
229 const struct intel_crtc_state *,
230 const struct drm_connector_state *);
231 void (*pre_enable)(struct intel_encoder *,
232 const struct intel_crtc_state *,
233 const struct drm_connector_state *);
234 void (*enable)(struct intel_encoder *,
235 const struct intel_crtc_state *,
236 const struct drm_connector_state *);
237 void (*disable)(struct intel_encoder *,
238 const struct intel_crtc_state *,
239 const struct drm_connector_state *);
240 void (*post_disable)(struct intel_encoder *,
241 const struct intel_crtc_state *,
242 const struct drm_connector_state *);
243 void (*post_pll_disable)(struct intel_encoder *,
244 const struct intel_crtc_state *,
245 const struct drm_connector_state *);
246 /* Read out the current hw state of this connector, returning true if
247 * the encoder is active. If the encoder is enabled it also set the pipe
248 * it is connected to in the pipe parameter. */
249 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
250 /* Reconstructs the equivalent mode flags for the current hardware
251 * state. This must be called _after_ display->get_pipe_config has
252 * pre-filled the pipe config. Note that intel_encoder->base.crtc must
253 * be set correctly before calling this function. */
254 void (*get_config)(struct intel_encoder *,
255 struct intel_crtc_state *pipe_config);
256 /* Returns a mask of power domains that need to be referenced as part
257 * of the hardware state readout code. */
258 u64 (*get_power_domains)(struct intel_encoder *encoder,
259 struct intel_crtc_state *crtc_state);
260 /*
261 * Called during system suspend after all pending requests for the
262 * encoder are flushed (for example for DP AUX transactions) and
263 * device interrupts are disabled.
264 */
265 void (*suspend)(struct intel_encoder *);
266 int crtc_mask;
267 enum hpd_pin hpd_pin;
268 enum intel_display_power_domain power_domain;
269 /* for communication with audio component; protected by av_mutex */
270 const struct drm_connector *audio_connector;
271 };
272
273 struct intel_panel {
274 struct drm_display_mode *fixed_mode;
275 struct drm_display_mode *downclock_mode;
276
277 /* backlight */
278 struct {
279 bool present;
280 u32 level;
281 u32 min;
282 u32 max;
283 bool enabled;
284 bool combination_mode; /* gen 2/4 only */
285 bool active_low_pwm;
286 bool alternate_pwm_increment; /* lpt+ */
287
288 /* PWM chip */
289 bool util_pin_active_low; /* bxt+ */
290 u8 controller; /* bxt+ only */
291 struct pwm_device *pwm;
292
293 struct backlight_device *device;
294
295 /* Connector and platform specific backlight functions */
296 int (*setup)(struct intel_connector *connector, enum pipe pipe);
297 uint32_t (*get)(struct intel_connector *connector);
298 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
299 void (*disable)(const struct drm_connector_state *conn_state);
300 void (*enable)(const struct intel_crtc_state *crtc_state,
301 const struct drm_connector_state *conn_state);
302 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
303 uint32_t hz);
304 void (*power)(struct intel_connector *, bool enable);
305 } backlight;
306 };
307
308 struct intel_digital_port;
309
310 /*
311 * This structure serves as a translation layer between the generic HDCP code
312 * and the bus-specific code. What that means is that HDCP over HDMI differs
313 * from HDCP over DP, so to account for these differences, we need to
314 * communicate with the receiver through this shim.
315 *
316 * For completeness, the 2 buses differ in the following ways:
317 * - DP AUX vs. DDC
318 * HDCP registers on the receiver are set via DP AUX for DP, and
319 * they are set via DDC for HDMI.
320 * - Receiver register offsets
321 * The offsets of the registers are different for DP vs. HDMI
322 * - Receiver register masks/offsets
323 * For instance, the ready bit for the KSV fifo is in a different
324 * place on DP vs HDMI
325 * - Receiver register names
326 * Seriously. In the DP spec, the 16-bit register containing
327 * downstream information is called BINFO, on HDMI it's called
328 * BSTATUS. To confuse matters further, DP has a BSTATUS register
329 * with a completely different definition.
330 * - KSV FIFO
331 * On HDMI, the ksv fifo is read all at once, whereas on DP it must
332 * be read 3 keys at a time
333 * - Aksv output
334 * Since Aksv is hidden in hardware, there's different procedures
335 * to send it over DP AUX vs DDC
336 */
337 struct intel_hdcp_shim {
338 /* Outputs the transmitter's An and Aksv values to the receiver. */
339 int (*write_an_aksv)(struct intel_digital_port *intel_dig_port, u8 *an);
340
341 /* Reads the receiver's key selection vector */
342 int (*read_bksv)(struct intel_digital_port *intel_dig_port, u8 *bksv);
343
344 /*
345 * Reads BINFO from DP receivers and BSTATUS from HDMI receivers. The
346 * definitions are the same in the respective specs, but the names are
347 * different. Call it BSTATUS since that's the name the HDMI spec
348 * uses and it was there first.
349 */
350 int (*read_bstatus)(struct intel_digital_port *intel_dig_port,
351 u8 *bstatus);
352
353 /* Determines whether a repeater is present downstream */
354 int (*repeater_present)(struct intel_digital_port *intel_dig_port,
355 bool *repeater_present);
356
357 /* Reads the receiver's Ri' value */
358 int (*read_ri_prime)(struct intel_digital_port *intel_dig_port, u8 *ri);
359
360 /* Determines if the receiver's KSV FIFO is ready for consumption */
361 int (*read_ksv_ready)(struct intel_digital_port *intel_dig_port,
362 bool *ksv_ready);
363
364 /* Reads the ksv fifo for num_downstream devices */
365 int (*read_ksv_fifo)(struct intel_digital_port *intel_dig_port,
366 int num_downstream, u8 *ksv_fifo);
367
368 /* Reads a 32-bit part of V' from the receiver */
369 int (*read_v_prime_part)(struct intel_digital_port *intel_dig_port,
370 int i, u32 *part);
371
372 /* Enables HDCP signalling on the port */
373 int (*toggle_signalling)(struct intel_digital_port *intel_dig_port,
374 bool enable);
375
376 /* Ensures the link is still protected */
377 bool (*check_link)(struct intel_digital_port *intel_dig_port);
378
379 /* Detects panel's hdcp capability. This is optional for HDMI. */
380 int (*hdcp_capable)(struct intel_digital_port *intel_dig_port,
381 bool *hdcp_capable);
382 };
383
384 struct intel_connector {
385 struct drm_connector base;
386 /*
387 * The fixed encoder this connector is connected to.
388 */
389 struct intel_encoder *encoder;
390
391 /* ACPI device id for ACPI and driver cooperation */
392 u32 acpi_device_id;
393
394 /* Reads out the current hw, returning true if the connector is enabled
395 * and active (i.e. dpms ON state). */
396 bool (*get_hw_state)(struct intel_connector *);
397
398 /* Panel info for eDP and LVDS */
399 struct intel_panel panel;
400
401 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
402 struct edid *edid;
403 struct edid *detect_edid;
404
405 /* since POLL and HPD connectors may use the same HPD line keep the native
406 state of connector->polled in case hotplug storm detection changes it */
407 u8 polled;
408
409 void *port; /* store this opaque as its illegal to dereference it */
410
411 struct intel_dp *mst_port;
412
413 /* Work struct to schedule a uevent on link train failure */
414 struct work_struct modeset_retry_work;
415
416 const struct intel_hdcp_shim *hdcp_shim;
417 struct mutex hdcp_mutex;
418 uint64_t hdcp_value; /* protected by hdcp_mutex */
419 struct delayed_work hdcp_check_work;
420 struct work_struct hdcp_prop_work;
421 };
422
423 struct intel_digital_connector_state {
424 struct drm_connector_state base;
425
426 enum hdmi_force_audio force_audio;
427 int broadcast_rgb;
428 };
429
430 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
431
432 struct dpll {
433 /* given values */
434 int n;
435 int m1, m2;
436 int p1, p2;
437 /* derived values */
438 int dot;
439 int vco;
440 int m;
441 int p;
442 };
443
444 struct intel_atomic_state {
445 struct drm_atomic_state base;
446
447 struct {
448 /*
449 * Logical state of cdclk (used for all scaling, watermark,
450 * etc. calculations and checks). This is computed as if all
451 * enabled crtcs were active.
452 */
453 struct intel_cdclk_state logical;
454
455 /*
456 * Actual state of cdclk, can be different from the logical
457 * state only when all crtc's are DPMS off.
458 */
459 struct intel_cdclk_state actual;
460 } cdclk;
461
462 bool dpll_set, modeset;
463
464 /*
465 * Does this transaction change the pipes that are active? This mask
466 * tracks which CRTC's have changed their active state at the end of
467 * the transaction (not counting the temporary disable during modesets).
468 * This mask should only be non-zero when intel_state->modeset is true,
469 * but the converse is not necessarily true; simply changing a mode may
470 * not flip the final active status of any CRTC's
471 */
472 unsigned int active_pipe_changes;
473
474 unsigned int active_crtcs;
475 /* minimum acceptable cdclk for each pipe */
476 int min_cdclk[I915_MAX_PIPES];
477 /* minimum acceptable voltage level for each pipe */
478 u8 min_voltage_level[I915_MAX_PIPES];
479
480 struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
481
482 /*
483 * Current watermarks can't be trusted during hardware readout, so
484 * don't bother calculating intermediate watermarks.
485 */
486 bool skip_intermediate_wm;
487
488 bool rps_interactive;
489
490 /* Gen9+ only */
491 struct skl_ddb_values wm_results;
492
493 struct i915_sw_fence commit_ready;
494
495 struct llist_node freed;
496 };
497
498 struct intel_plane_state {
499 struct drm_plane_state base;
500 struct i915_vma *vma;
501 unsigned long flags;
502 #define PLANE_HAS_FENCE BIT(0)
503
504 struct {
505 u32 offset;
506 int x, y;
507 } main;
508 struct {
509 u32 offset;
510 int x, y;
511 } aux;
512
513 /* plane control register */
514 u32 ctl;
515
516 /* plane color control register */
517 u32 color_ctl;
518
519 /*
520 * scaler_id
521 * = -1 : not using a scaler
522 * >= 0 : using a scalers
523 *
524 * plane requiring a scaler:
525 * - During check_plane, its bit is set in
526 * crtc_state->scaler_state.scaler_users by calling helper function
527 * update_scaler_plane.
528 * - scaler_id indicates the scaler it got assigned.
529 *
530 * plane doesn't require a scaler:
531 * - this can happen when scaling is no more required or plane simply
532 * got disabled.
533 * - During check_plane, corresponding bit is reset in
534 * crtc_state->scaler_state.scaler_users by calling helper function
535 * update_scaler_plane.
536 */
537 int scaler_id;
538
539 struct drm_intel_sprite_colorkey ckey;
540 };
541
542 struct intel_initial_plane_config {
543 struct intel_framebuffer *fb;
544 unsigned int tiling;
545 int size;
546 u32 base;
547 };
548
549 #define SKL_MIN_SRC_W 8
550 #define SKL_MAX_SRC_W 4096
551 #define SKL_MIN_SRC_H 8
552 #define SKL_MAX_SRC_H 4096
553 #define SKL_MIN_DST_W 8
554 #define SKL_MAX_DST_W 4096
555 #define SKL_MIN_DST_H 8
556 #define SKL_MAX_DST_H 4096
557 #define ICL_MAX_SRC_W 5120
558 #define ICL_MAX_SRC_H 4096
559 #define ICL_MAX_DST_W 5120
560 #define ICL_MAX_DST_H 4096
561 #define SKL_MIN_YUV_420_SRC_W 16
562 #define SKL_MIN_YUV_420_SRC_H 16
563
564 struct intel_scaler {
565 int in_use;
566 uint32_t mode;
567 };
568
569 struct intel_crtc_scaler_state {
570 #define SKL_NUM_SCALERS 2
571 struct intel_scaler scalers[SKL_NUM_SCALERS];
572
573 /*
574 * scaler_users: keeps track of users requesting scalers on this crtc.
575 *
576 * If a bit is set, a user is using a scaler.
577 * Here user can be a plane or crtc as defined below:
578 * bits 0-30 - plane (bit position is index from drm_plane_index)
579 * bit 31 - crtc
580 *
581 * Instead of creating a new index to cover planes and crtc, using
582 * existing drm_plane_index for planes which is well less than 31
583 * planes and bit 31 for crtc. This should be fine to cover all
584 * our platforms.
585 *
586 * intel_atomic_setup_scalers will setup available scalers to users
587 * requesting scalers. It will gracefully fail if request exceeds
588 * avilability.
589 */
590 #define SKL_CRTC_INDEX 31
591 unsigned scaler_users;
592
593 /* scaler used by crtc for panel fitting purpose */
594 int scaler_id;
595 };
596
597 /* drm_mode->private_flags */
598 #define I915_MODE_FLAG_INHERITED 1
599 /* Flag to get scanline using frame time stamps */
600 #define I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP (1<<1)
601
602 struct intel_pipe_wm {
603 struct intel_wm_level wm[5];
604 uint32_t linetime;
605 bool fbc_wm_enabled;
606 bool pipe_enabled;
607 bool sprites_enabled;
608 bool sprites_scaled;
609 };
610
611 struct skl_plane_wm {
612 struct skl_wm_level wm[8];
613 struct skl_wm_level uv_wm[8];
614 struct skl_wm_level trans_wm;
615 bool is_planar;
616 };
617
618 struct skl_pipe_wm {
619 struct skl_plane_wm planes[I915_MAX_PLANES];
620 uint32_t linetime;
621 };
622
623 enum vlv_wm_level {
624 VLV_WM_LEVEL_PM2,
625 VLV_WM_LEVEL_PM5,
626 VLV_WM_LEVEL_DDR_DVFS,
627 NUM_VLV_WM_LEVELS,
628 };
629
630 struct vlv_wm_state {
631 struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
632 struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
633 uint8_t num_levels;
634 bool cxsr;
635 };
636
637 struct vlv_fifo_state {
638 u16 plane[I915_MAX_PLANES];
639 };
640
641 enum g4x_wm_level {
642 G4X_WM_LEVEL_NORMAL,
643 G4X_WM_LEVEL_SR,
644 G4X_WM_LEVEL_HPLL,
645 NUM_G4X_WM_LEVELS,
646 };
647
648 struct g4x_wm_state {
649 struct g4x_pipe_wm wm;
650 struct g4x_sr_wm sr;
651 struct g4x_sr_wm hpll;
652 bool cxsr;
653 bool hpll_en;
654 bool fbc_en;
655 };
656
657 struct intel_crtc_wm_state {
658 union {
659 struct {
660 /*
661 * Intermediate watermarks; these can be
662 * programmed immediately since they satisfy
663 * both the current configuration we're
664 * switching away from and the new
665 * configuration we're switching to.
666 */
667 struct intel_pipe_wm intermediate;
668
669 /*
670 * Optimal watermarks, programmed post-vblank
671 * when this state is committed.
672 */
673 struct intel_pipe_wm optimal;
674 } ilk;
675
676 struct {
677 /* gen9+ only needs 1-step wm programming */
678 struct skl_pipe_wm optimal;
679 struct skl_ddb_entry ddb;
680 } skl;
681
682 struct {
683 /* "raw" watermarks (not inverted) */
684 struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
685 /* intermediate watermarks (inverted) */
686 struct vlv_wm_state intermediate;
687 /* optimal watermarks (inverted) */
688 struct vlv_wm_state optimal;
689 /* display FIFO split */
690 struct vlv_fifo_state fifo_state;
691 } vlv;
692
693 struct {
694 /* "raw" watermarks */
695 struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
696 /* intermediate watermarks */
697 struct g4x_wm_state intermediate;
698 /* optimal watermarks */
699 struct g4x_wm_state optimal;
700 } g4x;
701 };
702
703 /*
704 * Platforms with two-step watermark programming will need to
705 * update watermark programming post-vblank to switch from the
706 * safe intermediate watermarks to the optimal final
707 * watermarks.
708 */
709 bool need_postvbl_update;
710 };
711
712 struct intel_crtc_state {
713 struct drm_crtc_state base;
714
715 /**
716 * quirks - bitfield with hw state readout quirks
717 *
718 * For various reasons the hw state readout code might not be able to
719 * completely faithfully read out the current state. These cases are
720 * tracked with quirk flags so that fastboot and state checker can act
721 * accordingly.
722 */
723 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */
724 unsigned long quirks;
725
726 unsigned fb_bits; /* framebuffers to flip */
727 bool update_pipe; /* can a fast modeset be performed? */
728 bool disable_cxsr;
729 bool update_wm_pre, update_wm_post; /* watermarks are updated */
730 bool fb_changed; /* fb on any of the planes is changed */
731 bool fifo_changed; /* FIFO split is changed */
732
733 /* Pipe source size (ie. panel fitter input size)
734 * All planes will be positioned inside this space,
735 * and get clipped at the edges. */
736 int pipe_src_w, pipe_src_h;
737
738 /*
739 * Pipe pixel rate, adjusted for
740 * panel fitter/pipe scaler downscaling.
741 */
742 unsigned int pixel_rate;
743
744 /* Whether to set up the PCH/FDI. Note that we never allow sharing
745 * between pch encoders and cpu encoders. */
746 bool has_pch_encoder;
747
748 /* Are we sending infoframes on the attached port */
749 bool has_infoframe;
750
751 /* CPU Transcoder for the pipe. Currently this can only differ from the
752 * pipe on Haswell and later (where we have a special eDP transcoder)
753 * and Broxton (where we have special DSI transcoders). */
754 enum transcoder cpu_transcoder;
755
756 /*
757 * Use reduced/limited/broadcast rbg range, compressing from the full
758 * range fed into the crtcs.
759 */
760 bool limited_color_range;
761
762 /* Bitmask of encoder types (enum intel_output_type)
763 * driven by the pipe.
764 */
765 unsigned int output_types;
766
767 /* Whether we should send NULL infoframes. Required for audio. */
768 bool has_hdmi_sink;
769
770 /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
771 * has_dp_encoder is set. */
772 bool has_audio;
773
774 /*
775 * Enable dithering, used when the selected pipe bpp doesn't match the
776 * plane bpp.
777 */
778 bool dither;
779
780 /*
781 * Dither gets enabled for 18bpp which causes CRC mismatch errors for
782 * compliance video pattern tests.
783 * Disable dither only if it is a compliance test request for
784 * 18bpp.
785 */
786 bool dither_force_disable;
787
788 /* Controls for the clock computation, to override various stages. */
789 bool clock_set;
790
791 /* SDVO TV has a bunch of special case. To make multifunction encoders
792 * work correctly, we need to track this at runtime.*/
793 bool sdvo_tv_clock;
794
795 /*
796 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
797 * required. This is set in the 2nd loop of calling encoder's
798 * ->compute_config if the first pick doesn't work out.
799 */
800 bool bw_constrained;
801
802 /* Settings for the intel dpll used on pretty much everything but
803 * haswell. */
804 struct dpll dpll;
805
806 /* Selected dpll when shared or NULL. */
807 struct intel_shared_dpll *shared_dpll;
808
809 /* Actual register state of the dpll, for shared dpll cross-checking. */
810 struct intel_dpll_hw_state dpll_hw_state;
811
812 /* DSI PLL registers */
813 struct {
814 u32 ctrl, div;
815 } dsi_pll;
816
817 int pipe_bpp;
818 struct intel_link_m_n dp_m_n;
819
820 /* m2_n2 for eDP downclock */
821 struct intel_link_m_n dp_m2_n2;
822 bool has_drrs;
823
824 bool has_psr;
825 bool has_psr2;
826
827 /*
828 * Frequence the dpll for the port should run at. Differs from the
829 * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
830 * already multiplied by pixel_multiplier.
831 */
832 int port_clock;
833
834 /* Used by SDVO (and if we ever fix it, HDMI). */
835 unsigned pixel_multiplier;
836
837 uint8_t lane_count;
838
839 /*
840 * Used by platforms having DP/HDMI PHY with programmable lane
841 * latency optimization.
842 */
843 uint8_t lane_lat_optim_mask;
844
845 /* minimum acceptable voltage level */
846 u8 min_voltage_level;
847
848 /* Panel fitter controls for gen2-gen4 + VLV */
849 struct {
850 u32 control;
851 u32 pgm_ratios;
852 u32 lvds_border_bits;
853 } gmch_pfit;
854
855 /* Panel fitter placement and size for Ironlake+ */
856 struct {
857 u32 pos;
858 u32 size;
859 bool enabled;
860 bool force_thru;
861 } pch_pfit;
862
863 /* FDI configuration, only valid if has_pch_encoder is set. */
864 int fdi_lanes;
865 struct intel_link_m_n fdi_m_n;
866
867 bool ips_enabled;
868 bool ips_force_disable;
869
870 bool enable_fbc;
871
872 bool double_wide;
873
874 int pbn;
875
876 struct intel_crtc_scaler_state scaler_state;
877
878 /* w/a for waiting 2 vblanks during crtc enable */
879 enum pipe hsw_workaround_pipe;
880
881 /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
882 bool disable_lp_wm;
883
884 struct intel_crtc_wm_state wm;
885
886 /* Gamma mode programmed on the pipe */
887 uint32_t gamma_mode;
888
889 /* bitmask of visible planes (enum plane_id) */
890 u8 active_planes;
891 u8 nv12_planes;
892
893 /* HDMI scrambling status */
894 bool hdmi_scrambling;
895
896 /* HDMI High TMDS char rate ratio */
897 bool hdmi_high_tmds_clock_ratio;
898
899 /* output format is YCBCR 4:2:0 */
900 bool ycbcr420;
901 };
902
903 struct intel_crtc {
904 struct drm_crtc base;
905 enum pipe pipe;
906 /*
907 * Whether the crtc and the connected output pipeline is active. Implies
908 * that crtc->enabled is set, i.e. the current mode configuration has
909 * some outputs connected to this crtc.
910 */
911 bool active;
912 u8 plane_ids_mask;
913 unsigned long long enabled_power_domains;
914 struct intel_overlay *overlay;
915
916 struct intel_crtc_state *config;
917
918 /* global reset count when the last flip was submitted */
919 unsigned int reset_count;
920
921 /* Access to these should be protected by dev_priv->irq_lock. */
922 bool cpu_fifo_underrun_disabled;
923 bool pch_fifo_underrun_disabled;
924
925 /* per-pipe watermark state */
926 struct {
927 /* watermarks currently being used */
928 union {
929 struct intel_pipe_wm ilk;
930 struct vlv_wm_state vlv;
931 struct g4x_wm_state g4x;
932 } active;
933 } wm;
934
935 int scanline_offset;
936
937 struct {
938 unsigned start_vbl_count;
939 ktime_t start_vbl_time;
940 int min_vbl, max_vbl;
941 int scanline_start;
942 } debug;
943
944 /* scalers available on this crtc */
945 int num_scalers;
946 };
947
948 struct intel_plane {
949 struct drm_plane base;
950 enum i9xx_plane_id i9xx_plane;
951 enum plane_id id;
952 enum pipe pipe;
953 bool can_scale;
954 bool has_fbc;
955 bool has_ccs;
956 int max_downscale;
957 uint32_t frontbuffer_bit;
958
959 struct {
960 u32 base, cntl, size;
961 } cursor;
962
963 /*
964 * NOTE: Do not place new plane state fields here (e.g., when adding
965 * new plane properties). New runtime state should now be placed in
966 * the intel_plane_state structure and accessed via plane_state.
967 */
968
969 void (*update_plane)(struct intel_plane *plane,
970 const struct intel_crtc_state *crtc_state,
971 const struct intel_plane_state *plane_state);
972 void (*disable_plane)(struct intel_plane *plane,
973 struct intel_crtc *crtc);
974 bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
975 int (*check_plane)(struct intel_plane *plane,
976 struct intel_crtc_state *crtc_state,
977 struct intel_plane_state *state);
978 };
979
980 struct intel_watermark_params {
981 u16 fifo_size;
982 u16 max_wm;
983 u8 default_wm;
984 u8 guard_size;
985 u8 cacheline_size;
986 };
987
988 struct cxsr_latency {
989 bool is_desktop : 1;
990 bool is_ddr3 : 1;
991 u16 fsb_freq;
992 u16 mem_freq;
993 u16 display_sr;
994 u16 display_hpll_disable;
995 u16 cursor_sr;
996 u16 cursor_hpll_disable;
997 };
998
999 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
1000 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
1001 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
1002 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
1003 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
1004 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
1005 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
1006 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
1007 #define intel_fb_obj(x) ((x) ? to_intel_bo((x)->obj[0]) : NULL)
1008
1009 struct intel_hdmi {
1010 i915_reg_t hdmi_reg;
1011 int ddc_bus;
1012 struct {
1013 enum drm_dp_dual_mode_type type;
1014 int max_tmds_clock;
1015 } dp_dual_mode;
1016 bool has_hdmi_sink;
1017 bool has_audio;
1018 bool rgb_quant_range_selectable;
1019 struct intel_connector *attached_connector;
1020 struct cec_notifier *cec_notifier;
1021 };
1022
1023 struct intel_dp_mst_encoder;
1024 #define DP_MAX_DOWNSTREAM_PORTS 0x10
1025
1026 /*
1027 * enum link_m_n_set:
1028 * When platform provides two set of M_N registers for dp, we can
1029 * program them and switch between them incase of DRRS.
1030 * But When only one such register is provided, we have to program the
1031 * required divider value on that registers itself based on the DRRS state.
1032 *
1033 * M1_N1 : Program dp_m_n on M1_N1 registers
1034 * dp_m2_n2 on M2_N2 registers (If supported)
1035 *
1036 * M2_N2 : Program dp_m2_n2 on M1_N1 registers
1037 * M2_N2 registers are not supported
1038 */
1039
1040 enum link_m_n_set {
1041 /* Sets the m1_n1 and m2_n2 */
1042 M1_N1 = 0,
1043 M2_N2
1044 };
1045
1046 struct intel_dp_compliance_data {
1047 unsigned long edid;
1048 uint8_t video_pattern;
1049 uint16_t hdisplay, vdisplay;
1050 uint8_t bpc;
1051 };
1052
1053 struct intel_dp_compliance {
1054 unsigned long test_type;
1055 struct intel_dp_compliance_data test_data;
1056 bool test_active;
1057 int test_link_rate;
1058 u8 test_lane_count;
1059 };
1060
1061 struct intel_dp {
1062 i915_reg_t output_reg;
1063 uint32_t DP;
1064 int link_rate;
1065 uint8_t lane_count;
1066 uint8_t sink_count;
1067 bool link_mst;
1068 bool link_trained;
1069 bool has_audio;
1070 bool detect_done;
1071 bool reset_link_params;
1072 enum aux_ch aux_ch;
1073 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1074 uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1075 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1076 uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1077 /* source rates */
1078 int num_source_rates;
1079 const int *source_rates;
1080 /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
1081 int num_sink_rates;
1082 int sink_rates[DP_MAX_SUPPORTED_RATES];
1083 bool use_rate_select;
1084 /* intersection of source and sink rates */
1085 int num_common_rates;
1086 int common_rates[DP_MAX_SUPPORTED_RATES];
1087 /* Max lane count for the current link */
1088 int max_link_lane_count;
1089 /* Max rate for the current link */
1090 int max_link_rate;
1091 /* sink or branch descriptor */
1092 struct drm_dp_desc desc;
1093 struct drm_dp_aux aux;
1094 enum intel_display_power_domain aux_power_domain;
1095 uint8_t train_set[4];
1096 int panel_power_up_delay;
1097 int panel_power_down_delay;
1098 int panel_power_cycle_delay;
1099 int backlight_on_delay;
1100 int backlight_off_delay;
1101 struct delayed_work panel_vdd_work;
1102 bool want_panel_vdd;
1103 unsigned long last_power_on;
1104 unsigned long last_backlight_off;
1105 ktime_t panel_power_off_time;
1106
1107 struct notifier_block edp_notifier;
1108
1109 /*
1110 * Pipe whose power sequencer is currently locked into
1111 * this port. Only relevant on VLV/CHV.
1112 */
1113 enum pipe pps_pipe;
1114 /*
1115 * Pipe currently driving the port. Used for preventing
1116 * the use of the PPS for any pipe currentrly driving
1117 * external DP as that will mess things up on VLV.
1118 */
1119 enum pipe active_pipe;
1120 /*
1121 * Set if the sequencer may be reset due to a power transition,
1122 * requiring a reinitialization. Only relevant on BXT.
1123 */
1124 bool pps_reset;
1125 struct edp_power_seq pps_delays;
1126
1127 bool can_mst; /* this port supports mst */
1128 bool is_mst;
1129 int active_mst_links;
1130 /* connector directly attached - won't be use for modeset in mst world */
1131 struct intel_connector *attached_connector;
1132
1133 /* mst connector list */
1134 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1135 struct drm_dp_mst_topology_mgr mst_mgr;
1136
1137 uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1138 /*
1139 * This function returns the value we have to program the AUX_CTL
1140 * register with to kick off an AUX transaction.
1141 */
1142 uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1143 int send_bytes,
1144 uint32_t aux_clock_divider);
1145
1146 i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);
1147 i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);
1148
1149 /* This is called before a link training is starterd */
1150 void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1151
1152 /* Displayport compliance testing */
1153 struct intel_dp_compliance compliance;
1154 };
1155
1156 struct intel_lspcon {
1157 bool active;
1158 enum drm_lspcon_mode mode;
1159 };
1160
1161 struct intel_digital_port {
1162 struct intel_encoder base;
1163 u32 saved_port_bits;
1164 struct intel_dp dp;
1165 struct intel_hdmi hdmi;
1166 struct intel_lspcon lspcon;
1167 enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1168 bool release_cl2_override;
1169 uint8_t max_lanes;
1170 enum intel_display_power_domain ddi_io_power_domain;
1171
1172 void (*write_infoframe)(struct drm_encoder *encoder,
1173 const struct intel_crtc_state *crtc_state,
1174 unsigned int type,
1175 const void *frame, ssize_t len);
1176 void (*set_infoframes)(struct drm_encoder *encoder,
1177 bool enable,
1178 const struct intel_crtc_state *crtc_state,
1179 const struct drm_connector_state *conn_state);
1180 bool (*infoframe_enabled)(struct drm_encoder *encoder,
1181 const struct intel_crtc_state *pipe_config);
1182 };
1183
1184 struct intel_dp_mst_encoder {
1185 struct intel_encoder base;
1186 enum pipe pipe;
1187 struct intel_digital_port *primary;
1188 struct intel_connector *connector;
1189 };
1190
1191 static inline enum dpio_channel
vlv_dport_to_channel(struct intel_digital_port * dport)1192 vlv_dport_to_channel(struct intel_digital_port *dport)
1193 {
1194 switch (dport->base.port) {
1195 case PORT_B:
1196 case PORT_D:
1197 return DPIO_CH0;
1198 case PORT_C:
1199 return DPIO_CH1;
1200 default:
1201 BUG();
1202 }
1203 }
1204
1205 static inline enum dpio_phy
vlv_dport_to_phy(struct intel_digital_port * dport)1206 vlv_dport_to_phy(struct intel_digital_port *dport)
1207 {
1208 switch (dport->base.port) {
1209 case PORT_B:
1210 case PORT_C:
1211 return DPIO_PHY0;
1212 case PORT_D:
1213 return DPIO_PHY1;
1214 default:
1215 BUG();
1216 }
1217 }
1218
1219 static inline enum dpio_channel
vlv_pipe_to_channel(enum pipe pipe)1220 vlv_pipe_to_channel(enum pipe pipe)
1221 {
1222 switch (pipe) {
1223 case PIPE_A:
1224 case PIPE_C:
1225 return DPIO_CH0;
1226 case PIPE_B:
1227 return DPIO_CH1;
1228 default:
1229 BUG();
1230 }
1231 }
1232
1233 static inline struct intel_crtc *
intel_get_crtc_for_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1234 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1235 {
1236 return dev_priv->pipe_to_crtc_mapping[pipe];
1237 }
1238
1239 static inline struct intel_crtc *
intel_get_crtc_for_plane(struct drm_i915_private * dev_priv,enum i9xx_plane_id plane)1240 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum i9xx_plane_id plane)
1241 {
1242 return dev_priv->plane_to_crtc_mapping[plane];
1243 }
1244
1245 struct intel_load_detect_pipe {
1246 struct drm_atomic_state *restore_state;
1247 };
1248
1249 static inline struct intel_encoder *
intel_attached_encoder(struct drm_connector * connector)1250 intel_attached_encoder(struct drm_connector *connector)
1251 {
1252 return to_intel_connector(connector)->encoder;
1253 }
1254
intel_encoder_is_dig_port(struct intel_encoder * encoder)1255 static inline bool intel_encoder_is_dig_port(struct intel_encoder *encoder)
1256 {
1257 switch (encoder->type) {
1258 case INTEL_OUTPUT_DDI:
1259 case INTEL_OUTPUT_DP:
1260 case INTEL_OUTPUT_EDP:
1261 case INTEL_OUTPUT_HDMI:
1262 return true;
1263 default:
1264 return false;
1265 }
1266 }
1267
1268 static inline struct intel_digital_port *
enc_to_dig_port(struct drm_encoder * encoder)1269 enc_to_dig_port(struct drm_encoder *encoder)
1270 {
1271 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1272
1273 if (intel_encoder_is_dig_port(intel_encoder))
1274 return container_of(encoder, struct intel_digital_port,
1275 base.base);
1276 else
1277 return NULL;
1278 }
1279
1280 static inline struct intel_dp_mst_encoder *
enc_to_mst(struct drm_encoder * encoder)1281 enc_to_mst(struct drm_encoder *encoder)
1282 {
1283 return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1284 }
1285
enc_to_intel_dp(struct drm_encoder * encoder)1286 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1287 {
1288 return &enc_to_dig_port(encoder)->dp;
1289 }
1290
intel_encoder_is_dp(struct intel_encoder * encoder)1291 static inline bool intel_encoder_is_dp(struct intel_encoder *encoder)
1292 {
1293 switch (encoder->type) {
1294 case INTEL_OUTPUT_DP:
1295 case INTEL_OUTPUT_EDP:
1296 return true;
1297 case INTEL_OUTPUT_DDI:
1298 /* Skip pure HDMI/DVI DDI encoders */
1299 return i915_mmio_reg_valid(enc_to_intel_dp(&encoder->base)->output_reg);
1300 default:
1301 return false;
1302 }
1303 }
1304
1305 static inline struct intel_digital_port *
dp_to_dig_port(struct intel_dp * intel_dp)1306 dp_to_dig_port(struct intel_dp *intel_dp)
1307 {
1308 return container_of(intel_dp, struct intel_digital_port, dp);
1309 }
1310
1311 static inline struct intel_lspcon *
dp_to_lspcon(struct intel_dp * intel_dp)1312 dp_to_lspcon(struct intel_dp *intel_dp)
1313 {
1314 return &dp_to_dig_port(intel_dp)->lspcon;
1315 }
1316
1317 static inline struct intel_digital_port *
hdmi_to_dig_port(struct intel_hdmi * intel_hdmi)1318 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1319 {
1320 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1321 }
1322
1323 static inline struct intel_plane_state *
intel_atomic_get_new_plane_state(struct intel_atomic_state * state,struct intel_plane * plane)1324 intel_atomic_get_new_plane_state(struct intel_atomic_state *state,
1325 struct intel_plane *plane)
1326 {
1327 return to_intel_plane_state(drm_atomic_get_new_plane_state(&state->base,
1328 &plane->base));
1329 }
1330
1331 static inline struct intel_crtc_state *
intel_atomic_get_old_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1332 intel_atomic_get_old_crtc_state(struct intel_atomic_state *state,
1333 struct intel_crtc *crtc)
1334 {
1335 return to_intel_crtc_state(drm_atomic_get_old_crtc_state(&state->base,
1336 &crtc->base));
1337 }
1338
1339 static inline struct intel_crtc_state *
intel_atomic_get_new_crtc_state(struct intel_atomic_state * state,struct intel_crtc * crtc)1340 intel_atomic_get_new_crtc_state(struct intel_atomic_state *state,
1341 struct intel_crtc *crtc)
1342 {
1343 return to_intel_crtc_state(drm_atomic_get_new_crtc_state(&state->base,
1344 &crtc->base));
1345 }
1346
1347 /* intel_fifo_underrun.c */
1348 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, bool enable);
1350 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1351 enum pipe pch_transcoder,
1352 bool enable);
1353 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1354 enum pipe pipe);
1355 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1356 enum pipe pch_transcoder);
1357 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1358 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1359
1360 /* i915_irq.c */
1361 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1362 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1363 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1364 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1365 void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1366 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1367 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1368 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1369
gen6_sanitize_rps_pm_mask(const struct drm_i915_private * i915,u32 mask)1370 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1371 u32 mask)
1372 {
1373 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
1374 }
1375
1376 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1377 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
intel_irqs_enabled(struct drm_i915_private * dev_priv)1378 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1379 {
1380 /*
1381 * We only use drm_irq_uninstall() at unload and VT switch, so
1382 * this is the only thing we need to check.
1383 */
1384 return dev_priv->runtime_pm.irqs_enabled;
1385 }
1386
1387 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1388 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1389 u8 pipe_mask);
1390 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1391 u8 pipe_mask);
1392 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1393 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1394 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1395
1396 /* intel_crt.c */
1397 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
1398 i915_reg_t adpa_reg, enum pipe *pipe);
1399 void intel_crt_init(struct drm_i915_private *dev_priv);
1400 void intel_crt_reset(struct drm_encoder *encoder);
1401
1402 /* intel_ddi.c */
1403 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1404 const struct intel_crtc_state *old_crtc_state,
1405 const struct drm_connector_state *old_conn_state);
1406 void hsw_fdi_link_train(struct intel_crtc *crtc,
1407 const struct intel_crtc_state *crtc_state);
1408 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1409 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1410 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1411 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1412 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1413 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
1414 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1415 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1416 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1417 void intel_ddi_get_config(struct intel_encoder *encoder,
1418 struct intel_crtc_state *pipe_config);
1419
1420 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1421 bool state);
1422 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
1423 struct intel_crtc_state *crtc_state);
1424 u32 bxt_signal_levels(struct intel_dp *intel_dp);
1425 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1426 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1427 u8 intel_ddi_dp_pre_emphasis_max(struct intel_encoder *encoder,
1428 u8 voltage_swing);
1429 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1430 bool enable);
1431 void icl_map_plls_to_ports(struct drm_crtc *crtc,
1432 struct intel_crtc_state *crtc_state,
1433 struct drm_atomic_state *old_state);
1434 void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
1435 struct intel_crtc_state *crtc_state,
1436 struct drm_atomic_state *old_state);
1437
1438 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1439 int plane, unsigned int height);
1440
1441 /* intel_audio.c */
1442 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1443 void intel_audio_codec_enable(struct intel_encoder *encoder,
1444 const struct intel_crtc_state *crtc_state,
1445 const struct drm_connector_state *conn_state);
1446 void intel_audio_codec_disable(struct intel_encoder *encoder,
1447 const struct intel_crtc_state *old_crtc_state,
1448 const struct drm_connector_state *old_conn_state);
1449 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1450 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1451 void intel_audio_init(struct drm_i915_private *dev_priv);
1452 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1453
1454 /* intel_cdclk.c */
1455 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
1456 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1457 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1458 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1459 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1460 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1461 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1462 void icl_init_cdclk(struct drm_i915_private *dev_priv);
1463 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
1464 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1465 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1466 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1467 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1468 bool intel_cdclk_needs_modeset(const struct intel_cdclk_state *a,
1469 const struct intel_cdclk_state *b);
1470 bool intel_cdclk_changed(const struct intel_cdclk_state *a,
1471 const struct intel_cdclk_state *b);
1472 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1473 const struct intel_cdclk_state *cdclk_state);
1474 void intel_dump_cdclk_state(const struct intel_cdclk_state *cdclk_state,
1475 const char *context);
1476
1477 /* intel_display.c */
1478 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1479 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1480 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1481 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1482 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1483 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1484 const char *name, u32 reg, int ref_freq);
1485 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1486 const char *name, u32 reg);
1487 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1488 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1489 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1490 unsigned int intel_fb_xy_to_linear(int x, int y,
1491 const struct intel_plane_state *state,
1492 int plane);
1493 void intel_add_fb_offsets(int *x, int *y,
1494 const struct intel_plane_state *state, int plane);
1495 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1496 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1497 void intel_mark_busy(struct drm_i915_private *dev_priv);
1498 void intel_mark_idle(struct drm_i915_private *dev_priv);
1499 int intel_display_suspend(struct drm_device *dev);
1500 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1501 void intel_encoder_destroy(struct drm_encoder *encoder);
1502 int intel_connector_init(struct intel_connector *);
1503 struct intel_connector *intel_connector_alloc(void);
1504 void intel_connector_free(struct intel_connector *connector);
1505 bool intel_connector_get_hw_state(struct intel_connector *connector);
1506 void intel_connector_attach_encoder(struct intel_connector *connector,
1507 struct intel_encoder *encoder);
1508 struct drm_display_mode *
1509 intel_encoder_current_mode(struct intel_encoder *encoder);
1510 bool intel_port_is_tc(struct drm_i915_private *dev_priv, enum port port);
1511 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv,
1512 enum port port);
1513
1514 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1515 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
1516 struct drm_file *file_priv);
1517 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1518 enum pipe pipe);
1519 static inline bool
intel_crtc_has_type(const struct intel_crtc_state * crtc_state,enum intel_output_type type)1520 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1521 enum intel_output_type type)
1522 {
1523 return crtc_state->output_types & (1 << type);
1524 }
1525 static inline bool
intel_crtc_has_dp_encoder(const struct intel_crtc_state * crtc_state)1526 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1527 {
1528 return crtc_state->output_types &
1529 ((1 << INTEL_OUTPUT_DP) |
1530 (1 << INTEL_OUTPUT_DP_MST) |
1531 (1 << INTEL_OUTPUT_EDP));
1532 }
1533 static inline void
intel_wait_for_vblank(struct drm_i915_private * dev_priv,enum pipe pipe)1534 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1535 {
1536 drm_wait_one_vblank(&dev_priv->drm, pipe);
1537 }
1538 static inline void
intel_wait_for_vblank_if_active(struct drm_i915_private * dev_priv,int pipe)1539 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1540 {
1541 const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1542
1543 if (crtc->active)
1544 intel_wait_for_vblank(dev_priv, pipe);
1545 }
1546
1547 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1548
1549 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1550 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1551 struct intel_digital_port *dport,
1552 unsigned int expected_mask);
1553 int intel_get_load_detect_pipe(struct drm_connector *connector,
1554 const struct drm_display_mode *mode,
1555 struct intel_load_detect_pipe *old,
1556 struct drm_modeset_acquire_ctx *ctx);
1557 void intel_release_load_detect_pipe(struct drm_connector *connector,
1558 struct intel_load_detect_pipe *old,
1559 struct drm_modeset_acquire_ctx *ctx);
1560 struct i915_vma *
1561 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
1562 unsigned int rotation,
1563 bool uses_fence,
1564 unsigned long *out_flags);
1565 void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
1566 struct drm_framebuffer *
1567 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1568 struct drm_mode_fb_cmd2 *mode_cmd);
1569 int intel_prepare_plane_fb(struct drm_plane *plane,
1570 struct drm_plane_state *new_state);
1571 void intel_cleanup_plane_fb(struct drm_plane *plane,
1572 struct drm_plane_state *old_state);
1573 int intel_plane_atomic_get_property(struct drm_plane *plane,
1574 const struct drm_plane_state *state,
1575 struct drm_property *property,
1576 uint64_t *val);
1577 int intel_plane_atomic_set_property(struct drm_plane *plane,
1578 struct drm_plane_state *state,
1579 struct drm_property *property,
1580 uint64_t val);
1581 int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
1582 struct drm_crtc_state *crtc_state,
1583 const struct intel_plane_state *old_plane_state,
1584 struct drm_plane_state *plane_state);
1585
1586 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1587 enum pipe pipe);
1588
1589 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1590 const struct dpll *dpll);
1591 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1592 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1593
1594 /* modesetting asserts */
1595 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1596 enum pipe pipe);
1597 void assert_pll(struct drm_i915_private *dev_priv,
1598 enum pipe pipe, bool state);
1599 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1600 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1601 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1602 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1603 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1604 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1605 enum pipe pipe, bool state);
1606 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1607 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1608 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1609 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1610 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1611 u32 intel_compute_tile_offset(int *x, int *y,
1612 const struct intel_plane_state *state, int plane);
1613 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1614 void intel_finish_reset(struct drm_i915_private *dev_priv);
1615 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1616 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1617 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1618 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1619 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1620 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1621 unsigned int skl_cdclk_get_vco(unsigned int freq);
1622 void intel_dp_get_m_n(struct intel_crtc *crtc,
1623 struct intel_crtc_state *pipe_config);
1624 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1625 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1626 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1627 struct dpll *best_clock);
1628 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1629
1630 bool intel_crtc_active(struct intel_crtc *crtc);
1631 bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state);
1632 void hsw_enable_ips(const struct intel_crtc_state *crtc_state);
1633 void hsw_disable_ips(const struct intel_crtc_state *crtc_state);
1634 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1635 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1636 struct intel_crtc_state *pipe_config);
1637 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
1638 struct intel_crtc_state *crtc_state);
1639
1640 u16 skl_scaler_calc_phase(int sub, bool chroma_center);
1641 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1642 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
1643 uint32_t pixel_format);
1644
intel_plane_ggtt_offset(const struct intel_plane_state * state)1645 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1646 {
1647 return i915_ggtt_offset(state->vma);
1648 }
1649
1650 u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
1651 const struct intel_plane_state *plane_state);
1652 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1653 const struct intel_plane_state *plane_state);
1654 u32 glk_color_ctl(const struct intel_plane_state *plane_state);
1655 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1656 unsigned int rotation);
1657 int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
1658 struct intel_plane_state *plane_state);
1659 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1660 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
1661
1662 /* intel_csr.c */
1663 void intel_csr_ucode_init(struct drm_i915_private *);
1664 void intel_csr_load_program(struct drm_i915_private *);
1665 void intel_csr_ucode_fini(struct drm_i915_private *);
1666 void intel_csr_ucode_suspend(struct drm_i915_private *);
1667 void intel_csr_ucode_resume(struct drm_i915_private *);
1668
1669 /* intel_dp.c */
1670 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
1671 i915_reg_t dp_reg, enum port port,
1672 enum pipe *pipe);
1673 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1674 enum port port);
1675 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1676 struct intel_connector *intel_connector);
1677 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1678 int link_rate, uint8_t lane_count,
1679 bool link_mst);
1680 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1681 int link_rate, uint8_t lane_count);
1682 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1683 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1684 int intel_dp_retrain_link(struct intel_encoder *encoder,
1685 struct drm_modeset_acquire_ctx *ctx);
1686 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1687 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1688 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1689 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1690 bool intel_dp_compute_config(struct intel_encoder *encoder,
1691 struct intel_crtc_state *pipe_config,
1692 struct drm_connector_state *conn_state);
1693 bool intel_dp_is_edp(struct intel_dp *intel_dp);
1694 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
1695 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1696 bool long_hpd);
1697 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1698 const struct drm_connector_state *conn_state);
1699 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1700 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1701 void intel_edp_panel_on(struct intel_dp *intel_dp);
1702 void intel_edp_panel_off(struct intel_dp *intel_dp);
1703 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
1704 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
1705 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1706 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1707 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1708 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1709 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1710 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1711 void intel_plane_destroy(struct drm_plane *plane);
1712 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1713 const struct intel_crtc_state *crtc_state);
1714 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1715 const struct intel_crtc_state *crtc_state);
1716 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1717 unsigned int frontbuffer_bits);
1718 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1719 unsigned int frontbuffer_bits);
1720
1721 void
1722 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1723 uint8_t dp_train_pat);
1724 void
1725 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1726 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1727 uint8_t
1728 intel_dp_voltage_max(struct intel_dp *intel_dp);
1729 uint8_t
1730 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1731 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1732 uint8_t *link_bw, uint8_t *rate_select);
1733 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1734 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
1735 bool
1736 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1737
intel_dp_unused_lane_mask(int lane_count)1738 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1739 {
1740 return ~((1 << lane_count) - 1) & 0xf;
1741 }
1742
1743 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1744 int intel_dp_link_required(int pixel_clock, int bpp);
1745 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1746 bool intel_digital_port_connected(struct intel_encoder *encoder);
1747
1748 /* intel_dp_aux_backlight.c */
1749 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1750
1751 /* intel_dp_mst.c */
1752 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1753 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1754 /* vlv_dsi.c */
1755 void vlv_dsi_init(struct drm_i915_private *dev_priv);
1756
1757 /* intel_dsi_dcs_backlight.c */
1758 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1759
1760 /* intel_dvo.c */
1761 void intel_dvo_init(struct drm_i915_private *dev_priv);
1762 /* intel_hotplug.c */
1763 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1764 bool intel_encoder_hotplug(struct intel_encoder *encoder,
1765 struct intel_connector *connector);
1766
1767 /* legacy fbdev emulation in intel_fbdev.c */
1768 #ifdef CONFIG_DRM_FBDEV_EMULATION
1769 extern int intel_fbdev_init(struct drm_device *dev);
1770 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1771 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1772 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1773 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1774 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1775 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1776 #else
intel_fbdev_init(struct drm_device * dev)1777 static inline int intel_fbdev_init(struct drm_device *dev)
1778 {
1779 return 0;
1780 }
1781
intel_fbdev_initial_config_async(struct drm_device * dev)1782 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1783 {
1784 }
1785
intel_fbdev_unregister(struct drm_i915_private * dev_priv)1786 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1787 {
1788 }
1789
intel_fbdev_fini(struct drm_i915_private * dev_priv)1790 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1791 {
1792 }
1793
intel_fbdev_set_suspend(struct drm_device * dev,int state,bool synchronous)1794 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1795 {
1796 }
1797
intel_fbdev_output_poll_changed(struct drm_device * dev)1798 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1799 {
1800 }
1801
intel_fbdev_restore_mode(struct drm_device * dev)1802 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1803 {
1804 }
1805 #endif
1806
1807 /* intel_fbc.c */
1808 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1809 struct intel_atomic_state *state);
1810 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1811 void intel_fbc_pre_update(struct intel_crtc *crtc,
1812 struct intel_crtc_state *crtc_state,
1813 struct intel_plane_state *plane_state);
1814 void intel_fbc_post_update(struct intel_crtc *crtc);
1815 void intel_fbc_init(struct drm_i915_private *dev_priv);
1816 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1817 void intel_fbc_enable(struct intel_crtc *crtc,
1818 struct intel_crtc_state *crtc_state,
1819 struct intel_plane_state *plane_state);
1820 void intel_fbc_disable(struct intel_crtc *crtc);
1821 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1822 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1823 unsigned int frontbuffer_bits,
1824 enum fb_op_origin origin);
1825 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1826 unsigned int frontbuffer_bits, enum fb_op_origin origin);
1827 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1828 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1829 int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv);
1830
1831 /* intel_hdmi.c */
1832 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1833 enum port port);
1834 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1835 struct intel_connector *intel_connector);
1836 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1837 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1838 struct intel_crtc_state *pipe_config,
1839 struct drm_connector_state *conn_state);
1840 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1841 struct drm_connector *connector,
1842 bool high_tmds_clock_ratio,
1843 bool scrambling);
1844 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1845 void intel_infoframe_init(struct intel_digital_port *intel_dig_port);
1846
1847
1848 /* intel_lvds.c */
1849 bool intel_lvds_port_enabled(struct drm_i915_private *dev_priv,
1850 i915_reg_t lvds_reg, enum pipe *pipe);
1851 void intel_lvds_init(struct drm_i915_private *dev_priv);
1852 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1853 bool intel_is_dual_link_lvds(struct drm_device *dev);
1854
1855
1856 /* intel_modes.c */
1857 int intel_connector_update_modes(struct drm_connector *connector,
1858 struct edid *edid);
1859 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1860 void intel_attach_force_audio_property(struct drm_connector *connector);
1861 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1862 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1863
1864
1865 /* intel_overlay.c */
1866 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1867 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1868 int intel_overlay_switch_off(struct intel_overlay *overlay);
1869 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1870 struct drm_file *file_priv);
1871 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1872 struct drm_file *file_priv);
1873 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1874
1875
1876 /* intel_panel.c */
1877 int intel_panel_init(struct intel_panel *panel,
1878 struct drm_display_mode *fixed_mode,
1879 struct drm_display_mode *downclock_mode);
1880 void intel_panel_fini(struct intel_panel *panel);
1881 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1882 struct drm_display_mode *adjusted_mode);
1883 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1884 struct intel_crtc_state *pipe_config,
1885 int fitting_mode);
1886 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1887 struct intel_crtc_state *pipe_config,
1888 int fitting_mode);
1889 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1890 u32 level, u32 max);
1891 int intel_panel_setup_backlight(struct drm_connector *connector,
1892 enum pipe pipe);
1893 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1894 const struct drm_connector_state *conn_state);
1895 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1896 void intel_panel_destroy_backlight(struct drm_connector *connector);
1897 extern struct drm_display_mode *intel_find_panel_downclock(
1898 struct drm_i915_private *dev_priv,
1899 struct drm_display_mode *fixed_mode,
1900 struct drm_connector *connector);
1901
1902 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1903 int intel_backlight_device_register(struct intel_connector *connector);
1904 void intel_backlight_device_unregister(struct intel_connector *connector);
1905 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
intel_backlight_device_register(struct intel_connector * connector)1906 static inline int intel_backlight_device_register(struct intel_connector *connector)
1907 {
1908 return 0;
1909 }
intel_backlight_device_unregister(struct intel_connector * connector)1910 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1911 {
1912 }
1913 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1914
1915 /* intel_hdcp.c */
1916 void intel_hdcp_atomic_check(struct drm_connector *connector,
1917 struct drm_connector_state *old_state,
1918 struct drm_connector_state *new_state);
1919 int intel_hdcp_init(struct intel_connector *connector,
1920 const struct intel_hdcp_shim *hdcp_shim);
1921 int intel_hdcp_enable(struct intel_connector *connector);
1922 int intel_hdcp_disable(struct intel_connector *connector);
1923 int intel_hdcp_check_link(struct intel_connector *connector);
1924 bool is_hdcp_supported(struct drm_i915_private *dev_priv, enum port port);
1925
1926 /* intel_psr.c */
1927 #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support)
1928 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
1929 void intel_psr_enable(struct intel_dp *intel_dp,
1930 const struct intel_crtc_state *crtc_state);
1931 void intel_psr_disable(struct intel_dp *intel_dp,
1932 const struct intel_crtc_state *old_crtc_state);
1933 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1934 unsigned frontbuffer_bits,
1935 enum fb_op_origin origin);
1936 void intel_psr_flush(struct drm_i915_private *dev_priv,
1937 unsigned frontbuffer_bits,
1938 enum fb_op_origin origin);
1939 void intel_psr_init(struct drm_i915_private *dev_priv);
1940 void intel_psr_compute_config(struct intel_dp *intel_dp,
1941 struct intel_crtc_state *crtc_state);
1942 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
1943 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
1944 void intel_psr_short_pulse(struct intel_dp *intel_dp);
1945 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
1946
1947 /* intel_runtime_pm.c */
1948 int intel_power_domains_init(struct drm_i915_private *);
1949 void intel_power_domains_fini(struct drm_i915_private *);
1950 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1951 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1952 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1953 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1954 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1955 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1956 const char *
1957 intel_display_power_domain_str(enum intel_display_power_domain domain);
1958
1959 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1960 enum intel_display_power_domain domain);
1961 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1962 enum intel_display_power_domain domain);
1963 void intel_display_power_get(struct drm_i915_private *dev_priv,
1964 enum intel_display_power_domain domain);
1965 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1966 enum intel_display_power_domain domain);
1967 void intel_display_power_put(struct drm_i915_private *dev_priv,
1968 enum intel_display_power_domain domain);
1969 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
1970 u8 req_slices);
1971
1972 static inline void
assert_rpm_device_not_suspended(struct drm_i915_private * dev_priv)1973 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1974 {
1975 WARN_ONCE(dev_priv->runtime_pm.suspended,
1976 "Device suspended during HW access\n");
1977 }
1978
1979 static inline void
assert_rpm_wakelock_held(struct drm_i915_private * dev_priv)1980 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1981 {
1982 assert_rpm_device_not_suspended(dev_priv);
1983 WARN_ONCE(!atomic_read(&dev_priv->runtime_pm.wakeref_count),
1984 "RPM wakelock ref not held during HW access");
1985 }
1986
1987 /**
1988 * disable_rpm_wakeref_asserts - disable the RPM assert checks
1989 * @dev_priv: i915 device instance
1990 *
1991 * This function disable asserts that check if we hold an RPM wakelock
1992 * reference, while keeping the device-not-suspended checks still enabled.
1993 * It's meant to be used only in special circumstances where our rule about
1994 * the wakelock refcount wrt. the device power state doesn't hold. According
1995 * to this rule at any point where we access the HW or want to keep the HW in
1996 * an active state we must hold an RPM wakelock reference acquired via one of
1997 * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1998 * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1999 * forcewake release timer, and the GPU RPS and hangcheck works. All other
2000 * users should avoid using this function.
2001 *
2002 * Any calls to this function must have a symmetric call to
2003 * enable_rpm_wakeref_asserts().
2004 */
2005 static inline void
disable_rpm_wakeref_asserts(struct drm_i915_private * dev_priv)2006 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2007 {
2008 atomic_inc(&dev_priv->runtime_pm.wakeref_count);
2009 }
2010
2011 /**
2012 * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
2013 * @dev_priv: i915 device instance
2014 *
2015 * This function re-enables the RPM assert checks after disabling them with
2016 * disable_rpm_wakeref_asserts. It's meant to be used only in special
2017 * circumstances otherwise its use should be avoided.
2018 *
2019 * Any calls to this function must have a symmetric call to
2020 * disable_rpm_wakeref_asserts().
2021 */
2022 static inline void
enable_rpm_wakeref_asserts(struct drm_i915_private * dev_priv)2023 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
2024 {
2025 atomic_dec(&dev_priv->runtime_pm.wakeref_count);
2026 }
2027
2028 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
2029 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
2030 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
2031 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
2032
2033 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
2034
2035 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
2036 bool override, unsigned int mask);
2037 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
2038 enum dpio_channel ch, bool override);
2039
2040
2041 /* intel_pm.c */
2042 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
2043 void intel_suspend_hw(struct drm_i915_private *dev_priv);
2044 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
2045 void intel_update_watermarks(struct intel_crtc *crtc);
2046 void intel_init_pm(struct drm_i915_private *dev_priv);
2047 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
2048 void intel_pm_setup(struct drm_i915_private *dev_priv);
2049 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
2050 void intel_gpu_ips_teardown(void);
2051 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
2052 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
2053 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
2054 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
2055 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
2056 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
2057 void gen6_rps_busy(struct drm_i915_private *dev_priv);
2058 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
2059 void gen6_rps_idle(struct drm_i915_private *dev_priv);
2060 void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *rps);
2061 void g4x_wm_get_hw_state(struct drm_device *dev);
2062 void vlv_wm_get_hw_state(struct drm_device *dev);
2063 void ilk_wm_get_hw_state(struct drm_device *dev);
2064 void skl_wm_get_hw_state(struct drm_device *dev);
2065 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2066 struct skl_ddb_allocation *ddb /* out */);
2067 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
2068 struct skl_pipe_wm *out);
2069 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
2070 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
2071 bool intel_can_enable_sagv(struct drm_atomic_state *state);
2072 int intel_enable_sagv(struct drm_i915_private *dev_priv);
2073 int intel_disable_sagv(struct drm_i915_private *dev_priv);
2074 bool skl_wm_level_equals(const struct skl_wm_level *l1,
2075 const struct skl_wm_level *l2);
2076 bool skl_ddb_allocation_overlaps(struct drm_i915_private *dev_priv,
2077 const struct skl_ddb_entry **entries,
2078 const struct skl_ddb_entry *ddb,
2079 int ignore);
2080 bool ilk_disable_lp_wm(struct drm_device *dev);
2081 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
2082 struct intel_crtc_state *cstate);
2083 void intel_init_ipc(struct drm_i915_private *dev_priv);
2084 void intel_enable_ipc(struct drm_i915_private *dev_priv);
2085
2086 /* intel_sdvo.c */
2087 bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
2088 i915_reg_t sdvo_reg, enum pipe *pipe);
2089 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
2090 i915_reg_t reg, enum port port);
2091
2092
2093 /* intel_sprite.c */
2094 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
2095 int usecs);
2096 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
2097 enum pipe pipe, int plane);
2098 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
2099 struct drm_file *file_priv);
2100 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state);
2101 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state);
2102 void skl_update_plane(struct intel_plane *plane,
2103 const struct intel_crtc_state *crtc_state,
2104 const struct intel_plane_state *plane_state);
2105 void skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc);
2106 bool skl_plane_get_hw_state(struct intel_plane *plane, enum pipe *pipe);
2107 bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
2108 enum pipe pipe, enum plane_id plane_id);
2109 bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
2110 enum pipe pipe, enum plane_id plane_id);
2111
2112 /* intel_tv.c */
2113 void intel_tv_init(struct drm_i915_private *dev_priv);
2114
2115 /* intel_atomic.c */
2116 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
2117 const struct drm_connector_state *state,
2118 struct drm_property *property,
2119 uint64_t *val);
2120 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
2121 struct drm_connector_state *state,
2122 struct drm_property *property,
2123 uint64_t val);
2124 int intel_digital_connector_atomic_check(struct drm_connector *conn,
2125 struct drm_connector_state *new_state);
2126 struct drm_connector_state *
2127 intel_digital_connector_duplicate_state(struct drm_connector *connector);
2128
2129 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
2130 void intel_crtc_destroy_state(struct drm_crtc *crtc,
2131 struct drm_crtc_state *state);
2132 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
2133 void intel_atomic_state_clear(struct drm_atomic_state *);
2134
2135 static inline struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state * state,struct intel_crtc * crtc)2136 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
2137 struct intel_crtc *crtc)
2138 {
2139 struct drm_crtc_state *crtc_state;
2140 crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
2141 if (IS_ERR(crtc_state))
2142 return ERR_CAST(crtc_state);
2143
2144 return to_intel_crtc_state(crtc_state);
2145 }
2146
2147 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
2148 struct intel_crtc *intel_crtc,
2149 struct intel_crtc_state *crtc_state);
2150
2151 /* intel_atomic_plane.c */
2152 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
2153 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
2154 void intel_plane_destroy_state(struct drm_plane *plane,
2155 struct drm_plane_state *state);
2156 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
2157 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
2158 struct intel_crtc_state *crtc_state,
2159 const struct intel_plane_state *old_plane_state,
2160 struct intel_plane_state *intel_state);
2161
2162 /* intel_color.c */
2163 void intel_color_init(struct drm_crtc *crtc);
2164 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
2165 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
2166 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
2167
2168 /* intel_lspcon.c */
2169 bool lspcon_init(struct intel_digital_port *intel_dig_port);
2170 void lspcon_resume(struct intel_lspcon *lspcon);
2171 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
2172
2173 /* intel_pipe_crc.c */
2174 #ifdef CONFIG_DEBUG_FS
2175 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
2176 size_t *values_cnt);
2177 void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc);
2178 void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc);
2179 #else
2180 #define intel_crtc_set_crc_source NULL
intel_crtc_disable_pipe_crc(struct intel_crtc * crtc)2181 static inline void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc)
2182 {
2183 }
2184
intel_crtc_enable_pipe_crc(struct intel_crtc * crtc)2185 static inline void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc)
2186 {
2187 }
2188 #endif
2189 #endif /* __INTEL_DRV_H__ */
2190
