1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Hantro G1 post-processor support
4 *
5 * Copyright (C) 2019 Collabora, Ltd.
6 */
7
8 #include <linux/dma-mapping.h>
9 #include <linux/types.h>
10
11 #include "hantro.h"
12 #include "hantro_hw.h"
13 #include "hantro_g1_regs.h"
14
15 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \
16 { \
17 hantro_reg_write(vpu, \
18 &(vpu)->variant->postproc_regs->reg_name, \
19 val); \
20 }
21
22 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \
23 { \
24 hantro_reg_write_s(vpu, \
25 &(vpu)->variant->postproc_regs->reg_name, \
26 val); \
27 }
28
29 #define VPU_PP_IN_YUYV 0x0
30 #define VPU_PP_IN_NV12 0x1
31 #define VPU_PP_IN_YUV420 0x2
32 #define VPU_PP_IN_YUV240_TILED 0x5
33 #define VPU_PP_OUT_RGB 0x0
34 #define VPU_PP_OUT_YUYV 0x3
35
36 const struct hantro_postproc_regs hantro_g1_postproc_regs = {
37 .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1},
38 .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f},
39 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1},
40 .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1},
41 .out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1},
42 .out_luma_base = {G1_REG_PP_OUT_LUMA_BASE, 0, 0xffffffff},
43 .input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff},
44 .input_height = {G1_REG_PP_INPUT_SIZE, 9, 0x1ff},
45 .output_width = {G1_REG_PP_CONTROL, 4, 0x7ff},
46 .output_height = {G1_REG_PP_CONTROL, 15, 0x7ff},
47 .input_fmt = {G1_REG_PP_CONTROL, 29, 0x7},
48 .output_fmt = {G1_REG_PP_CONTROL, 26, 0x7},
49 .orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff},
50 .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff},
51 };
52
hantro_needs_postproc(const struct hantro_ctx * ctx,const struct hantro_fmt * fmt)53 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
54 const struct hantro_fmt *fmt)
55 {
56 struct hantro_dev *vpu = ctx->dev;
57
58 if (ctx->is_encoder)
59 return false;
60
61 if (!vpu->variant->postproc_fmts)
62 return false;
63
64 return fmt->fourcc != V4L2_PIX_FMT_NV12;
65 }
66
hantro_postproc_enable(struct hantro_ctx * ctx)67 void hantro_postproc_enable(struct hantro_ctx *ctx)
68 {
69 struct hantro_dev *vpu = ctx->dev;
70 struct vb2_v4l2_buffer *dst_buf;
71 u32 src_pp_fmt, dst_pp_fmt;
72 dma_addr_t dst_dma;
73
74 if (!vpu->variant->postproc_regs)
75 return;
76
77 /* Turn on pipeline mode. Must be done first. */
78 HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1);
79
80 src_pp_fmt = VPU_PP_IN_NV12;
81
82 switch (ctx->vpu_dst_fmt->fourcc) {
83 case V4L2_PIX_FMT_YUYV:
84 dst_pp_fmt = VPU_PP_OUT_YUYV;
85 break;
86 default:
87 WARN(1, "output format %d not supported by the post-processor, this wasn't expected.",
88 ctx->vpu_dst_fmt->fourcc);
89 dst_pp_fmt = 0;
90 break;
91 }
92
93 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
94 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
95
96 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1);
97 HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1);
98 HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1);
99 HANTRO_PP_REG_WRITE(vpu, max_burst, 16);
100 HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma);
101 HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width));
102 HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height));
103 HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt);
104 HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt);
105 HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width);
106 HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height);
107 HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width));
108 HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width);
109 }
110
hantro_postproc_free(struct hantro_ctx * ctx)111 void hantro_postproc_free(struct hantro_ctx *ctx)
112 {
113 struct hantro_dev *vpu = ctx->dev;
114 unsigned int i;
115
116 for (i = 0; i < VB2_MAX_FRAME; ++i) {
117 struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
118
119 if (priv->cpu) {
120 dma_free_attrs(vpu->dev, priv->size, priv->cpu,
121 priv->dma, priv->attrs);
122 priv->cpu = NULL;
123 }
124 }
125 }
126
hantro_postproc_alloc(struct hantro_ctx * ctx)127 int hantro_postproc_alloc(struct hantro_ctx *ctx)
128 {
129 struct hantro_dev *vpu = ctx->dev;
130 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
131 struct vb2_queue *cap_queue = &m2m_ctx->cap_q_ctx.q;
132 unsigned int num_buffers = cap_queue->num_buffers;
133 unsigned int i, buf_size;
134
135 buf_size = ctx->dst_fmt.plane_fmt[0].sizeimage +
136 hantro_h264_mv_size(ctx->dst_fmt.width,
137 ctx->dst_fmt.height);
138
139 for (i = 0; i < num_buffers; ++i) {
140 struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i];
141
142 /*
143 * The buffers on this queue are meant as intermediate
144 * buffers for the decoder, so no mapping is needed.
145 */
146 priv->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
147 priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma,
148 GFP_KERNEL, priv->attrs);
149 if (!priv->cpu)
150 return -ENOMEM;
151 priv->size = buf_size;
152 }
153 return 0;
154 }
155
hantro_postproc_disable(struct hantro_ctx * ctx)156 void hantro_postproc_disable(struct hantro_ctx *ctx)
157 {
158 struct hantro_dev *vpu = ctx->dev;
159
160 if (!vpu->variant->postproc_regs)
161 return;
162
163 HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0);
164 }
165
