1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #ifndef MLX5_DRIVER_H
34 #define MLX5_DRIVER_H
35
36 #include <linux/kernel.h>
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/irq.h>
40 #include <linux/spinlock_types.h>
41 #include <linux/semaphore.h>
42 #include <linux/slab.h>
43 #include <linux/vmalloc.h>
44 #include <linux/xarray.h>
45 #include <linux/workqueue.h>
46 #include <linux/mempool.h>
47 #include <linux/interrupt.h>
48 #include <linux/idr.h>
49 #include <linux/notifier.h>
50 #include <linux/refcount.h>
51 #include <linux/auxiliary_bus.h>
52
53 #include <linux/mlx5/device.h>
54 #include <linux/mlx5/doorbell.h>
55 #include <linux/mlx5/eq.h>
56 #include <linux/timecounter.h>
57 #include <linux/ptp_clock_kernel.h>
58 #include <net/devlink.h>
59
60 #define MLX5_ADEV_NAME "mlx5_core"
61
62 #define MLX5_IRQ_EQ_CTRL (U8_MAX)
63
64 enum {
65 MLX5_BOARD_ID_LEN = 64,
66 };
67
68 enum {
69 MLX5_CMD_WQ_MAX_NAME = 32,
70 };
71
72 enum {
73 CMD_OWNER_SW = 0x0,
74 CMD_OWNER_HW = 0x1,
75 CMD_STATUS_SUCCESS = 0,
76 };
77
78 enum mlx5_sqp_t {
79 MLX5_SQP_SMI = 0,
80 MLX5_SQP_GSI = 1,
81 MLX5_SQP_IEEE_1588 = 2,
82 MLX5_SQP_SNIFFER = 3,
83 MLX5_SQP_SYNC_UMR = 4,
84 };
85
86 enum {
87 MLX5_MAX_PORTS = 4,
88 };
89
90 enum {
91 MLX5_ATOMIC_MODE_OFFSET = 16,
92 MLX5_ATOMIC_MODE_IB_COMP = 1,
93 MLX5_ATOMIC_MODE_CX = 2,
94 MLX5_ATOMIC_MODE_8B = 3,
95 MLX5_ATOMIC_MODE_16B = 4,
96 MLX5_ATOMIC_MODE_32B = 5,
97 MLX5_ATOMIC_MODE_64B = 6,
98 MLX5_ATOMIC_MODE_128B = 7,
99 MLX5_ATOMIC_MODE_256B = 8,
100 };
101
102 enum {
103 MLX5_REG_QPTS = 0x4002,
104 MLX5_REG_QETCR = 0x4005,
105 MLX5_REG_QTCT = 0x400a,
106 MLX5_REG_QPDPM = 0x4013,
107 MLX5_REG_QCAM = 0x4019,
108 MLX5_REG_DCBX_PARAM = 0x4020,
109 MLX5_REG_DCBX_APP = 0x4021,
110 MLX5_REG_FPGA_CAP = 0x4022,
111 MLX5_REG_FPGA_CTRL = 0x4023,
112 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
113 MLX5_REG_CORE_DUMP = 0x402e,
114 MLX5_REG_PCAP = 0x5001,
115 MLX5_REG_PMTU = 0x5003,
116 MLX5_REG_PTYS = 0x5004,
117 MLX5_REG_PAOS = 0x5006,
118 MLX5_REG_PFCC = 0x5007,
119 MLX5_REG_PPCNT = 0x5008,
120 MLX5_REG_PPTB = 0x500b,
121 MLX5_REG_PBMC = 0x500c,
122 MLX5_REG_PMAOS = 0x5012,
123 MLX5_REG_PUDE = 0x5009,
124 MLX5_REG_PMPE = 0x5010,
125 MLX5_REG_PELC = 0x500e,
126 MLX5_REG_PVLC = 0x500f,
127 MLX5_REG_PCMR = 0x5041,
128 MLX5_REG_PDDR = 0x5031,
129 MLX5_REG_PMLP = 0x5002,
130 MLX5_REG_PPLM = 0x5023,
131 MLX5_REG_PCAM = 0x507f,
132 MLX5_REG_NODE_DESC = 0x6001,
133 MLX5_REG_HOST_ENDIANNESS = 0x7004,
134 MLX5_REG_MCIA = 0x9014,
135 MLX5_REG_MFRL = 0x9028,
136 MLX5_REG_MLCR = 0x902b,
137 MLX5_REG_MRTC = 0x902d,
138 MLX5_REG_MTRC_CAP = 0x9040,
139 MLX5_REG_MTRC_CONF = 0x9041,
140 MLX5_REG_MTRC_STDB = 0x9042,
141 MLX5_REG_MTRC_CTRL = 0x9043,
142 MLX5_REG_MPEIN = 0x9050,
143 MLX5_REG_MPCNT = 0x9051,
144 MLX5_REG_MTPPS = 0x9053,
145 MLX5_REG_MTPPSE = 0x9054,
146 MLX5_REG_MTUTC = 0x9055,
147 MLX5_REG_MPEGC = 0x9056,
148 MLX5_REG_MCQS = 0x9060,
149 MLX5_REG_MCQI = 0x9061,
150 MLX5_REG_MCC = 0x9062,
151 MLX5_REG_MCDA = 0x9063,
152 MLX5_REG_MCAM = 0x907f,
153 MLX5_REG_MIRC = 0x9162,
154 MLX5_REG_SBCAM = 0xB01F,
155 MLX5_REG_RESOURCE_DUMP = 0xC000,
156 MLX5_REG_DTOR = 0xC00E,
157 };
158
159 enum mlx5_qpts_trust_state {
160 MLX5_QPTS_TRUST_PCP = 1,
161 MLX5_QPTS_TRUST_DSCP = 2,
162 };
163
164 enum mlx5_dcbx_oper_mode {
165 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
166 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
167 };
168
169 enum {
170 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
171 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
172 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
173 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
174 };
175
176 enum mlx5_page_fault_resume_flags {
177 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
178 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
179 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
180 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
181 };
182
183 enum dbg_rsc_type {
184 MLX5_DBG_RSC_QP,
185 MLX5_DBG_RSC_EQ,
186 MLX5_DBG_RSC_CQ,
187 };
188
189 enum port_state_policy {
190 MLX5_POLICY_DOWN = 0,
191 MLX5_POLICY_UP = 1,
192 MLX5_POLICY_FOLLOW = 2,
193 MLX5_POLICY_INVALID = 0xffffffff
194 };
195
196 enum mlx5_coredev_type {
197 MLX5_COREDEV_PF,
198 MLX5_COREDEV_VF,
199 MLX5_COREDEV_SF,
200 };
201
202 struct mlx5_field_desc {
203 int i;
204 };
205
206 struct mlx5_rsc_debug {
207 struct mlx5_core_dev *dev;
208 void *object;
209 enum dbg_rsc_type type;
210 struct dentry *root;
211 struct mlx5_field_desc fields[];
212 };
213
214 enum mlx5_dev_event {
215 MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */
216 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
217 };
218
219 enum mlx5_port_status {
220 MLX5_PORT_UP = 1,
221 MLX5_PORT_DOWN = 2,
222 };
223
224 enum mlx5_cmdif_state {
225 MLX5_CMDIF_STATE_UNINITIALIZED,
226 MLX5_CMDIF_STATE_UP,
227 MLX5_CMDIF_STATE_DOWN,
228 };
229
230 struct mlx5_cmd_first {
231 __be32 data[4];
232 };
233
234 struct mlx5_cmd_msg {
235 struct list_head list;
236 struct cmd_msg_cache *parent;
237 u32 len;
238 struct mlx5_cmd_first first;
239 struct mlx5_cmd_mailbox *next;
240 };
241
242 struct mlx5_cmd_debug {
243 struct dentry *dbg_root;
244 void *in_msg;
245 void *out_msg;
246 u8 status;
247 u16 inlen;
248 u16 outlen;
249 };
250
251 struct cmd_msg_cache {
252 /* protect block chain allocations
253 */
254 spinlock_t lock;
255 struct list_head head;
256 unsigned int max_inbox_size;
257 unsigned int num_ent;
258 };
259
260 enum {
261 MLX5_NUM_COMMAND_CACHES = 5,
262 };
263
264 struct mlx5_cmd_stats {
265 u64 sum;
266 u64 n;
267 /* number of times command failed */
268 u64 failed;
269 /* number of times command failed on bad status returned by FW */
270 u64 failed_mbox_status;
271 /* last command failed returned errno */
272 u32 last_failed_errno;
273 /* last bad status returned by FW */
274 u8 last_failed_mbox_status;
275 /* last command failed syndrome returned by FW */
276 u32 last_failed_syndrome;
277 struct dentry *root;
278 /* protect command average calculations */
279 spinlock_t lock;
280 };
281
282 struct mlx5_cmd {
283 struct mlx5_nb nb;
284
285 enum mlx5_cmdif_state state;
286 void *cmd_alloc_buf;
287 dma_addr_t alloc_dma;
288 int alloc_size;
289 void *cmd_buf;
290 dma_addr_t dma;
291 u16 cmdif_rev;
292 u8 log_sz;
293 u8 log_stride;
294 int max_reg_cmds;
295 int events;
296 u32 __iomem *vector;
297
298 /* protect command queue allocations
299 */
300 spinlock_t alloc_lock;
301
302 /* protect token allocations
303 */
304 spinlock_t token_lock;
305 u8 token;
306 unsigned long bitmask;
307 char wq_name[MLX5_CMD_WQ_MAX_NAME];
308 struct workqueue_struct *wq;
309 struct semaphore sem;
310 struct semaphore pages_sem;
311 int mode;
312 u16 allowed_opcode;
313 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
314 struct dma_pool *pool;
315 struct mlx5_cmd_debug dbg;
316 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
317 int checksum_disabled;
318 struct mlx5_cmd_stats *stats;
319 };
320
321 struct mlx5_cmd_mailbox {
322 void *buf;
323 dma_addr_t dma;
324 struct mlx5_cmd_mailbox *next;
325 };
326
327 struct mlx5_buf_list {
328 void *buf;
329 dma_addr_t map;
330 };
331
332 struct mlx5_frag_buf {
333 struct mlx5_buf_list *frags;
334 int npages;
335 int size;
336 u8 page_shift;
337 };
338
339 struct mlx5_frag_buf_ctrl {
340 struct mlx5_buf_list *frags;
341 u32 sz_m1;
342 u16 frag_sz_m1;
343 u16 strides_offset;
344 u8 log_sz;
345 u8 log_stride;
346 u8 log_frag_strides;
347 };
348
349 struct mlx5_core_psv {
350 u32 psv_idx;
351 struct psv_layout {
352 u32 pd;
353 u16 syndrome;
354 u16 reserved;
355 u16 bg;
356 u16 app_tag;
357 u32 ref_tag;
358 } psv;
359 };
360
361 struct mlx5_core_sig_ctx {
362 struct mlx5_core_psv psv_memory;
363 struct mlx5_core_psv psv_wire;
364 struct ib_sig_err err_item;
365 bool sig_status_checked;
366 bool sig_err_exists;
367 u32 sigerr_count;
368 };
369
370 #define MLX5_24BIT_MASK ((1 << 24) - 1)
371
372 enum mlx5_res_type {
373 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
374 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
375 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
376 MLX5_RES_SRQ = 3,
377 MLX5_RES_XSRQ = 4,
378 MLX5_RES_XRQ = 5,
379 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
380 };
381
382 struct mlx5_core_rsc_common {
383 enum mlx5_res_type res;
384 refcount_t refcount;
385 struct completion free;
386 };
387
388 struct mlx5_uars_page {
389 void __iomem *map;
390 bool wc;
391 u32 index;
392 struct list_head list;
393 unsigned int bfregs;
394 unsigned long *reg_bitmap; /* for non fast path bf regs */
395 unsigned long *fp_bitmap;
396 unsigned int reg_avail;
397 unsigned int fp_avail;
398 struct kref ref_count;
399 struct mlx5_core_dev *mdev;
400 };
401
402 struct mlx5_bfreg_head {
403 /* protect blue flame registers allocations */
404 struct mutex lock;
405 struct list_head list;
406 };
407
408 struct mlx5_bfreg_data {
409 struct mlx5_bfreg_head reg_head;
410 struct mlx5_bfreg_head wc_head;
411 };
412
413 struct mlx5_sq_bfreg {
414 void __iomem *map;
415 struct mlx5_uars_page *up;
416 bool wc;
417 u32 index;
418 unsigned int offset;
419 };
420
421 struct mlx5_core_health {
422 struct health_buffer __iomem *health;
423 __be32 __iomem *health_counter;
424 struct timer_list timer;
425 u32 prev;
426 int miss_counter;
427 u8 synd;
428 u32 fatal_error;
429 u32 crdump_size;
430 /* wq spinlock to synchronize draining */
431 spinlock_t wq_lock;
432 struct workqueue_struct *wq;
433 unsigned long flags;
434 struct work_struct fatal_report_work;
435 struct work_struct report_work;
436 struct devlink_health_reporter *fw_reporter;
437 struct devlink_health_reporter *fw_fatal_reporter;
438 struct delayed_work update_fw_log_ts_work;
439 };
440
441 struct mlx5_qp_table {
442 struct notifier_block nb;
443
444 /* protect radix tree
445 */
446 spinlock_t lock;
447 struct radix_tree_root tree;
448 };
449
450 enum {
451 MLX5_PF_NOTIFY_DISABLE_VF,
452 MLX5_PF_NOTIFY_ENABLE_VF,
453 };
454
455 struct mlx5_vf_context {
456 int enabled;
457 u64 port_guid;
458 u64 node_guid;
459 /* Valid bits are used to validate administrative guid only.
460 * Enabled after ndo_set_vf_guid
461 */
462 u8 port_guid_valid:1;
463 u8 node_guid_valid:1;
464 enum port_state_policy policy;
465 struct blocking_notifier_head notifier;
466 };
467
468 struct mlx5_core_sriov {
469 struct mlx5_vf_context *vfs_ctx;
470 int num_vfs;
471 u16 max_vfs;
472 };
473
474 struct mlx5_fc_pool {
475 struct mlx5_core_dev *dev;
476 struct mutex pool_lock; /* protects pool lists */
477 struct list_head fully_used;
478 struct list_head partially_used;
479 struct list_head unused;
480 int available_fcs;
481 int used_fcs;
482 int threshold;
483 };
484
485 struct mlx5_fc_stats {
486 spinlock_t counters_idr_lock; /* protects counters_idr */
487 struct idr counters_idr;
488 struct list_head counters;
489 struct llist_head addlist;
490 struct llist_head dellist;
491
492 struct workqueue_struct *wq;
493 struct delayed_work work;
494 unsigned long next_query;
495 unsigned long sampling_interval; /* jiffies */
496 u32 *bulk_query_out;
497 int bulk_query_len;
498 size_t num_counters;
499 bool bulk_query_alloc_failed;
500 unsigned long next_bulk_query_alloc;
501 struct mlx5_fc_pool fc_pool;
502 };
503
504 struct mlx5_events;
505 struct mlx5_mpfs;
506 struct mlx5_eswitch;
507 struct mlx5_lag;
508 struct mlx5_devcom;
509 struct mlx5_fw_reset;
510 struct mlx5_eq_table;
511 struct mlx5_irq_table;
512 struct mlx5_vhca_state_notifier;
513 struct mlx5_sf_dev_table;
514 struct mlx5_sf_hw_table;
515 struct mlx5_sf_table;
516
517 struct mlx5_rate_limit {
518 u32 rate;
519 u32 max_burst_sz;
520 u16 typical_pkt_sz;
521 };
522
523 struct mlx5_rl_entry {
524 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
525 u64 refcount;
526 u16 index;
527 u16 uid;
528 u8 dedicated : 1;
529 };
530
531 struct mlx5_rl_table {
532 /* protect rate limit table */
533 struct mutex rl_lock;
534 u16 max_size;
535 u32 max_rate;
536 u32 min_rate;
537 struct mlx5_rl_entry *rl_entry;
538 u64 refcount;
539 };
540
541 struct mlx5_core_roce {
542 struct mlx5_flow_table *ft;
543 struct mlx5_flow_group *fg;
544 struct mlx5_flow_handle *allow_rule;
545 };
546
547 enum {
548 MLX5_PRIV_FLAGS_DISABLE_IB_ADEV = 1 << 0,
549 MLX5_PRIV_FLAGS_DISABLE_ALL_ADEV = 1 << 1,
550 /* Set during device detach to block any further devices
551 * creation/deletion on drivers rescan. Unset during device attach.
552 */
553 MLX5_PRIV_FLAGS_DETACH = 1 << 2,
554 /* Distinguish between mlx5e_probe/remove called by module init/cleanup
555 * and called by other flows which can already hold devlink lock
556 */
557 MLX5_PRIV_FLAGS_MLX5E_LOCKED_FLOW = 1 << 3,
558 };
559
560 struct mlx5_adev {
561 struct auxiliary_device adev;
562 struct mlx5_core_dev *mdev;
563 int idx;
564 };
565
566 struct mlx5_debugfs_entries {
567 struct dentry *dbg_root;
568 struct dentry *qp_debugfs;
569 struct dentry *eq_debugfs;
570 struct dentry *cq_debugfs;
571 struct dentry *cmdif_debugfs;
572 struct dentry *pages_debugfs;
573 struct dentry *lag_debugfs;
574 };
575
576 struct mlx5_ft_pool;
577 struct mlx5_priv {
578 /* IRQ table valid only for real pci devices PF or VF */
579 struct mlx5_irq_table *irq_table;
580 struct mlx5_eq_table *eq_table;
581
582 /* pages stuff */
583 struct mlx5_nb pg_nb;
584 struct workqueue_struct *pg_wq;
585 struct xarray page_root_xa;
586 u32 fw_pages;
587 atomic_t reg_pages;
588 struct list_head free_list;
589 u32 vfs_pages;
590 u32 host_pf_pages;
591 u32 fw_pages_alloc_failed;
592 u32 give_pages_dropped;
593 u32 reclaim_pages_discard;
594
595 struct mlx5_core_health health;
596 struct list_head traps;
597
598 struct mlx5_debugfs_entries dbg;
599
600 /* start: alloc staff */
601 /* protect buffer allocation according to numa node */
602 struct mutex alloc_mutex;
603 int numa_node;
604
605 struct mutex pgdir_mutex;
606 struct list_head pgdir_list;
607 /* end: alloc staff */
608
609 struct list_head ctx_list;
610 spinlock_t ctx_lock;
611 struct mlx5_adev **adev;
612 int adev_idx;
613 int sw_vhca_id;
614 struct mlx5_events *events;
615
616 struct mlx5_flow_steering *steering;
617 struct mlx5_mpfs *mpfs;
618 struct mlx5_eswitch *eswitch;
619 struct mlx5_core_sriov sriov;
620 struct mlx5_lag *lag;
621 u32 flags;
622 struct mlx5_devcom *devcom;
623 struct mlx5_fw_reset *fw_reset;
624 struct mlx5_core_roce roce;
625 struct mlx5_fc_stats fc_stats;
626 struct mlx5_rl_table rl_table;
627 struct mlx5_ft_pool *ft_pool;
628
629 struct mlx5_bfreg_data bfregs;
630 struct mlx5_uars_page *uar;
631 #ifdef CONFIG_MLX5_SF
632 struct mlx5_vhca_state_notifier *vhca_state_notifier;
633 struct mlx5_sf_dev_table *sf_dev_table;
634 struct mlx5_core_dev *parent_mdev;
635 #endif
636 #ifdef CONFIG_MLX5_SF_MANAGER
637 struct mlx5_sf_hw_table *sf_hw_table;
638 struct mlx5_sf_table *sf_table;
639 #endif
640 };
641
642 enum mlx5_device_state {
643 MLX5_DEVICE_STATE_UP = 1,
644 MLX5_DEVICE_STATE_INTERNAL_ERROR,
645 };
646
647 enum mlx5_interface_state {
648 MLX5_INTERFACE_STATE_UP = BIT(0),
649 MLX5_BREAK_FW_WAIT = BIT(1),
650 };
651
652 enum mlx5_pci_status {
653 MLX5_PCI_STATUS_DISABLED,
654 MLX5_PCI_STATUS_ENABLED,
655 };
656
657 enum mlx5_pagefault_type_flags {
658 MLX5_PFAULT_REQUESTOR = 1 << 0,
659 MLX5_PFAULT_WRITE = 1 << 1,
660 MLX5_PFAULT_RDMA = 1 << 2,
661 };
662
663 struct mlx5_td {
664 /* protects tirs list changes while tirs refresh */
665 struct mutex list_lock;
666 struct list_head tirs_list;
667 u32 tdn;
668 };
669
670 struct mlx5e_resources {
671 struct mlx5e_hw_objs {
672 u32 pdn;
673 struct mlx5_td td;
674 u32 mkey;
675 struct mlx5_sq_bfreg bfreg;
676 } hw_objs;
677 struct devlink_port dl_port;
678 struct net_device *uplink_netdev;
679 };
680
681 enum mlx5_sw_icm_type {
682 MLX5_SW_ICM_TYPE_STEERING,
683 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
684 MLX5_SW_ICM_TYPE_HEADER_MODIFY_PATTERN,
685 };
686
687 #define MLX5_MAX_RESERVED_GIDS 8
688
689 struct mlx5_rsvd_gids {
690 unsigned int start;
691 unsigned int count;
692 struct ida ida;
693 };
694
695 #define MAX_PIN_NUM 8
696 struct mlx5_pps {
697 u8 pin_caps[MAX_PIN_NUM];
698 struct work_struct out_work;
699 u64 start[MAX_PIN_NUM];
700 u8 enabled;
701 u64 min_npps_period;
702 u64 min_out_pulse_duration_ns;
703 };
704
705 struct mlx5_timer {
706 struct cyclecounter cycles;
707 struct timecounter tc;
708 u32 nominal_c_mult;
709 unsigned long overflow_period;
710 struct delayed_work overflow_work;
711 };
712
713 struct mlx5_clock {
714 struct mlx5_nb pps_nb;
715 seqlock_t lock;
716 struct hwtstamp_config hwtstamp_config;
717 struct ptp_clock *ptp;
718 struct ptp_clock_info ptp_info;
719 struct mlx5_pps pps_info;
720 struct mlx5_timer timer;
721 };
722
723 struct mlx5_dm;
724 struct mlx5_fw_tracer;
725 struct mlx5_vxlan;
726 struct mlx5_geneve;
727 struct mlx5_hv_vhca;
728
729 #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
730 #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
731
732 enum {
733 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
734 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
735 };
736
737 enum {
738 MKEY_CACHE_LAST_STD_ENTRY = 20,
739 MLX5_IMR_MTT_CACHE_ENTRY,
740 MLX5_IMR_KSM_CACHE_ENTRY,
741 MAX_MKEY_CACHE_ENTRIES
742 };
743
744 struct mlx5_profile {
745 u64 mask;
746 u8 log_max_qp;
747 struct {
748 int size;
749 int limit;
750 } mr_cache[MAX_MKEY_CACHE_ENTRIES];
751 };
752
753 struct mlx5_hca_cap {
754 u32 cur[MLX5_UN_SZ_DW(hca_cap_union)];
755 u32 max[MLX5_UN_SZ_DW(hca_cap_union)];
756 };
757
758 struct mlx5_core_dev {
759 struct device *device;
760 enum mlx5_coredev_type coredev_type;
761 struct pci_dev *pdev;
762 /* sync pci state */
763 struct mutex pci_status_mutex;
764 enum mlx5_pci_status pci_status;
765 u8 rev_id;
766 char board_id[MLX5_BOARD_ID_LEN];
767 struct mlx5_cmd cmd;
768 struct {
769 struct mlx5_hca_cap *hca[MLX5_CAP_NUM];
770 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
771 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
772 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
773 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
774 u8 embedded_cpu;
775 } caps;
776 struct mlx5_timeouts *timeouts;
777 u64 sys_image_guid;
778 phys_addr_t iseg_base;
779 struct mlx5_init_seg __iomem *iseg;
780 phys_addr_t bar_addr;
781 enum mlx5_device_state state;
782 /* sync interface state */
783 struct mutex intf_state_mutex;
784 struct lock_class_key lock_key;
785 unsigned long intf_state;
786 struct mlx5_priv priv;
787 struct mlx5_profile profile;
788 u32 issi;
789 struct mlx5e_resources mlx5e_res;
790 struct mlx5_dm *dm;
791 struct mlx5_vxlan *vxlan;
792 struct mlx5_geneve *geneve;
793 struct {
794 struct mlx5_rsvd_gids reserved_gids;
795 u32 roce_en;
796 } roce;
797 #ifdef CONFIG_MLX5_FPGA
798 struct mlx5_fpga_device *fpga;
799 #endif
800 struct mlx5_clock clock;
801 struct mlx5_ib_clock_info *clock_info;
802 struct mlx5_fw_tracer *tracer;
803 struct mlx5_rsc_dump *rsc_dump;
804 u32 vsc_addr;
805 struct mlx5_hv_vhca *hv_vhca;
806 };
807
808 struct mlx5_db {
809 __be32 *db;
810 union {
811 struct mlx5_db_pgdir *pgdir;
812 struct mlx5_ib_user_db_page *user_page;
813 } u;
814 dma_addr_t dma;
815 int index;
816 };
817
818 enum {
819 MLX5_COMP_EQ_SIZE = 1024,
820 };
821
822 enum {
823 MLX5_PTYS_IB = 1 << 0,
824 MLX5_PTYS_EN = 1 << 2,
825 };
826
827 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
828
829 enum {
830 MLX5_CMD_ENT_STATE_PENDING_COMP,
831 };
832
833 struct mlx5_cmd_work_ent {
834 unsigned long state;
835 struct mlx5_cmd_msg *in;
836 struct mlx5_cmd_msg *out;
837 void *uout;
838 int uout_size;
839 mlx5_cmd_cbk_t callback;
840 struct delayed_work cb_timeout_work;
841 void *context;
842 int idx;
843 struct completion handling;
844 struct completion done;
845 struct mlx5_cmd *cmd;
846 struct work_struct work;
847 struct mlx5_cmd_layout *lay;
848 int ret;
849 int page_queue;
850 u8 status;
851 u8 token;
852 u64 ts1;
853 u64 ts2;
854 u16 op;
855 bool polling;
856 /* Track the max comp handlers */
857 refcount_t refcnt;
858 };
859
860 enum phy_port_state {
861 MLX5_AAA_111
862 };
863
864 struct mlx5_hca_vport_context {
865 u32 field_select;
866 bool sm_virt_aware;
867 bool has_smi;
868 bool has_raw;
869 enum port_state_policy policy;
870 enum phy_port_state phys_state;
871 enum ib_port_state vport_state;
872 u8 port_physical_state;
873 u64 sys_image_guid;
874 u64 port_guid;
875 u64 node_guid;
876 u32 cap_mask1;
877 u32 cap_mask1_perm;
878 u16 cap_mask2;
879 u16 cap_mask2_perm;
880 u16 lid;
881 u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */
882 u8 lmc;
883 u8 subnet_timeout;
884 u16 sm_lid;
885 u8 sm_sl;
886 u16 qkey_violation_counter;
887 u16 pkey_violation_counter;
888 bool grh_required;
889 };
890
891 #define STRUCT_FIELD(header, field) \
892 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
893 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
894
895 extern struct dentry *mlx5_debugfs_root;
896
fw_rev_maj(struct mlx5_core_dev * dev)897 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
898 {
899 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
900 }
901
fw_rev_min(struct mlx5_core_dev * dev)902 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
903 {
904 return ioread32be(&dev->iseg->fw_rev) >> 16;
905 }
906
fw_rev_sub(struct mlx5_core_dev * dev)907 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
908 {
909 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
910 }
911
mlx5_base_mkey(const u32 key)912 static inline u32 mlx5_base_mkey(const u32 key)
913 {
914 return key & 0xffffff00u;
915 }
916
wq_get_byte_sz(u8 log_sz,u8 log_stride)917 static inline u32 wq_get_byte_sz(u8 log_sz, u8 log_stride)
918 {
919 return ((u32)1 << log_sz) << log_stride;
920 }
921
mlx5_init_fbc_offset(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,u16 strides_offset,struct mlx5_frag_buf_ctrl * fbc)922 static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
923 u8 log_stride, u8 log_sz,
924 u16 strides_offset,
925 struct mlx5_frag_buf_ctrl *fbc)
926 {
927 fbc->frags = frags;
928 fbc->log_stride = log_stride;
929 fbc->log_sz = log_sz;
930 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
931 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
932 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
933 fbc->strides_offset = strides_offset;
934 }
935
mlx5_init_fbc(struct mlx5_buf_list * frags,u8 log_stride,u8 log_sz,struct mlx5_frag_buf_ctrl * fbc)936 static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
937 u8 log_stride, u8 log_sz,
938 struct mlx5_frag_buf_ctrl *fbc)
939 {
940 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
941 }
942
mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl * fbc,u32 ix)943 static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
944 u32 ix)
945 {
946 unsigned int frag;
947
948 ix += fbc->strides_offset;
949 frag = ix >> fbc->log_frag_strides;
950
951 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
952 }
953
954 static inline u32
mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl * fbc,u32 ix)955 mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
956 {
957 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
958
959 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
960 }
961
962 enum {
963 CMD_ALLOWED_OPCODE_ALL,
964 };
965
966 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
967 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
968 void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
969
970 struct mlx5_async_ctx {
971 struct mlx5_core_dev *dev;
972 atomic_t num_inflight;
973 struct completion inflight_done;
974 };
975
976 struct mlx5_async_work;
977
978 typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
979
980 struct mlx5_async_work {
981 struct mlx5_async_ctx *ctx;
982 mlx5_async_cbk_t user_callback;
983 u16 opcode; /* cmd opcode */
984 u16 op_mod; /* cmd op_mod */
985 void *out; /* pointer to the cmd output buffer */
986 };
987
988 void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
989 struct mlx5_async_ctx *ctx);
990 void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
991 int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
992 void *out, int out_size, mlx5_async_cbk_t callback,
993 struct mlx5_async_work *work);
994 void mlx5_cmd_out_err(struct mlx5_core_dev *dev, u16 opcode, u16 op_mod, void *out);
995 int mlx5_cmd_do(struct mlx5_core_dev *dev, void *in, int in_size, void *out, int out_size);
996 int mlx5_cmd_check(struct mlx5_core_dev *dev, int err, void *in, void *out);
997 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
998 int out_size);
999
1000 #define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
1001 ({ \
1002 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
1003 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
1004 })
1005
1006 #define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
1007 ({ \
1008 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
1009 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
1010 })
1011
1012 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1013 void *out, int out_size);
1014 bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
1015
1016 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
1017 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
1018 int mlx5_health_init(struct mlx5_core_dev *dev);
1019 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
1020 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
1021 void mlx5_start_health_fw_log_up(struct mlx5_core_dev *dev);
1022 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
1023 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
1024 int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
1025 struct mlx5_frag_buf *buf, int node);
1026 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
1027 struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1028 gfp_t flags, int npages);
1029 void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
1030 struct mlx5_cmd_mailbox *head);
1031 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, u32 *mkey, u32 *in,
1032 int inlen);
1033 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, u32 mkey);
1034 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, u32 mkey, u32 *out,
1035 int outlen);
1036 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
1037 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1038 int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1039 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1040 void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1041 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1042 void mlx5_pages_debugfs_init(struct mlx5_core_dev *dev);
1043 void mlx5_pages_debugfs_cleanup(struct mlx5_core_dev *dev);
1044 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1045 s32 npages, bool ec_function);
1046 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1047 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1048 void mlx5_register_debugfs(void);
1049 void mlx5_unregister_debugfs(void);
1050
1051 void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
1052 void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
1053 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn);
1054 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1055 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1056
1057 struct dentry *mlx5_debugfs_get_dev_root(struct mlx5_core_dev *dev);
1058 void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1059 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1060 int mlx5_access_reg(struct mlx5_core_dev *dev, void *data_in, int size_in,
1061 void *data_out, int size_out, u16 reg_id, int arg,
1062 int write, bool verbose);
1063 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1064 int size_in, void *data_out, int size_out,
1065 u16 reg_num, int arg, int write);
1066
1067 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1068 int node);
1069
mlx5_db_alloc(struct mlx5_core_dev * dev,struct mlx5_db * db)1070 static inline int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db)
1071 {
1072 return mlx5_db_alloc_node(dev, db, dev->priv.numa_node);
1073 }
1074
1075 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1076
1077 const char *mlx5_command_str(int command);
1078 void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1079 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1080 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1081 int npsvs, u32 *sig_index);
1082 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1083 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1084 int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1085 struct mlx5_odp_caps *odp_caps);
1086
1087 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1088 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1089 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1090 struct mlx5_rate_limit *rl);
1091 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1092 bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1093 int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1094 bool dedicated_entry, u16 *index);
1095 void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1096 bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1097 struct mlx5_rate_limit *rl_1);
1098 int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1099 bool map_wc, bool fast_path);
1100 void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1101
1102 unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1103 struct cpumask *
1104 mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1105 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1106 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1107 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1108 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1109
mlx5_mkey_to_idx(u32 mkey)1110 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1111 {
1112 return mkey >> 8;
1113 }
1114
mlx5_idx_to_mkey(u32 mkey_idx)1115 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1116 {
1117 return mkey_idx << 8;
1118 }
1119
mlx5_mkey_variant(u32 mkey)1120 static inline u8 mlx5_mkey_variant(u32 mkey)
1121 {
1122 return mkey & 0xff;
1123 }
1124
1125 /* Async-atomic event notifier used by mlx5 core to forward FW
1126 * evetns received from event queue to mlx5 consumers.
1127 * Optimise event queue dipatching.
1128 */
1129 int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1130 int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1131
1132 /* Async-atomic event notifier used for forwarding
1133 * evetns from the event queue into the to mlx5 events dispatcher,
1134 * eswitch, clock and others.
1135 */
1136 int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1137 int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1138
1139 /* Blocking event notifier used to forward SW events, used for slow path */
1140 int mlx5_blocking_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1141 int mlx5_blocking_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1142 int mlx5_blocking_notifier_call_chain(struct mlx5_core_dev *dev, unsigned int event,
1143 void *data);
1144
1145 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1146
1147 int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1148 int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1149 bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1150 bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1151 bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1152 bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev);
1153 bool mlx5_lag_is_master(struct mlx5_core_dev *dev);
1154 bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev);
1155 struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1156 u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1157 struct net_device *slave);
1158 int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1159 u64 *values,
1160 int num_counters,
1161 size_t *offsets);
1162 struct mlx5_core_dev *mlx5_lag_get_peer_mdev(struct mlx5_core_dev *dev);
1163 u8 mlx5_lag_get_num_ports(struct mlx5_core_dev *dev);
1164 struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1165 void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1166 int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1167 u64 length, u32 log_alignment, u16 uid,
1168 phys_addr_t *addr, u32 *obj_id);
1169 int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1170 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1171
1172 struct mlx5_core_dev *mlx5_vf_get_core_dev(struct pci_dev *pdev);
1173 void mlx5_vf_put_core_dev(struct mlx5_core_dev *mdev);
1174
1175 int mlx5_sriov_blocking_notifier_register(struct mlx5_core_dev *mdev,
1176 int vf_id,
1177 struct notifier_block *nb);
1178 void mlx5_sriov_blocking_notifier_unregister(struct mlx5_core_dev *mdev,
1179 int vf_id,
1180 struct notifier_block *nb);
1181 #ifdef CONFIG_MLX5_CORE_IPOIB
1182 struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1183 struct ib_device *ibdev,
1184 const char *name,
1185 void (*setup)(struct net_device *));
1186 #endif /* CONFIG_MLX5_CORE_IPOIB */
1187 int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1188 struct ib_device *device,
1189 struct rdma_netdev_alloc_params *params);
1190
1191 enum {
1192 MLX5_PCI_DEV_IS_VF = 1 << 0,
1193 };
1194
mlx5_core_is_pf(const struct mlx5_core_dev * dev)1195 static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1196 {
1197 return dev->coredev_type == MLX5_COREDEV_PF;
1198 }
1199
mlx5_core_is_vf(const struct mlx5_core_dev * dev)1200 static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1201 {
1202 return dev->coredev_type == MLX5_COREDEV_VF;
1203 }
1204
mlx5_core_is_ecpf(const struct mlx5_core_dev * dev)1205 static inline bool mlx5_core_is_ecpf(const struct mlx5_core_dev *dev)
1206 {
1207 return dev->caps.embedded_cpu;
1208 }
1209
1210 static inline bool
mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev * dev)1211 mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1212 {
1213 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1214 }
1215
mlx5_ecpf_vport_exists(const struct mlx5_core_dev * dev)1216 static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1217 {
1218 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1219 }
1220
mlx5_core_max_vfs(const struct mlx5_core_dev * dev)1221 static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1222 {
1223 return dev->priv.sriov.max_vfs;
1224 }
1225
mlx5_get_gid_table_len(u16 param)1226 static inline int mlx5_get_gid_table_len(u16 param)
1227 {
1228 if (param > 4) {
1229 pr_warn("gid table length is zero\n");
1230 return 0;
1231 }
1232
1233 return 8 * (1 << param);
1234 }
1235
mlx5_rl_is_supported(struct mlx5_core_dev * dev)1236 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1237 {
1238 return !!(dev->priv.rl_table.max_size);
1239 }
1240
mlx5_core_is_mp_slave(struct mlx5_core_dev * dev)1241 static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1242 {
1243 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1244 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1245 }
1246
mlx5_core_is_mp_master(struct mlx5_core_dev * dev)1247 static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1248 {
1249 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1250 }
1251
mlx5_core_mp_enabled(struct mlx5_core_dev * dev)1252 static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1253 {
1254 return mlx5_core_is_mp_slave(dev) ||
1255 mlx5_core_is_mp_master(dev);
1256 }
1257
mlx5_core_native_port_num(struct mlx5_core_dev * dev)1258 static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1259 {
1260 if (!mlx5_core_mp_enabled(dev))
1261 return 1;
1262
1263 return MLX5_CAP_GEN(dev, native_port_num);
1264 }
1265
mlx5_get_dev_index(struct mlx5_core_dev * dev)1266 static inline int mlx5_get_dev_index(struct mlx5_core_dev *dev)
1267 {
1268 int idx = MLX5_CAP_GEN(dev, native_port_num);
1269
1270 if (idx >= 1 && idx <= MLX5_MAX_PORTS)
1271 return idx - 1;
1272 else
1273 return PCI_FUNC(dev->pdev->devfn);
1274 }
1275
1276 enum {
1277 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1278 };
1279
1280 bool mlx5_is_roce_on(struct mlx5_core_dev *dev);
1281
mlx5_get_roce_state(struct mlx5_core_dev * dev)1282 static inline bool mlx5_get_roce_state(struct mlx5_core_dev *dev)
1283 {
1284 if (MLX5_CAP_GEN(dev, roce_rw_supported))
1285 return MLX5_CAP_GEN(dev, roce);
1286
1287 /* If RoCE cap is read-only in FW, get RoCE state from devlink
1288 * in order to support RoCE enable/disable feature
1289 */
1290 return mlx5_is_roce_on(dev);
1291 }
1292
1293 enum {
1294 MLX5_OCTWORD = 16,
1295 };
1296
1297 #endif /* MLX5_DRIVER_H */
1298
