1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #ifndef ATH11K_HW_H
7 #define ATH11K_HW_H
8
9 #include "wmi.h"
10
11 /* Target configuration defines */
12
13 /* Num VDEVS per radio */
14 #define TARGET_NUM_VDEVS (16 + 1)
15
16 #define TARGET_NUM_PEERS_PDEV (512 + TARGET_NUM_VDEVS)
17
18 /* Num of peers for Single Radio mode */
19 #define TARGET_NUM_PEERS_SINGLE (TARGET_NUM_PEERS_PDEV)
20
21 /* Num of peers for DBS */
22 #define TARGET_NUM_PEERS_DBS (2 * TARGET_NUM_PEERS_PDEV)
23
24 /* Num of peers for DBS_SBS */
25 #define TARGET_NUM_PEERS_DBS_SBS (3 * TARGET_NUM_PEERS_PDEV)
26
27 /* Max num of stations (per radio) */
28 #define TARGET_NUM_STATIONS 512
29
30 #define TARGET_NUM_PEERS(x) TARGET_NUM_PEERS_##x
31 #define TARGET_NUM_PEER_KEYS 2
32 #define TARGET_NUM_TIDS(x) (2 * TARGET_NUM_PEERS(x) + \
33 4 * TARGET_NUM_VDEVS + 8)
34
35 #define TARGET_AST_SKID_LIMIT 16
36 #define TARGET_NUM_OFFLD_PEERS 4
37 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4
38
39 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
40 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4))
41 #define TARGET_RX_TIMEOUT_LO_PRI 100
42 #define TARGET_RX_TIMEOUT_HI_PRI 40
43
44 #define TARGET_DECAP_MODE_RAW 0
45 #define TARGET_DECAP_MODE_NATIVE_WIFI 1
46 #define TARGET_DECAP_MODE_ETH 2
47
48 #define TARGET_SCAN_MAX_PENDING_REQS 4
49 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
50 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
51 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
52 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3
53 #define TARGET_NUM_MCAST_GROUPS 12
54 #define TARGET_NUM_MCAST_TABLE_ELEMS 64
55 #define TARGET_MCAST2UCAST_MODE 2
56 #define TARGET_TX_DBG_LOG_SIZE 1024
57 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
58 #define TARGET_VOW_CONFIG 0
59 #define TARGET_NUM_MSDU_DESC (2500)
60 #define TARGET_MAX_FRAG_ENTRIES 6
61 #define TARGET_MAX_BCN_OFFLD 16
62 #define TARGET_NUM_WDS_ENTRIES 32
63 #define TARGET_DMA_BURST_SIZE 1
64 #define TARGET_RX_BATCHMODE 1
65
66 #define ATH11K_HW_MAX_QUEUES 4
67 #define ATH11K_QUEUE_LEN 4096
68
69 #define ATH11k_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4
70
71 #define ATH11K_FW_DIR "ath11k"
72
73 #define ATH11K_BOARD_MAGIC "QCA-ATH11K-BOARD"
74 #define ATH11K_BOARD_API2_FILE "board-2.bin"
75 #define ATH11K_DEFAULT_BOARD_FILE "board.bin"
76 #define ATH11K_DEFAULT_CAL_FILE "caldata.bin"
77 #define ATH11K_AMSS_FILE "amss.bin"
78 #define ATH11K_M3_FILE "m3.bin"
79
80 enum ath11k_hw_rate_cck {
81 ATH11K_HW_RATE_CCK_LP_11M = 0,
82 ATH11K_HW_RATE_CCK_LP_5_5M,
83 ATH11K_HW_RATE_CCK_LP_2M,
84 ATH11K_HW_RATE_CCK_LP_1M,
85 ATH11K_HW_RATE_CCK_SP_11M,
86 ATH11K_HW_RATE_CCK_SP_5_5M,
87 ATH11K_HW_RATE_CCK_SP_2M,
88 };
89
90 enum ath11k_hw_rate_ofdm {
91 ATH11K_HW_RATE_OFDM_48M = 0,
92 ATH11K_HW_RATE_OFDM_24M,
93 ATH11K_HW_RATE_OFDM_12M,
94 ATH11K_HW_RATE_OFDM_6M,
95 ATH11K_HW_RATE_OFDM_54M,
96 ATH11K_HW_RATE_OFDM_36M,
97 ATH11K_HW_RATE_OFDM_18M,
98 ATH11K_HW_RATE_OFDM_9M,
99 };
100
101 enum ath11k_bus {
102 ATH11K_BUS_AHB,
103 ATH11K_BUS_PCI,
104 };
105
106 #define ATH11K_EXT_IRQ_GRP_NUM_MAX 11
107
108 struct ath11k_hw_ring_mask {
109 u8 tx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
110 u8 rx_mon_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
111 u8 rx[ATH11K_EXT_IRQ_GRP_NUM_MAX];
112 u8 rx_err[ATH11K_EXT_IRQ_GRP_NUM_MAX];
113 u8 rx_wbm_rel[ATH11K_EXT_IRQ_GRP_NUM_MAX];
114 u8 reo_status[ATH11K_EXT_IRQ_GRP_NUM_MAX];
115 u8 rxdma2host[ATH11K_EXT_IRQ_GRP_NUM_MAX];
116 u8 host2rxdma[ATH11K_EXT_IRQ_GRP_NUM_MAX];
117 };
118
119 struct ath11k_hw_params {
120 const char *name;
121 u16 hw_rev;
122 u8 max_radios;
123 u32 bdf_addr;
124
125 struct {
126 const char *dir;
127 size_t board_size;
128 size_t cal_size;
129 } fw;
130
131 const struct ath11k_hw_ops *hw_ops;
132 const struct ath11k_hw_ring_mask *ring_mask;
133
134 bool internal_sleep_clock;
135
136 const struct ath11k_hw_regs *regs;
137 const struct ce_attr *host_ce_config;
138 u32 ce_count;
139 const struct ce_pipe_config *target_ce_config;
140 u32 target_ce_count;
141 const struct service_to_pipe *svc_to_ce_map;
142 u32 svc_to_ce_map_len;
143
144 bool single_pdev_only;
145
146 /* For example on QCA6390 struct
147 * wmi_init_cmd_param::band_to_mac_config needs to be false as the
148 * firmware creates the mapping.
149 */
150 bool needs_band_to_mac;
151
152 bool rxdma1_enable;
153 int num_rxmda_per_pdev;
154 bool rx_mac_buf_ring;
155 bool vdev_start_delay;
156 bool htt_peer_map_v2;
157 bool tcl_0_only;
158 u8 spectral_fft_sz;
159
160 u16 interface_modes;
161 bool supports_monitor;
162 bool supports_shadow_regs;
163 bool idle_ps;
164 };
165
166 struct ath11k_hw_ops {
167 u8 (*get_hw_mac_from_pdev_id)(int pdev_id);
168 void (*wmi_init_config)(struct ath11k_base *ab,
169 struct target_resource_config *config);
170 int (*mac_id_to_pdev_id)(struct ath11k_hw_params *hw, int mac_id);
171 int (*mac_id_to_srng_id)(struct ath11k_hw_params *hw, int mac_id);
172 };
173
174 extern const struct ath11k_hw_ops ipq8074_ops;
175 extern const struct ath11k_hw_ops ipq6018_ops;
176 extern const struct ath11k_hw_ops qca6390_ops;
177
178 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074;
179 extern const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390;
180
181 static inline
ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params * hw,int pdev_idx)182 int ath11k_hw_get_mac_from_pdev_id(struct ath11k_hw_params *hw,
183 int pdev_idx)
184 {
185 if (hw->hw_ops->get_hw_mac_from_pdev_id)
186 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx);
187
188 return 0;
189 }
190
ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params * hw,int mac_id)191 static inline int ath11k_hw_mac_id_to_pdev_id(struct ath11k_hw_params *hw,
192 int mac_id)
193 {
194 if (hw->hw_ops->mac_id_to_pdev_id)
195 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id);
196
197 return 0;
198 }
199
ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params * hw,int mac_id)200 static inline int ath11k_hw_mac_id_to_srng_id(struct ath11k_hw_params *hw,
201 int mac_id)
202 {
203 if (hw->hw_ops->mac_id_to_srng_id)
204 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id);
205
206 return 0;
207 }
208
209 struct ath11k_fw_ie {
210 __le32 id;
211 __le32 len;
212 u8 data[];
213 };
214
215 enum ath11k_bd_ie_board_type {
216 ATH11K_BD_IE_BOARD_NAME = 0,
217 ATH11K_BD_IE_BOARD_DATA = 1,
218 };
219
220 enum ath11k_bd_ie_type {
221 /* contains sub IEs of enum ath11k_bd_ie_board_type */
222 ATH11K_BD_IE_BOARD = 0,
223 ATH11K_BD_IE_BOARD_EXT = 1,
224 };
225
226 struct ath11k_hw_regs {
227 u32 hal_tcl1_ring_base_lsb;
228 u32 hal_tcl1_ring_base_msb;
229 u32 hal_tcl1_ring_id;
230 u32 hal_tcl1_ring_misc;
231 u32 hal_tcl1_ring_tp_addr_lsb;
232 u32 hal_tcl1_ring_tp_addr_msb;
233 u32 hal_tcl1_ring_consumer_int_setup_ix0;
234 u32 hal_tcl1_ring_consumer_int_setup_ix1;
235 u32 hal_tcl1_ring_msi1_base_lsb;
236 u32 hal_tcl1_ring_msi1_base_msb;
237 u32 hal_tcl1_ring_msi1_data;
238 u32 hal_tcl2_ring_base_lsb;
239 u32 hal_tcl_ring_base_lsb;
240
241 u32 hal_tcl_status_ring_base_lsb;
242
243 u32 hal_reo1_ring_base_lsb;
244 u32 hal_reo1_ring_base_msb;
245 u32 hal_reo1_ring_id;
246 u32 hal_reo1_ring_misc;
247 u32 hal_reo1_ring_hp_addr_lsb;
248 u32 hal_reo1_ring_hp_addr_msb;
249 u32 hal_reo1_ring_producer_int_setup;
250 u32 hal_reo1_ring_msi1_base_lsb;
251 u32 hal_reo1_ring_msi1_base_msb;
252 u32 hal_reo1_ring_msi1_data;
253 u32 hal_reo2_ring_base_lsb;
254 u32 hal_reo1_aging_thresh_ix_0;
255 u32 hal_reo1_aging_thresh_ix_1;
256 u32 hal_reo1_aging_thresh_ix_2;
257 u32 hal_reo1_aging_thresh_ix_3;
258
259 u32 hal_reo1_ring_hp;
260 u32 hal_reo1_ring_tp;
261 u32 hal_reo2_ring_hp;
262
263 u32 hal_reo_tcl_ring_base_lsb;
264 u32 hal_reo_tcl_ring_hp;
265
266 u32 hal_reo_status_ring_base_lsb;
267 u32 hal_reo_status_hp;
268 };
269
270 extern const struct ath11k_hw_regs ipq8074_regs;
271 extern const struct ath11k_hw_regs qca6390_regs;
272
273 #endif
274
