1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "changk104.h"
23 #include "cgrp.h"
24
25 #include <core/client.h>
26 #include <core/gpuobj.h>
27
28 #include <nvif/cla06f.h>
29 #include <nvif/unpack.h>
30
31 static int
gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan * chan,bool ce,bool valid)32 gv100_fifo_gpfifo_engine_valid(struct gk104_fifo_chan *chan, bool ce, bool valid)
33 {
34 struct nvkm_subdev *subdev = &chan->base.fifo->engine.subdev;
35 struct nvkm_device *device = subdev->device;
36 const u32 mask = ce ? 0x00020000 : 0x00010000;
37 const u32 data = valid ? mask : 0x00000000;
38 int ret;
39
40 /* Block runlist to prevent the channel from being rescheduled. */
41 mutex_lock(&subdev->mutex);
42 nvkm_mask(device, 0x002630, BIT(chan->runl), BIT(chan->runl));
43
44 /* Preempt the channel. */
45 ret = gk104_fifo_gpfifo_kick_locked(chan);
46 if (ret == 0) {
47 /* Update engine context validity. */
48 nvkm_kmap(chan->base.inst);
49 nvkm_mo32(chan->base.inst, 0x0ac, mask, data);
50 nvkm_done(chan->base.inst);
51 }
52
53 /* Resume runlist. */
54 nvkm_mask(device, 0x002630, BIT(chan->runl), 0);
55 mutex_unlock(&subdev->mutex);
56 return ret;
57 }
58
59 static int
gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,bool suspend)60 gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
61 struct nvkm_engine *engine, bool suspend)
62 {
63 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
64 struct nvkm_gpuobj *inst = chan->base.inst;
65 int ret;
66
67 if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
68 engine->subdev.index <= NVKM_ENGINE_CE_LAST)
69 return gk104_fifo_gpfifo_kick(chan);
70
71 ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
72 if (ret && suspend)
73 return ret;
74
75 nvkm_kmap(inst);
76 nvkm_wo32(inst, 0x0210, 0x00000000);
77 nvkm_wo32(inst, 0x0214, 0x00000000);
78 nvkm_done(inst);
79 return ret;
80 }
81
82 static int
gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)83 gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
84 struct nvkm_engine *engine)
85 {
86 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
87 struct nvkm_gpuobj *inst = chan->base.inst;
88 u64 addr;
89
90 if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
91 engine->subdev.index <= NVKM_ENGINE_CE_LAST)
92 return 0;
93
94 addr = chan->engn[engine->subdev.index].vma->addr;
95 nvkm_kmap(inst);
96 nvkm_wo32(inst, 0x210, lower_32_bits(addr) | 0x00000004);
97 nvkm_wo32(inst, 0x214, upper_32_bits(addr));
98 nvkm_done(inst);
99
100 return gv100_fifo_gpfifo_engine_valid(chan, false, true);
101 }
102
103 const struct nvkm_fifo_chan_func
104 gv100_fifo_gpfifo_func = {
105 .dtor = gk104_fifo_gpfifo_dtor,
106 .init = gk104_fifo_gpfifo_init,
107 .fini = gk104_fifo_gpfifo_fini,
108 .ntfy = gf100_fifo_chan_ntfy,
109 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
110 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
111 .engine_init = gv100_fifo_gpfifo_engine_init,
112 .engine_fini = gv100_fifo_gpfifo_engine_fini,
113 };
114
115 static int
gv100_fifo_gpfifo_new_(struct gk104_fifo * fifo,u64 * runlists,u16 * chid,u64 vmm,u64 ioffset,u64 ilength,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)116 gv100_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
117 u64 vmm, u64 ioffset, u64 ilength,
118 const struct nvkm_oclass *oclass,
119 struct nvkm_object **pobject)
120 {
121 struct gk104_fifo_chan *chan;
122 int runlist = ffs(*runlists) -1, ret, i;
123 unsigned long engm;
124 u64 subdevs = 0;
125 u64 usermem;
126
127 if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
128 return -EINVAL;
129 *runlists = BIT_ULL(runlist);
130
131 engm = fifo->runlist[runlist].engm;
132 for_each_set_bit(i, &engm, fifo->engine_nr) {
133 if (fifo->engine[i].engine)
134 subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
135 }
136
137 /* Allocate the channel. */
138 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
139 return -ENOMEM;
140 *pobject = &chan->base.object;
141 chan->fifo = fifo;
142 chan->runl = runlist;
143 INIT_LIST_HEAD(&chan->head);
144
145 ret = nvkm_fifo_chan_ctor(&gv100_fifo_gpfifo_func, &fifo->base,
146 0x1000, 0x1000, true, vmm, 0, subdevs,
147 1, fifo->user.bar->addr, 0x200,
148 oclass, &chan->base);
149 if (ret)
150 return ret;
151
152 *chid = chan->base.chid;
153
154 /* Hack to support GPUs where even individual channels should be
155 * part of a channel group.
156 */
157 if (fifo->func->cgrp_force) {
158 if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
159 return -ENOMEM;
160 chan->cgrp->id = chan->base.chid;
161 INIT_LIST_HEAD(&chan->cgrp->head);
162 INIT_LIST_HEAD(&chan->cgrp->chan);
163 chan->cgrp->chan_nr = 0;
164 }
165
166 /* Clear channel control registers. */
167 usermem = chan->base.chid * 0x200;
168 ilength = order_base_2(ilength / 8);
169
170 nvkm_kmap(fifo->user.mem);
171 for (i = 0; i < 0x200; i += 4)
172 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
173 nvkm_done(fifo->user.mem);
174 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
175
176 /* RAMFC */
177 nvkm_kmap(chan->base.inst);
178 nvkm_wo32(chan->base.inst, 0x008, lower_32_bits(usermem));
179 nvkm_wo32(chan->base.inst, 0x00c, upper_32_bits(usermem));
180 nvkm_wo32(chan->base.inst, 0x010, 0x0000face);
181 nvkm_wo32(chan->base.inst, 0x030, 0x7ffff902);
182 nvkm_wo32(chan->base.inst, 0x048, lower_32_bits(ioffset));
183 nvkm_wo32(chan->base.inst, 0x04c, upper_32_bits(ioffset) |
184 (ilength << 16));
185 nvkm_wo32(chan->base.inst, 0x084, 0x20400000);
186 nvkm_wo32(chan->base.inst, 0x094, 0x30000001);
187 nvkm_wo32(chan->base.inst, 0x0e4, 0x00000020);
188 nvkm_wo32(chan->base.inst, 0x0e8, chan->base.chid);
189 nvkm_wo32(chan->base.inst, 0x0f4, 0x00001100);
190 nvkm_wo32(chan->base.inst, 0x0f8, 0x10003080);
191 nvkm_mo32(chan->base.inst, 0x218, 0x00000000, 0x00000000);
192 nvkm_wo32(chan->base.inst, 0x220, 0x020a1000);
193 nvkm_wo32(chan->base.inst, 0x224, 0x00000000);
194 nvkm_done(chan->base.inst);
195 return gv100_fifo_gpfifo_engine_valid(chan, true, true);
196 }
197
198 int
gv100_fifo_gpfifo_new(struct gk104_fifo * fifo,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)199 gv100_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass,
200 void *data, u32 size, struct nvkm_object **pobject)
201 {
202 struct nvkm_object *parent = oclass->parent;
203 union {
204 struct kepler_channel_gpfifo_a_v0 v0;
205 } *args = data;
206 int ret = -ENOSYS;
207
208 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
209 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
210 nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
211 "ioffset %016llx ilength %08x "
212 "runlist %016llx\n",
213 args->v0.version, args->v0.vmm, args->v0.ioffset,
214 args->v0.ilength, args->v0.runlist);
215 return gv100_fifo_gpfifo_new_(fifo,
216 &args->v0.runlist,
217 &args->v0.chid,
218 args->v0.vmm,
219 args->v0.ioffset,
220 args->v0.ilength,
221 oclass, pobject);
222 }
223
224 return ret;
225 }
226
