1 /*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 #include "gk104.h"
23 #include "cgrp.h"
24 #include "changk104.h"
25 #include "user.h"
26
27 #include <core/gpuobj.h>
28
29 #include <nvif/class.h>
30
31 void
gv100_fifo_runlist_chan(struct gk104_fifo_chan * chan,struct nvkm_memory * memory,u32 offset)32 gv100_fifo_runlist_chan(struct gk104_fifo_chan *chan,
33 struct nvkm_memory *memory, u32 offset)
34 {
35 struct nvkm_memory *usermem = chan->fifo->user.mem;
36 const u64 user = nvkm_memory_addr(usermem) + (chan->base.chid * 0x200);
37 const u64 inst = chan->base.inst->addr;
38
39 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user));
40 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user));
41 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->base.chid);
42 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst));
43 }
44
45 void
gv100_fifo_runlist_cgrp(struct nvkm_fifo_cgrp * cgrp,struct nvkm_memory * memory,u32 offset)46 gv100_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *cgrp,
47 struct nvkm_memory *memory, u32 offset)
48 {
49 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001);
50 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr);
51 nvkm_wo32(memory, offset + 0x8, cgrp->id);
52 nvkm_wo32(memory, offset + 0xc, 0x00000000);
53 }
54
55 const struct gk104_fifo_runlist_func
56 gv100_fifo_runlist = {
57 .size = 16,
58 .cgrp = gv100_fifo_runlist_cgrp,
59 .chan = gv100_fifo_runlist_chan,
60 .commit = gk104_fifo_runlist_commit,
61 };
62
63 const struct nvkm_enum
64 gv100_fifo_fault_gpcclient[] = {
65 { 0x00, "T1_0" },
66 { 0x01, "T1_1" },
67 { 0x02, "T1_2" },
68 { 0x03, "T1_3" },
69 { 0x04, "T1_4" },
70 { 0x05, "T1_5" },
71 { 0x06, "T1_6" },
72 { 0x07, "T1_7" },
73 { 0x08, "PE_0" },
74 { 0x09, "PE_1" },
75 { 0x0a, "PE_2" },
76 { 0x0b, "PE_3" },
77 { 0x0c, "PE_4" },
78 { 0x0d, "PE_5" },
79 { 0x0e, "PE_6" },
80 { 0x0f, "PE_7" },
81 { 0x10, "RAST" },
82 { 0x11, "GCC" },
83 { 0x12, "GPCCS" },
84 { 0x13, "PROP_0" },
85 { 0x14, "PROP_1" },
86 { 0x15, "PROP_2" },
87 { 0x16, "PROP_3" },
88 { 0x17, "GPM" },
89 { 0x18, "LTP_UTLB_0" },
90 { 0x19, "LTP_UTLB_1" },
91 { 0x1a, "LTP_UTLB_2" },
92 { 0x1b, "LTP_UTLB_3" },
93 { 0x1c, "LTP_UTLB_4" },
94 { 0x1d, "LTP_UTLB_5" },
95 { 0x1e, "LTP_UTLB_6" },
96 { 0x1f, "LTP_UTLB_7" },
97 { 0x20, "RGG_UTLB" },
98 { 0x21, "T1_8" },
99 { 0x22, "T1_9" },
100 { 0x23, "T1_10" },
101 { 0x24, "T1_11" },
102 { 0x25, "T1_12" },
103 { 0x26, "T1_13" },
104 { 0x27, "T1_14" },
105 { 0x28, "T1_15" },
106 { 0x29, "TPCCS_0" },
107 { 0x2a, "TPCCS_1" },
108 { 0x2b, "TPCCS_2" },
109 { 0x2c, "TPCCS_3" },
110 { 0x2d, "TPCCS_4" },
111 { 0x2e, "TPCCS_5" },
112 { 0x2f, "TPCCS_6" },
113 { 0x30, "TPCCS_7" },
114 { 0x31, "PE_8" },
115 { 0x32, "PE_9" },
116 { 0x33, "TPCCS_8" },
117 { 0x34, "TPCCS_9" },
118 { 0x35, "T1_16" },
119 { 0x36, "T1_17" },
120 { 0x37, "T1_18" },
121 { 0x38, "T1_19" },
122 { 0x39, "PE_10" },
123 { 0x3a, "PE_11" },
124 { 0x3b, "TPCCS_10" },
125 { 0x3c, "TPCCS_11" },
126 { 0x3d, "T1_20" },
127 { 0x3e, "T1_21" },
128 { 0x3f, "T1_22" },
129 { 0x40, "T1_23" },
130 { 0x41, "PE_12" },
131 { 0x42, "PE_13" },
132 { 0x43, "TPCCS_12" },
133 { 0x44, "TPCCS_13" },
134 { 0x45, "T1_24" },
135 { 0x46, "T1_25" },
136 { 0x47, "T1_26" },
137 { 0x48, "T1_27" },
138 { 0x49, "PE_14" },
139 { 0x4a, "PE_15" },
140 { 0x4b, "TPCCS_14" },
141 { 0x4c, "TPCCS_15" },
142 { 0x4d, "T1_28" },
143 { 0x4e, "T1_29" },
144 { 0x4f, "T1_30" },
145 { 0x50, "T1_31" },
146 { 0x51, "PE_16" },
147 { 0x52, "PE_17" },
148 { 0x53, "TPCCS_16" },
149 { 0x54, "TPCCS_17" },
150 { 0x55, "T1_32" },
151 { 0x56, "T1_33" },
152 { 0x57, "T1_34" },
153 { 0x58, "T1_35" },
154 { 0x59, "PE_18" },
155 { 0x5a, "PE_19" },
156 { 0x5b, "TPCCS_18" },
157 { 0x5c, "TPCCS_19" },
158 { 0x5d, "T1_36" },
159 { 0x5e, "T1_37" },
160 { 0x5f, "T1_38" },
161 { 0x60, "T1_39" },
162 {}
163 };
164
165 const struct nvkm_enum
166 gv100_fifo_fault_hubclient[] = {
167 { 0x00, "VIP" },
168 { 0x01, "CE0" },
169 { 0x02, "CE1" },
170 { 0x03, "DNISO" },
171 { 0x04, "FE" },
172 { 0x05, "FECS" },
173 { 0x06, "HOST" },
174 { 0x07, "HOST_CPU" },
175 { 0x08, "HOST_CPU_NB" },
176 { 0x09, "ISO" },
177 { 0x0a, "MMU" },
178 { 0x0b, "NVDEC" },
179 { 0x0d, "NVENC1" },
180 { 0x0e, "NISO" },
181 { 0x0f, "P2P" },
182 { 0x10, "PD" },
183 { 0x11, "PERF" },
184 { 0x12, "PMU" },
185 { 0x13, "RASTERTWOD" },
186 { 0x14, "SCC" },
187 { 0x15, "SCC_NB" },
188 { 0x16, "SEC" },
189 { 0x17, "SSYNC" },
190 { 0x18, "CE2" },
191 { 0x19, "XV" },
192 { 0x1a, "MMU_NB" },
193 { 0x1b, "NVENC0" },
194 { 0x1c, "DFALCON" },
195 { 0x1d, "SKED" },
196 { 0x1e, "AFALCON" },
197 { 0x1f, "DONT_CARE" },
198 { 0x20, "HSCE0" },
199 { 0x21, "HSCE1" },
200 { 0x22, "HSCE2" },
201 { 0x23, "HSCE3" },
202 { 0x24, "HSCE4" },
203 { 0x25, "HSCE5" },
204 { 0x26, "HSCE6" },
205 { 0x27, "HSCE7" },
206 { 0x28, "HSCE8" },
207 { 0x29, "HSCE9" },
208 { 0x2a, "HSHUB" },
209 { 0x2b, "PTP_X0" },
210 { 0x2c, "PTP_X1" },
211 { 0x2d, "PTP_X2" },
212 { 0x2e, "PTP_X3" },
213 { 0x2f, "PTP_X4" },
214 { 0x30, "PTP_X5" },
215 { 0x31, "PTP_X6" },
216 { 0x32, "PTP_X7" },
217 { 0x33, "NVENC2" },
218 { 0x34, "VPR_SCRUBBER0" },
219 { 0x35, "VPR_SCRUBBER1" },
220 { 0x36, "DWBIF" },
221 { 0x37, "FBFALCON" },
222 { 0x38, "CE_SHIM" },
223 { 0x39, "GSP" },
224 {}
225 };
226
227 const struct nvkm_enum
228 gv100_fifo_fault_reason[] = {
229 { 0x00, "PDE" },
230 { 0x01, "PDE_SIZE" },
231 { 0x02, "PTE" },
232 { 0x03, "VA_LIMIT_VIOLATION" },
233 { 0x04, "UNBOUND_INST_BLOCK" },
234 { 0x05, "PRIV_VIOLATION" },
235 { 0x06, "RO_VIOLATION" },
236 { 0x07, "WO_VIOLATION" },
237 { 0x08, "PITCH_MASK_VIOLATION" },
238 { 0x09, "WORK_CREATION" },
239 { 0x0a, "UNSUPPORTED_APERTURE" },
240 { 0x0b, "COMPRESSION_FAILURE" },
241 { 0x0c, "UNSUPPORTED_KIND" },
242 { 0x0d, "REGION_VIOLATION" },
243 { 0x0e, "POISONED" },
244 { 0x0f, "ATOMIC_VIOLATION" },
245 {}
246 };
247
248 static const struct nvkm_enum
249 gv100_fifo_fault_engine[] = {
250 { 0x01, "DISPLAY" },
251 { 0x03, "PTP" },
252 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
253 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
254 { 0x06, "PWR_PMU" },
255 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB },
256 { 0x09, "PERF" },
257 { 0x1f, "PHYSICAL" },
258 { 0x20, "HOST0" },
259 { 0x21, "HOST1" },
260 { 0x22, "HOST2" },
261 { 0x23, "HOST3" },
262 { 0x24, "HOST4" },
263 { 0x25, "HOST5" },
264 { 0x26, "HOST6" },
265 { 0x27, "HOST7" },
266 { 0x28, "HOST8" },
267 { 0x29, "HOST9" },
268 { 0x2a, "HOST10" },
269 { 0x2b, "HOST11" },
270 { 0x2c, "HOST12" },
271 { 0x2d, "HOST13" },
272 {}
273 };
274
275 const struct nvkm_enum
276 gv100_fifo_fault_access[] = {
277 { 0x0, "VIRT_READ" },
278 { 0x1, "VIRT_WRITE" },
279 { 0x2, "VIRT_ATOMIC" },
280 { 0x3, "VIRT_PREFETCH" },
281 { 0x4, "VIRT_ATOMIC_WEAK" },
282 { 0x8, "PHYS_READ" },
283 { 0x9, "PHYS_WRITE" },
284 { 0xa, "PHYS_ATOMIC" },
285 { 0xb, "PHYS_PREFETCH" },
286 {}
287 };
288
289 static const struct gk104_fifo_func
290 gv100_fifo = {
291 .pbdma = &gm200_fifo_pbdma,
292 .fault.access = gv100_fifo_fault_access,
293 .fault.engine = gv100_fifo_fault_engine,
294 .fault.reason = gv100_fifo_fault_reason,
295 .fault.hubclient = gv100_fifo_fault_hubclient,
296 .fault.gpcclient = gv100_fifo_fault_gpcclient,
297 .runlist = &gv100_fifo_runlist,
298 .user = {{-1,-1,VOLTA_USERMODE_A }, gv100_fifo_user_new },
299 .chan = {{ 0, 0,VOLTA_CHANNEL_GPFIFO_A}, gv100_fifo_gpfifo_new },
300 .cgrp_force = true,
301 };
302
303 int
gv100_fifo_new(struct nvkm_device * device,int index,struct nvkm_fifo ** pfifo)304 gv100_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
305 {
306 return gk104_fifo_new_(&gv100_fifo, device, index, 4096, pfifo);
307 }
308
