1 /* 2 * Copyright 2018 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 #include "priv.h" 23 #include "chan.h" 24 #include "chid.h" 25 #include "cgrp.h" 26 #include "runl.h" 27 #include "runq.h" 28 29 #include <core/gpuobj.h> 30 #include <subdev/mmu.h> 31 32 #include <nvif/class.h> 33 34 static u32 gv100_chan_doorbell_handle(struct nvkm_chan * chan)35 gv100_chan_doorbell_handle(struct nvkm_chan *chan) 36 { 37 return chan->id; 38 } 39 40 static int gv100_chan_ramfc_write(struct nvkm_chan * chan,u64 offset,u64 length,u32 devm,bool priv)41 gv100_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv) 42 { 43 const u64 userd = nvkm_memory_addr(chan->userd.mem) + chan->userd.base; 44 const u32 limit2 = ilog2(length / 8); 45 46 nvkm_kmap(chan->inst); 47 nvkm_wo32(chan->inst, 0x008, lower_32_bits(userd)); 48 nvkm_wo32(chan->inst, 0x00c, upper_32_bits(userd)); 49 nvkm_wo32(chan->inst, 0x010, 0x0000face); 50 nvkm_wo32(chan->inst, 0x030, 0x7ffff902); 51 nvkm_wo32(chan->inst, 0x048, lower_32_bits(offset)); 52 nvkm_wo32(chan->inst, 0x04c, upper_32_bits(offset) | (limit2 << 16)); 53 nvkm_wo32(chan->inst, 0x084, 0x20400000); 54 nvkm_wo32(chan->inst, 0x094, 0x30000000 | devm); 55 nvkm_wo32(chan->inst, 0x0e4, priv ? 0x00000020 : 0x00000000); 56 nvkm_wo32(chan->inst, 0x0e8, chan->id); 57 nvkm_wo32(chan->inst, 0x0f4, 0x00001000 | (priv ? 0x00000100 : 0x00000000)); 58 nvkm_wo32(chan->inst, 0x0f8, 0x10003080); 59 nvkm_mo32(chan->inst, 0x218, 0x00000000, 0x00000000); 60 nvkm_done(chan->inst); 61 return 0; 62 } 63 64 const struct nvkm_chan_func_ramfc 65 gv100_chan_ramfc = { 66 .write = gv100_chan_ramfc_write, 67 .devm = 0xfff, 68 .priv = true, 69 }; 70 71 const struct nvkm_chan_func_userd 72 gv100_chan_userd = { 73 .bar = -1, 74 .size = 0x200, 75 .clear = gf100_chan_userd_clear, 76 }; 77 78 static const struct nvkm_chan_func 79 gv100_chan = { 80 .inst = &gf100_chan_inst, 81 .userd = &gv100_chan_userd, 82 .ramfc = &gv100_chan_ramfc, 83 .bind = gk104_chan_bind_inst, 84 .unbind = gk104_chan_unbind, 85 .start = gk104_chan_start, 86 .stop = gk104_chan_stop, 87 .preempt = gk110_chan_preempt, 88 .doorbell_handle = gv100_chan_doorbell_handle, 89 }; 90 91 void gv100_ectx_bind(struct nvkm_engn * engn,struct nvkm_cctx * cctx,struct nvkm_chan * chan)92 gv100_ectx_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan) 93 { 94 u64 addr = 0ULL; 95 96 if (cctx) { 97 addr = cctx->vctx->vma->addr; 98 addr |= 4ULL; 99 } 100 101 nvkm_kmap(chan->inst); 102 nvkm_wo32(chan->inst, 0x210, lower_32_bits(addr)); 103 nvkm_wo32(chan->inst, 0x214, upper_32_bits(addr)); 104 nvkm_mo32(chan->inst, 0x0ac, 0x00010000, cctx ? 0x00010000 : 0x00000000); 105 nvkm_done(chan->inst); 106 } 107 108 const struct nvkm_engn_func 109 gv100_engn = { 110 .chsw = gk104_engn_chsw, 111 .cxid = gk104_engn_cxid, 112 .ctor = gk104_ectx_ctor, 113 .bind = gv100_ectx_bind, 114 }; 115 116 void gv100_ectx_ce_bind(struct nvkm_engn * engn,struct nvkm_cctx * cctx,struct nvkm_chan * chan)117 gv100_ectx_ce_bind(struct nvkm_engn *engn, struct nvkm_cctx *cctx, struct nvkm_chan *chan) 118 { 119 const u64 bar2 = cctx ? nvkm_memory_bar2(cctx->vctx->inst->memory) : 0ULL; 120 121 nvkm_kmap(chan->inst); 122 nvkm_wo32(chan->inst, 0x220, lower_32_bits(bar2)); 123 nvkm_wo32(chan->inst, 0x224, upper_32_bits(bar2)); 124 nvkm_mo32(chan->inst, 0x0ac, 0x00020000, cctx ? 0x00020000 : 0x00000000); 125 nvkm_done(chan->inst); 126 } 127 128 int gv100_ectx_ce_ctor(struct nvkm_engn * engn,struct nvkm_vctx * vctx)129 gv100_ectx_ce_ctor(struct nvkm_engn *engn, struct nvkm_vctx *vctx) 130 { 131 if (nvkm_memory_bar2(vctx->inst->memory) == ~0ULL) 132 return -EFAULT; 133 134 return 0; 135 } 136 137 const struct nvkm_engn_func 138 gv100_engn_ce = { 139 .chsw = gk104_engn_chsw, 140 .cxid = gk104_engn_cxid, 141 .ctor = gv100_ectx_ce_ctor, 142 .bind = gv100_ectx_ce_bind, 143 }; 144 145 static bool gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq * runq,int chid)146 gv100_runq_intr_1_ctxnotvalid(struct nvkm_runq *runq, int chid) 147 { 148 struct nvkm_fifo *fifo = runq->fifo; 149 struct nvkm_device *device = fifo->engine.subdev.device; 150 struct nvkm_chan *chan; 151 unsigned long flags; 152 153 RUNQ_ERROR(runq, "CTXNOTVALID chid:%d", chid); 154 155 chan = nvkm_chan_get_chid(&fifo->engine, chid, &flags); 156 if (WARN_ON_ONCE(!chan)) 157 return false; 158 159 nvkm_chan_error(chan, true); 160 nvkm_chan_put(&chan, flags); 161 162 nvkm_mask(device, 0x0400ac + (runq->id * 0x2000), 0x00030000, 0x00030000); 163 nvkm_wr32(device, 0x040148 + (runq->id * 0x2000), 0x80000000); 164 return true; 165 } 166 167 const struct nvkm_runq_func 168 gv100_runq = { 169 .init = gk208_runq_init, 170 .intr = gk104_runq_intr, 171 .intr_0_names = gk104_runq_intr_0_names, 172 .intr_1_ctxnotvalid = gv100_runq_intr_1_ctxnotvalid, 173 .idle = gk104_runq_idle, 174 }; 175 176 void gv100_runl_preempt(struct nvkm_runl * runl)177 gv100_runl_preempt(struct nvkm_runl *runl) 178 { 179 nvkm_wr32(runl->fifo->engine.subdev.device, 0x002638, BIT(runl->id)); 180 } 181 182 void gv100_runl_insert_chan(struct nvkm_chan * chan,struct nvkm_memory * memory,u64 offset)183 gv100_runl_insert_chan(struct nvkm_chan *chan, struct nvkm_memory *memory, u64 offset) 184 { 185 const u64 user = nvkm_memory_addr(chan->userd.mem) + chan->userd.base; 186 const u64 inst = chan->inst->addr; 187 188 nvkm_wo32(memory, offset + 0x0, lower_32_bits(user) | chan->runq << 1); 189 nvkm_wo32(memory, offset + 0x4, upper_32_bits(user)); 190 nvkm_wo32(memory, offset + 0x8, lower_32_bits(inst) | chan->id); 191 nvkm_wo32(memory, offset + 0xc, upper_32_bits(inst)); 192 } 193 194 void gv100_runl_insert_cgrp(struct nvkm_cgrp * cgrp,struct nvkm_memory * memory,u64 offset)195 gv100_runl_insert_cgrp(struct nvkm_cgrp *cgrp, struct nvkm_memory *memory, u64 offset) 196 { 197 nvkm_wo32(memory, offset + 0x0, (128 << 24) | (3 << 16) | 0x00000001); 198 nvkm_wo32(memory, offset + 0x4, cgrp->chan_nr); 199 nvkm_wo32(memory, offset + 0x8, cgrp->id); 200 nvkm_wo32(memory, offset + 0xc, 0x00000000); 201 } 202 203 static const struct nvkm_runl_func 204 gv100_runl = { 205 .runqs = 2, 206 .size = 16, 207 .update = nv50_runl_update, 208 .insert_cgrp = gv100_runl_insert_cgrp, 209 .insert_chan = gv100_runl_insert_chan, 210 .commit = gk104_runl_commit, 211 .wait = nv50_runl_wait, 212 .pending = gk104_runl_pending, 213 .block = gk104_runl_block, 214 .allow = gk104_runl_allow, 215 .preempt = gv100_runl_preempt, 216 .preempt_pending = gf100_runl_preempt_pending, 217 }; 218 219 const struct nvkm_enum 220 gv100_fifo_mmu_fault_gpcclient[] = { 221 { 0x00, "T1_0" }, 222 { 0x01, "T1_1" }, 223 { 0x02, "T1_2" }, 224 { 0x03, "T1_3" }, 225 { 0x04, "T1_4" }, 226 { 0x05, "T1_5" }, 227 { 0x06, "T1_6" }, 228 { 0x07, "T1_7" }, 229 { 0x08, "PE_0" }, 230 { 0x09, "PE_1" }, 231 { 0x0a, "PE_2" }, 232 { 0x0b, "PE_3" }, 233 { 0x0c, "PE_4" }, 234 { 0x0d, "PE_5" }, 235 { 0x0e, "PE_6" }, 236 { 0x0f, "PE_7" }, 237 { 0x10, "RAST" }, 238 { 0x11, "GCC" }, 239 { 0x12, "GPCCS" }, 240 { 0x13, "PROP_0" }, 241 { 0x14, "PROP_1" }, 242 { 0x15, "PROP_2" }, 243 { 0x16, "PROP_3" }, 244 { 0x17, "GPM" }, 245 { 0x18, "LTP_UTLB_0" }, 246 { 0x19, "LTP_UTLB_1" }, 247 { 0x1a, "LTP_UTLB_2" }, 248 { 0x1b, "LTP_UTLB_3" }, 249 { 0x1c, "LTP_UTLB_4" }, 250 { 0x1d, "LTP_UTLB_5" }, 251 { 0x1e, "LTP_UTLB_6" }, 252 { 0x1f, "LTP_UTLB_7" }, 253 { 0x20, "RGG_UTLB" }, 254 { 0x21, "T1_8" }, 255 { 0x22, "T1_9" }, 256 { 0x23, "T1_10" }, 257 { 0x24, "T1_11" }, 258 { 0x25, "T1_12" }, 259 { 0x26, "T1_13" }, 260 { 0x27, "T1_14" }, 261 { 0x28, "T1_15" }, 262 { 0x29, "TPCCS_0" }, 263 { 0x2a, "TPCCS_1" }, 264 { 0x2b, "TPCCS_2" }, 265 { 0x2c, "TPCCS_3" }, 266 { 0x2d, "TPCCS_4" }, 267 { 0x2e, "TPCCS_5" }, 268 { 0x2f, "TPCCS_6" }, 269 { 0x30, "TPCCS_7" }, 270 { 0x31, "PE_8" }, 271 { 0x32, "PE_9" }, 272 { 0x33, "TPCCS_8" }, 273 { 0x34, "TPCCS_9" }, 274 { 0x35, "T1_16" }, 275 { 0x36, "T1_17" }, 276 { 0x37, "T1_18" }, 277 { 0x38, "T1_19" }, 278 { 0x39, "PE_10" }, 279 { 0x3a, "PE_11" }, 280 { 0x3b, "TPCCS_10" }, 281 { 0x3c, "TPCCS_11" }, 282 { 0x3d, "T1_20" }, 283 { 0x3e, "T1_21" }, 284 { 0x3f, "T1_22" }, 285 { 0x40, "T1_23" }, 286 { 0x41, "PE_12" }, 287 { 0x42, "PE_13" }, 288 { 0x43, "TPCCS_12" }, 289 { 0x44, "TPCCS_13" }, 290 { 0x45, "T1_24" }, 291 { 0x46, "T1_25" }, 292 { 0x47, "T1_26" }, 293 { 0x48, "T1_27" }, 294 { 0x49, "PE_14" }, 295 { 0x4a, "PE_15" }, 296 { 0x4b, "TPCCS_14" }, 297 { 0x4c, "TPCCS_15" }, 298 { 0x4d, "T1_28" }, 299 { 0x4e, "T1_29" }, 300 { 0x4f, "T1_30" }, 301 { 0x50, "T1_31" }, 302 { 0x51, "PE_16" }, 303 { 0x52, "PE_17" }, 304 { 0x53, "TPCCS_16" }, 305 { 0x54, "TPCCS_17" }, 306 { 0x55, "T1_32" }, 307 { 0x56, "T1_33" }, 308 { 0x57, "T1_34" }, 309 { 0x58, "T1_35" }, 310 { 0x59, "PE_18" }, 311 { 0x5a, "PE_19" }, 312 { 0x5b, "TPCCS_18" }, 313 { 0x5c, "TPCCS_19" }, 314 { 0x5d, "T1_36" }, 315 { 0x5e, "T1_37" }, 316 { 0x5f, "T1_38" }, 317 { 0x60, "T1_39" }, 318 {} 319 }; 320 321 const struct nvkm_enum 322 gv100_fifo_mmu_fault_hubclient[] = { 323 { 0x00, "VIP" }, 324 { 0x01, "CE0" }, 325 { 0x02, "CE1" }, 326 { 0x03, "DNISO" }, 327 { 0x04, "FE" }, 328 { 0x05, "FECS" }, 329 { 0x06, "HOST" }, 330 { 0x07, "HOST_CPU" }, 331 { 0x08, "HOST_CPU_NB" }, 332 { 0x09, "ISO" }, 333 { 0x0a, "MMU" }, 334 { 0x0b, "NVDEC" }, 335 { 0x0d, "NVENC1" }, 336 { 0x0e, "NISO" }, 337 { 0x0f, "P2P" }, 338 { 0x10, "PD" }, 339 { 0x11, "PERF" }, 340 { 0x12, "PMU" }, 341 { 0x13, "RASTERTWOD" }, 342 { 0x14, "SCC" }, 343 { 0x15, "SCC_NB" }, 344 { 0x16, "SEC" }, 345 { 0x17, "SSYNC" }, 346 { 0x18, "CE2" }, 347 { 0x19, "XV" }, 348 { 0x1a, "MMU_NB" }, 349 { 0x1b, "NVENC0" }, 350 { 0x1c, "DFALCON" }, 351 { 0x1d, "SKED" }, 352 { 0x1e, "AFALCON" }, 353 { 0x1f, "DONT_CARE" }, 354 { 0x20, "HSCE0" }, 355 { 0x21, "HSCE1" }, 356 { 0x22, "HSCE2" }, 357 { 0x23, "HSCE3" }, 358 { 0x24, "HSCE4" }, 359 { 0x25, "HSCE5" }, 360 { 0x26, "HSCE6" }, 361 { 0x27, "HSCE7" }, 362 { 0x28, "HSCE8" }, 363 { 0x29, "HSCE9" }, 364 { 0x2a, "HSHUB" }, 365 { 0x2b, "PTP_X0" }, 366 { 0x2c, "PTP_X1" }, 367 { 0x2d, "PTP_X2" }, 368 { 0x2e, "PTP_X3" }, 369 { 0x2f, "PTP_X4" }, 370 { 0x30, "PTP_X5" }, 371 { 0x31, "PTP_X6" }, 372 { 0x32, "PTP_X7" }, 373 { 0x33, "NVENC2" }, 374 { 0x34, "VPR_SCRUBBER0" }, 375 { 0x35, "VPR_SCRUBBER1" }, 376 { 0x36, "DWBIF" }, 377 { 0x37, "FBFALCON" }, 378 { 0x38, "CE_SHIM" }, 379 { 0x39, "GSP" }, 380 {} 381 }; 382 383 const struct nvkm_enum 384 gv100_fifo_mmu_fault_reason[] = { 385 { 0x00, "PDE" }, 386 { 0x01, "PDE_SIZE" }, 387 { 0x02, "PTE" }, 388 { 0x03, "VA_LIMIT_VIOLATION" }, 389 { 0x04, "UNBOUND_INST_BLOCK" }, 390 { 0x05, "PRIV_VIOLATION" }, 391 { 0x06, "RO_VIOLATION" }, 392 { 0x07, "WO_VIOLATION" }, 393 { 0x08, "PITCH_MASK_VIOLATION" }, 394 { 0x09, "WORK_CREATION" }, 395 { 0x0a, "UNSUPPORTED_APERTURE" }, 396 { 0x0b, "COMPRESSION_FAILURE" }, 397 { 0x0c, "UNSUPPORTED_KIND" }, 398 { 0x0d, "REGION_VIOLATION" }, 399 { 0x0e, "POISONED" }, 400 { 0x0f, "ATOMIC_VIOLATION" }, 401 {} 402 }; 403 404 static const struct nvkm_enum 405 gv100_fifo_mmu_fault_engine[] = { 406 { 0x01, "DISPLAY" }, 407 { 0x03, "PTP" }, 408 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR }, 409 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM }, 410 { 0x06, "PWR_PMU" }, 411 { 0x08, "IFB", NULL, NVKM_ENGINE_IFB }, 412 { 0x09, "PERF" }, 413 { 0x1f, "PHYSICAL" }, 414 { 0x20, "HOST0" }, 415 { 0x21, "HOST1" }, 416 { 0x22, "HOST2" }, 417 { 0x23, "HOST3" }, 418 { 0x24, "HOST4" }, 419 { 0x25, "HOST5" }, 420 { 0x26, "HOST6" }, 421 { 0x27, "HOST7" }, 422 { 0x28, "HOST8" }, 423 { 0x29, "HOST9" }, 424 { 0x2a, "HOST10" }, 425 { 0x2b, "HOST11" }, 426 { 0x2c, "HOST12" }, 427 { 0x2d, "HOST13" }, 428 {} 429 }; 430 431 const struct nvkm_enum 432 gv100_fifo_mmu_fault_access[] = { 433 { 0x0, "VIRT_READ" }, 434 { 0x1, "VIRT_WRITE" }, 435 { 0x2, "VIRT_ATOMIC" }, 436 { 0x3, "VIRT_PREFETCH" }, 437 { 0x4, "VIRT_ATOMIC_WEAK" }, 438 { 0x8, "PHYS_READ" }, 439 { 0x9, "PHYS_WRITE" }, 440 { 0xa, "PHYS_ATOMIC" }, 441 { 0xb, "PHYS_PREFETCH" }, 442 {} 443 }; 444 445 static const struct nvkm_fifo_func_mmu_fault 446 gv100_fifo_mmu_fault = { 447 .recover = gf100_fifo_mmu_fault_recover, 448 .access = gv100_fifo_mmu_fault_access, 449 .engine = gv100_fifo_mmu_fault_engine, 450 .reason = gv100_fifo_mmu_fault_reason, 451 .hubclient = gv100_fifo_mmu_fault_hubclient, 452 .gpcclient = gv100_fifo_mmu_fault_gpcclient, 453 }; 454 455 static void gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo * fifo,u32 engm)456 gv100_fifo_intr_ctxsw_timeout(struct nvkm_fifo *fifo, u32 engm) 457 { 458 struct nvkm_runl *runl; 459 struct nvkm_engn *engn; 460 461 nvkm_runl_foreach(runl, fifo) { 462 nvkm_runl_foreach_engn_cond(engn, runl, engm & BIT(engn->id)) 463 nvkm_runl_rc_engn(runl, engn); 464 } 465 } 466 467 static const struct nvkm_fifo_func 468 gv100_fifo = { 469 .chid_nr = gm200_fifo_chid_nr, 470 .chid_ctor = gk110_fifo_chid_ctor, 471 .runq_nr = gm200_fifo_runq_nr, 472 .runl_ctor = gk104_fifo_runl_ctor, 473 .init = gk104_fifo_init, 474 .init_pbdmas = gk104_fifo_init_pbdmas, 475 .intr = gk104_fifo_intr, 476 .intr_ctxsw_timeout = gv100_fifo_intr_ctxsw_timeout, 477 .mmu_fault = &gv100_fifo_mmu_fault, 478 .nonstall = &gf100_fifo_nonstall, 479 .runl = &gv100_runl, 480 .runq = &gv100_runq, 481 .engn = &gv100_engn, 482 .engn_ce = &gv100_engn_ce, 483 .cgrp = {{ 0, 0, KEPLER_CHANNEL_GROUP_A }, &gk110_cgrp, .force = true }, 484 .chan = {{ 0, 0, VOLTA_CHANNEL_GPFIFO_A }, &gv100_chan }, 485 }; 486 487 int gv100_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)488 gv100_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, 489 struct nvkm_fifo **pfifo) 490 { 491 return nvkm_fifo_new_(&gv100_fifo, device, type, inst, pfifo); 492 } 493
