1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/irq.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8660.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 model = "Qualcomm MSM8660"; 13 compatible = "qcom,msm8660"; 14 interrupt-parent = <&intc>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu@0 { 21 compatible = "qcom,scorpion"; 22 enable-method = "qcom,gcc-msm8660"; 23 device_type = "cpu"; 24 reg = <0>; 25 next-level-cache = <&L2>; 26 }; 27 28 cpu@1 { 29 compatible = "qcom,scorpion"; 30 enable-method = "qcom,gcc-msm8660"; 31 device_type = "cpu"; 32 reg = <1>; 33 next-level-cache = <&L2>; 34 }; 35 36 L2: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 }; 40 }; 41 42 memory { 43 device_type = "memory"; 44 reg = <0x0 0x0>; 45 }; 46 47 cpu-pmu { 48 compatible = "qcom,scorpion-mp-pmu"; 49 interrupts = <1 9 0x304>; 50 }; 51 52 clocks { 53 cxo_board { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <19200000>; 57 }; 58 59 pxo_board { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 }; 64 65 sleep_clk { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <32768>; 69 }; 70 }; 71 72 /* 73 * These channels from the ADC are simply hardware monitors. 74 * That is why the ADC is referred to as "HKADC" - HouseKeeping 75 * ADC. 76 */ 77 iio-hwmon { 78 compatible = "iio-hwmon"; 79 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 80 <&xoadc 0x00 0x02>, /* DC in (charger) */ 81 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 82 <&xoadc 0x00 0x0b>, /* Die temperature */ 83 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 84 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 85 <&xoadc 0x00 0x0e>; /* Reference voltage 0.325V */ 86 }; 87 88 soc: soc { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 ranges; 92 compatible = "simple-bus"; 93 94 intc: interrupt-controller@2080000 { 95 compatible = "qcom,msm-8660-qgic"; 96 interrupt-controller; 97 #interrupt-cells = <3>; 98 reg = < 0x02080000 0x1000 >, 99 < 0x02081000 0x1000 >; 100 }; 101 102 timer@2000000 { 103 compatible = "qcom,scss-timer", "qcom,msm-timer"; 104 interrupts = <1 0 0x301>, 105 <1 1 0x301>, 106 <1 2 0x301>; 107 reg = <0x02000000 0x100>; 108 clock-frequency = <27000000>, 109 <32768>; 110 cpu-offset = <0x40000>; 111 }; 112 113 tlmm: pinctrl@800000 { 114 compatible = "qcom,msm8660-pinctrl"; 115 reg = <0x800000 0x4000>; 116 117 gpio-controller; 118 #gpio-cells = <2>; 119 interrupts = <0 16 0x4>; 120 interrupt-controller; 121 #interrupt-cells = <2>; 122 123 }; 124 125 gcc: clock-controller@900000 { 126 compatible = "qcom,gcc-msm8660"; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 reg = <0x900000 0x4000>; 130 }; 131 132 gsbi6: gsbi@16500000 { 133 compatible = "qcom,gsbi-v1.0.0"; 134 cell-index = <12>; 135 reg = <0x16500000 0x100>; 136 clocks = <&gcc GSBI6_H_CLK>; 137 clock-names = "iface"; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges; 141 status = "disabled"; 142 143 syscon-tcsr = <&tcsr>; 144 145 gsbi6_serial: serial@16540000 { 146 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 147 reg = <0x16540000 0x1000>, 148 <0x16500000 0x1000>; 149 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 151 clock-names = "core", "iface"; 152 status = "disabled"; 153 }; 154 155 gsbi6_i2c: i2c@16580000 { 156 compatible = "qcom,i2c-qup-v1.1.1"; 157 reg = <0x16580000 0x1000>; 158 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 160 clock-names = "core", "iface"; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 status = "disabled"; 164 }; 165 }; 166 167 gsbi7: gsbi@16600000 { 168 compatible = "qcom,gsbi-v1.0.0"; 169 cell-index = <12>; 170 reg = <0x16600000 0x100>; 171 clocks = <&gcc GSBI7_H_CLK>; 172 clock-names = "iface"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges; 176 status = "disabled"; 177 178 syscon-tcsr = <&tcsr>; 179 180 gsbi7_serial: serial@16640000 { 181 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 182 reg = <0x16640000 0x1000>, 183 <0x16600000 0x1000>; 184 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 186 clock-names = "core", "iface"; 187 status = "disabled"; 188 }; 189 190 gsbi7_i2c: i2c@16680000 { 191 compatible = "qcom,i2c-qup-v1.1.1"; 192 reg = <0x16680000 0x1000>; 193 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 194 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 195 clock-names = "core", "iface"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 status = "disabled"; 199 }; 200 }; 201 202 gsbi8: gsbi@19800000 { 203 compatible = "qcom,gsbi-v1.0.0"; 204 cell-index = <12>; 205 reg = <0x19800000 0x100>; 206 clocks = <&gcc GSBI8_H_CLK>; 207 clock-names = "iface"; 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 syscon-tcsr = <&tcsr>; 213 214 gsbi8_i2c: i2c@19880000 { 215 compatible = "qcom,i2c-qup-v1.1.1"; 216 reg = <0x19880000 0x1000>; 217 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 218 clocks = <&gcc GSBI8_QUP_CLK>, <&gcc GSBI8_H_CLK>; 219 clock-names = "core", "iface"; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 status = "disabled"; 223 }; 224 }; 225 226 gsbi12: gsbi@19c00000 { 227 compatible = "qcom,gsbi-v1.0.0"; 228 cell-index = <12>; 229 reg = <0x19c00000 0x100>; 230 clocks = <&gcc GSBI12_H_CLK>; 231 clock-names = "iface"; 232 #address-cells = <1>; 233 #size-cells = <1>; 234 ranges; 235 236 syscon-tcsr = <&tcsr>; 237 238 gsbi12_serial: serial@19c40000 { 239 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 240 reg = <0x19c40000 0x1000>, 241 <0x19c00000 0x1000>; 242 interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; 244 clock-names = "core", "iface"; 245 status = "disabled"; 246 }; 247 248 gsbi12_i2c: i2c@19c80000 { 249 compatible = "qcom,i2c-qup-v1.1.1"; 250 reg = <0x19c80000 0x1000>; 251 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>; 253 clock-names = "core", "iface"; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 status = "disabled"; 257 }; 258 }; 259 260 external-bus@1a100000 { 261 compatible = "qcom,msm8660-ebi2"; 262 #address-cells = <2>; 263 #size-cells = <1>; 264 ranges = <0 0x0 0x1a800000 0x00800000>, 265 <1 0x0 0x1b000000 0x00800000>, 266 <2 0x0 0x1b800000 0x00800000>, 267 <3 0x0 0x1d000000 0x08000000>, 268 <4 0x0 0x1c800000 0x00800000>, 269 <5 0x0 0x1c000000 0x00800000>; 270 reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>; 271 reg-names = "ebi2", "xmem"; 272 clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>; 273 clock-names = "ebi2x", "ebi2"; 274 status = "disabled"; 275 }; 276 277 qcom,ssbi@500000 { 278 compatible = "qcom,ssbi"; 279 reg = <0x500000 0x1000>; 280 qcom,controller-type = "pmic-arbiter"; 281 282 pm8058: pmic@0 { 283 compatible = "qcom,pm8058"; 284 interrupt-parent = <&tlmm>; 285 interrupts = <88 8>; 286 #interrupt-cells = <2>; 287 interrupt-controller; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 291 pm8058_gpio: gpio@150 { 292 compatible = "qcom,pm8058-gpio", 293 "qcom,ssbi-gpio"; 294 reg = <0x150>; 295 interrupt-controller; 296 #interrupt-cells = <2>; 297 gpio-controller; 298 gpio-ranges = <&pm8058_gpio 0 0 44>; 299 #gpio-cells = <2>; 300 301 }; 302 303 pm8058_mpps: mpps@50 { 304 compatible = "qcom,pm8058-mpp", 305 "qcom,ssbi-mpp"; 306 reg = <0x50>; 307 gpio-controller; 308 #gpio-cells = <2>; 309 interrupt-parent = <&pm8058>; 310 interrupts = 311 <128 IRQ_TYPE_NONE>, 312 <129 IRQ_TYPE_NONE>, 313 <130 IRQ_TYPE_NONE>, 314 <131 IRQ_TYPE_NONE>, 315 <132 IRQ_TYPE_NONE>, 316 <133 IRQ_TYPE_NONE>, 317 <134 IRQ_TYPE_NONE>, 318 <135 IRQ_TYPE_NONE>, 319 <136 IRQ_TYPE_NONE>, 320 <137 IRQ_TYPE_NONE>, 321 <138 IRQ_TYPE_NONE>, 322 <139 IRQ_TYPE_NONE>; 323 }; 324 325 pwrkey@1c { 326 compatible = "qcom,pm8058-pwrkey"; 327 reg = <0x1c>; 328 interrupt-parent = <&pm8058>; 329 interrupts = <50 1>, <51 1>; 330 debounce = <15625>; 331 pull-up; 332 }; 333 334 keypad@148 { 335 compatible = "qcom,pm8058-keypad"; 336 reg = <0x148>; 337 interrupt-parent = <&pm8058>; 338 interrupts = <74 1>, <75 1>; 339 debounce = <15>; 340 scan-delay = <32>; 341 row-hold = <91500>; 342 }; 343 344 xoadc: xoadc@197 { 345 compatible = "qcom,pm8058-adc"; 346 reg = <0x197>; 347 interrupts-extended = <&pm8058 76 IRQ_TYPE_EDGE_RISING>; 348 #address-cells = <2>; 349 #size-cells = <0>; 350 #io-channel-cells = <2>; 351 352 vcoin: adc-channel@0 { 353 reg = <0x00 0x00>; 354 }; 355 vbat: adc-channel@1 { 356 reg = <0x00 0x01>; 357 }; 358 dcin: adc-channel@2 { 359 reg = <0x00 0x02>; 360 }; 361 ichg: adc-channel@3 { 362 reg = <0x00 0x03>; 363 }; 364 vph_pwr: adc-channel@4 { 365 reg = <0x00 0x04>; 366 }; 367 usb_vbus: adc-channel@a { 368 reg = <0x00 0x0a>; 369 }; 370 die_temp: adc-channel@b { 371 reg = <0x00 0x0b>; 372 }; 373 ref_625mv: adc-channel@c { 374 reg = <0x00 0x0c>; 375 }; 376 ref_1250mv: adc-channel@d { 377 reg = <0x00 0x0d>; 378 }; 379 ref_325mv: adc-channel@e { 380 reg = <0x00 0x0e>; 381 }; 382 ref_muxoff: adc-channel@f { 383 reg = <0x00 0x0f>; 384 }; 385 }; 386 387 rtc@1e8 { 388 compatible = "qcom,pm8058-rtc"; 389 reg = <0x1e8>; 390 interrupt-parent = <&pm8058>; 391 interrupts = <39 1>; 392 allow-set-time; 393 }; 394 395 vibrator@4a { 396 compatible = "qcom,pm8058-vib"; 397 reg = <0x4a>; 398 }; 399 }; 400 }; 401 402 l2cc: clock-controller@2082000 { 403 compatible = "syscon"; 404 reg = <0x02082000 0x1000>; 405 }; 406 407 rpm: rpm@104000 { 408 compatible = "qcom,rpm-msm8660"; 409 reg = <0x00104000 0x1000>; 410 qcom,ipc = <&l2cc 0x8 2>; 411 412 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 415 interrupt-names = "ack", "err", "wakeup"; 416 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 417 clock-names = "ram"; 418 419 rpmcc: clock-controller { 420 compatible = "qcom,rpmcc-msm8660", "qcom,rpmcc"; 421 #clock-cells = <1>; 422 }; 423 424 pm8901-regulators { 425 compatible = "qcom,rpm-pm8901-regulators"; 426 427 pm8901_l0: l0 {}; 428 pm8901_l1: l1 {}; 429 pm8901_l2: l2 {}; 430 pm8901_l3: l3 {}; 431 pm8901_l4: l4 {}; 432 pm8901_l5: l5 {}; 433 pm8901_l6: l6 {}; 434 435 /* S0 and S1 Handled as SAW regulators by SPM */ 436 pm8901_s2: s2 {}; 437 pm8901_s3: s3 {}; 438 pm8901_s4: s4 {}; 439 440 pm8901_lvs0: lvs0 {}; 441 pm8901_lvs1: lvs1 {}; 442 pm8901_lvs2: lvs2 {}; 443 pm8901_lvs3: lvs3 {}; 444 445 pm8901_mvs: mvs {}; 446 }; 447 448 pm8058-regulators { 449 compatible = "qcom,rpm-pm8058-regulators"; 450 451 pm8058_l0: l0 {}; 452 pm8058_l1: l1 {}; 453 pm8058_l2: l2 {}; 454 pm8058_l3: l3 {}; 455 pm8058_l4: l4 {}; 456 pm8058_l5: l5 {}; 457 pm8058_l6: l6 {}; 458 pm8058_l7: l7 {}; 459 pm8058_l8: l8 {}; 460 pm8058_l9: l9 {}; 461 pm8058_l10: l10 {}; 462 pm8058_l11: l11 {}; 463 pm8058_l12: l12 {}; 464 pm8058_l13: l13 {}; 465 pm8058_l14: l14 {}; 466 pm8058_l15: l15 {}; 467 pm8058_l16: l16 {}; 468 pm8058_l17: l17 {}; 469 pm8058_l18: l18 {}; 470 pm8058_l19: l19 {}; 471 pm8058_l20: l20 {}; 472 pm8058_l21: l21 {}; 473 pm8058_l22: l22 {}; 474 pm8058_l23: l23 {}; 475 pm8058_l24: l24 {}; 476 pm8058_l25: l25 {}; 477 478 pm8058_s0: s0 {}; 479 pm8058_s1: s1 {}; 480 pm8058_s2: s2 {}; 481 pm8058_s3: s3 {}; 482 pm8058_s4: s4 {}; 483 484 pm8058_lvs0: lvs0 {}; 485 pm8058_lvs1: lvs1 {}; 486 487 pm8058_ncp: ncp {}; 488 }; 489 }; 490 491 amba { 492 compatible = "simple-bus"; 493 #address-cells = <1>; 494 #size-cells = <1>; 495 ranges; 496 sdcc1: sdcc@12400000 { 497 status = "disabled"; 498 compatible = "arm,pl18x", "arm,primecell"; 499 arm,primecell-periphid = <0x00051180>; 500 reg = <0x12400000 0x8000>; 501 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 502 interrupt-names = "cmd_irq"; 503 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 504 clock-names = "mclk", "apb_pclk"; 505 bus-width = <8>; 506 max-frequency = <48000000>; 507 non-removable; 508 cap-sd-highspeed; 509 cap-mmc-highspeed; 510 }; 511 512 sdcc2: sdcc@12140000 { 513 status = "disabled"; 514 compatible = "arm,pl18x", "arm,primecell"; 515 arm,primecell-periphid = <0x00051180>; 516 reg = <0x12140000 0x8000>; 517 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 518 interrupt-names = "cmd_irq"; 519 clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>; 520 clock-names = "mclk", "apb_pclk"; 521 bus-width = <8>; 522 max-frequency = <48000000>; 523 cap-sd-highspeed; 524 cap-mmc-highspeed; 525 }; 526 527 sdcc3: sdcc@12180000 { 528 compatible = "arm,pl18x", "arm,primecell"; 529 arm,primecell-periphid = <0x00051180>; 530 status = "disabled"; 531 reg = <0x12180000 0x8000>; 532 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 533 interrupt-names = "cmd_irq"; 534 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 535 clock-names = "mclk", "apb_pclk"; 536 bus-width = <4>; 537 cap-sd-highspeed; 538 cap-mmc-highspeed; 539 max-frequency = <48000000>; 540 no-1-8-v; 541 }; 542 543 sdcc4: sdcc@121c0000 { 544 compatible = "arm,pl18x", "arm,primecell"; 545 arm,primecell-periphid = <0x00051180>; 546 status = "disabled"; 547 reg = <0x121c0000 0x8000>; 548 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "cmd_irq"; 550 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 551 clock-names = "mclk", "apb_pclk"; 552 bus-width = <4>; 553 max-frequency = <48000000>; 554 cap-sd-highspeed; 555 cap-mmc-highspeed; 556 }; 557 558 sdcc5: sdcc@12200000 { 559 compatible = "arm,pl18x", "arm,primecell"; 560 arm,primecell-periphid = <0x00051180>; 561 status = "disabled"; 562 reg = <0x12200000 0x8000>; 563 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 564 interrupt-names = "cmd_irq"; 565 clocks = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>; 566 clock-names = "mclk", "apb_pclk"; 567 bus-width = <4>; 568 cap-sd-highspeed; 569 cap-mmc-highspeed; 570 max-frequency = <48000000>; 571 }; 572 }; 573 574 tcsr: syscon@1a400000 { 575 compatible = "qcom,tcsr-msm8660", "syscon"; 576 reg = <0x1a400000 0x100>; 577 }; 578 }; 579 580}; 581
