1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include "skeleton.dtsi" 5#include <dt-bindings/clock/qcom,gcc-msm8960.h> 6#include <dt-bindings/reset/qcom,gcc-msm8960.h> 7#include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/soc/qcom,gsbi.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12/ { 13 model = "Qualcomm APQ8064"; 14 compatible = "qcom,apq8064"; 15 interrupt-parent = <&intc>; 16 17 reserved-memory { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 ranges; 21 22 smem_region: smem@80000000 { 23 reg = <0x80000000 0x200000>; 24 no-map; 25 }; 26 27 wcnss_mem: wcnss@8f000000 { 28 reg = <0x8f000000 0x700000>; 29 no-map; 30 }; 31 }; 32 33 cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 CPU0: cpu@0 { 38 compatible = "qcom,krait"; 39 enable-method = "qcom,kpss-acc-v1"; 40 device_type = "cpu"; 41 reg = <0>; 42 next-level-cache = <&L2>; 43 qcom,acc = <&acc0>; 44 qcom,saw = <&saw0>; 45 cpu-idle-states = <&CPU_SPC>; 46 }; 47 48 CPU1: cpu@1 { 49 compatible = "qcom,krait"; 50 enable-method = "qcom,kpss-acc-v1"; 51 device_type = "cpu"; 52 reg = <1>; 53 next-level-cache = <&L2>; 54 qcom,acc = <&acc1>; 55 qcom,saw = <&saw1>; 56 cpu-idle-states = <&CPU_SPC>; 57 }; 58 59 CPU2: cpu@2 { 60 compatible = "qcom,krait"; 61 enable-method = "qcom,kpss-acc-v1"; 62 device_type = "cpu"; 63 reg = <2>; 64 next-level-cache = <&L2>; 65 qcom,acc = <&acc2>; 66 qcom,saw = <&saw2>; 67 cpu-idle-states = <&CPU_SPC>; 68 }; 69 70 CPU3: cpu@3 { 71 compatible = "qcom,krait"; 72 enable-method = "qcom,kpss-acc-v1"; 73 device_type = "cpu"; 74 reg = <3>; 75 next-level-cache = <&L2>; 76 qcom,acc = <&acc3>; 77 qcom,saw = <&saw3>; 78 cpu-idle-states = <&CPU_SPC>; 79 }; 80 81 L2: l2-cache { 82 compatible = "cache"; 83 cache-level = <2>; 84 }; 85 86 idle-states { 87 CPU_SPC: spc { 88 compatible = "qcom,idle-state-spc", 89 "arm,idle-state"; 90 entry-latency-us = <400>; 91 exit-latency-us = <900>; 92 min-residency-us = <3000>; 93 }; 94 }; 95 }; 96 97 thermal-zones { 98 cpu-thermal0 { 99 polling-delay-passive = <250>; 100 polling-delay = <1000>; 101 102 thermal-sensors = <&gcc 7>; 103 coefficients = <1199 0>; 104 105 trips { 106 cpu_alert0: trip0 { 107 temperature = <75000>; 108 hysteresis = <2000>; 109 type = "passive"; 110 }; 111 cpu_crit0: trip1 { 112 temperature = <110000>; 113 hysteresis = <2000>; 114 type = "critical"; 115 }; 116 }; 117 }; 118 119 cpu-thermal1 { 120 polling-delay-passive = <250>; 121 polling-delay = <1000>; 122 123 thermal-sensors = <&gcc 8>; 124 coefficients = <1132 0>; 125 126 trips { 127 cpu_alert1: trip0 { 128 temperature = <75000>; 129 hysteresis = <2000>; 130 type = "passive"; 131 }; 132 cpu_crit1: trip1 { 133 temperature = <110000>; 134 hysteresis = <2000>; 135 type = "critical"; 136 }; 137 }; 138 }; 139 140 cpu-thermal2 { 141 polling-delay-passive = <250>; 142 polling-delay = <1000>; 143 144 thermal-sensors = <&gcc 9>; 145 coefficients = <1199 0>; 146 147 trips { 148 cpu_alert2: trip0 { 149 temperature = <75000>; 150 hysteresis = <2000>; 151 type = "passive"; 152 }; 153 cpu_crit2: trip1 { 154 temperature = <110000>; 155 hysteresis = <2000>; 156 type = "critical"; 157 }; 158 }; 159 }; 160 161 cpu-thermal3 { 162 polling-delay-passive = <250>; 163 polling-delay = <1000>; 164 165 thermal-sensors = <&gcc 10>; 166 coefficients = <1132 0>; 167 168 trips { 169 cpu_alert3: trip0 { 170 temperature = <75000>; 171 hysteresis = <2000>; 172 type = "passive"; 173 }; 174 cpu_crit3: trip1 { 175 temperature = <110000>; 176 hysteresis = <2000>; 177 type = "critical"; 178 }; 179 }; 180 }; 181 }; 182 183 cpu-pmu { 184 compatible = "qcom,krait-pmu"; 185 interrupts = <1 10 0x304>; 186 }; 187 188 clocks { 189 cxo_board: cxo_board { 190 compatible = "fixed-clock"; 191 #clock-cells = <0>; 192 clock-frequency = <19200000>; 193 }; 194 195 pxo_board { 196 compatible = "fixed-clock"; 197 #clock-cells = <0>; 198 clock-frequency = <27000000>; 199 }; 200 201 sleep_clk: sleep_clk { 202 compatible = "fixed-clock"; 203 #clock-cells = <0>; 204 clock-frequency = <32768>; 205 }; 206 }; 207 208 sfpb_mutex: hwmutex { 209 compatible = "qcom,sfpb-mutex"; 210 syscon = <&sfpb_wrapper_mutex 0x604 0x4>; 211 #hwlock-cells = <1>; 212 }; 213 214 smem { 215 compatible = "qcom,smem"; 216 memory-region = <&smem_region>; 217 218 hwlocks = <&sfpb_mutex 3>; 219 }; 220 221 smd { 222 compatible = "qcom,smd"; 223 224 modem@0 { 225 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>; 226 227 qcom,ipc = <&l2cc 8 3>; 228 qcom,smd-edge = <0>; 229 230 status = "disabled"; 231 }; 232 233 q6@1 { 234 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>; 235 236 qcom,ipc = <&l2cc 8 15>; 237 qcom,smd-edge = <1>; 238 239 status = "disabled"; 240 }; 241 242 dsps@3 { 243 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>; 244 245 qcom,ipc = <&sps_sic_non_secure 0x4080 0>; 246 qcom,smd-edge = <3>; 247 248 status = "disabled"; 249 }; 250 251 riva@6 { 252 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>; 253 254 qcom,ipc = <&l2cc 8 25>; 255 qcom,smd-edge = <6>; 256 257 status = "disabled"; 258 }; 259 }; 260 261 smsm { 262 compatible = "qcom,smsm"; 263 264 #address-cells = <1>; 265 #size-cells = <0>; 266 267 qcom,ipc-1 = <&l2cc 8 4>; 268 qcom,ipc-2 = <&l2cc 8 14>; 269 qcom,ipc-3 = <&l2cc 8 23>; 270 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>; 271 272 apps_smsm: apps@0 { 273 reg = <0>; 274 #qcom,smem-state-cells = <1>; 275 }; 276 277 modem_smsm: modem@1 { 278 reg = <1>; 279 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>; 280 281 interrupt-controller; 282 #interrupt-cells = <2>; 283 }; 284 285 q6_smsm: q6@2 { 286 reg = <2>; 287 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>; 288 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 293 wcnss_smsm: wcnss@3 { 294 reg = <3>; 295 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>; 296 297 interrupt-controller; 298 #interrupt-cells = <2>; 299 }; 300 301 dsps_smsm: dsps@4 { 302 reg = <4>; 303 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>; 304 305 interrupt-controller; 306 #interrupt-cells = <2>; 307 }; 308 }; 309 310 firmware { 311 scm { 312 compatible = "qcom,scm-apq8064"; 313 314 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>; 315 clock-names = "core"; 316 }; 317 }; 318 319 320 /* 321 * These channels from the ADC are simply hardware monitors. 322 * That is why the ADC is referred to as "HKADC" - HouseKeeping 323 * ADC. 324 */ 325 iio-hwmon { 326 compatible = "iio-hwmon"; 327 io-channels = <&xoadc 0x00 0x01>, /* Battery */ 328 <&xoadc 0x00 0x02>, /* DC in (charger) */ 329 <&xoadc 0x00 0x04>, /* VPH the main system voltage */ 330 <&xoadc 0x00 0x0b>, /* Die temperature */ 331 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */ 332 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */ 333 <&xoadc 0x00 0x0e>; /* Charger temperature */ 334 }; 335 336 soc: soc { 337 #address-cells = <1>; 338 #size-cells = <1>; 339 ranges; 340 compatible = "simple-bus"; 341 342 tlmm_pinmux: pinctrl@800000 { 343 compatible = "qcom,apq8064-pinctrl"; 344 reg = <0x800000 0x4000>; 345 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; 351 352 pinctrl-names = "default"; 353 pinctrl-0 = <&ps_hold>; 354 }; 355 356 sfpb_wrapper_mutex: syscon@1200000 { 357 compatible = "syscon"; 358 reg = <0x01200000 0x8000>; 359 }; 360 361 intc: interrupt-controller@2000000 { 362 compatible = "qcom,msm-qgic2"; 363 interrupt-controller; 364 #interrupt-cells = <3>; 365 reg = <0x02000000 0x1000>, 366 <0x02002000 0x1000>; 367 }; 368 369 timer@200a000 { 370 compatible = "qcom,kpss-timer", 371 "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; 372 interrupts = <1 1 0x301>, 373 <1 2 0x301>, 374 <1 3 0x301>; 375 reg = <0x0200a000 0x100>; 376 clock-frequency = <27000000>, 377 <32768>; 378 cpu-offset = <0x80000>; 379 }; 380 381 acc0: clock-controller@2088000 { 382 compatible = "qcom,kpss-acc-v1"; 383 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 384 }; 385 386 acc1: clock-controller@2098000 { 387 compatible = "qcom,kpss-acc-v1"; 388 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 389 }; 390 391 acc2: clock-controller@20a8000 { 392 compatible = "qcom,kpss-acc-v1"; 393 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; 394 }; 395 396 acc3: clock-controller@20b8000 { 397 compatible = "qcom,kpss-acc-v1"; 398 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; 399 }; 400 401 saw0: power-controller@2089000 { 402 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 403 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 404 regulator; 405 }; 406 407 saw1: power-controller@2099000 { 408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 409 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 410 regulator; 411 }; 412 413 saw2: power-controller@20a9000 { 414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 415 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; 416 regulator; 417 }; 418 419 saw3: power-controller@20b9000 { 420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; 421 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; 422 regulator; 423 }; 424 425 sps_sic_non_secure: sps-sic-non-secure@12100000 { 426 compatible = "syscon"; 427 reg = <0x12100000 0x10000>; 428 }; 429 430 gsbi1: gsbi@12440000 { 431 status = "disabled"; 432 compatible = "qcom,gsbi-v1.0.0"; 433 cell-index = <1>; 434 reg = <0x12440000 0x100>; 435 clocks = <&gcc GSBI1_H_CLK>; 436 clock-names = "iface"; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 ranges; 440 441 syscon-tcsr = <&tcsr>; 442 443 gsbi1_serial: serial@12450000 { 444 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 445 reg = <0x12450000 0x100>, 446 <0x12400000 0x03>; 447 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 448 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 449 clock-names = "core", "iface"; 450 status = "disabled"; 451 }; 452 453 gsbi1_i2c: i2c@12460000 { 454 compatible = "qcom,i2c-qup-v1.1.1"; 455 pinctrl-0 = <&i2c1_pins>; 456 pinctrl-1 = <&i2c1_pins_sleep>; 457 pinctrl-names = "default", "sleep"; 458 reg = <0x12460000 0x1000>; 459 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 461 clock-names = "core", "iface"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 status = "disabled"; 465 }; 466 467 }; 468 469 gsbi2: gsbi@12480000 { 470 status = "disabled"; 471 compatible = "qcom,gsbi-v1.0.0"; 472 cell-index = <2>; 473 reg = <0x12480000 0x100>; 474 clocks = <&gcc GSBI2_H_CLK>; 475 clock-names = "iface"; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 ranges; 479 480 syscon-tcsr = <&tcsr>; 481 482 gsbi2_i2c: i2c@124a0000 { 483 compatible = "qcom,i2c-qup-v1.1.1"; 484 reg = <0x124a0000 0x1000>; 485 pinctrl-0 = <&i2c2_pins>; 486 pinctrl-1 = <&i2c2_pins_sleep>; 487 pinctrl-names = "default", "sleep"; 488 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>; 489 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 490 clock-names = "core", "iface"; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 }; 496 497 gsbi3: gsbi@16200000 { 498 status = "disabled"; 499 compatible = "qcom,gsbi-v1.0.0"; 500 cell-index = <3>; 501 reg = <0x16200000 0x100>; 502 clocks = <&gcc GSBI3_H_CLK>; 503 clock-names = "iface"; 504 #address-cells = <1>; 505 #size-cells = <1>; 506 ranges; 507 gsbi3_i2c: i2c@16280000 { 508 compatible = "qcom,i2c-qup-v1.1.1"; 509 pinctrl-0 = <&i2c3_pins>; 510 pinctrl-1 = <&i2c3_pins_sleep>; 511 pinctrl-names = "default", "sleep"; 512 reg = <0x16280000 0x1000>; 513 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 514 clocks = <&gcc GSBI3_QUP_CLK>, 515 <&gcc GSBI3_H_CLK>; 516 clock-names = "core", "iface"; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 }; 522 523 gsbi4: gsbi@16300000 { 524 status = "disabled"; 525 compatible = "qcom,gsbi-v1.0.0"; 526 cell-index = <4>; 527 reg = <0x16300000 0x03>; 528 clocks = <&gcc GSBI4_H_CLK>; 529 clock-names = "iface"; 530 #address-cells = <1>; 531 #size-cells = <1>; 532 ranges; 533 534 gsbi4_i2c: i2c@16380000 { 535 compatible = "qcom,i2c-qup-v1.1.1"; 536 pinctrl-0 = <&i2c4_pins>; 537 pinctrl-1 = <&i2c4_pins_sleep>; 538 pinctrl-names = "default", "sleep"; 539 reg = <0x16380000 0x1000>; 540 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&gcc GSBI4_QUP_CLK>, 542 <&gcc GSBI4_H_CLK>; 543 clock-names = "core", "iface"; 544 status = "disabled"; 545 }; 546 }; 547 548 gsbi5: gsbi@1a200000 { 549 status = "disabled"; 550 compatible = "qcom,gsbi-v1.0.0"; 551 cell-index = <5>; 552 reg = <0x1a200000 0x03>; 553 clocks = <&gcc GSBI5_H_CLK>; 554 clock-names = "iface"; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 ranges; 558 559 gsbi5_serial: serial@1a240000 { 560 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 561 reg = <0x1a240000 0x100>, 562 <0x1a200000 0x03>; 563 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 565 clock-names = "core", "iface"; 566 status = "disabled"; 567 }; 568 569 gsbi5_spi: spi@1a280000 { 570 compatible = "qcom,spi-qup-v1.1.1"; 571 reg = <0x1a280000 0x1000>; 572 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; 573 pinctrl-0 = <&spi5_default>; 574 pinctrl-1 = <&spi5_sleep>; 575 pinctrl-names = "default", "sleep"; 576 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 577 clock-names = "core", "iface"; 578 status = "disabled"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 }; 582 }; 583 584 gsbi6: gsbi@16500000 { 585 status = "disabled"; 586 compatible = "qcom,gsbi-v1.0.0"; 587 cell-index = <6>; 588 reg = <0x16500000 0x03>; 589 clocks = <&gcc GSBI6_H_CLK>; 590 clock-names = "iface"; 591 #address-cells = <1>; 592 #size-cells = <1>; 593 ranges; 594 595 gsbi6_serial: serial@16540000 { 596 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 597 reg = <0x16540000 0x100>, 598 <0x16500000 0x03>; 599 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>; 601 clock-names = "core", "iface"; 602 status = "disabled"; 603 }; 604 605 gsbi6_i2c: i2c@16580000 { 606 compatible = "qcom,i2c-qup-v1.1.1"; 607 pinctrl-0 = <&i2c6_pins>; 608 pinctrl-1 = <&i2c6_pins_sleep>; 609 pinctrl-names = "default", "sleep"; 610 reg = <0x16580000 0x1000>; 611 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&gcc GSBI6_QUP_CLK>, 613 <&gcc GSBI6_H_CLK>; 614 clock-names = "core", "iface"; 615 status = "disabled"; 616 }; 617 }; 618 619 gsbi7: gsbi@16600000 { 620 status = "disabled"; 621 compatible = "qcom,gsbi-v1.0.0"; 622 cell-index = <7>; 623 reg = <0x16600000 0x100>; 624 clocks = <&gcc GSBI7_H_CLK>; 625 clock-names = "iface"; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 ranges; 629 syscon-tcsr = <&tcsr>; 630 631 gsbi7_serial: serial@16640000 { 632 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 633 reg = <0x16640000 0x1000>, 634 <0x16600000 0x1000>; 635 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 637 clock-names = "core", "iface"; 638 status = "disabled"; 639 }; 640 641 gsbi7_i2c: i2c@16680000 { 642 compatible = "qcom,i2c-qup-v1.1.1"; 643 pinctrl-0 = <&i2c7_pins>; 644 pinctrl-1 = <&i2c7_pins_sleep>; 645 pinctrl-names = "default", "sleep"; 646 reg = <0x16680000 0x1000>; 647 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&gcc GSBI7_QUP_CLK>, 649 <&gcc GSBI7_H_CLK>; 650 clock-names = "core", "iface"; 651 status = "disabled"; 652 }; 653 }; 654 655 rng@1a500000 { 656 compatible = "qcom,prng"; 657 reg = <0x1a500000 0x200>; 658 clocks = <&gcc PRNG_CLK>; 659 clock-names = "core"; 660 }; 661 662 ssbi@c00000 { 663 compatible = "qcom,ssbi"; 664 reg = <0x00c00000 0x1000>; 665 qcom,controller-type = "pmic-arbiter"; 666 667 pm8821: pmic@1 { 668 compatible = "qcom,pm8821"; 669 interrupt-parent = <&tlmm_pinmux>; 670 interrupts = <76 IRQ_TYPE_LEVEL_LOW>; 671 #interrupt-cells = <2>; 672 interrupt-controller; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 676 pm8821_mpps: mpps@50 { 677 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp"; 678 reg = <0x50>; 679 interrupts = <24 IRQ_TYPE_NONE>, 680 <25 IRQ_TYPE_NONE>, 681 <26 IRQ_TYPE_NONE>, 682 <27 IRQ_TYPE_NONE>; 683 gpio-controller; 684 #gpio-cells = <2>; 685 }; 686 }; 687 }; 688 689 qcom,ssbi@500000 { 690 compatible = "qcom,ssbi"; 691 reg = <0x00500000 0x1000>; 692 qcom,controller-type = "pmic-arbiter"; 693 694 pmicintc: pmic@0 { 695 compatible = "qcom,pm8921"; 696 interrupt-parent = <&tlmm_pinmux>; 697 interrupts = <74 8>; 698 #interrupt-cells = <2>; 699 interrupt-controller; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 pm8921_gpio: gpio@150 { 704 705 compatible = "qcom,pm8921-gpio", 706 "qcom,ssbi-gpio"; 707 reg = <0x150>; 708 interrupts = <192 IRQ_TYPE_NONE>, 709 <193 IRQ_TYPE_NONE>, 710 <194 IRQ_TYPE_NONE>, 711 <195 IRQ_TYPE_NONE>, 712 <196 IRQ_TYPE_NONE>, 713 <197 IRQ_TYPE_NONE>, 714 <198 IRQ_TYPE_NONE>, 715 <199 IRQ_TYPE_NONE>, 716 <200 IRQ_TYPE_NONE>, 717 <201 IRQ_TYPE_NONE>, 718 <202 IRQ_TYPE_NONE>, 719 <203 IRQ_TYPE_NONE>, 720 <204 IRQ_TYPE_NONE>, 721 <205 IRQ_TYPE_NONE>, 722 <206 IRQ_TYPE_NONE>, 723 <207 IRQ_TYPE_NONE>, 724 <208 IRQ_TYPE_NONE>, 725 <209 IRQ_TYPE_NONE>, 726 <210 IRQ_TYPE_NONE>, 727 <211 IRQ_TYPE_NONE>, 728 <212 IRQ_TYPE_NONE>, 729 <213 IRQ_TYPE_NONE>, 730 <214 IRQ_TYPE_NONE>, 731 <215 IRQ_TYPE_NONE>, 732 <216 IRQ_TYPE_NONE>, 733 <217 IRQ_TYPE_NONE>, 734 <218 IRQ_TYPE_NONE>, 735 <219 IRQ_TYPE_NONE>, 736 <220 IRQ_TYPE_NONE>, 737 <221 IRQ_TYPE_NONE>, 738 <222 IRQ_TYPE_NONE>, 739 <223 IRQ_TYPE_NONE>, 740 <224 IRQ_TYPE_NONE>, 741 <225 IRQ_TYPE_NONE>, 742 <226 IRQ_TYPE_NONE>, 743 <227 IRQ_TYPE_NONE>, 744 <228 IRQ_TYPE_NONE>, 745 <229 IRQ_TYPE_NONE>, 746 <230 IRQ_TYPE_NONE>, 747 <231 IRQ_TYPE_NONE>, 748 <232 IRQ_TYPE_NONE>, 749 <233 IRQ_TYPE_NONE>, 750 <234 IRQ_TYPE_NONE>, 751 <235 IRQ_TYPE_NONE>; 752 gpio-controller; 753 #gpio-cells = <2>; 754 755 }; 756 757 pm8921_mpps: mpps@50 { 758 compatible = "qcom,pm8921-mpp", 759 "qcom,ssbi-mpp"; 760 reg = <0x50>; 761 gpio-controller; 762 #gpio-cells = <2>; 763 interrupts = 764 <128 IRQ_TYPE_NONE>, 765 <129 IRQ_TYPE_NONE>, 766 <130 IRQ_TYPE_NONE>, 767 <131 IRQ_TYPE_NONE>, 768 <132 IRQ_TYPE_NONE>, 769 <133 IRQ_TYPE_NONE>, 770 <134 IRQ_TYPE_NONE>, 771 <135 IRQ_TYPE_NONE>, 772 <136 IRQ_TYPE_NONE>, 773 <137 IRQ_TYPE_NONE>, 774 <138 IRQ_TYPE_NONE>, 775 <139 IRQ_TYPE_NONE>; 776 }; 777 778 rtc@11d { 779 compatible = "qcom,pm8921-rtc"; 780 interrupt-parent = <&pmicintc>; 781 interrupts = <39 1>; 782 reg = <0x11d>; 783 allow-set-time; 784 }; 785 786 pwrkey@1c { 787 compatible = "qcom,pm8921-pwrkey"; 788 reg = <0x1c>; 789 interrupt-parent = <&pmicintc>; 790 interrupts = <50 1>, <51 1>; 791 debounce = <15625>; 792 pull-up; 793 }; 794 795 xoadc: xoadc@197 { 796 compatible = "qcom,pm8921-adc"; 797 reg = <197>; 798 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>; 799 #address-cells = <2>; 800 #size-cells = <0>; 801 #io-channel-cells = <2>; 802 803 vcoin: adc-channel@00 { 804 reg = <0x00 0x00>; 805 }; 806 vbat: adc-channel@01 { 807 reg = <0x00 0x01>; 808 }; 809 dcin: adc-channel@02 { 810 reg = <0x00 0x02>; 811 }; 812 vph_pwr: adc-channel@04 { 813 reg = <0x00 0x04>; 814 }; 815 batt_therm: adc-channel@08 { 816 reg = <0x00 0x08>; 817 }; 818 batt_id: adc-channel@09 { 819 reg = <0x00 0x09>; 820 }; 821 usb_vbus: adc-channel@0a { 822 reg = <0x00 0x0a>; 823 }; 824 die_temp: adc-channel@0b { 825 reg = <0x00 0x0b>; 826 }; 827 ref_625mv: adc-channel@0c { 828 reg = <0x00 0x0c>; 829 }; 830 ref_1250mv: adc-channel@0d { 831 reg = <0x00 0x0d>; 832 }; 833 chg_temp: adc-channel@0e { 834 reg = <0x00 0x0e>; 835 }; 836 ref_muxoff: adc-channel@0f { 837 reg = <0x00 0x0f>; 838 }; 839 }; 840 }; 841 }; 842 843 qfprom: qfprom@700000 { 844 compatible = "qcom,qfprom"; 845 reg = <0x00700000 0x1000>; 846 #address-cells = <1>; 847 #size-cells = <1>; 848 ranges; 849 tsens_calib: calib { 850 reg = <0x404 0x10>; 851 }; 852 tsens_backup: backup_calib { 853 reg = <0x414 0x10>; 854 }; 855 }; 856 857 gcc: clock-controller@900000 { 858 compatible = "qcom,gcc-apq8064"; 859 reg = <0x00900000 0x4000>; 860 nvmem-cells = <&tsens_calib>, <&tsens_backup>; 861 nvmem-cell-names = "calib", "calib_backup"; 862 #clock-cells = <1>; 863 #reset-cells = <1>; 864 #thermal-sensor-cells = <1>; 865 }; 866 867 lcc: clock-controller@28000000 { 868 compatible = "qcom,lcc-apq8064"; 869 reg = <0x28000000 0x1000>; 870 #clock-cells = <1>; 871 #reset-cells = <1>; 872 }; 873 874 mmcc: clock-controller@4000000 { 875 compatible = "qcom,mmcc-apq8064"; 876 reg = <0x4000000 0x1000>; 877 #clock-cells = <1>; 878 #reset-cells = <1>; 879 }; 880 881 l2cc: clock-controller@2011000 { 882 compatible = "syscon"; 883 reg = <0x2011000 0x1000>; 884 }; 885 886 rpm@108000 { 887 compatible = "qcom,rpm-apq8064"; 888 reg = <0x108000 0x1000>; 889 qcom,ipc = <&l2cc 0x8 2>; 890 891 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 892 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 893 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 894 interrupt-names = "ack", "err", "wakeup"; 895 896 rpmcc: clock-controller { 897 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc"; 898 #clock-cells = <1>; 899 }; 900 901 regulators { 902 compatible = "qcom,rpm-pm8921-regulators"; 903 904 pm8921_s1: s1 {}; 905 pm8921_s2: s2 {}; 906 pm8921_s3: s3 {}; 907 pm8921_s4: s4 {}; 908 pm8921_s7: s7 {}; 909 pm8921_s8: s8 {}; 910 911 pm8921_l1: l1 {}; 912 pm8921_l2: l2 {}; 913 pm8921_l3: l3 {}; 914 pm8921_l4: l4 {}; 915 pm8921_l5: l5 {}; 916 pm8921_l6: l6 {}; 917 pm8921_l7: l7 {}; 918 pm8921_l8: l8 {}; 919 pm8921_l9: l9 {}; 920 pm8921_l10: l10 {}; 921 pm8921_l11: l11 {}; 922 pm8921_l12: l12 {}; 923 pm8921_l14: l14 {}; 924 pm8921_l15: l15 {}; 925 pm8921_l16: l16 {}; 926 pm8921_l17: l17 {}; 927 pm8921_l18: l18 {}; 928 pm8921_l21: l21 {}; 929 pm8921_l22: l22 {}; 930 pm8921_l23: l23 {}; 931 pm8921_l24: l24 {}; 932 pm8921_l25: l25 {}; 933 pm8921_l26: l26 {}; 934 pm8921_l27: l27 {}; 935 pm8921_l28: l28 {}; 936 pm8921_l29: l29 {}; 937 938 pm8921_lvs1: lvs1 {}; 939 pm8921_lvs2: lvs2 {}; 940 pm8921_lvs3: lvs3 {}; 941 pm8921_lvs4: lvs4 {}; 942 pm8921_lvs5: lvs5 {}; 943 pm8921_lvs6: lvs6 {}; 944 pm8921_lvs7: lvs7 {}; 945 946 pm8921_usb_switch: usb-switch {}; 947 948 pm8921_hdmi_switch: hdmi-switch { 949 bias-pull-down; 950 }; 951 952 pm8921_ncp: ncp {}; 953 }; 954 }; 955 956 usb1: usb@12500000 { 957 compatible = "qcom,ci-hdrc"; 958 reg = <0x12500000 0x200>, 959 <0x12500200 0x200>; 960 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 961 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; 962 clock-names = "core", "iface"; 963 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>; 964 assigned-clock-rates = <60000000>; 965 resets = <&gcc USB_HS1_RESET>; 966 reset-names = "core"; 967 phy_type = "ulpi"; 968 ahb-burst-config = <0>; 969 phys = <&usb_hs1_phy>; 970 phy-names = "usb-phy"; 971 status = "disabled"; 972 #reset-cells = <1>; 973 974 ulpi { 975 usb_hs1_phy: phy { 976 compatible = "qcom,usb-hs-phy-apq8064", 977 "qcom,usb-hs-phy"; 978 clocks = <&sleep_clk>, <&cxo_board>; 979 clock-names = "sleep", "ref"; 980 resets = <&usb1 0>; 981 reset-names = "por"; 982 #phy-cells = <0>; 983 }; 984 }; 985 }; 986 987 usb3: usb@12520000 { 988 compatible = "qcom,ci-hdrc"; 989 reg = <0x12520000 0x200>, 990 <0x12520200 0x200>; 991 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>; 993 clock-names = "core", "iface"; 994 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>; 995 assigned-clock-rates = <60000000>; 996 resets = <&gcc USB_HS3_RESET>; 997 reset-names = "core"; 998 phy_type = "ulpi"; 999 ahb-burst-config = <0>; 1000 phys = <&usb_hs3_phy>; 1001 phy-names = "usb-phy"; 1002 status = "disabled"; 1003 #reset-cells = <1>; 1004 1005 ulpi { 1006 usb_hs3_phy: phy { 1007 compatible = "qcom,usb-hs-phy-apq8064", 1008 "qcom,usb-hs-phy"; 1009 #phy-cells = <0>; 1010 clocks = <&sleep_clk>, <&cxo_board>; 1011 clock-names = "sleep", "ref"; 1012 resets = <&usb3 0>; 1013 reset-names = "por"; 1014 }; 1015 }; 1016 }; 1017 1018 usb4: usb@12530000 { 1019 compatible = "qcom,ci-hdrc"; 1020 reg = <0x12530000 0x200>, 1021 <0x12530200 0x200>; 1022 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>; 1024 clock-names = "core", "iface"; 1025 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>; 1026 assigned-clock-rates = <60000000>; 1027 resets = <&gcc USB_HS4_RESET>; 1028 reset-names = "core"; 1029 phy_type = "ulpi"; 1030 ahb-burst-config = <0>; 1031 phys = <&usb_hs4_phy>; 1032 phy-names = "usb-phy"; 1033 status = "disabled"; 1034 #reset-cells = <1>; 1035 1036 ulpi { 1037 usb_hs4_phy: phy { 1038 compatible = "qcom,usb-hs-phy-apq8064", 1039 "qcom,usb-hs-phy"; 1040 #phy-cells = <0>; 1041 clocks = <&sleep_clk>, <&cxo_board>; 1042 clock-names = "sleep", "ref"; 1043 resets = <&usb4 0>; 1044 reset-names = "por"; 1045 }; 1046 }; 1047 }; 1048 1049 sata_phy0: phy@1b400000 { 1050 compatible = "qcom,apq8064-sata-phy"; 1051 status = "disabled"; 1052 reg = <0x1b400000 0x200>; 1053 reg-names = "phy_mem"; 1054 clocks = <&gcc SATA_PHY_CFG_CLK>; 1055 clock-names = "cfg"; 1056 #phy-cells = <0>; 1057 }; 1058 1059 sata0: sata@29000000 { 1060 compatible = "qcom,apq8064-ahci", "generic-ahci"; 1061 status = "disabled"; 1062 reg = <0x29000000 0x180>; 1063 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1064 1065 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1066 <&gcc SATA_H_CLK>, 1067 <&gcc SATA_A_CLK>, 1068 <&gcc SATA_RXOOB_CLK>, 1069 <&gcc SATA_PMALIVE_CLK>; 1070 clock-names = "slave_iface", 1071 "iface", 1072 "bus", 1073 "rxoob", 1074 "core_pmalive"; 1075 1076 assigned-clocks = <&gcc SATA_RXOOB_CLK>, 1077 <&gcc SATA_PMALIVE_CLK>; 1078 assigned-clock-rates = <100000000>, <100000000>; 1079 1080 phys = <&sata_phy0>; 1081 phy-names = "sata-phy"; 1082 ports-implemented = <0x1>; 1083 }; 1084 1085 /* Temporary fixed regulator */ 1086 sdcc1bam:dma@12402000{ 1087 compatible = "qcom,bam-v1.3.0"; 1088 reg = <0x12402000 0x8000>; 1089 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&gcc SDC1_H_CLK>; 1091 clock-names = "bam_clk"; 1092 #dma-cells = <1>; 1093 qcom,ee = <0>; 1094 }; 1095 1096 sdcc3bam:dma@12182000{ 1097 compatible = "qcom,bam-v1.3.0"; 1098 reg = <0x12182000 0x8000>; 1099 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&gcc SDC3_H_CLK>; 1101 clock-names = "bam_clk"; 1102 #dma-cells = <1>; 1103 qcom,ee = <0>; 1104 }; 1105 1106 sdcc4bam:dma@121c2000{ 1107 compatible = "qcom,bam-v1.3.0"; 1108 reg = <0x121c2000 0x8000>; 1109 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&gcc SDC4_H_CLK>; 1111 clock-names = "bam_clk"; 1112 #dma-cells = <1>; 1113 qcom,ee = <0>; 1114 }; 1115 1116 amba { 1117 compatible = "simple-bus"; 1118 #address-cells = <1>; 1119 #size-cells = <1>; 1120 ranges; 1121 sdcc1: sdcc@12400000 { 1122 status = "disabled"; 1123 compatible = "arm,pl18x", "arm,primecell"; 1124 pinctrl-names = "default"; 1125 pinctrl-0 = <&sdcc1_pins>; 1126 arm,primecell-periphid = <0x00051180>; 1127 reg = <0x12400000 0x2000>; 1128 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1129 interrupt-names = "cmd_irq"; 1130 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 1131 clock-names = "mclk", "apb_pclk"; 1132 bus-width = <8>; 1133 max-frequency = <96000000>; 1134 non-removable; 1135 cap-sd-highspeed; 1136 cap-mmc-highspeed; 1137 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 1138 dma-names = "tx", "rx"; 1139 }; 1140 1141 sdcc3: sdcc@12180000 { 1142 compatible = "arm,pl18x", "arm,primecell"; 1143 arm,primecell-periphid = <0x00051180>; 1144 status = "disabled"; 1145 reg = <0x12180000 0x2000>; 1146 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1147 interrupt-names = "cmd_irq"; 1148 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 1149 clock-names = "mclk", "apb_pclk"; 1150 bus-width = <4>; 1151 cap-sd-highspeed; 1152 cap-mmc-highspeed; 1153 max-frequency = <192000000>; 1154 no-1-8-v; 1155 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 1156 dma-names = "tx", "rx"; 1157 }; 1158 1159 sdcc4: sdcc@121c0000 { 1160 compatible = "arm,pl18x", "arm,primecell"; 1161 arm,primecell-periphid = <0x00051180>; 1162 status = "disabled"; 1163 reg = <0x121c0000 0x2000>; 1164 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1165 interrupt-names = "cmd_irq"; 1166 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; 1167 clock-names = "mclk", "apb_pclk"; 1168 bus-width = <4>; 1169 cap-sd-highspeed; 1170 cap-mmc-highspeed; 1171 max-frequency = <48000000>; 1172 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; 1173 dma-names = "tx", "rx"; 1174 pinctrl-names = "default"; 1175 pinctrl-0 = <&sdc4_gpios>; 1176 }; 1177 }; 1178 1179 tcsr: syscon@1a400000 { 1180 compatible = "qcom,tcsr-apq8064", "syscon"; 1181 reg = <0x1a400000 0x100>; 1182 }; 1183 1184 gpu: adreno-3xx@4300000 { 1185 compatible = "qcom,adreno-3xx"; 1186 reg = <0x04300000 0x20000>; 1187 reg-names = "kgsl_3d0_reg_memory"; 1188 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1189 interrupt-names = "kgsl_3d0_irq"; 1190 clock-names = 1191 "core_clk", 1192 "iface_clk", 1193 "mem_clk", 1194 "mem_iface_clk"; 1195 clocks = 1196 <&mmcc GFX3D_CLK>, 1197 <&mmcc GFX3D_AHB_CLK>, 1198 <&mmcc GFX3D_AXI_CLK>, 1199 <&mmcc MMSS_IMEM_AHB_CLK>; 1200 qcom,chipid = <0x03020002>; 1201 1202 iommus = <&gfx3d 0 1203 &gfx3d 1 1204 &gfx3d 2 1205 &gfx3d 3 1206 &gfx3d 4 1207 &gfx3d 5 1208 &gfx3d 6 1209 &gfx3d 7 1210 &gfx3d 8 1211 &gfx3d 9 1212 &gfx3d 10 1213 &gfx3d 11 1214 &gfx3d 12 1215 &gfx3d 13 1216 &gfx3d 14 1217 &gfx3d 15 1218 &gfx3d 16 1219 &gfx3d 17 1220 &gfx3d 18 1221 &gfx3d 19 1222 &gfx3d 20 1223 &gfx3d 21 1224 &gfx3d 22 1225 &gfx3d 23 1226 &gfx3d 24 1227 &gfx3d 25 1228 &gfx3d 26 1229 &gfx3d 27 1230 &gfx3d 28 1231 &gfx3d 29 1232 &gfx3d 30 1233 &gfx3d 31 1234 &gfx3d1 0 1235 &gfx3d1 1 1236 &gfx3d1 2 1237 &gfx3d1 3 1238 &gfx3d1 4 1239 &gfx3d1 5 1240 &gfx3d1 6 1241 &gfx3d1 7 1242 &gfx3d1 8 1243 &gfx3d1 9 1244 &gfx3d1 10 1245 &gfx3d1 11 1246 &gfx3d1 12 1247 &gfx3d1 13 1248 &gfx3d1 14 1249 &gfx3d1 15 1250 &gfx3d1 16 1251 &gfx3d1 17 1252 &gfx3d1 18 1253 &gfx3d1 19 1254 &gfx3d1 20 1255 &gfx3d1 21 1256 &gfx3d1 22 1257 &gfx3d1 23 1258 &gfx3d1 24 1259 &gfx3d1 25 1260 &gfx3d1 26 1261 &gfx3d1 27 1262 &gfx3d1 28 1263 &gfx3d1 29 1264 &gfx3d1 30 1265 &gfx3d1 31>; 1266 1267 qcom,gpu-pwrlevels { 1268 compatible = "qcom,gpu-pwrlevels"; 1269 qcom,gpu-pwrlevel@0 { 1270 qcom,gpu-freq = <450000000>; 1271 }; 1272 qcom,gpu-pwrlevel@1 { 1273 qcom,gpu-freq = <27000000>; 1274 }; 1275 }; 1276 }; 1277 1278 mmss_sfpb: syscon@5700000 { 1279 compatible = "syscon"; 1280 reg = <0x5700000 0x70>; 1281 }; 1282 1283 dsi0: mdss_dsi@4700000 { 1284 compatible = "qcom,mdss-dsi-ctrl"; 1285 label = "MDSS DSI CTRL->0"; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1289 reg = <0x04700000 0x200>; 1290 reg-names = "dsi_ctrl"; 1291 1292 clocks = <&mmcc DSI_M_AHB_CLK>, 1293 <&mmcc DSI_S_AHB_CLK>, 1294 <&mmcc AMP_AHB_CLK>, 1295 <&mmcc DSI_CLK>, 1296 <&mmcc DSI1_BYTE_CLK>, 1297 <&mmcc DSI_PIXEL_CLK>, 1298 <&mmcc DSI1_ESC_CLK>; 1299 clock-names = "iface_clk", "bus_clk", "core_mmss_clk", 1300 "src_clk", "byte_clk", "pixel_clk", 1301 "core_clk"; 1302 1303 assigned-clocks = <&mmcc DSI1_BYTE_SRC>, 1304 <&mmcc DSI1_ESC_SRC>, 1305 <&mmcc DSI_SRC>, 1306 <&mmcc DSI_PIXEL_SRC>; 1307 assigned-clock-parents = <&dsi0_phy 0>, 1308 <&dsi0_phy 0>, 1309 <&dsi0_phy 1>, 1310 <&dsi0_phy 1>; 1311 syscon-sfpb = <&mmss_sfpb>; 1312 phys = <&dsi0_phy>; 1313 ports { 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 1317 port@0 { 1318 reg = <0>; 1319 dsi0_in: endpoint { 1320 }; 1321 }; 1322 1323 port@1 { 1324 reg = <1>; 1325 dsi0_out: endpoint { 1326 }; 1327 }; 1328 }; 1329 }; 1330 1331 1332 dsi0_phy: dsi-phy@4700200 { 1333 compatible = "qcom,dsi-phy-28nm-8960"; 1334 #clock-cells = <1>; 1335 #phy-cells = <0>; 1336 1337 reg = <0x04700200 0x100>, 1338 <0x04700300 0x200>, 1339 <0x04700500 0x5c>; 1340 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator"; 1341 clock-names = "iface_clk"; 1342 clocks = <&mmcc DSI_M_AHB_CLK>; 1343 }; 1344 1345 1346 mdp_port0: iommu@7500000 { 1347 compatible = "qcom,apq8064-iommu"; 1348 #iommu-cells = <1>; 1349 clock-names = 1350 "smmu_pclk", 1351 "iommu_clk"; 1352 clocks = 1353 <&mmcc SMMU_AHB_CLK>, 1354 <&mmcc MDP_AXI_CLK>; 1355 reg = <0x07500000 0x100000>; 1356 interrupts = 1357 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1359 qcom,ncb = <2>; 1360 }; 1361 1362 mdp_port1: iommu@7600000 { 1363 compatible = "qcom,apq8064-iommu"; 1364 #iommu-cells = <1>; 1365 clock-names = 1366 "smmu_pclk", 1367 "iommu_clk"; 1368 clocks = 1369 <&mmcc SMMU_AHB_CLK>, 1370 <&mmcc MDP_AXI_CLK>; 1371 reg = <0x07600000 0x100000>; 1372 interrupts = 1373 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1375 qcom,ncb = <2>; 1376 }; 1377 1378 gfx3d: iommu@7c00000 { 1379 compatible = "qcom,apq8064-iommu"; 1380 #iommu-cells = <1>; 1381 clock-names = 1382 "smmu_pclk", 1383 "iommu_clk"; 1384 clocks = 1385 <&mmcc SMMU_AHB_CLK>, 1386 <&mmcc GFX3D_AXI_CLK>; 1387 reg = <0x07c00000 0x100000>; 1388 interrupts = 1389 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 1391 qcom,ncb = <3>; 1392 }; 1393 1394 gfx3d1: iommu@7d00000 { 1395 compatible = "qcom,apq8064-iommu"; 1396 #iommu-cells = <1>; 1397 clock-names = 1398 "smmu_pclk", 1399 "iommu_clk"; 1400 clocks = 1401 <&mmcc SMMU_AHB_CLK>, 1402 <&mmcc GFX3D_AXI_CLK>; 1403 reg = <0x07d00000 0x100000>; 1404 interrupts = 1405 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1407 qcom,ncb = <3>; 1408 }; 1409 1410 pcie: pci@1b500000 { 1411 compatible = "qcom,pcie-apq8064", "snps,dw-pcie"; 1412 reg = <0x1b500000 0x1000 1413 0x1b502000 0x80 1414 0x1b600000 0x100 1415 0x0ff00000 0x100000>; 1416 reg-names = "dbi", "elbi", "parf", "config"; 1417 device_type = "pci"; 1418 linux,pci-domain = <0>; 1419 bus-range = <0x00 0xff>; 1420 num-lanes = <1>; 1421 #address-cells = <3>; 1422 #size-cells = <2>; 1423 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */ 1424 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */ 1425 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1426 interrupt-names = "msi"; 1427 #interrupt-cells = <1>; 1428 interrupt-map-mask = <0 0 0 0x7>; 1429 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1430 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1431 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1432 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1433 clocks = <&gcc PCIE_A_CLK>, 1434 <&gcc PCIE_H_CLK>, 1435 <&gcc PCIE_PHY_REF_CLK>; 1436 clock-names = "core", "iface", "phy"; 1437 resets = <&gcc PCIE_ACLK_RESET>, 1438 <&gcc PCIE_HCLK_RESET>, 1439 <&gcc PCIE_POR_RESET>, 1440 <&gcc PCIE_PCI_RESET>, 1441 <&gcc PCIE_PHY_RESET>; 1442 reset-names = "axi", "ahb", "por", "pci", "phy"; 1443 status = "disabled"; 1444 }; 1445 1446 hdmi: hdmi-tx@4a00000 { 1447 compatible = "qcom,hdmi-tx-8960"; 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&hdmi_pinctrl>; 1450 reg = <0x04a00000 0x2f0>; 1451 reg-names = "core_physical"; 1452 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1453 clocks = <&mmcc HDMI_APP_CLK>, 1454 <&mmcc HDMI_M_AHB_CLK>, 1455 <&mmcc HDMI_S_AHB_CLK>; 1456 clock-names = "core_clk", 1457 "master_iface_clk", 1458 "slave_iface_clk"; 1459 1460 phys = <&hdmi_phy>; 1461 phy-names = "hdmi-phy"; 1462 1463 ports { 1464 #address-cells = <1>; 1465 #size-cells = <0>; 1466 1467 port@0 { 1468 reg = <0>; 1469 hdmi_in: endpoint { 1470 }; 1471 }; 1472 1473 port@1 { 1474 reg = <1>; 1475 hdmi_out: endpoint { 1476 }; 1477 }; 1478 }; 1479 }; 1480 1481 hdmi_phy: hdmi-phy@4a00400 { 1482 compatible = "qcom,hdmi-phy-8960"; 1483 reg = <0x4a00400 0x60>, 1484 <0x4a00500 0x100>; 1485 reg-names = "hdmi_phy", 1486 "hdmi_pll"; 1487 1488 clocks = <&mmcc HDMI_S_AHB_CLK>; 1489 clock-names = "slave_iface_clk"; 1490 #phy-cells = <0>; 1491 }; 1492 1493 mdp: mdp@5100000 { 1494 compatible = "qcom,mdp4"; 1495 reg = <0x05100000 0xf0000>; 1496 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&mmcc MDP_CLK>, 1498 <&mmcc MDP_AHB_CLK>, 1499 <&mmcc MDP_AXI_CLK>, 1500 <&mmcc MDP_LUT_CLK>, 1501 <&mmcc HDMI_TV_CLK>, 1502 <&mmcc MDP_TV_CLK>; 1503 clock-names = "core_clk", 1504 "iface_clk", 1505 "bus_clk", 1506 "lut_clk", 1507 "hdmi_clk", 1508 "tv_clk"; 1509 1510 iommus = <&mdp_port0 0 1511 &mdp_port0 2 1512 &mdp_port1 0 1513 &mdp_port1 2>; 1514 1515 ports { 1516 #address-cells = <1>; 1517 #size-cells = <0>; 1518 1519 port@0 { 1520 reg = <0>; 1521 mdp_lvds_out: endpoint { 1522 }; 1523 }; 1524 1525 port@1 { 1526 reg = <1>; 1527 mdp_dsi1_out: endpoint { 1528 }; 1529 }; 1530 1531 port@2 { 1532 reg = <2>; 1533 mdp_dsi2_out: endpoint { 1534 }; 1535 }; 1536 1537 port@3 { 1538 reg = <3>; 1539 mdp_dtv_out: endpoint { 1540 }; 1541 }; 1542 }; 1543 }; 1544 1545 riva: riva-pil@3204000 { 1546 compatible = "qcom,riva-pil"; 1547 1548 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>; 1549 reg-names = "ccu", "dxe", "pmu"; 1550 1551 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 1552 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>; 1553 interrupt-names = "wdog", "fatal"; 1554 1555 memory-region = <&wcnss_mem>; 1556 1557 vddcx-supply = <&pm8921_s3>; 1558 vddmx-supply = <&pm8921_l24>; 1559 vddpx-supply = <&pm8921_s4>; 1560 1561 status = "disabled"; 1562 1563 iris { 1564 compatible = "qcom,wcn3660"; 1565 1566 clocks = <&cxo_board>; 1567 clock-names = "xo"; 1568 1569 vddxo-supply = <&pm8921_l4>; 1570 vddrfa-supply = <&pm8921_s2>; 1571 vddpa-supply = <&pm8921_l10>; 1572 vdddig-supply = <&pm8921_lvs2>; 1573 }; 1574 1575 smd-edge { 1576 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 1577 1578 qcom,ipc = <&l2cc 8 25>; 1579 qcom,smd-edge = <6>; 1580 1581 label = "riva"; 1582 1583 wcnss { 1584 compatible = "qcom,wcnss"; 1585 qcom,smd-channels = "WCNSS_CTRL"; 1586 1587 qcom,mmio = <&riva>; 1588 1589 bt { 1590 compatible = "qcom,wcnss-bt"; 1591 }; 1592 1593 wifi { 1594 compatible = "qcom,wcnss-wlan"; 1595 1596 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 1598 interrupt-names = "tx", "rx"; 1599 1600 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1601 qcom,smem-state-names = "tx-enable", "tx-rings-empty"; 1602 }; 1603 }; 1604 }; 1605 }; 1606 1607 etb@1a01000 { 1608 compatible = "coresight-etb10", "arm,primecell"; 1609 reg = <0x1a01000 0x1000>; 1610 1611 clocks = <&rpmcc RPM_QDSS_CLK>; 1612 clock-names = "apb_pclk"; 1613 1614 port { 1615 etb_in: endpoint { 1616 slave-mode; 1617 remote-endpoint = <&replicator_out0>; 1618 }; 1619 }; 1620 }; 1621 1622 tpiu@1a03000 { 1623 compatible = "arm,coresight-tpiu", "arm,primecell"; 1624 reg = <0x1a03000 0x1000>; 1625 1626 clocks = <&rpmcc RPM_QDSS_CLK>; 1627 clock-names = "apb_pclk"; 1628 1629 port { 1630 tpiu_in: endpoint { 1631 slave-mode; 1632 remote-endpoint = <&replicator_out1>; 1633 }; 1634 }; 1635 }; 1636 1637 replicator { 1638 compatible = "arm,coresight-replicator"; 1639 1640 clocks = <&rpmcc RPM_QDSS_CLK>; 1641 clock-names = "apb_pclk"; 1642 1643 ports { 1644 #address-cells = <1>; 1645 #size-cells = <0>; 1646 1647 port@0 { 1648 reg = <0>; 1649 replicator_out0: endpoint { 1650 remote-endpoint = <&etb_in>; 1651 }; 1652 }; 1653 port@1 { 1654 reg = <1>; 1655 replicator_out1: endpoint { 1656 remote-endpoint = <&tpiu_in>; 1657 }; 1658 }; 1659 port@2 { 1660 reg = <0>; 1661 replicator_in: endpoint { 1662 slave-mode; 1663 remote-endpoint = <&funnel_out>; 1664 }; 1665 }; 1666 }; 1667 }; 1668 1669 funnel@1a04000 { 1670 compatible = "arm,coresight-funnel", "arm,primecell"; 1671 reg = <0x1a04000 0x1000>; 1672 1673 clocks = <&rpmcc RPM_QDSS_CLK>; 1674 clock-names = "apb_pclk"; 1675 1676 ports { 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 1680 /* 1681 * Not described input ports: 1682 * 2 - connected to STM component 1683 * 3 - not-connected 1684 * 6 - not-connected 1685 * 7 - not-connected 1686 */ 1687 port@0 { 1688 reg = <0>; 1689 funnel_in0: endpoint { 1690 slave-mode; 1691 remote-endpoint = <&etm0_out>; 1692 }; 1693 }; 1694 port@1 { 1695 reg = <1>; 1696 funnel_in1: endpoint { 1697 slave-mode; 1698 remote-endpoint = <&etm1_out>; 1699 }; 1700 }; 1701 port@4 { 1702 reg = <4>; 1703 funnel_in4: endpoint { 1704 slave-mode; 1705 remote-endpoint = <&etm2_out>; 1706 }; 1707 }; 1708 port@5 { 1709 reg = <5>; 1710 funnel_in5: endpoint { 1711 slave-mode; 1712 remote-endpoint = <&etm3_out>; 1713 }; 1714 }; 1715 port@8 { 1716 reg = <0>; 1717 funnel_out: endpoint { 1718 remote-endpoint = <&replicator_in>; 1719 }; 1720 }; 1721 }; 1722 }; 1723 1724 etm@1a1c000 { 1725 compatible = "arm,coresight-etm3x", "arm,primecell"; 1726 reg = <0x1a1c000 0x1000>; 1727 1728 clocks = <&rpmcc RPM_QDSS_CLK>; 1729 clock-names = "apb_pclk"; 1730 1731 cpu = <&CPU0>; 1732 1733 port { 1734 etm0_out: endpoint { 1735 remote-endpoint = <&funnel_in0>; 1736 }; 1737 }; 1738 }; 1739 1740 etm@1a1d000 { 1741 compatible = "arm,coresight-etm3x", "arm,primecell"; 1742 reg = <0x1a1d000 0x1000>; 1743 1744 clocks = <&rpmcc RPM_QDSS_CLK>; 1745 clock-names = "apb_pclk"; 1746 1747 cpu = <&CPU1>; 1748 1749 port { 1750 etm1_out: endpoint { 1751 remote-endpoint = <&funnel_in1>; 1752 }; 1753 }; 1754 }; 1755 1756 etm@1a1e000 { 1757 compatible = "arm,coresight-etm3x", "arm,primecell"; 1758 reg = <0x1a1e000 0x1000>; 1759 1760 clocks = <&rpmcc RPM_QDSS_CLK>; 1761 clock-names = "apb_pclk"; 1762 1763 cpu = <&CPU2>; 1764 1765 port { 1766 etm2_out: endpoint { 1767 remote-endpoint = <&funnel_in4>; 1768 }; 1769 }; 1770 }; 1771 1772 etm@1a1f000 { 1773 compatible = "arm,coresight-etm3x", "arm,primecell"; 1774 reg = <0x1a1f000 0x1000>; 1775 1776 clocks = <&rpmcc RPM_QDSS_CLK>; 1777 clock-names = "apb_pclk"; 1778 1779 cpu = <&CPU3>; 1780 1781 port { 1782 etm3_out: endpoint { 1783 remote-endpoint = <&funnel_in5>; 1784 }; 1785 }; 1786 }; 1787 }; 1788}; 1789#include "qcom-apq8064-pins.dtsi" 1790
