1 /*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <drm/drmP.h>
25 #include <drm/drm_cache.h>
26 #include "amdgpu.h"
27 #include "gmc_v6_0.h"
28 #include "amdgpu_ucode.h"
29
30 #include "bif/bif_3_0_d.h"
31 #include "bif/bif_3_0_sh_mask.h"
32 #include "oss/oss_1_0_d.h"
33 #include "oss/oss_1_0_sh_mask.h"
34 #include "gmc/gmc_6_0_d.h"
35 #include "gmc/gmc_6_0_sh_mask.h"
36 #include "dce/dce_6_0_d.h"
37 #include "dce/dce_6_0_sh_mask.h"
38 #include "si_enums.h"
39
40 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev);
41 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev);
42 static int gmc_v6_0_wait_for_idle(void *handle);
43
44 MODULE_FIRMWARE("amdgpu/tahiti_mc.bin");
45 MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin");
46 MODULE_FIRMWARE("amdgpu/verde_mc.bin");
47 MODULE_FIRMWARE("amdgpu/oland_mc.bin");
48 MODULE_FIRMWARE("amdgpu/si58_mc.bin");
49
50 #define MC_SEQ_MISC0__MT__MASK 0xf0000000
51 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000
52 #define MC_SEQ_MISC0__MT__DDR2 0x20000000
53 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000
54 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000
55 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000
56 #define MC_SEQ_MISC0__MT__HBM 0x60000000
57 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000
58
59
60 static const u32 crtc_offsets[6] =
61 {
62 SI_CRTC0_REGISTER_OFFSET,
63 SI_CRTC1_REGISTER_OFFSET,
64 SI_CRTC2_REGISTER_OFFSET,
65 SI_CRTC3_REGISTER_OFFSET,
66 SI_CRTC4_REGISTER_OFFSET,
67 SI_CRTC5_REGISTER_OFFSET
68 };
69
gmc_v6_0_mc_stop(struct amdgpu_device * adev)70 static void gmc_v6_0_mc_stop(struct amdgpu_device *adev)
71 {
72 u32 blackout;
73
74 gmc_v6_0_wait_for_idle((void *)adev);
75
76 blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
77 if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) {
78 /* Block CPU access */
79 WREG32(mmBIF_FB_EN, 0);
80 /* blackout the MC */
81 blackout = REG_SET_FIELD(blackout,
82 MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
83 WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
84 }
85 /* wait for the MC to settle */
86 udelay(100);
87
88 }
89
gmc_v6_0_mc_resume(struct amdgpu_device * adev)90 static void gmc_v6_0_mc_resume(struct amdgpu_device *adev)
91 {
92 u32 tmp;
93
94 /* unblackout the MC */
95 tmp = RREG32(mmMC_SHARED_BLACKOUT_CNTL);
96 tmp = REG_SET_FIELD(tmp, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE, 0);
97 WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
98 /* allow CPU access */
99 tmp = REG_SET_FIELD(0, BIF_FB_EN, FB_READ_EN, 1);
100 tmp = REG_SET_FIELD(tmp, BIF_FB_EN, FB_WRITE_EN, 1);
101 WREG32(mmBIF_FB_EN, tmp);
102 }
103
gmc_v6_0_init_microcode(struct amdgpu_device * adev)104 static int gmc_v6_0_init_microcode(struct amdgpu_device *adev)
105 {
106 const char *chip_name;
107 char fw_name[30];
108 int err;
109 bool is_58_fw = false;
110
111 DRM_DEBUG("\n");
112
113 switch (adev->asic_type) {
114 case CHIP_TAHITI:
115 chip_name = "tahiti";
116 break;
117 case CHIP_PITCAIRN:
118 chip_name = "pitcairn";
119 break;
120 case CHIP_VERDE:
121 chip_name = "verde";
122 break;
123 case CHIP_OLAND:
124 chip_name = "oland";
125 break;
126 case CHIP_HAINAN:
127 chip_name = "hainan";
128 break;
129 default: BUG();
130 }
131
132 /* this memory configuration requires special firmware */
133 if (((RREG32(mmMC_SEQ_MISC0) & 0xff000000) >> 24) == 0x58)
134 is_58_fw = true;
135
136 if (is_58_fw)
137 snprintf(fw_name, sizeof(fw_name), "amdgpu/si58_mc.bin");
138 else
139 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
140 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev);
141 if (err)
142 goto out;
143
144 err = amdgpu_ucode_validate(adev->gmc.fw);
145
146 out:
147 if (err) {
148 dev_err(adev->dev,
149 "si_mc: Failed to load firmware \"%s\"\n",
150 fw_name);
151 release_firmware(adev->gmc.fw);
152 adev->gmc.fw = NULL;
153 }
154 return err;
155 }
156
gmc_v6_0_mc_load_microcode(struct amdgpu_device * adev)157 static int gmc_v6_0_mc_load_microcode(struct amdgpu_device *adev)
158 {
159 const __le32 *new_fw_data = NULL;
160 u32 running;
161 const __le32 *new_io_mc_regs = NULL;
162 int i, regs_size, ucode_size;
163 const struct mc_firmware_header_v1_0 *hdr;
164
165 if (!adev->gmc.fw)
166 return -EINVAL;
167
168 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data;
169
170 amdgpu_ucode_print_mc_hdr(&hdr->header);
171
172 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version);
173 regs_size = le32_to_cpu(hdr->io_debug_size_bytes) / (4 * 2);
174 new_io_mc_regs = (const __le32 *)
175 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes));
176 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
177 new_fw_data = (const __le32 *)
178 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
179
180 running = RREG32(mmMC_SEQ_SUP_CNTL) & MC_SEQ_SUP_CNTL__RUN_MASK;
181
182 if (running == 0) {
183
184 /* reset the engine and set to writable */
185 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
186 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
187
188 /* load mc io regs */
189 for (i = 0; i < regs_size; i++) {
190 WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
191 WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
192 }
193 /* load the MC ucode */
194 for (i = 0; i < ucode_size; i++) {
195 WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
196 }
197
198 /* put the engine back into the active state */
199 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
200 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
201 WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
202
203 /* wait for training to complete */
204 for (i = 0; i < adev->usec_timeout; i++) {
205 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D0_MASK)
206 break;
207 udelay(1);
208 }
209 for (i = 0; i < adev->usec_timeout; i++) {
210 if (RREG32(mmMC_SEQ_TRAIN_WAKEUP_CNTL) & MC_SEQ_TRAIN_WAKEUP_CNTL__TRAIN_DONE_D1_MASK)
211 break;
212 udelay(1);
213 }
214
215 }
216
217 return 0;
218 }
219
gmc_v6_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)220 static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev,
221 struct amdgpu_gmc *mc)
222 {
223 u64 base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF;
224 base <<= 24;
225
226 amdgpu_device_vram_location(adev, &adev->gmc, base);
227 amdgpu_device_gart_location(adev, mc);
228 }
229
gmc_v6_0_mc_program(struct amdgpu_device * adev)230 static void gmc_v6_0_mc_program(struct amdgpu_device *adev)
231 {
232 int i, j;
233
234 /* Initialize HDP */
235 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
236 WREG32((0xb05 + j), 0x00000000);
237 WREG32((0xb06 + j), 0x00000000);
238 WREG32((0xb07 + j), 0x00000000);
239 WREG32((0xb08 + j), 0x00000000);
240 WREG32((0xb09 + j), 0x00000000);
241 }
242 WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
243
244 if (gmc_v6_0_wait_for_idle((void *)adev)) {
245 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
246 }
247
248 if (adev->mode_info.num_crtc) {
249 u32 tmp;
250
251 /* Lockout access through VGA aperture*/
252 tmp = RREG32(mmVGA_HDP_CONTROL);
253 tmp |= VGA_HDP_CONTROL__VGA_MEMORY_DISABLE_MASK;
254 WREG32(mmVGA_HDP_CONTROL, tmp);
255
256 /* disable VGA render */
257 tmp = RREG32(mmVGA_RENDER_CONTROL);
258 tmp &= ~VGA_VSTATUS_CNTL;
259 WREG32(mmVGA_RENDER_CONTROL, tmp);
260 }
261 /* Update configuration */
262 WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
263 adev->gmc.vram_start >> 12);
264 WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
265 adev->gmc.vram_end >> 12);
266 WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
267 adev->vram_scratch.gpu_addr >> 12);
268 WREG32(mmMC_VM_AGP_BASE, 0);
269 WREG32(mmMC_VM_AGP_TOP, 0x0FFFFFFF);
270 WREG32(mmMC_VM_AGP_BOT, 0x0FFFFFFF);
271
272 if (gmc_v6_0_wait_for_idle((void *)adev)) {
273 dev_warn(adev->dev, "Wait for MC idle timedout !\n");
274 }
275 }
276
gmc_v6_0_mc_init(struct amdgpu_device * adev)277 static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
278 {
279
280 u32 tmp;
281 int chansize, numchan;
282 int r;
283
284 tmp = RREG32(mmMC_ARB_RAMCFG);
285 if (tmp & (1 << 11)) {
286 chansize = 16;
287 } else if (tmp & MC_ARB_RAMCFG__CHANSIZE_MASK) {
288 chansize = 64;
289 } else {
290 chansize = 32;
291 }
292 tmp = RREG32(mmMC_SHARED_CHMAP);
293 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
294 case 0:
295 default:
296 numchan = 1;
297 break;
298 case 1:
299 numchan = 2;
300 break;
301 case 2:
302 numchan = 4;
303 break;
304 case 3:
305 numchan = 8;
306 break;
307 case 4:
308 numchan = 3;
309 break;
310 case 5:
311 numchan = 6;
312 break;
313 case 6:
314 numchan = 10;
315 break;
316 case 7:
317 numchan = 12;
318 break;
319 case 8:
320 numchan = 16;
321 break;
322 }
323 adev->gmc.vram_width = numchan * chansize;
324 /* size in MB on si */
325 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
326 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL;
327
328 if (!(adev->flags & AMD_IS_APU)) {
329 r = amdgpu_device_resize_fb_bar(adev);
330 if (r)
331 return r;
332 }
333 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
334 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
335 adev->gmc.visible_vram_size = adev->gmc.aper_size;
336
337 /* set the gart size */
338 if (amdgpu_gart_size == -1) {
339 switch (adev->asic_type) {
340 case CHIP_HAINAN: /* no MM engines */
341 default:
342 adev->gmc.gart_size = 256ULL << 20;
343 break;
344 case CHIP_VERDE: /* UVD, VCE do not support GPUVM */
345 case CHIP_TAHITI: /* UVD, VCE do not support GPUVM */
346 case CHIP_PITCAIRN: /* UVD, VCE do not support GPUVM */
347 case CHIP_OLAND: /* UVD, VCE do not support GPUVM */
348 adev->gmc.gart_size = 1024ULL << 20;
349 break;
350 }
351 } else {
352 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
353 }
354
355 gmc_v6_0_vram_gtt_location(adev, &adev->gmc);
356
357 return 0;
358 }
359
gmc_v6_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid)360 static void gmc_v6_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid)
361 {
362 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
363 }
364
gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)365 static uint64_t gmc_v6_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
366 unsigned vmid, uint64_t pd_addr)
367 {
368 uint32_t reg;
369
370 /* write new base address */
371 if (vmid < 8)
372 reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
373 else
374 reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8);
375 amdgpu_ring_emit_wreg(ring, reg, pd_addr >> 12);
376
377 /* bits 0-15 are the VM contexts0-15 */
378 amdgpu_ring_emit_wreg(ring, mmVM_INVALIDATE_REQUEST, 1 << vmid);
379
380 return pd_addr;
381 }
382
gmc_v6_0_set_pte_pde(struct amdgpu_device * adev,void * cpu_pt_addr,uint32_t gpu_page_idx,uint64_t addr,uint64_t flags)383 static int gmc_v6_0_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr,
384 uint32_t gpu_page_idx, uint64_t addr,
385 uint64_t flags)
386 {
387 void __iomem *ptr = (void *)cpu_pt_addr;
388 uint64_t value;
389
390 value = addr & 0xFFFFFFFFFFFFF000ULL;
391 value |= flags;
392 writeq(value, ptr + (gpu_page_idx * 8));
393
394 return 0;
395 }
396
gmc_v6_0_get_vm_pte_flags(struct amdgpu_device * adev,uint32_t flags)397 static uint64_t gmc_v6_0_get_vm_pte_flags(struct amdgpu_device *adev,
398 uint32_t flags)
399 {
400 uint64_t pte_flag = 0;
401
402 if (flags & AMDGPU_VM_PAGE_READABLE)
403 pte_flag |= AMDGPU_PTE_READABLE;
404 if (flags & AMDGPU_VM_PAGE_WRITEABLE)
405 pte_flag |= AMDGPU_PTE_WRITEABLE;
406 if (flags & AMDGPU_VM_PAGE_PRT)
407 pte_flag |= AMDGPU_PTE_PRT;
408
409 return pte_flag;
410 }
411
gmc_v6_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)412 static void gmc_v6_0_get_vm_pde(struct amdgpu_device *adev, int level,
413 uint64_t *addr, uint64_t *flags)
414 {
415 BUG_ON(*addr & 0xFFFFFF0000000FFFULL);
416 }
417
gmc_v6_0_set_fault_enable_default(struct amdgpu_device * adev,bool value)418 static void gmc_v6_0_set_fault_enable_default(struct amdgpu_device *adev,
419 bool value)
420 {
421 u32 tmp;
422
423 tmp = RREG32(mmVM_CONTEXT1_CNTL);
424 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
425 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
426 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
427 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
428 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
429 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
430 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
431 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
432 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
433 READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
434 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
435 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
436 WREG32(mmVM_CONTEXT1_CNTL, tmp);
437 }
438
439 /**
440 + * gmc_v8_0_set_prt - set PRT VM fault
441 + *
442 + * @adev: amdgpu_device pointer
443 + * @enable: enable/disable VM fault handling for PRT
444 +*/
gmc_v6_0_set_prt(struct amdgpu_device * adev,bool enable)445 static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
446 {
447 u32 tmp;
448
449 if (enable && !adev->gmc.prt_warning) {
450 dev_warn(adev->dev, "Disabling VM faults because of PRT request!\n");
451 adev->gmc.prt_warning = true;
452 }
453
454 tmp = RREG32(mmVM_PRT_CNTL);
455 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
456 CB_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
457 enable);
458 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
459 TC_DISABLE_FAULT_ON_UNMAPPED_ACCESS,
460 enable);
461 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
462 L2_CACHE_STORE_INVALID_ENTRIES,
463 enable);
464 tmp = REG_SET_FIELD(tmp, VM_PRT_CNTL,
465 L1_TLB_STORE_INVALID_ENTRIES,
466 enable);
467 WREG32(mmVM_PRT_CNTL, tmp);
468
469 if (enable) {
470 uint32_t low = AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT;
471 uint32_t high = adev->vm_manager.max_pfn -
472 (AMDGPU_VA_RESERVED_SIZE >> AMDGPU_GPU_PAGE_SHIFT);
473
474 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
475 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
476 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
477 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
478 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
479 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
480 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
481 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
482 } else {
483 WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
484 WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
485 WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
486 WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
487 WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
488 WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
489 WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
490 WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
491 }
492 }
493
gmc_v6_0_gart_enable(struct amdgpu_device * adev)494 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
495 {
496 int r, i;
497 u32 field;
498
499 if (adev->gart.robj == NULL) {
500 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
501 return -EINVAL;
502 }
503 r = amdgpu_gart_table_vram_pin(adev);
504 if (r)
505 return r;
506 /* Setup TLB control */
507 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
508 (0xA << 7) |
509 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK |
510 MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_FRAGMENT_PROCESSING_MASK |
511 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
512 MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK |
513 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
514 /* Setup L2 cache */
515 WREG32(mmVM_L2_CNTL,
516 VM_L2_CNTL__ENABLE_L2_CACHE_MASK |
517 VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK |
518 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
519 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
520 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
521 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
522 WREG32(mmVM_L2_CNTL2,
523 VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK |
524 VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK);
525
526 field = adev->vm_manager.fragment_size;
527 WREG32(mmVM_L2_CNTL3,
528 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
529 (field << VM_L2_CNTL3__BANK_SELECT__SHIFT) |
530 (field << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
531 /* setup context0 */
532 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
533 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
534 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
535 WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
536 (u32)(adev->dummy_page_addr >> 12));
537 WREG32(mmVM_CONTEXT0_CNTL2, 0);
538 WREG32(mmVM_CONTEXT0_CNTL,
539 VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK |
540 (0UL << VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
541 VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK);
542
543 WREG32(0x575, 0);
544 WREG32(0x576, 0);
545 WREG32(0x577, 0);
546
547 /* empty context1-15 */
548 /* set vm size, must be a multiple of 4 */
549 WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
550 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
551 /* Assign the pt base to something valid for now; the pts used for
552 * the VMs are determined by the application and setup and assigned
553 * on the fly in the vm part of radeon_gart.c
554 */
555 for (i = 1; i < 16; i++) {
556 if (i < 8)
557 WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
558 adev->gart.table_addr >> 12);
559 else
560 WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
561 adev->gart.table_addr >> 12);
562 }
563
564 /* enable context1-15 */
565 WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
566 (u32)(adev->dummy_page_addr >> 12));
567 WREG32(mmVM_CONTEXT1_CNTL2, 4);
568 WREG32(mmVM_CONTEXT1_CNTL,
569 VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK |
570 (1UL << VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT) |
571 ((adev->vm_manager.block_size - 9)
572 << VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT));
573 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
574 gmc_v6_0_set_fault_enable_default(adev, false);
575 else
576 gmc_v6_0_set_fault_enable_default(adev, true);
577
578 gmc_v6_0_flush_gpu_tlb(adev, 0);
579 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
580 (unsigned)(adev->gmc.gart_size >> 20),
581 (unsigned long long)adev->gart.table_addr);
582 adev->gart.ready = true;
583 return 0;
584 }
585
gmc_v6_0_gart_init(struct amdgpu_device * adev)586 static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
587 {
588 int r;
589
590 if (adev->gart.robj) {
591 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
592 return 0;
593 }
594 r = amdgpu_gart_init(adev);
595 if (r)
596 return r;
597 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
598 adev->gart.gart_pte_flags = 0;
599 return amdgpu_gart_table_vram_alloc(adev);
600 }
601
gmc_v6_0_gart_disable(struct amdgpu_device * adev)602 static void gmc_v6_0_gart_disable(struct amdgpu_device *adev)
603 {
604 /*unsigned i;
605
606 for (i = 1; i < 16; ++i) {
607 uint32_t reg;
608 if (i < 8)
609 reg = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i ;
610 else
611 reg = VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (i - 8);
612 adev->vm_manager.saved_table_addr[i] = RREG32(reg);
613 }*/
614
615 /* Disable all tables */
616 WREG32(mmVM_CONTEXT0_CNTL, 0);
617 WREG32(mmVM_CONTEXT1_CNTL, 0);
618 /* Setup TLB control */
619 WREG32(mmMC_VM_MX_L1_TLB_CNTL,
620 MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK |
621 (0UL << MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT));
622 /* Setup L2 cache */
623 WREG32(mmVM_L2_CNTL,
624 VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK |
625 VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK |
626 (7UL << VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT) |
627 (1UL << VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT));
628 WREG32(mmVM_L2_CNTL2, 0);
629 WREG32(mmVM_L2_CNTL3,
630 VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK |
631 (0UL << VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT));
632 amdgpu_gart_table_vram_unpin(adev);
633 }
634
gmc_v6_0_vm_decode_fault(struct amdgpu_device * adev,u32 status,u32 addr,u32 mc_client)635 static void gmc_v6_0_vm_decode_fault(struct amdgpu_device *adev,
636 u32 status, u32 addr, u32 mc_client)
637 {
638 u32 mc_id;
639 u32 vmid = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS, VMID);
640 u32 protections = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
641 PROTECTIONS);
642 char block[5] = { mc_client >> 24, (mc_client >> 16) & 0xff,
643 (mc_client >> 8) & 0xff, mc_client & 0xff, 0 };
644
645 mc_id = REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
646 MEMORY_CLIENT_ID);
647
648 dev_err(adev->dev, "VM fault (0x%02x, vmid %d) at page %u, %s from '%s' (0x%08x) (%d)\n",
649 protections, vmid, addr,
650 REG_GET_FIELD(status, VM_CONTEXT1_PROTECTION_FAULT_STATUS,
651 MEMORY_CLIENT_RW) ?
652 "write" : "read", block, mc_client, mc_id);
653 }
654
655 /*
656 static const u32 mc_cg_registers[] = {
657 MC_HUB_MISC_HUB_CG,
658 MC_HUB_MISC_SIP_CG,
659 MC_HUB_MISC_VM_CG,
660 MC_XPB_CLK_GAT,
661 ATC_MISC_CG,
662 MC_CITF_MISC_WR_CG,
663 MC_CITF_MISC_RD_CG,
664 MC_CITF_MISC_VM_CG,
665 VM_L2_CG,
666 };
667
668 static const u32 mc_cg_ls_en[] = {
669 MC_HUB_MISC_HUB_CG__MEM_LS_ENABLE_MASK,
670 MC_HUB_MISC_SIP_CG__MEM_LS_ENABLE_MASK,
671 MC_HUB_MISC_VM_CG__MEM_LS_ENABLE_MASK,
672 MC_XPB_CLK_GAT__MEM_LS_ENABLE_MASK,
673 ATC_MISC_CG__MEM_LS_ENABLE_MASK,
674 MC_CITF_MISC_WR_CG__MEM_LS_ENABLE_MASK,
675 MC_CITF_MISC_RD_CG__MEM_LS_ENABLE_MASK,
676 MC_CITF_MISC_VM_CG__MEM_LS_ENABLE_MASK,
677 VM_L2_CG__MEM_LS_ENABLE_MASK,
678 };
679
680 static const u32 mc_cg_en[] = {
681 MC_HUB_MISC_HUB_CG__ENABLE_MASK,
682 MC_HUB_MISC_SIP_CG__ENABLE_MASK,
683 MC_HUB_MISC_VM_CG__ENABLE_MASK,
684 MC_XPB_CLK_GAT__ENABLE_MASK,
685 ATC_MISC_CG__ENABLE_MASK,
686 MC_CITF_MISC_WR_CG__ENABLE_MASK,
687 MC_CITF_MISC_RD_CG__ENABLE_MASK,
688 MC_CITF_MISC_VM_CG__ENABLE_MASK,
689 VM_L2_CG__ENABLE_MASK,
690 };
691
692 static void gmc_v6_0_enable_mc_ls(struct amdgpu_device *adev,
693 bool enable)
694 {
695 int i;
696 u32 orig, data;
697
698 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
699 orig = data = RREG32(mc_cg_registers[i]);
700 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_LS))
701 data |= mc_cg_ls_en[i];
702 else
703 data &= ~mc_cg_ls_en[i];
704 if (data != orig)
705 WREG32(mc_cg_registers[i], data);
706 }
707 }
708
709 static void gmc_v6_0_enable_mc_mgcg(struct amdgpu_device *adev,
710 bool enable)
711 {
712 int i;
713 u32 orig, data;
714
715 for (i = 0; i < ARRAY_SIZE(mc_cg_registers); i++) {
716 orig = data = RREG32(mc_cg_registers[i]);
717 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_MC_MGCG))
718 data |= mc_cg_en[i];
719 else
720 data &= ~mc_cg_en[i];
721 if (data != orig)
722 WREG32(mc_cg_registers[i], data);
723 }
724 }
725
726 static void gmc_v6_0_enable_bif_mgls(struct amdgpu_device *adev,
727 bool enable)
728 {
729 u32 orig, data;
730
731 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
732
733 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_BIF_LS)) {
734 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 1);
735 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 1);
736 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 1);
737 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 1);
738 } else {
739 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_LS_EN, 0);
740 data = REG_SET_FIELD(data, PCIE_CNTL2, MST_MEM_LS_EN, 0);
741 data = REG_SET_FIELD(data, PCIE_CNTL2, REPLAY_MEM_LS_EN, 0);
742 data = REG_SET_FIELD(data, PCIE_CNTL2, SLV_MEM_AGGRESSIVE_LS_EN, 0);
743 }
744
745 if (orig != data)
746 WREG32_PCIE(ixPCIE_CNTL2, data);
747 }
748
749 static void gmc_v6_0_enable_hdp_mgcg(struct amdgpu_device *adev,
750 bool enable)
751 {
752 u32 orig, data;
753
754 orig = data = RREG32(mmHDP_HOST_PATH_CNTL);
755
756 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_MGCG))
757 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 0);
758 else
759 data = REG_SET_FIELD(data, HDP_HOST_PATH_CNTL, CLOCK_GATING_DIS, 1);
760
761 if (orig != data)
762 WREG32(mmHDP_HOST_PATH_CNTL, data);
763 }
764
765 static void gmc_v6_0_enable_hdp_ls(struct amdgpu_device *adev,
766 bool enable)
767 {
768 u32 orig, data;
769
770 orig = data = RREG32(mmHDP_MEM_POWER_LS);
771
772 if (enable && (adev->cg_flags & AMDGPU_CG_SUPPORT_HDP_LS))
773 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 1);
774 else
775 data = REG_SET_FIELD(data, HDP_MEM_POWER_LS, LS_ENABLE, 0);
776
777 if (orig != data)
778 WREG32(mmHDP_MEM_POWER_LS, data);
779 }
780 */
781
gmc_v6_0_convert_vram_type(int mc_seq_vram_type)782 static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type)
783 {
784 switch (mc_seq_vram_type) {
785 case MC_SEQ_MISC0__MT__GDDR1:
786 return AMDGPU_VRAM_TYPE_GDDR1;
787 case MC_SEQ_MISC0__MT__DDR2:
788 return AMDGPU_VRAM_TYPE_DDR2;
789 case MC_SEQ_MISC0__MT__GDDR3:
790 return AMDGPU_VRAM_TYPE_GDDR3;
791 case MC_SEQ_MISC0__MT__GDDR4:
792 return AMDGPU_VRAM_TYPE_GDDR4;
793 case MC_SEQ_MISC0__MT__GDDR5:
794 return AMDGPU_VRAM_TYPE_GDDR5;
795 case MC_SEQ_MISC0__MT__DDR3:
796 return AMDGPU_VRAM_TYPE_DDR3;
797 default:
798 return AMDGPU_VRAM_TYPE_UNKNOWN;
799 }
800 }
801
gmc_v6_0_early_init(void * handle)802 static int gmc_v6_0_early_init(void *handle)
803 {
804 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
805
806 gmc_v6_0_set_gmc_funcs(adev);
807 gmc_v6_0_set_irq_funcs(adev);
808
809 return 0;
810 }
811
gmc_v6_0_late_init(void * handle)812 static int gmc_v6_0_late_init(void *handle)
813 {
814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
815
816 amdgpu_bo_late_init(adev);
817
818 if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS)
819 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
820 else
821 return 0;
822 }
823
gmc_v6_0_get_vbios_fb_size(struct amdgpu_device * adev)824 static unsigned gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev)
825 {
826 u32 d1vga_control = RREG32(mmD1VGA_CONTROL);
827 unsigned size;
828
829 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
830 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
831 } else {
832 u32 viewport = RREG32(mmVIEWPORT_SIZE);
833 size = (REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
834 REG_GET_FIELD(viewport, VIEWPORT_SIZE, VIEWPORT_WIDTH) *
835 4);
836 }
837 /* return 0 if the pre-OS buffer uses up most of vram */
838 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024))
839 return 0;
840 return size;
841 }
842
gmc_v6_0_sw_init(void * handle)843 static int gmc_v6_0_sw_init(void *handle)
844 {
845 int r;
846 int dma_bits;
847 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
848
849 if (adev->flags & AMD_IS_APU) {
850 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
851 } else {
852 u32 tmp = RREG32(mmMC_SEQ_MISC0);
853 tmp &= MC_SEQ_MISC0__MT__MASK;
854 adev->gmc.vram_type = gmc_v6_0_convert_vram_type(tmp);
855 }
856
857 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
858 if (r)
859 return r;
860
861 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
862 if (r)
863 return r;
864
865 amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
866
867 adev->gmc.mc_mask = 0xffffffffffULL;
868
869 adev->need_dma32 = false;
870 dma_bits = adev->need_dma32 ? 32 : 40;
871 r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
872 if (r) {
873 adev->need_dma32 = true;
874 dma_bits = 32;
875 dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
876 }
877 r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
878 if (r) {
879 pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
880 dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
881 }
882 adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
883
884 r = gmc_v6_0_init_microcode(adev);
885 if (r) {
886 dev_err(adev->dev, "Failed to load mc firmware!\n");
887 return r;
888 }
889
890 r = gmc_v6_0_mc_init(adev);
891 if (r)
892 return r;
893
894 adev->gmc.stolen_size = gmc_v6_0_get_vbios_fb_size(adev);
895
896 r = amdgpu_bo_init(adev);
897 if (r)
898 return r;
899
900 r = gmc_v6_0_gart_init(adev);
901 if (r)
902 return r;
903
904 /*
905 * number of VMs
906 * VMID 0 is reserved for System
907 * amdgpu graphics/compute will use VMIDs 1-7
908 * amdkfd will use VMIDs 8-15
909 */
910 adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
911 amdgpu_vm_manager_init(adev);
912
913 /* base offset of vram pages */
914 if (adev->flags & AMD_IS_APU) {
915 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
916
917 tmp <<= 22;
918 adev->vm_manager.vram_base_offset = tmp;
919 } else {
920 adev->vm_manager.vram_base_offset = 0;
921 }
922
923 return 0;
924 }
925
gmc_v6_0_sw_fini(void * handle)926 static int gmc_v6_0_sw_fini(void *handle)
927 {
928 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
929
930 amdgpu_gem_force_release(adev);
931 amdgpu_vm_manager_fini(adev);
932 amdgpu_gart_table_vram_free(adev);
933 amdgpu_bo_fini(adev);
934 amdgpu_gart_fini(adev);
935 release_firmware(adev->gmc.fw);
936 adev->gmc.fw = NULL;
937
938 return 0;
939 }
940
gmc_v6_0_hw_init(void * handle)941 static int gmc_v6_0_hw_init(void *handle)
942 {
943 int r;
944 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
945
946 gmc_v6_0_mc_program(adev);
947
948 if (!(adev->flags & AMD_IS_APU)) {
949 r = gmc_v6_0_mc_load_microcode(adev);
950 if (r) {
951 dev_err(adev->dev, "Failed to load MC firmware!\n");
952 return r;
953 }
954 }
955
956 r = gmc_v6_0_gart_enable(adev);
957 if (r)
958 return r;
959
960 return r;
961 }
962
gmc_v6_0_hw_fini(void * handle)963 static int gmc_v6_0_hw_fini(void *handle)
964 {
965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
966
967 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
968 gmc_v6_0_gart_disable(adev);
969
970 return 0;
971 }
972
gmc_v6_0_suspend(void * handle)973 static int gmc_v6_0_suspend(void *handle)
974 {
975 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
976
977 gmc_v6_0_hw_fini(adev);
978
979 return 0;
980 }
981
gmc_v6_0_resume(void * handle)982 static int gmc_v6_0_resume(void *handle)
983 {
984 int r;
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
986
987 r = gmc_v6_0_hw_init(adev);
988 if (r)
989 return r;
990
991 amdgpu_vmid_reset_all(adev);
992
993 return 0;
994 }
995
gmc_v6_0_is_idle(void * handle)996 static bool gmc_v6_0_is_idle(void *handle)
997 {
998 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
999 u32 tmp = RREG32(mmSRBM_STATUS);
1000
1001 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1002 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK | SRBM_STATUS__VMC_BUSY_MASK))
1003 return false;
1004
1005 return true;
1006 }
1007
gmc_v6_0_wait_for_idle(void * handle)1008 static int gmc_v6_0_wait_for_idle(void *handle)
1009 {
1010 unsigned i;
1011 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1012
1013 for (i = 0; i < adev->usec_timeout; i++) {
1014 if (gmc_v6_0_is_idle(handle))
1015 return 0;
1016 udelay(1);
1017 }
1018 return -ETIMEDOUT;
1019
1020 }
1021
gmc_v6_0_soft_reset(void * handle)1022 static int gmc_v6_0_soft_reset(void *handle)
1023 {
1024 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1025 u32 srbm_soft_reset = 0;
1026 u32 tmp = RREG32(mmSRBM_STATUS);
1027
1028 if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
1029 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1030 SRBM_SOFT_RESET, SOFT_RESET_VMC, 1);
1031
1032 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1033 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1034 if (!(adev->flags & AMD_IS_APU))
1035 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1036 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1037 }
1038
1039 if (srbm_soft_reset) {
1040 gmc_v6_0_mc_stop(adev);
1041 if (gmc_v6_0_wait_for_idle(adev)) {
1042 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
1043 }
1044
1045
1046 tmp = RREG32(mmSRBM_SOFT_RESET);
1047 tmp |= srbm_soft_reset;
1048 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1049 WREG32(mmSRBM_SOFT_RESET, tmp);
1050 tmp = RREG32(mmSRBM_SOFT_RESET);
1051
1052 udelay(50);
1053
1054 tmp &= ~srbm_soft_reset;
1055 WREG32(mmSRBM_SOFT_RESET, tmp);
1056 tmp = RREG32(mmSRBM_SOFT_RESET);
1057
1058 udelay(50);
1059
1060 gmc_v6_0_mc_resume(adev);
1061 udelay(50);
1062 }
1063
1064 return 0;
1065 }
1066
gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)1067 static int gmc_v6_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
1068 struct amdgpu_irq_src *src,
1069 unsigned type,
1070 enum amdgpu_interrupt_state state)
1071 {
1072 u32 tmp;
1073 u32 bits = (VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1074 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1075 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1076 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1077 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
1078 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK);
1079
1080 switch (state) {
1081 case AMDGPU_IRQ_STATE_DISABLE:
1082 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1083 tmp &= ~bits;
1084 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1085 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1086 tmp &= ~bits;
1087 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1088 break;
1089 case AMDGPU_IRQ_STATE_ENABLE:
1090 tmp = RREG32(mmVM_CONTEXT0_CNTL);
1091 tmp |= bits;
1092 WREG32(mmVM_CONTEXT0_CNTL, tmp);
1093 tmp = RREG32(mmVM_CONTEXT1_CNTL);
1094 tmp |= bits;
1095 WREG32(mmVM_CONTEXT1_CNTL, tmp);
1096 break;
1097 default:
1098 break;
1099 }
1100
1101 return 0;
1102 }
1103
gmc_v6_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1104 static int gmc_v6_0_process_interrupt(struct amdgpu_device *adev,
1105 struct amdgpu_irq_src *source,
1106 struct amdgpu_iv_entry *entry)
1107 {
1108 u32 addr, status;
1109
1110 addr = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR);
1111 status = RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS);
1112 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1);
1113
1114 if (!addr && !status)
1115 return 0;
1116
1117 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
1118 gmc_v6_0_set_fault_enable_default(adev, false);
1119
1120 if (printk_ratelimit()) {
1121 dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
1122 entry->src_id, entry->src_data[0]);
1123 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1124 addr);
1125 dev_err(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1126 status);
1127 gmc_v6_0_vm_decode_fault(adev, status, addr, 0);
1128 }
1129
1130 return 0;
1131 }
1132
gmc_v6_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)1133 static int gmc_v6_0_set_clockgating_state(void *handle,
1134 enum amd_clockgating_state state)
1135 {
1136 return 0;
1137 }
1138
gmc_v6_0_set_powergating_state(void * handle,enum amd_powergating_state state)1139 static int gmc_v6_0_set_powergating_state(void *handle,
1140 enum amd_powergating_state state)
1141 {
1142 return 0;
1143 }
1144
1145 static const struct amd_ip_funcs gmc_v6_0_ip_funcs = {
1146 .name = "gmc_v6_0",
1147 .early_init = gmc_v6_0_early_init,
1148 .late_init = gmc_v6_0_late_init,
1149 .sw_init = gmc_v6_0_sw_init,
1150 .sw_fini = gmc_v6_0_sw_fini,
1151 .hw_init = gmc_v6_0_hw_init,
1152 .hw_fini = gmc_v6_0_hw_fini,
1153 .suspend = gmc_v6_0_suspend,
1154 .resume = gmc_v6_0_resume,
1155 .is_idle = gmc_v6_0_is_idle,
1156 .wait_for_idle = gmc_v6_0_wait_for_idle,
1157 .soft_reset = gmc_v6_0_soft_reset,
1158 .set_clockgating_state = gmc_v6_0_set_clockgating_state,
1159 .set_powergating_state = gmc_v6_0_set_powergating_state,
1160 };
1161
1162 static const struct amdgpu_gmc_funcs gmc_v6_0_gmc_funcs = {
1163 .flush_gpu_tlb = gmc_v6_0_flush_gpu_tlb,
1164 .emit_flush_gpu_tlb = gmc_v6_0_emit_flush_gpu_tlb,
1165 .set_pte_pde = gmc_v6_0_set_pte_pde,
1166 .set_prt = gmc_v6_0_set_prt,
1167 .get_vm_pde = gmc_v6_0_get_vm_pde,
1168 .get_vm_pte_flags = gmc_v6_0_get_vm_pte_flags
1169 };
1170
1171 static const struct amdgpu_irq_src_funcs gmc_v6_0_irq_funcs = {
1172 .set = gmc_v6_0_vm_fault_interrupt_state,
1173 .process = gmc_v6_0_process_interrupt,
1174 };
1175
gmc_v6_0_set_gmc_funcs(struct amdgpu_device * adev)1176 static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev)
1177 {
1178 if (adev->gmc.gmc_funcs == NULL)
1179 adev->gmc.gmc_funcs = &gmc_v6_0_gmc_funcs;
1180 }
1181
gmc_v6_0_set_irq_funcs(struct amdgpu_device * adev)1182 static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1183 {
1184 adev->gmc.vm_fault.num_types = 1;
1185 adev->gmc.vm_fault.funcs = &gmc_v6_0_irq_funcs;
1186 }
1187
1188 const struct amdgpu_ip_block_version gmc_v6_0_ip_block =
1189 {
1190 .type = AMD_IP_BLOCK_TYPE_GMC,
1191 .major = 6,
1192 .minor = 0,
1193 .rev = 0,
1194 .funcs = &gmc_v6_0_ip_funcs,
1195 };
1196
