1 /*
2 * Copyright 2016 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "gk104.h"
25 #include "changk104.h"
26
27 #include <core/gpuobj.h>
28
29 #include <nvif/class.h>
30
31 static void
gm107_fifo_runlist_chan(struct gk104_fifo_chan * chan,struct nvkm_memory * memory,u32 offset)32 gm107_fifo_runlist_chan(struct gk104_fifo_chan *chan,
33 struct nvkm_memory *memory, u32 offset)
34 {
35 nvkm_wo32(memory, offset + 0, chan->base.chid);
36 nvkm_wo32(memory, offset + 4, chan->base.inst->addr >> 12);
37 }
38
39 const struct gk104_fifo_runlist_func
40 gm107_fifo_runlist = {
41 .size = 8,
42 .cgrp = gk110_fifo_runlist_cgrp,
43 .chan = gm107_fifo_runlist_chan,
44 };
45
46 const struct nvkm_enum
47 gm107_fifo_fault_engine[] = {
48 { 0x01, "DISPLAY" },
49 { 0x02, "CAPTURE" },
50 { 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
51 { 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
52 { 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
53 { 0x06, "SCHED" },
54 { 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
55 { 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
56 { 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
57 { 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
58 { 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
59 { 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
60 { 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
61 { 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
62 { 0x0f, "HOSTSR" },
63 { 0x13, "PERF" },
64 { 0x17, "PMU" },
65 { 0x18, "PTP" },
66 {}
67 };
68
69 static const struct gk104_fifo_func
70 gm107_fifo = {
71 .init_pbdma_timeout = gk208_fifo_init_pbdma_timeout,
72 .fault.access = gk104_fifo_fault_access,
73 .fault.engine = gm107_fifo_fault_engine,
74 .fault.reason = gk104_fifo_fault_reason,
75 .fault.hubclient = gk104_fifo_fault_hubclient,
76 .fault.gpcclient = gk104_fifo_fault_gpcclient,
77 .runlist = &gm107_fifo_runlist,
78 .chan = {{0,0,KEPLER_CHANNEL_GPFIFO_B}, gk104_fifo_gpfifo_new },
79 };
80
81 int
gm107_fifo_new(struct nvkm_device * device,int index,struct nvkm_fifo ** pfifo)82 gm107_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
83 {
84 return gk104_fifo_new_(&gm107_fifo, device, index, 2048, pfifo);
85 }
86
