1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "changk104.h"
25 #include "cgrp.h"
26
27 #include <core/client.h>
28 #include <core/gpuobj.h>
29 #include <subdev/fb.h>
30 #include <subdev/mmu.h>
31 #include <subdev/timer.h>
32
33 #include <nvif/class.h>
34 #include <nvif/cla06f.h>
35 #include <nvif/unpack.h>
36
37 int
gk104_fifo_gpfifo_kick_locked(struct gk104_fifo_chan * chan)38 gk104_fifo_gpfifo_kick_locked(struct gk104_fifo_chan *chan)
39 {
40 struct gk104_fifo *fifo = chan->fifo;
41 struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
42 struct nvkm_device *device = subdev->device;
43 struct nvkm_client *client = chan->base.object.client;
44 struct nvkm_fifo_cgrp *cgrp = chan->cgrp;
45 int ret = 0;
46
47 if (cgrp)
48 nvkm_wr32(device, 0x002634, cgrp->id | 0x01000000);
49 else
50 nvkm_wr32(device, 0x002634, chan->base.chid);
51 if (nvkm_msec(device, 2000,
52 if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
53 break;
54 ) < 0) {
55 nvkm_error(subdev, "%s %d [%s] kick timeout\n",
56 cgrp ? "tsg" : "channel",
57 cgrp ? cgrp->id : chan->base.chid, client->name);
58 nvkm_fifo_recover_chan(&fifo->base, chan->base.chid);
59 ret = -ETIMEDOUT;
60 }
61 return ret;
62 }
63
64 int
gk104_fifo_gpfifo_kick(struct gk104_fifo_chan * chan)65 gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
66 {
67 int ret;
68 mutex_lock(&chan->base.fifo->engine.subdev.mutex);
69 ret = gk104_fifo_gpfifo_kick_locked(chan);
70 mutex_unlock(&chan->base.fifo->engine.subdev.mutex);
71 return ret;
72 }
73
74 static u32
gk104_fifo_gpfifo_engine_addr(struct nvkm_engine * engine)75 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
76 {
77 switch (engine->subdev.index) {
78 case NVKM_ENGINE_SW :
79 case NVKM_ENGINE_CE0...NVKM_ENGINE_CE_LAST:
80 return 0;
81 case NVKM_ENGINE_GR : return 0x0210;
82 case NVKM_ENGINE_SEC : return 0x0220;
83 case NVKM_ENGINE_MSPDEC: return 0x0250;
84 case NVKM_ENGINE_MSPPP : return 0x0260;
85 case NVKM_ENGINE_MSVLD : return 0x0270;
86 case NVKM_ENGINE_VIC : return 0x0280;
87 case NVKM_ENGINE_MSENC : return 0x0290;
88 case NVKM_ENGINE_NVDEC : return 0x02100270;
89 case NVKM_ENGINE_NVENC0: return 0x02100290;
90 case NVKM_ENGINE_NVENC1: return 0x0210;
91 default:
92 WARN_ON(1);
93 return 0;
94 }
95 }
96
97 static int
gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,bool suspend)98 gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
99 struct nvkm_engine *engine, bool suspend)
100 {
101 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
102 struct nvkm_gpuobj *inst = chan->base.inst;
103 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
104 int ret;
105
106 ret = gk104_fifo_gpfifo_kick(chan);
107 if (ret && suspend)
108 return ret;
109
110 if (offset) {
111 nvkm_kmap(inst);
112 nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
113 nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
114 if ((offset >>= 16)) {
115 nvkm_wo32(inst, offset + 0x00, 0x00000000);
116 nvkm_wo32(inst, offset + 0x04, 0x00000000);
117 }
118 nvkm_done(inst);
119 }
120
121 return ret;
122 }
123
124 static int
gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)125 gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
126 struct nvkm_engine *engine)
127 {
128 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
129 struct nvkm_gpuobj *inst = chan->base.inst;
130 u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
131
132 if (offset) {
133 u64 addr = chan->engn[engine->subdev.index].vma->addr;
134 u32 datalo = lower_32_bits(addr) | 0x00000004;
135 u32 datahi = upper_32_bits(addr);
136 nvkm_kmap(inst);
137 nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
138 nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
139 if ((offset >>= 16)) {
140 nvkm_wo32(inst, offset + 0x00, datalo);
141 nvkm_wo32(inst, offset + 0x04, datahi);
142 }
143 nvkm_done(inst);
144 }
145
146 return 0;
147 }
148
149 void
gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan * base,struct nvkm_engine * engine)150 gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
151 struct nvkm_engine *engine)
152 {
153 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
154 nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
155 nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
156 }
157
158 int
gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan * base,struct nvkm_engine * engine,struct nvkm_object * object)159 gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
160 struct nvkm_engine *engine,
161 struct nvkm_object *object)
162 {
163 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
164 int engn = engine->subdev.index;
165 int ret;
166
167 if (!gk104_fifo_gpfifo_engine_addr(engine))
168 return 0;
169
170 ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
171 if (ret)
172 return ret;
173
174 ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size,
175 &chan->engn[engn].vma);
176 if (ret)
177 return ret;
178
179 return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm,
180 chan->engn[engn].vma, NULL, 0);
181 }
182
183 void
gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan * base)184 gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
185 {
186 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
187 struct gk104_fifo *fifo = chan->fifo;
188 struct nvkm_device *device = fifo->base.engine.subdev.device;
189 u32 coff = chan->base.chid * 8;
190
191 if (!list_empty(&chan->head)) {
192 gk104_fifo_runlist_remove(fifo, chan);
193 nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
194 gk104_fifo_gpfifo_kick(chan);
195 gk104_fifo_runlist_commit(fifo, chan->runl);
196 }
197
198 nvkm_wr32(device, 0x800000 + coff, 0x00000000);
199 }
200
201 void
gk104_fifo_gpfifo_init(struct nvkm_fifo_chan * base)202 gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
203 {
204 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
205 struct gk104_fifo *fifo = chan->fifo;
206 struct nvkm_device *device = fifo->base.engine.subdev.device;
207 u32 addr = chan->base.inst->addr >> 12;
208 u32 coff = chan->base.chid * 8;
209
210 nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
211 nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
212
213 if (list_empty(&chan->head) && !chan->killed) {
214 gk104_fifo_runlist_insert(fifo, chan);
215 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
216 gk104_fifo_runlist_commit(fifo, chan->runl);
217 nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
218 }
219 }
220
221 void *
gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan * base)222 gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
223 {
224 struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
225 kfree(chan->cgrp);
226 return chan;
227 }
228
229 const struct nvkm_fifo_chan_func
230 gk104_fifo_gpfifo_func = {
231 .dtor = gk104_fifo_gpfifo_dtor,
232 .init = gk104_fifo_gpfifo_init,
233 .fini = gk104_fifo_gpfifo_fini,
234 .ntfy = gf100_fifo_chan_ntfy,
235 .engine_ctor = gk104_fifo_gpfifo_engine_ctor,
236 .engine_dtor = gk104_fifo_gpfifo_engine_dtor,
237 .engine_init = gk104_fifo_gpfifo_engine_init,
238 .engine_fini = gk104_fifo_gpfifo_engine_fini,
239 };
240
241 static int
gk104_fifo_gpfifo_new_(struct gk104_fifo * fifo,u64 * runlists,u16 * chid,u64 vmm,u64 ioffset,u64 ilength,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)242 gk104_fifo_gpfifo_new_(struct gk104_fifo *fifo, u64 *runlists, u16 *chid,
243 u64 vmm, u64 ioffset, u64 ilength,
244 const struct nvkm_oclass *oclass,
245 struct nvkm_object **pobject)
246 {
247 struct gk104_fifo_chan *chan;
248 int runlist = ffs(*runlists) -1, ret, i;
249 unsigned long engm;
250 u64 subdevs = 0;
251 u64 usermem;
252
253 if (!vmm || runlist < 0 || runlist >= fifo->runlist_nr)
254 return -EINVAL;
255 *runlists = BIT_ULL(runlist);
256
257 engm = fifo->runlist[runlist].engm;
258 for_each_set_bit(i, &engm, fifo->engine_nr) {
259 if (fifo->engine[i].engine)
260 subdevs |= BIT_ULL(fifo->engine[i].engine->subdev.index);
261 }
262
263 if (subdevs & BIT_ULL(NVKM_ENGINE_GR))
264 subdevs |= BIT_ULL(NVKM_ENGINE_SW);
265
266 /* Allocate the channel. */
267 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
268 return -ENOMEM;
269 *pobject = &chan->base.object;
270 chan->fifo = fifo;
271 chan->runl = runlist;
272 INIT_LIST_HEAD(&chan->head);
273
274 ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
275 0x1000, 0x1000, true, vmm, 0, subdevs,
276 1, fifo->user.bar->addr, 0x200,
277 oclass, &chan->base);
278 if (ret)
279 return ret;
280
281 *chid = chan->base.chid;
282
283 /* Hack to support GPUs where even individual channels should be
284 * part of a channel group.
285 */
286 if (fifo->func->cgrp_force) {
287 if (!(chan->cgrp = kmalloc(sizeof(*chan->cgrp), GFP_KERNEL)))
288 return -ENOMEM;
289 chan->cgrp->id = chan->base.chid;
290 INIT_LIST_HEAD(&chan->cgrp->head);
291 INIT_LIST_HEAD(&chan->cgrp->chan);
292 chan->cgrp->chan_nr = 0;
293 }
294
295 /* Clear channel control registers. */
296 usermem = chan->base.chid * 0x200;
297 ilength = order_base_2(ilength / 8);
298
299 nvkm_kmap(fifo->user.mem);
300 for (i = 0; i < 0x200; i += 4)
301 nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
302 nvkm_done(fifo->user.mem);
303 usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
304
305 /* RAMFC */
306 nvkm_kmap(chan->base.inst);
307 nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
308 nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
309 nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
310 nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
311 nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
312 nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
313 (ilength << 16));
314 nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
315 nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
316 nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
317 nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
318 nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
319 nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
320 nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
321 nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
322 nvkm_done(chan->base.inst);
323 return 0;
324 }
325
326 int
gk104_fifo_gpfifo_new(struct gk104_fifo * fifo,const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)327 gk104_fifo_gpfifo_new(struct gk104_fifo *fifo, const struct nvkm_oclass *oclass,
328 void *data, u32 size, struct nvkm_object **pobject)
329 {
330 struct nvkm_object *parent = oclass->parent;
331 union {
332 struct kepler_channel_gpfifo_a_v0 v0;
333 } *args = data;
334 int ret = -ENOSYS;
335
336 nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
337 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
338 nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
339 "ioffset %016llx ilength %08x "
340 "runlist %016llx\n",
341 args->v0.version, args->v0.vmm, args->v0.ioffset,
342 args->v0.ilength, args->v0.runlist);
343 return gk104_fifo_gpfifo_new_(fifo,
344 &args->v0.runlist,
345 &args->v0.chid,
346 args->v0.vmm,
347 args->v0.ioffset,
348 args->v0.ilength,
349 oclass, pobject);
350 }
351
352 return ret;
353 }
354
