1 /*
2  * OMAP4 specific common source file.
3  *
4  * Copyright (C) 2010 Texas Instruments, Inc.
5  * Author:
6  *	Santosh Shilimkar <santosh.shilimkar@ti.com>
7  *
8  *
9  * This program is free software,you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/irq.h>
18 #include <linux/irqchip.h>
19 #include <linux/platform_device.h>
20 #include <linux/memblock.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/export.h>
24 #include <linux/irqchip/arm-gic.h>
25 #include <linux/of_address.h>
26 #include <linux/reboot.h>
27 #include <linux/genalloc.h>
28 
29 #include <asm/hardware/cache-l2x0.h>
30 #include <asm/mach/map.h>
31 #include <asm/memblock.h>
32 #include <asm/smp_twd.h>
33 
34 #include "omap-wakeupgen.h"
35 #include "soc.h"
36 #include "iomap.h"
37 #include "common.h"
38 #include "prminst44xx.h"
39 #include "prcm_mpu44xx.h"
40 #include "omap4-sar-layout.h"
41 #include "omap-secure.h"
42 #include "sram.h"
43 
44 #ifdef CONFIG_CACHE_L2X0
45 static void __iomem *l2cache_base;
46 #endif
47 
48 static void __iomem *sar_ram_base;
49 static void __iomem *gic_dist_base_addr;
50 static void __iomem *twd_base;
51 
52 #define IRQ_LOCALTIMER		29
53 
54 #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
55 
56 /* Used to implement memory barrier on DRAM path */
57 #define OMAP4_DRAM_BARRIER_VA			0xfe600000
58 
59 static void __iomem *dram_sync, *sram_sync;
60 static phys_addr_t dram_sync_paddr;
61 static u32 dram_sync_size;
62 
63 /*
64  * The OMAP4 bus structure contains asynchronous bridges which can buffer
65  * data writes from the MPU. These asynchronous bridges can be found on
66  * paths between the MPU to EMIF, and the MPU to L3 interconnects.
67  *
68  * We need to be careful about re-ordering which can happen as a result
69  * of different accesses being performed via different paths, and
70  * therefore different asynchronous bridges.
71  */
72 
73 /*
74  * OMAP4 interconnect barrier which is called for each mb() and wmb().
75  * This is to ensure that normal paths to DRAM (normal memory, cacheable
76  * accesses) are properly synchronised with writes to DMA coherent memory
77  * (normal memory, uncacheable) and device writes.
78  *
79  * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
80  * path, as we need to ensure that data is visible to other system
81  * masters prior to writes to those system masters being seen.
82  *
83  * Note: the SRAM path is not synchronised via mb() and wmb().
84  */
omap4_mb(void)85 static void omap4_mb(void)
86 {
87 	if (dram_sync)
88 		writel_relaxed(0, dram_sync);
89 }
90 
91 /*
92  * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
93  *
94  * If a data is stalled inside asynchronous bridge because of back
95  * pressure, it may be accepted multiple times, creating pointer
96  * misalignment that will corrupt next transfers on that data path until
97  * next reset of the system. No recovery procedure once the issue is hit,
98  * the path remains consistently broken.
99  *
100  * Async bridges can be found on paths between MPU to EMIF and MPU to L3
101  * interconnects.
102  *
103  * This situation can happen only when the idle is initiated by a Master
104  * Request Disconnection (which is trigged by software when executing WFI
105  * on the CPU).
106  *
107  * The work-around for this errata needs all the initiators connected
108  * through an async bridge to ensure that data path is properly drained
109  * before issuing WFI. This condition will be met if one Strongly ordered
110  * access is performed to the target right before executing the WFI.
111  *
112  * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
113  * IO barrier ensure that there is no synchronisation loss on initiators
114  * operating on both interconnect port simultaneously.
115  *
116  * This is a stronger version of the OMAP4 memory barrier below, and
117  * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
118  * as well, and is necessary prior to executing a WFI.
119  */
omap_interconnect_sync(void)120 void omap_interconnect_sync(void)
121 {
122 	if (dram_sync && sram_sync) {
123 		writel_relaxed(readl_relaxed(dram_sync), dram_sync);
124 		writel_relaxed(readl_relaxed(sram_sync), sram_sync);
125 		isb();
126 	}
127 }
128 
omap4_sram_init(void)129 static int __init omap4_sram_init(void)
130 {
131 	struct device_node *np;
132 	struct gen_pool *sram_pool;
133 
134 	np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
135 	if (!np)
136 		pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
137 			__func__);
138 	sram_pool = of_gen_pool_get(np, "sram", 0);
139 	if (!sram_pool)
140 		pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
141 			__func__);
142 	else
143 		sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
144 
145 	return 0;
146 }
147 omap_arch_initcall(omap4_sram_init);
148 
149 /* Steal one page physical memory for barrier implementation */
omap_barrier_reserve_memblock(void)150 void __init omap_barrier_reserve_memblock(void)
151 {
152 	dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
153 	dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
154 }
155 
omap_barriers_init(void)156 void __init omap_barriers_init(void)
157 {
158 	struct map_desc dram_io_desc[1];
159 
160 	dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
161 	dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
162 	dram_io_desc[0].length = dram_sync_size;
163 	dram_io_desc[0].type = MT_MEMORY_RW_SO;
164 	iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
165 	dram_sync = (void __iomem *) dram_io_desc[0].virtual;
166 
167 	pr_info("OMAP4: Map %pa to %p for dram barrier\n",
168 		&dram_sync_paddr, dram_sync);
169 
170 	soc_mb = omap4_mb;
171 }
172 
173 #endif
174 
gic_dist_disable(void)175 void gic_dist_disable(void)
176 {
177 	if (gic_dist_base_addr)
178 		writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
179 }
180 
gic_dist_enable(void)181 void gic_dist_enable(void)
182 {
183 	if (gic_dist_base_addr)
184 		writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
185 }
186 
gic_dist_disabled(void)187 bool gic_dist_disabled(void)
188 {
189 	return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
190 }
191 
gic_timer_retrigger(void)192 void gic_timer_retrigger(void)
193 {
194 	u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
195 	u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
196 	u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
197 
198 	if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
199 		/*
200 		 * The local timer interrupt got lost while the distributor was
201 		 * disabled.  Ack the pending interrupt, and retrigger it.
202 		 */
203 		pr_warn("%s: lost localtimer interrupt\n", __func__);
204 		writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
205 		if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
206 			writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
207 			twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
208 			writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
209 		}
210 	}
211 }
212 
213 #ifdef CONFIG_CACHE_L2X0
214 
omap4_get_l2cache_base(void)215 void __iomem *omap4_get_l2cache_base(void)
216 {
217 	return l2cache_base;
218 }
219 
omap4_l2c310_write_sec(unsigned long val,unsigned reg)220 void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
221 {
222 	unsigned smc_op;
223 
224 	switch (reg) {
225 	case L2X0_CTRL:
226 		smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
227 		break;
228 
229 	case L2X0_AUX_CTRL:
230 		smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
231 		break;
232 
233 	case L2X0_DEBUG_CTRL:
234 		smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
235 		break;
236 
237 	case L310_PREFETCH_CTRL:
238 		smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
239 		break;
240 
241 	case L310_POWER_CTRL:
242 		pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
243 		return;
244 
245 	default:
246 		WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
247 		return;
248 	}
249 
250 	omap_smc1(smc_op, val);
251 }
252 
omap_l2_cache_init(void)253 int __init omap_l2_cache_init(void)
254 {
255 	/* Static mapping, never released */
256 	l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
257 	if (WARN_ON(!l2cache_base))
258 		return -ENOMEM;
259 	return 0;
260 }
261 #endif
262 
omap4_get_sar_ram_base(void)263 void __iomem *omap4_get_sar_ram_base(void)
264 {
265 	return sar_ram_base;
266 }
267 
268 /*
269  * SAR RAM used to save and restore the HW context in low power modes.
270  * Note that we need to initialize this very early for kexec. See
271  * omap4_mpuss_early_init().
272  */
omap4_sar_ram_init(void)273 void __init omap4_sar_ram_init(void)
274 {
275 	unsigned long sar_base;
276 
277 	/*
278 	 * To avoid code running on other OMAPs in
279 	 * multi-omap builds
280 	 */
281 	if (cpu_is_omap44xx())
282 		sar_base = OMAP44XX_SAR_RAM_BASE;
283 	else if (soc_is_omap54xx())
284 		sar_base = OMAP54XX_SAR_RAM_BASE;
285 	else
286 		return;
287 
288 	/* Static mapping, never released */
289 	sar_ram_base = ioremap(sar_base, SZ_16K);
290 	if (WARN_ON(!sar_ram_base))
291 		return;
292 }
293 
294 static const struct of_device_id intc_match[] = {
295 	{ .compatible = "ti,omap4-wugen-mpu", },
296 	{ .compatible = "ti,omap5-wugen-mpu", },
297 	{ },
298 };
299 
300 static struct device_node *intc_node;
301 
omap_gic_of_init(void)302 void __init omap_gic_of_init(void)
303 {
304 	struct device_node *np;
305 
306 	intc_node = of_find_matching_node(NULL, intc_match);
307 	if (WARN_ON(!intc_node)) {
308 		pr_err("No WUGEN found in DT, system will misbehave.\n");
309 		pr_err("UPDATE YOUR DEVICE TREE!\n");
310 	}
311 
312 	/* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
313 	if (!cpu_is_omap446x())
314 		goto skip_errata_init;
315 
316 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
317 	gic_dist_base_addr = of_iomap(np, 0);
318 	WARN_ON(!gic_dist_base_addr);
319 
320 	np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
321 	twd_base = of_iomap(np, 0);
322 	WARN_ON(!twd_base);
323 
324 skip_errata_init:
325 	irqchip_init();
326 }
327