1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "gf100.h"
25 #include "ctxgf100.h"
26 #include "fuc/os.h"
27
28 #include <core/client.h>
29 #include <core/option.h>
30 #include <core/firmware.h>
31 #include <subdev/secboot.h>
32 #include <subdev/fb.h>
33 #include <subdev/mc.h>
34 #include <subdev/pmu.h>
35 #include <subdev/therm.h>
36 #include <subdev/timer.h>
37 #include <engine/fifo.h>
38
39 #include <nvif/class.h>
40 #include <nvif/cl9097.h>
41 #include <nvif/if900d.h>
42 #include <nvif/unpack.h>
43
44 /*******************************************************************************
45 * Zero Bandwidth Clear
46 ******************************************************************************/
47
48 static void
gf100_gr_zbc_clear_color(struct gf100_gr * gr,int zbc)49 gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc)
50 {
51 struct nvkm_device *device = gr->base.engine.subdev.device;
52 if (gr->zbc_color[zbc].format) {
53 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]);
54 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]);
55 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]);
56 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]);
57 }
58 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format);
59 nvkm_wr32(device, 0x405820, zbc);
60 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */
61 }
62
63 static int
gf100_gr_zbc_color_get(struct gf100_gr * gr,int format,const u32 ds[4],const u32 l2[4])64 gf100_gr_zbc_color_get(struct gf100_gr *gr, int format,
65 const u32 ds[4], const u32 l2[4])
66 {
67 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
68 int zbc = -ENOSPC, i;
69
70 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
71 if (gr->zbc_color[i].format) {
72 if (gr->zbc_color[i].format != format)
73 continue;
74 if (memcmp(gr->zbc_color[i].ds, ds, sizeof(
75 gr->zbc_color[i].ds)))
76 continue;
77 if (memcmp(gr->zbc_color[i].l2, l2, sizeof(
78 gr->zbc_color[i].l2))) {
79 WARN_ON(1);
80 return -EINVAL;
81 }
82 return i;
83 } else {
84 zbc = (zbc < 0) ? i : zbc;
85 }
86 }
87
88 if (zbc < 0)
89 return zbc;
90
91 memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds));
92 memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2));
93 gr->zbc_color[zbc].format = format;
94 nvkm_ltc_zbc_color_get(ltc, zbc, l2);
95 gr->func->zbc->clear_color(gr, zbc);
96 return zbc;
97 }
98
99 static void
gf100_gr_zbc_clear_depth(struct gf100_gr * gr,int zbc)100 gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc)
101 {
102 struct nvkm_device *device = gr->base.engine.subdev.device;
103 if (gr->zbc_depth[zbc].format)
104 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds);
105 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format);
106 nvkm_wr32(device, 0x405820, zbc);
107 nvkm_wr32(device, 0x405824, 0x00000005); /* TRIGGER | WRITE | DEPTH */
108 }
109
110 static int
gf100_gr_zbc_depth_get(struct gf100_gr * gr,int format,const u32 ds,const u32 l2)111 gf100_gr_zbc_depth_get(struct gf100_gr *gr, int format,
112 const u32 ds, const u32 l2)
113 {
114 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
115 int zbc = -ENOSPC, i;
116
117 for (i = ltc->zbc_min; i <= ltc->zbc_max; i++) {
118 if (gr->zbc_depth[i].format) {
119 if (gr->zbc_depth[i].format != format)
120 continue;
121 if (gr->zbc_depth[i].ds != ds)
122 continue;
123 if (gr->zbc_depth[i].l2 != l2) {
124 WARN_ON(1);
125 return -EINVAL;
126 }
127 return i;
128 } else {
129 zbc = (zbc < 0) ? i : zbc;
130 }
131 }
132
133 if (zbc < 0)
134 return zbc;
135
136 gr->zbc_depth[zbc].format = format;
137 gr->zbc_depth[zbc].ds = ds;
138 gr->zbc_depth[zbc].l2 = l2;
139 nvkm_ltc_zbc_depth_get(ltc, zbc, l2);
140 gr->func->zbc->clear_depth(gr, zbc);
141 return zbc;
142 }
143
144 const struct gf100_gr_func_zbc
145 gf100_gr_zbc = {
146 .clear_color = gf100_gr_zbc_clear_color,
147 .clear_depth = gf100_gr_zbc_clear_depth,
148 };
149
150 /*******************************************************************************
151 * Graphics object classes
152 ******************************************************************************/
153 #define gf100_gr_object(p) container_of((p), struct gf100_gr_object, object)
154
155 struct gf100_gr_object {
156 struct nvkm_object object;
157 struct gf100_gr_chan *chan;
158 };
159
160 static int
gf100_fermi_mthd_zbc_color(struct nvkm_object * object,void * data,u32 size)161 gf100_fermi_mthd_zbc_color(struct nvkm_object *object, void *data, u32 size)
162 {
163 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
164 union {
165 struct fermi_a_zbc_color_v0 v0;
166 } *args = data;
167 int ret = -ENOSYS;
168
169 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
170 switch (args->v0.format) {
171 case FERMI_A_ZBC_COLOR_V0_FMT_ZERO:
172 case FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE:
173 case FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32:
174 case FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16:
175 case FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16:
176 case FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16:
177 case FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16:
178 case FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16:
179 case FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8:
180 case FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8:
181 case FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10:
182 case FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10:
183 case FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8:
184 case FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8:
185 case FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8:
186 case FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8:
187 case FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8:
188 case FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10:
189 case FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11:
190 ret = gf100_gr_zbc_color_get(gr, args->v0.format,
191 args->v0.ds,
192 args->v0.l2);
193 if (ret >= 0) {
194 args->v0.index = ret;
195 return 0;
196 }
197 break;
198 default:
199 return -EINVAL;
200 }
201 }
202
203 return ret;
204 }
205
206 static int
gf100_fermi_mthd_zbc_depth(struct nvkm_object * object,void * data,u32 size)207 gf100_fermi_mthd_zbc_depth(struct nvkm_object *object, void *data, u32 size)
208 {
209 struct gf100_gr *gr = gf100_gr(nvkm_gr(object->engine));
210 union {
211 struct fermi_a_zbc_depth_v0 v0;
212 } *args = data;
213 int ret = -ENOSYS;
214
215 if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
216 switch (args->v0.format) {
217 case FERMI_A_ZBC_DEPTH_V0_FMT_FP32:
218 ret = gf100_gr_zbc_depth_get(gr, args->v0.format,
219 args->v0.ds,
220 args->v0.l2);
221 return (ret >= 0) ? 0 : -ENOSPC;
222 default:
223 return -EINVAL;
224 }
225 }
226
227 return ret;
228 }
229
230 static int
gf100_fermi_mthd(struct nvkm_object * object,u32 mthd,void * data,u32 size)231 gf100_fermi_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
232 {
233 nvif_ioctl(object, "fermi mthd %08x\n", mthd);
234 switch (mthd) {
235 case FERMI_A_ZBC_COLOR:
236 return gf100_fermi_mthd_zbc_color(object, data, size);
237 case FERMI_A_ZBC_DEPTH:
238 return gf100_fermi_mthd_zbc_depth(object, data, size);
239 default:
240 break;
241 }
242 return -EINVAL;
243 }
244
245 const struct nvkm_object_func
246 gf100_fermi = {
247 .mthd = gf100_fermi_mthd,
248 };
249
250 static void
gf100_gr_mthd_set_shader_exceptions(struct nvkm_device * device,u32 data)251 gf100_gr_mthd_set_shader_exceptions(struct nvkm_device *device, u32 data)
252 {
253 nvkm_wr32(device, 0x419e44, data ? 0xffffffff : 0x00000000);
254 nvkm_wr32(device, 0x419e4c, data ? 0xffffffff : 0x00000000);
255 }
256
257 static bool
gf100_gr_mthd_sw(struct nvkm_device * device,u16 class,u32 mthd,u32 data)258 gf100_gr_mthd_sw(struct nvkm_device *device, u16 class, u32 mthd, u32 data)
259 {
260 switch (class & 0x00ff) {
261 case 0x97:
262 case 0xc0:
263 switch (mthd) {
264 case 0x1528:
265 gf100_gr_mthd_set_shader_exceptions(device, data);
266 return true;
267 default:
268 break;
269 }
270 break;
271 default:
272 break;
273 }
274 return false;
275 }
276
277 static const struct nvkm_object_func
278 gf100_gr_object_func = {
279 };
280
281 static int
gf100_gr_object_new(const struct nvkm_oclass * oclass,void * data,u32 size,struct nvkm_object ** pobject)282 gf100_gr_object_new(const struct nvkm_oclass *oclass, void *data, u32 size,
283 struct nvkm_object **pobject)
284 {
285 struct gf100_gr_chan *chan = gf100_gr_chan(oclass->parent);
286 struct gf100_gr_object *object;
287
288 if (!(object = kzalloc(sizeof(*object), GFP_KERNEL)))
289 return -ENOMEM;
290 *pobject = &object->object;
291
292 nvkm_object_ctor(oclass->base.func ? oclass->base.func :
293 &gf100_gr_object_func, oclass, &object->object);
294 object->chan = chan;
295 return 0;
296 }
297
298 static int
gf100_gr_object_get(struct nvkm_gr * base,int index,struct nvkm_sclass * sclass)299 gf100_gr_object_get(struct nvkm_gr *base, int index, struct nvkm_sclass *sclass)
300 {
301 struct gf100_gr *gr = gf100_gr(base);
302 int c = 0;
303
304 while (gr->func->sclass[c].oclass) {
305 if (c++ == index) {
306 *sclass = gr->func->sclass[index];
307 sclass->ctor = gf100_gr_object_new;
308 return index;
309 }
310 }
311
312 return c;
313 }
314
315 /*******************************************************************************
316 * PGRAPH context
317 ******************************************************************************/
318
319 static int
gf100_gr_chan_bind(struct nvkm_object * object,struct nvkm_gpuobj * parent,int align,struct nvkm_gpuobj ** pgpuobj)320 gf100_gr_chan_bind(struct nvkm_object *object, struct nvkm_gpuobj *parent,
321 int align, struct nvkm_gpuobj **pgpuobj)
322 {
323 struct gf100_gr_chan *chan = gf100_gr_chan(object);
324 struct gf100_gr *gr = chan->gr;
325 int ret, i;
326
327 ret = nvkm_gpuobj_new(gr->base.engine.subdev.device, gr->size,
328 align, false, parent, pgpuobj);
329 if (ret)
330 return ret;
331
332 nvkm_kmap(*pgpuobj);
333 for (i = 0; i < gr->size; i += 4)
334 nvkm_wo32(*pgpuobj, i, gr->data[i / 4]);
335
336 if (!gr->firmware) {
337 nvkm_wo32(*pgpuobj, 0x00, chan->mmio_nr / 2);
338 nvkm_wo32(*pgpuobj, 0x04, chan->mmio_vma->addr >> 8);
339 } else {
340 nvkm_wo32(*pgpuobj, 0xf4, 0);
341 nvkm_wo32(*pgpuobj, 0xf8, 0);
342 nvkm_wo32(*pgpuobj, 0x10, chan->mmio_nr / 2);
343 nvkm_wo32(*pgpuobj, 0x14, lower_32_bits(chan->mmio_vma->addr));
344 nvkm_wo32(*pgpuobj, 0x18, upper_32_bits(chan->mmio_vma->addr));
345 nvkm_wo32(*pgpuobj, 0x1c, 1);
346 nvkm_wo32(*pgpuobj, 0x20, 0);
347 nvkm_wo32(*pgpuobj, 0x28, 0);
348 nvkm_wo32(*pgpuobj, 0x2c, 0);
349 }
350 nvkm_done(*pgpuobj);
351 return 0;
352 }
353
354 static void *
gf100_gr_chan_dtor(struct nvkm_object * object)355 gf100_gr_chan_dtor(struct nvkm_object *object)
356 {
357 struct gf100_gr_chan *chan = gf100_gr_chan(object);
358 int i;
359
360 for (i = 0; i < ARRAY_SIZE(chan->data); i++) {
361 nvkm_vmm_put(chan->vmm, &chan->data[i].vma);
362 nvkm_memory_unref(&chan->data[i].mem);
363 }
364
365 nvkm_vmm_put(chan->vmm, &chan->mmio_vma);
366 nvkm_memory_unref(&chan->mmio);
367 nvkm_vmm_unref(&chan->vmm);
368 return chan;
369 }
370
371 static const struct nvkm_object_func
372 gf100_gr_chan = {
373 .dtor = gf100_gr_chan_dtor,
374 .bind = gf100_gr_chan_bind,
375 };
376
377 static int
gf100_gr_chan_new(struct nvkm_gr * base,struct nvkm_fifo_chan * fifoch,const struct nvkm_oclass * oclass,struct nvkm_object ** pobject)378 gf100_gr_chan_new(struct nvkm_gr *base, struct nvkm_fifo_chan *fifoch,
379 const struct nvkm_oclass *oclass,
380 struct nvkm_object **pobject)
381 {
382 struct gf100_gr *gr = gf100_gr(base);
383 struct gf100_gr_data *data = gr->mmio_data;
384 struct gf100_gr_mmio *mmio = gr->mmio_list;
385 struct gf100_gr_chan *chan;
386 struct gf100_vmm_map_v0 args = { .priv = 1 };
387 struct nvkm_device *device = gr->base.engine.subdev.device;
388 int ret, i;
389
390 if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
391 return -ENOMEM;
392 nvkm_object_ctor(&gf100_gr_chan, oclass, &chan->object);
393 chan->gr = gr;
394 chan->vmm = nvkm_vmm_ref(fifoch->vmm);
395 *pobject = &chan->object;
396
397 /* allocate memory for a "mmio list" buffer that's used by the HUB
398 * fuc to modify some per-context register settings on first load
399 * of the context.
400 */
401 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x1000, 0x100,
402 false, &chan->mmio);
403 if (ret)
404 return ret;
405
406 ret = nvkm_vmm_get(fifoch->vmm, 12, 0x1000, &chan->mmio_vma);
407 if (ret)
408 return ret;
409
410 ret = nvkm_memory_map(chan->mmio, 0, fifoch->vmm,
411 chan->mmio_vma, &args, sizeof(args));
412 if (ret)
413 return ret;
414
415 /* allocate buffers referenced by mmio list */
416 for (i = 0; data->size && i < ARRAY_SIZE(gr->mmio_data); i++) {
417 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
418 data->size, data->align, false,
419 &chan->data[i].mem);
420 if (ret)
421 return ret;
422
423 ret = nvkm_vmm_get(fifoch->vmm, 12,
424 nvkm_memory_size(chan->data[i].mem),
425 &chan->data[i].vma);
426 if (ret)
427 return ret;
428
429 args.priv = data->priv;
430
431 ret = nvkm_memory_map(chan->data[i].mem, 0, chan->vmm,
432 chan->data[i].vma, &args, sizeof(args));
433 if (ret)
434 return ret;
435
436 data++;
437 }
438
439 /* finally, fill in the mmio list and point the context at it */
440 nvkm_kmap(chan->mmio);
441 for (i = 0; mmio->addr && i < ARRAY_SIZE(gr->mmio_list); i++) {
442 u32 addr = mmio->addr;
443 u32 data = mmio->data;
444
445 if (mmio->buffer >= 0) {
446 u64 info = chan->data[mmio->buffer].vma->addr;
447 data |= info >> mmio->shift;
448 }
449
450 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, addr);
451 nvkm_wo32(chan->mmio, chan->mmio_nr++ * 4, data);
452 mmio++;
453 }
454 nvkm_done(chan->mmio);
455 return 0;
456 }
457
458 /*******************************************************************************
459 * PGRAPH register lists
460 ******************************************************************************/
461
462 const struct gf100_gr_init
463 gf100_gr_init_main_0[] = {
464 { 0x400080, 1, 0x04, 0x003083c2 },
465 { 0x400088, 1, 0x04, 0x00006fe7 },
466 { 0x40008c, 1, 0x04, 0x00000000 },
467 { 0x400090, 1, 0x04, 0x00000030 },
468 { 0x40013c, 1, 0x04, 0x013901f7 },
469 { 0x400140, 1, 0x04, 0x00000100 },
470 { 0x400144, 1, 0x04, 0x00000000 },
471 { 0x400148, 1, 0x04, 0x00000110 },
472 { 0x400138, 1, 0x04, 0x00000000 },
473 { 0x400130, 2, 0x04, 0x00000000 },
474 { 0x400124, 1, 0x04, 0x00000002 },
475 {}
476 };
477
478 const struct gf100_gr_init
479 gf100_gr_init_fe_0[] = {
480 { 0x40415c, 1, 0x04, 0x00000000 },
481 { 0x404170, 1, 0x04, 0x00000000 },
482 {}
483 };
484
485 const struct gf100_gr_init
486 gf100_gr_init_pri_0[] = {
487 { 0x404488, 2, 0x04, 0x00000000 },
488 {}
489 };
490
491 const struct gf100_gr_init
492 gf100_gr_init_rstr2d_0[] = {
493 { 0x407808, 1, 0x04, 0x00000000 },
494 {}
495 };
496
497 const struct gf100_gr_init
498 gf100_gr_init_pd_0[] = {
499 { 0x406024, 1, 0x04, 0x00000000 },
500 {}
501 };
502
503 const struct gf100_gr_init
504 gf100_gr_init_ds_0[] = {
505 { 0x405844, 1, 0x04, 0x00ffffff },
506 { 0x405850, 1, 0x04, 0x00000000 },
507 { 0x405908, 1, 0x04, 0x00000000 },
508 {}
509 };
510
511 const struct gf100_gr_init
512 gf100_gr_init_scc_0[] = {
513 { 0x40803c, 1, 0x04, 0x00000000 },
514 {}
515 };
516
517 const struct gf100_gr_init
518 gf100_gr_init_prop_0[] = {
519 { 0x4184a0, 1, 0x04, 0x00000000 },
520 {}
521 };
522
523 const struct gf100_gr_init
524 gf100_gr_init_gpc_unk_0[] = {
525 { 0x418604, 1, 0x04, 0x00000000 },
526 { 0x418680, 1, 0x04, 0x00000000 },
527 { 0x418714, 1, 0x04, 0x80000000 },
528 { 0x418384, 1, 0x04, 0x00000000 },
529 {}
530 };
531
532 const struct gf100_gr_init
533 gf100_gr_init_setup_0[] = {
534 { 0x418814, 3, 0x04, 0x00000000 },
535 {}
536 };
537
538 const struct gf100_gr_init
539 gf100_gr_init_crstr_0[] = {
540 { 0x418b04, 1, 0x04, 0x00000000 },
541 {}
542 };
543
544 const struct gf100_gr_init
545 gf100_gr_init_setup_1[] = {
546 { 0x4188c8, 1, 0x04, 0x80000000 },
547 { 0x4188cc, 1, 0x04, 0x00000000 },
548 { 0x4188d0, 1, 0x04, 0x00010000 },
549 { 0x4188d4, 1, 0x04, 0x00000001 },
550 {}
551 };
552
553 const struct gf100_gr_init
554 gf100_gr_init_zcull_0[] = {
555 { 0x418910, 1, 0x04, 0x00010001 },
556 { 0x418914, 1, 0x04, 0x00000301 },
557 { 0x418918, 1, 0x04, 0x00800000 },
558 { 0x418980, 1, 0x04, 0x77777770 },
559 { 0x418984, 3, 0x04, 0x77777777 },
560 {}
561 };
562
563 const struct gf100_gr_init
564 gf100_gr_init_gpm_0[] = {
565 { 0x418c04, 1, 0x04, 0x00000000 },
566 { 0x418c88, 1, 0x04, 0x00000000 },
567 {}
568 };
569
570 const struct gf100_gr_init
571 gf100_gr_init_gpc_unk_1[] = {
572 { 0x418d00, 1, 0x04, 0x00000000 },
573 { 0x418f08, 1, 0x04, 0x00000000 },
574 { 0x418e00, 1, 0x04, 0x00000050 },
575 { 0x418e08, 1, 0x04, 0x00000000 },
576 {}
577 };
578
579 const struct gf100_gr_init
580 gf100_gr_init_gcc_0[] = {
581 { 0x41900c, 1, 0x04, 0x00000000 },
582 { 0x419018, 1, 0x04, 0x00000000 },
583 {}
584 };
585
586 const struct gf100_gr_init
587 gf100_gr_init_tpccs_0[] = {
588 { 0x419d08, 2, 0x04, 0x00000000 },
589 { 0x419d10, 1, 0x04, 0x00000014 },
590 {}
591 };
592
593 const struct gf100_gr_init
594 gf100_gr_init_tex_0[] = {
595 { 0x419ab0, 1, 0x04, 0x00000000 },
596 { 0x419ab8, 1, 0x04, 0x000000e7 },
597 { 0x419abc, 2, 0x04, 0x00000000 },
598 {}
599 };
600
601 const struct gf100_gr_init
602 gf100_gr_init_pe_0[] = {
603 { 0x41980c, 3, 0x04, 0x00000000 },
604 { 0x419844, 1, 0x04, 0x00000000 },
605 { 0x41984c, 1, 0x04, 0x00005bc5 },
606 { 0x419850, 4, 0x04, 0x00000000 },
607 {}
608 };
609
610 const struct gf100_gr_init
611 gf100_gr_init_l1c_0[] = {
612 { 0x419c98, 1, 0x04, 0x00000000 },
613 { 0x419ca8, 1, 0x04, 0x80000000 },
614 { 0x419cb4, 1, 0x04, 0x00000000 },
615 { 0x419cb8, 1, 0x04, 0x00008bf4 },
616 { 0x419cbc, 1, 0x04, 0x28137606 },
617 { 0x419cc0, 2, 0x04, 0x00000000 },
618 {}
619 };
620
621 const struct gf100_gr_init
622 gf100_gr_init_wwdx_0[] = {
623 { 0x419bd4, 1, 0x04, 0x00800000 },
624 { 0x419bdc, 1, 0x04, 0x00000000 },
625 {}
626 };
627
628 const struct gf100_gr_init
629 gf100_gr_init_tpccs_1[] = {
630 { 0x419d2c, 1, 0x04, 0x00000000 },
631 {}
632 };
633
634 const struct gf100_gr_init
635 gf100_gr_init_mpc_0[] = {
636 { 0x419c0c, 1, 0x04, 0x00000000 },
637 {}
638 };
639
640 static const struct gf100_gr_init
641 gf100_gr_init_sm_0[] = {
642 { 0x419e00, 1, 0x04, 0x00000000 },
643 { 0x419ea0, 1, 0x04, 0x00000000 },
644 { 0x419ea4, 1, 0x04, 0x00000100 },
645 { 0x419ea8, 1, 0x04, 0x00001100 },
646 { 0x419eac, 1, 0x04, 0x11100702 },
647 { 0x419eb0, 1, 0x04, 0x00000003 },
648 { 0x419eb4, 4, 0x04, 0x00000000 },
649 { 0x419ec8, 1, 0x04, 0x06060618 },
650 { 0x419ed0, 1, 0x04, 0x0eff0e38 },
651 { 0x419ed4, 1, 0x04, 0x011104f1 },
652 { 0x419edc, 1, 0x04, 0x00000000 },
653 { 0x419f00, 1, 0x04, 0x00000000 },
654 { 0x419f2c, 1, 0x04, 0x00000000 },
655 {}
656 };
657
658 const struct gf100_gr_init
659 gf100_gr_init_be_0[] = {
660 { 0x40880c, 1, 0x04, 0x00000000 },
661 { 0x408910, 9, 0x04, 0x00000000 },
662 { 0x408950, 1, 0x04, 0x00000000 },
663 { 0x408954, 1, 0x04, 0x0000ffff },
664 { 0x408984, 1, 0x04, 0x00000000 },
665 { 0x408988, 1, 0x04, 0x08040201 },
666 { 0x40898c, 1, 0x04, 0x80402010 },
667 {}
668 };
669
670 const struct gf100_gr_init
671 gf100_gr_init_fe_1[] = {
672 { 0x4040f0, 1, 0x04, 0x00000000 },
673 {}
674 };
675
676 const struct gf100_gr_init
677 gf100_gr_init_pe_1[] = {
678 { 0x419880, 1, 0x04, 0x00000002 },
679 {}
680 };
681
682 static const struct gf100_gr_pack
683 gf100_gr_pack_mmio[] = {
684 { gf100_gr_init_main_0 },
685 { gf100_gr_init_fe_0 },
686 { gf100_gr_init_pri_0 },
687 { gf100_gr_init_rstr2d_0 },
688 { gf100_gr_init_pd_0 },
689 { gf100_gr_init_ds_0 },
690 { gf100_gr_init_scc_0 },
691 { gf100_gr_init_prop_0 },
692 { gf100_gr_init_gpc_unk_0 },
693 { gf100_gr_init_setup_0 },
694 { gf100_gr_init_crstr_0 },
695 { gf100_gr_init_setup_1 },
696 { gf100_gr_init_zcull_0 },
697 { gf100_gr_init_gpm_0 },
698 { gf100_gr_init_gpc_unk_1 },
699 { gf100_gr_init_gcc_0 },
700 { gf100_gr_init_tpccs_0 },
701 { gf100_gr_init_tex_0 },
702 { gf100_gr_init_pe_0 },
703 { gf100_gr_init_l1c_0 },
704 { gf100_gr_init_wwdx_0 },
705 { gf100_gr_init_tpccs_1 },
706 { gf100_gr_init_mpc_0 },
707 { gf100_gr_init_sm_0 },
708 { gf100_gr_init_be_0 },
709 { gf100_gr_init_fe_1 },
710 { gf100_gr_init_pe_1 },
711 {}
712 };
713
714 /*******************************************************************************
715 * PGRAPH engine/subdev functions
716 ******************************************************************************/
717
718 static bool
gf100_gr_chsw_load(struct nvkm_gr * base)719 gf100_gr_chsw_load(struct nvkm_gr *base)
720 {
721 struct gf100_gr *gr = gf100_gr(base);
722 if (!gr->firmware) {
723 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c);
724 if (trace & 0x00000040)
725 return true;
726 } else {
727 u32 mthd = nvkm_rd32(gr->base.engine.subdev.device, 0x409808);
728 if (mthd & 0x00080000)
729 return true;
730 }
731 return false;
732 }
733
734 int
gf100_gr_rops(struct gf100_gr * gr)735 gf100_gr_rops(struct gf100_gr *gr)
736 {
737 struct nvkm_device *device = gr->base.engine.subdev.device;
738 return (nvkm_rd32(device, 0x409604) & 0x001f0000) >> 16;
739 }
740
741 void
gf100_gr_zbc_init(struct gf100_gr * gr)742 gf100_gr_zbc_init(struct gf100_gr *gr)
743 {
744 const u32 zero[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
745 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
746 const u32 one[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
747 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff };
748 const u32 f32_0[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000,
749 0x00000000, 0x00000000, 0x00000000, 0x00000000 };
750 const u32 f32_1[] = { 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000,
751 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000 };
752 struct nvkm_ltc *ltc = gr->base.engine.subdev.device->ltc;
753 int index, c = ltc->zbc_min, d = ltc->zbc_min, s = ltc->zbc_min;
754
755 if (!gr->zbc_color[0].format) {
756 gf100_gr_zbc_color_get(gr, 1, & zero[0], &zero[4]); c++;
757 gf100_gr_zbc_color_get(gr, 2, & one[0], &one[4]); c++;
758 gf100_gr_zbc_color_get(gr, 4, &f32_0[0], &f32_0[4]); c++;
759 gf100_gr_zbc_color_get(gr, 4, &f32_1[0], &f32_1[4]); c++;
760 gf100_gr_zbc_depth_get(gr, 1, 0x00000000, 0x00000000); d++;
761 gf100_gr_zbc_depth_get(gr, 1, 0x3f800000, 0x3f800000); d++;
762 if (gr->func->zbc->stencil_get) {
763 gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++;
764 gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++;
765 gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++;
766 }
767 }
768
769 for (index = c; index <= ltc->zbc_max; index++)
770 gr->func->zbc->clear_color(gr, index);
771 for (index = d; index <= ltc->zbc_max; index++)
772 gr->func->zbc->clear_depth(gr, index);
773
774 if (gr->func->zbc->clear_stencil) {
775 for (index = s; index <= ltc->zbc_max; index++)
776 gr->func->zbc->clear_stencil(gr, index);
777 }
778 }
779
780 /**
781 * Wait until GR goes idle. GR is considered idle if it is disabled by the
782 * MC (0x200) register, or GR is not busy and a context switch is not in
783 * progress.
784 */
785 int
gf100_gr_wait_idle(struct gf100_gr * gr)786 gf100_gr_wait_idle(struct gf100_gr *gr)
787 {
788 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
789 struct nvkm_device *device = subdev->device;
790 unsigned long end_jiffies = jiffies + msecs_to_jiffies(2000);
791 bool gr_enabled, ctxsw_active, gr_busy;
792
793 do {
794 /*
795 * required to make sure FIFO_ENGINE_STATUS (0x2640) is
796 * up-to-date
797 */
798 nvkm_rd32(device, 0x400700);
799
800 gr_enabled = nvkm_rd32(device, 0x200) & 0x1000;
801 ctxsw_active = nvkm_rd32(device, 0x2640) & 0x8000;
802 gr_busy = nvkm_rd32(device, 0x40060c) & 0x1;
803
804 if (!gr_enabled || (!gr_busy && !ctxsw_active))
805 return 0;
806 } while (time_before(jiffies, end_jiffies));
807
808 nvkm_error(subdev,
809 "wait for idle timeout (en: %d, ctxsw: %d, busy: %d)\n",
810 gr_enabled, ctxsw_active, gr_busy);
811 return -EAGAIN;
812 }
813
814 void
gf100_gr_mmio(struct gf100_gr * gr,const struct gf100_gr_pack * p)815 gf100_gr_mmio(struct gf100_gr *gr, const struct gf100_gr_pack *p)
816 {
817 struct nvkm_device *device = gr->base.engine.subdev.device;
818 const struct gf100_gr_pack *pack;
819 const struct gf100_gr_init *init;
820
821 pack_for_each_init(init, pack, p) {
822 u32 next = init->addr + init->count * init->pitch;
823 u32 addr = init->addr;
824 while (addr < next) {
825 nvkm_wr32(device, addr, init->data);
826 addr += init->pitch;
827 }
828 }
829 }
830
831 void
gf100_gr_icmd(struct gf100_gr * gr,const struct gf100_gr_pack * p)832 gf100_gr_icmd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
833 {
834 struct nvkm_device *device = gr->base.engine.subdev.device;
835 const struct gf100_gr_pack *pack;
836 const struct gf100_gr_init *init;
837 u32 data = 0;
838
839 nvkm_wr32(device, 0x400208, 0x80000000);
840
841 pack_for_each_init(init, pack, p) {
842 u32 next = init->addr + init->count * init->pitch;
843 u32 addr = init->addr;
844
845 if ((pack == p && init == p->init) || data != init->data) {
846 nvkm_wr32(device, 0x400204, init->data);
847 data = init->data;
848 }
849
850 while (addr < next) {
851 nvkm_wr32(device, 0x400200, addr);
852 /**
853 * Wait for GR to go idle after submitting a
854 * GO_IDLE bundle
855 */
856 if ((addr & 0xffff) == 0xe100)
857 gf100_gr_wait_idle(gr);
858 nvkm_msec(device, 2000,
859 if (!(nvkm_rd32(device, 0x400700) & 0x00000004))
860 break;
861 );
862 addr += init->pitch;
863 }
864 }
865
866 nvkm_wr32(device, 0x400208, 0x00000000);
867 }
868
869 void
gf100_gr_mthd(struct gf100_gr * gr,const struct gf100_gr_pack * p)870 gf100_gr_mthd(struct gf100_gr *gr, const struct gf100_gr_pack *p)
871 {
872 struct nvkm_device *device = gr->base.engine.subdev.device;
873 const struct gf100_gr_pack *pack;
874 const struct gf100_gr_init *init;
875 u32 data = 0;
876
877 pack_for_each_init(init, pack, p) {
878 u32 ctrl = 0x80000000 | pack->type;
879 u32 next = init->addr + init->count * init->pitch;
880 u32 addr = init->addr;
881
882 if ((pack == p && init == p->init) || data != init->data) {
883 nvkm_wr32(device, 0x40448c, init->data);
884 data = init->data;
885 }
886
887 while (addr < next) {
888 nvkm_wr32(device, 0x404488, ctrl | (addr << 14));
889 addr += init->pitch;
890 }
891 }
892 }
893
894 u64
gf100_gr_units(struct nvkm_gr * base)895 gf100_gr_units(struct nvkm_gr *base)
896 {
897 struct gf100_gr *gr = gf100_gr(base);
898 u64 cfg;
899
900 cfg = (u32)gr->gpc_nr;
901 cfg |= (u32)gr->tpc_total << 8;
902 cfg |= (u64)gr->rop_nr << 32;
903
904 return cfg;
905 }
906
907 static const struct nvkm_bitfield gf100_dispatch_error[] = {
908 { 0x00000001, "INJECTED_BUNDLE_ERROR" },
909 { 0x00000002, "CLASS_SUBCH_MISMATCH" },
910 { 0x00000004, "SUBCHSW_DURING_NOTIFY" },
911 {}
912 };
913
914 static const struct nvkm_bitfield gf100_m2mf_error[] = {
915 { 0x00000001, "PUSH_TOO_MUCH_DATA" },
916 { 0x00000002, "PUSH_NOT_ENOUGH_DATA" },
917 {}
918 };
919
920 static const struct nvkm_bitfield gf100_unk6_error[] = {
921 { 0x00000001, "TEMP_TOO_SMALL" },
922 {}
923 };
924
925 static const struct nvkm_bitfield gf100_ccache_error[] = {
926 { 0x00000001, "INTR" },
927 { 0x00000002, "LDCONST_OOB" },
928 {}
929 };
930
931 static const struct nvkm_bitfield gf100_macro_error[] = {
932 { 0x00000001, "TOO_FEW_PARAMS" },
933 { 0x00000002, "TOO_MANY_PARAMS" },
934 { 0x00000004, "ILLEGAL_OPCODE" },
935 { 0x00000008, "DOUBLE_BRANCH" },
936 { 0x00000010, "WATCHDOG" },
937 {}
938 };
939
940 static const struct nvkm_bitfield gk104_sked_error[] = {
941 { 0x00000040, "CTA_RESUME" },
942 { 0x00000080, "CONSTANT_BUFFER_SIZE" },
943 { 0x00000200, "LOCAL_MEMORY_SIZE_POS" },
944 { 0x00000400, "LOCAL_MEMORY_SIZE_NEG" },
945 { 0x00000800, "WARP_CSTACK_SIZE" },
946 { 0x00001000, "TOTAL_TEMP_SIZE" },
947 { 0x00002000, "REGISTER_COUNT" },
948 { 0x00040000, "TOTAL_THREADS" },
949 { 0x00100000, "PROGRAM_OFFSET" },
950 { 0x00200000, "SHARED_MEMORY_SIZE" },
951 { 0x00800000, "CTA_THREAD_DIMENSION_ZERO" },
952 { 0x01000000, "MEMORY_WINDOW_OVERLAP" },
953 { 0x02000000, "SHARED_CONFIG_TOO_SMALL" },
954 { 0x04000000, "TOTAL_REGISTER_COUNT" },
955 {}
956 };
957
958 static const struct nvkm_bitfield gf100_gpc_rop_error[] = {
959 { 0x00000002, "RT_PITCH_OVERRUN" },
960 { 0x00000010, "RT_WIDTH_OVERRUN" },
961 { 0x00000020, "RT_HEIGHT_OVERRUN" },
962 { 0x00000080, "ZETA_STORAGE_TYPE_MISMATCH" },
963 { 0x00000100, "RT_STORAGE_TYPE_MISMATCH" },
964 { 0x00000400, "RT_LINEAR_MISMATCH" },
965 {}
966 };
967
968 static void
gf100_gr_trap_gpc_rop(struct gf100_gr * gr,int gpc)969 gf100_gr_trap_gpc_rop(struct gf100_gr *gr, int gpc)
970 {
971 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
972 struct nvkm_device *device = subdev->device;
973 char error[128];
974 u32 trap[4];
975
976 trap[0] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0420)) & 0x3fffffff;
977 trap[1] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0434));
978 trap[2] = nvkm_rd32(device, GPC_UNIT(gpc, 0x0438));
979 trap[3] = nvkm_rd32(device, GPC_UNIT(gpc, 0x043c));
980
981 nvkm_snprintbf(error, sizeof(error), gf100_gpc_rop_error, trap[0]);
982
983 nvkm_error(subdev, "GPC%d/PROP trap: %08x [%s] x = %u, y = %u, "
984 "format = %x, storage type = %x\n",
985 gpc, trap[0], error, trap[1] & 0xffff, trap[1] >> 16,
986 (trap[2] >> 8) & 0x3f, trap[3] & 0xff);
987 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
988 }
989
990 const struct nvkm_enum gf100_mp_warp_error[] = {
991 { 0x01, "STACK_ERROR" },
992 { 0x02, "API_STACK_ERROR" },
993 { 0x03, "RET_EMPTY_STACK_ERROR" },
994 { 0x04, "PC_WRAP" },
995 { 0x05, "MISALIGNED_PC" },
996 { 0x06, "PC_OVERFLOW" },
997 { 0x07, "MISALIGNED_IMMC_ADDR" },
998 { 0x08, "MISALIGNED_REG" },
999 { 0x09, "ILLEGAL_INSTR_ENCODING" },
1000 { 0x0a, "ILLEGAL_SPH_INSTR_COMBO" },
1001 { 0x0b, "ILLEGAL_INSTR_PARAM" },
1002 { 0x0c, "INVALID_CONST_ADDR" },
1003 { 0x0d, "OOR_REG" },
1004 { 0x0e, "OOR_ADDR" },
1005 { 0x0f, "MISALIGNED_ADDR" },
1006 { 0x10, "INVALID_ADDR_SPACE" },
1007 { 0x11, "ILLEGAL_INSTR_PARAM2" },
1008 { 0x12, "INVALID_CONST_ADDR_LDC" },
1009 { 0x13, "GEOMETRY_SM_ERROR" },
1010 { 0x14, "DIVERGENT" },
1011 { 0x15, "WARP_EXIT" },
1012 {}
1013 };
1014
1015 const struct nvkm_bitfield gf100_mp_global_error[] = {
1016 { 0x00000001, "SM_TO_SM_FAULT" },
1017 { 0x00000002, "L1_ERROR" },
1018 { 0x00000004, "MULTIPLE_WARP_ERRORS" },
1019 { 0x00000008, "PHYSICAL_STACK_OVERFLOW" },
1020 { 0x00000010, "BPT_INT" },
1021 { 0x00000020, "BPT_PAUSE" },
1022 { 0x00000040, "SINGLE_STEP_COMPLETE" },
1023 { 0x20000000, "ECC_SEC_ERROR" },
1024 { 0x40000000, "ECC_DED_ERROR" },
1025 { 0x80000000, "TIMEOUT" },
1026 {}
1027 };
1028
1029 void
gf100_gr_trap_mp(struct gf100_gr * gr,int gpc,int tpc)1030 gf100_gr_trap_mp(struct gf100_gr *gr, int gpc, int tpc)
1031 {
1032 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1033 struct nvkm_device *device = subdev->device;
1034 u32 werr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x648));
1035 u32 gerr = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x650));
1036 const struct nvkm_enum *warp;
1037 char glob[128];
1038
1039 nvkm_snprintbf(glob, sizeof(glob), gf100_mp_global_error, gerr);
1040 warp = nvkm_enum_find(gf100_mp_warp_error, werr & 0xffff);
1041
1042 nvkm_error(subdev, "GPC%i/TPC%i/MP trap: "
1043 "global %08x [%s] warp %04x [%s]\n",
1044 gpc, tpc, gerr, glob, werr, warp ? warp->name : "");
1045
1046 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x648), 0x00000000);
1047 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x650), gerr);
1048 }
1049
1050 static void
gf100_gr_trap_tpc(struct gf100_gr * gr,int gpc,int tpc)1051 gf100_gr_trap_tpc(struct gf100_gr *gr, int gpc, int tpc)
1052 {
1053 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1054 struct nvkm_device *device = subdev->device;
1055 u32 stat = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0508));
1056
1057 if (stat & 0x00000001) {
1058 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0224));
1059 nvkm_error(subdev, "GPC%d/TPC%d/TEX: %08x\n", gpc, tpc, trap);
1060 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0224), 0xc0000000);
1061 stat &= ~0x00000001;
1062 }
1063
1064 if (stat & 0x00000002) {
1065 gr->func->trap_mp(gr, gpc, tpc);
1066 stat &= ~0x00000002;
1067 }
1068
1069 if (stat & 0x00000004) {
1070 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0084));
1071 nvkm_error(subdev, "GPC%d/TPC%d/POLY: %08x\n", gpc, tpc, trap);
1072 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0084), 0xc0000000);
1073 stat &= ~0x00000004;
1074 }
1075
1076 if (stat & 0x00000008) {
1077 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x048c));
1078 nvkm_error(subdev, "GPC%d/TPC%d/L1C: %08x\n", gpc, tpc, trap);
1079 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x048c), 0xc0000000);
1080 stat &= ~0x00000008;
1081 }
1082
1083 if (stat & 0x00000010) {
1084 u32 trap = nvkm_rd32(device, TPC_UNIT(gpc, tpc, 0x0430));
1085 nvkm_error(subdev, "GPC%d/TPC%d/MPC: %08x\n", gpc, tpc, trap);
1086 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x0430), 0xc0000000);
1087 stat &= ~0x00000010;
1088 }
1089
1090 if (stat) {
1091 nvkm_error(subdev, "GPC%d/TPC%d/%08x: unknown\n", gpc, tpc, stat);
1092 }
1093 }
1094
1095 static void
gf100_gr_trap_gpc(struct gf100_gr * gr,int gpc)1096 gf100_gr_trap_gpc(struct gf100_gr *gr, int gpc)
1097 {
1098 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1099 struct nvkm_device *device = subdev->device;
1100 u32 stat = nvkm_rd32(device, GPC_UNIT(gpc, 0x2c90));
1101 int tpc;
1102
1103 if (stat & 0x00000001) {
1104 gf100_gr_trap_gpc_rop(gr, gpc);
1105 stat &= ~0x00000001;
1106 }
1107
1108 if (stat & 0x00000002) {
1109 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0900));
1110 nvkm_error(subdev, "GPC%d/ZCULL: %08x\n", gpc, trap);
1111 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
1112 stat &= ~0x00000002;
1113 }
1114
1115 if (stat & 0x00000004) {
1116 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x1028));
1117 nvkm_error(subdev, "GPC%d/CCACHE: %08x\n", gpc, trap);
1118 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
1119 stat &= ~0x00000004;
1120 }
1121
1122 if (stat & 0x00000008) {
1123 u32 trap = nvkm_rd32(device, GPC_UNIT(gpc, 0x0824));
1124 nvkm_error(subdev, "GPC%d/ESETUP: %08x\n", gpc, trap);
1125 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
1126 stat &= ~0x00000009;
1127 }
1128
1129 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
1130 u32 mask = 0x00010000 << tpc;
1131 if (stat & mask) {
1132 gf100_gr_trap_tpc(gr, gpc, tpc);
1133 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), mask);
1134 stat &= ~mask;
1135 }
1136 }
1137
1138 if (stat) {
1139 nvkm_error(subdev, "GPC%d/%08x: unknown\n", gpc, stat);
1140 }
1141 }
1142
1143 static void
gf100_gr_trap_intr(struct gf100_gr * gr)1144 gf100_gr_trap_intr(struct gf100_gr *gr)
1145 {
1146 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1147 struct nvkm_device *device = subdev->device;
1148 char error[128];
1149 u32 trap = nvkm_rd32(device, 0x400108);
1150 int rop, gpc;
1151
1152 if (trap & 0x00000001) {
1153 u32 stat = nvkm_rd32(device, 0x404000);
1154
1155 nvkm_snprintbf(error, sizeof(error), gf100_dispatch_error,
1156 stat & 0x3fffffff);
1157 nvkm_error(subdev, "DISPATCH %08x [%s]\n", stat, error);
1158 nvkm_wr32(device, 0x404000, 0xc0000000);
1159 nvkm_wr32(device, 0x400108, 0x00000001);
1160 trap &= ~0x00000001;
1161 }
1162
1163 if (trap & 0x00000002) {
1164 u32 stat = nvkm_rd32(device, 0x404600);
1165
1166 nvkm_snprintbf(error, sizeof(error), gf100_m2mf_error,
1167 stat & 0x3fffffff);
1168 nvkm_error(subdev, "M2MF %08x [%s]\n", stat, error);
1169
1170 nvkm_wr32(device, 0x404600, 0xc0000000);
1171 nvkm_wr32(device, 0x400108, 0x00000002);
1172 trap &= ~0x00000002;
1173 }
1174
1175 if (trap & 0x00000008) {
1176 u32 stat = nvkm_rd32(device, 0x408030);
1177
1178 nvkm_snprintbf(error, sizeof(error), gf100_ccache_error,
1179 stat & 0x3fffffff);
1180 nvkm_error(subdev, "CCACHE %08x [%s]\n", stat, error);
1181 nvkm_wr32(device, 0x408030, 0xc0000000);
1182 nvkm_wr32(device, 0x400108, 0x00000008);
1183 trap &= ~0x00000008;
1184 }
1185
1186 if (trap & 0x00000010) {
1187 u32 stat = nvkm_rd32(device, 0x405840);
1188 nvkm_error(subdev, "SHADER %08x, sph: 0x%06x, stage: 0x%02x\n",
1189 stat, stat & 0xffffff, (stat >> 24) & 0x3f);
1190 nvkm_wr32(device, 0x405840, 0xc0000000);
1191 nvkm_wr32(device, 0x400108, 0x00000010);
1192 trap &= ~0x00000010;
1193 }
1194
1195 if (trap & 0x00000040) {
1196 u32 stat = nvkm_rd32(device, 0x40601c);
1197
1198 nvkm_snprintbf(error, sizeof(error), gf100_unk6_error,
1199 stat & 0x3fffffff);
1200 nvkm_error(subdev, "UNK6 %08x [%s]\n", stat, error);
1201
1202 nvkm_wr32(device, 0x40601c, 0xc0000000);
1203 nvkm_wr32(device, 0x400108, 0x00000040);
1204 trap &= ~0x00000040;
1205 }
1206
1207 if (trap & 0x00000080) {
1208 u32 stat = nvkm_rd32(device, 0x404490);
1209 u32 pc = nvkm_rd32(device, 0x404494);
1210 u32 op = nvkm_rd32(device, 0x40449c);
1211
1212 nvkm_snprintbf(error, sizeof(error), gf100_macro_error,
1213 stat & 0x1fffffff);
1214 nvkm_error(subdev, "MACRO %08x [%s], pc: 0x%03x%s, op: 0x%08x\n",
1215 stat, error, pc & 0x7ff,
1216 (pc & 0x10000000) ? "" : " (invalid)",
1217 op);
1218
1219 nvkm_wr32(device, 0x404490, 0xc0000000);
1220 nvkm_wr32(device, 0x400108, 0x00000080);
1221 trap &= ~0x00000080;
1222 }
1223
1224 if (trap & 0x00000100) {
1225 u32 stat = nvkm_rd32(device, 0x407020) & 0x3fffffff;
1226
1227 nvkm_snprintbf(error, sizeof(error), gk104_sked_error, stat);
1228 nvkm_error(subdev, "SKED: %08x [%s]\n", stat, error);
1229
1230 if (stat)
1231 nvkm_wr32(device, 0x407020, 0x40000000);
1232 nvkm_wr32(device, 0x400108, 0x00000100);
1233 trap &= ~0x00000100;
1234 }
1235
1236 if (trap & 0x01000000) {
1237 u32 stat = nvkm_rd32(device, 0x400118);
1238 for (gpc = 0; stat && gpc < gr->gpc_nr; gpc++) {
1239 u32 mask = 0x00000001 << gpc;
1240 if (stat & mask) {
1241 gf100_gr_trap_gpc(gr, gpc);
1242 nvkm_wr32(device, 0x400118, mask);
1243 stat &= ~mask;
1244 }
1245 }
1246 nvkm_wr32(device, 0x400108, 0x01000000);
1247 trap &= ~0x01000000;
1248 }
1249
1250 if (trap & 0x02000000) {
1251 for (rop = 0; rop < gr->rop_nr; rop++) {
1252 u32 statz = nvkm_rd32(device, ROP_UNIT(rop, 0x070));
1253 u32 statc = nvkm_rd32(device, ROP_UNIT(rop, 0x144));
1254 nvkm_error(subdev, "ROP%d %08x %08x\n",
1255 rop, statz, statc);
1256 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0xc0000000);
1257 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0xc0000000);
1258 }
1259 nvkm_wr32(device, 0x400108, 0x02000000);
1260 trap &= ~0x02000000;
1261 }
1262
1263 if (trap) {
1264 nvkm_error(subdev, "TRAP UNHANDLED %08x\n", trap);
1265 nvkm_wr32(device, 0x400108, trap);
1266 }
1267 }
1268
1269 static void
gf100_gr_ctxctl_debug_unit(struct gf100_gr * gr,u32 base)1270 gf100_gr_ctxctl_debug_unit(struct gf100_gr *gr, u32 base)
1271 {
1272 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1273 struct nvkm_device *device = subdev->device;
1274 nvkm_error(subdev, "%06x - done %08x\n", base,
1275 nvkm_rd32(device, base + 0x400));
1276 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1277 nvkm_rd32(device, base + 0x800),
1278 nvkm_rd32(device, base + 0x804),
1279 nvkm_rd32(device, base + 0x808),
1280 nvkm_rd32(device, base + 0x80c));
1281 nvkm_error(subdev, "%06x - stat %08x %08x %08x %08x\n", base,
1282 nvkm_rd32(device, base + 0x810),
1283 nvkm_rd32(device, base + 0x814),
1284 nvkm_rd32(device, base + 0x818),
1285 nvkm_rd32(device, base + 0x81c));
1286 }
1287
1288 void
gf100_gr_ctxctl_debug(struct gf100_gr * gr)1289 gf100_gr_ctxctl_debug(struct gf100_gr *gr)
1290 {
1291 struct nvkm_device *device = gr->base.engine.subdev.device;
1292 u32 gpcnr = nvkm_rd32(device, 0x409604) & 0xffff;
1293 u32 gpc;
1294
1295 gf100_gr_ctxctl_debug_unit(gr, 0x409000);
1296 for (gpc = 0; gpc < gpcnr; gpc++)
1297 gf100_gr_ctxctl_debug_unit(gr, 0x502000 + (gpc * 0x8000));
1298 }
1299
1300 static void
gf100_gr_ctxctl_isr(struct gf100_gr * gr)1301 gf100_gr_ctxctl_isr(struct gf100_gr *gr)
1302 {
1303 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1304 struct nvkm_device *device = subdev->device;
1305 u32 stat = nvkm_rd32(device, 0x409c18);
1306
1307 if (!gr->firmware && (stat & 0x00000001)) {
1308 u32 code = nvkm_rd32(device, 0x409814);
1309 if (code == E_BAD_FWMTHD) {
1310 u32 class = nvkm_rd32(device, 0x409808);
1311 u32 addr = nvkm_rd32(device, 0x40980c);
1312 u32 subc = (addr & 0x00070000) >> 16;
1313 u32 mthd = (addr & 0x00003ffc);
1314 u32 data = nvkm_rd32(device, 0x409810);
1315
1316 nvkm_error(subdev, "FECS MTHD subc %d class %04x "
1317 "mthd %04x data %08x\n",
1318 subc, class, mthd, data);
1319 } else {
1320 nvkm_error(subdev, "FECS ucode error %d\n", code);
1321 }
1322 nvkm_wr32(device, 0x409c20, 0x00000001);
1323 stat &= ~0x00000001;
1324 }
1325
1326 if (!gr->firmware && (stat & 0x00080000)) {
1327 nvkm_error(subdev, "FECS watchdog timeout\n");
1328 gf100_gr_ctxctl_debug(gr);
1329 nvkm_wr32(device, 0x409c20, 0x00080000);
1330 stat &= ~0x00080000;
1331 }
1332
1333 if (stat) {
1334 nvkm_error(subdev, "FECS %08x\n", stat);
1335 gf100_gr_ctxctl_debug(gr);
1336 nvkm_wr32(device, 0x409c20, stat);
1337 }
1338 }
1339
1340 static void
gf100_gr_intr(struct nvkm_gr * base)1341 gf100_gr_intr(struct nvkm_gr *base)
1342 {
1343 struct gf100_gr *gr = gf100_gr(base);
1344 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1345 struct nvkm_device *device = subdev->device;
1346 struct nvkm_fifo_chan *chan;
1347 unsigned long flags;
1348 u64 inst = nvkm_rd32(device, 0x409b00) & 0x0fffffff;
1349 u32 stat = nvkm_rd32(device, 0x400100);
1350 u32 addr = nvkm_rd32(device, 0x400704);
1351 u32 mthd = (addr & 0x00003ffc);
1352 u32 subc = (addr & 0x00070000) >> 16;
1353 u32 data = nvkm_rd32(device, 0x400708);
1354 u32 code = nvkm_rd32(device, 0x400110);
1355 u32 class;
1356 const char *name = "unknown";
1357 int chid = -1;
1358
1359 chan = nvkm_fifo_chan_inst(device->fifo, (u64)inst << 12, &flags);
1360 if (chan) {
1361 name = chan->object.client->name;
1362 chid = chan->chid;
1363 }
1364
1365 if (device->card_type < NV_E0 || subc < 4)
1366 class = nvkm_rd32(device, 0x404200 + (subc * 4));
1367 else
1368 class = 0x0000;
1369
1370 if (stat & 0x00000001) {
1371 /*
1372 * notifier interrupt, only needed for cyclestats
1373 * can be safely ignored
1374 */
1375 nvkm_wr32(device, 0x400100, 0x00000001);
1376 stat &= ~0x00000001;
1377 }
1378
1379 if (stat & 0x00000010) {
1380 if (!gf100_gr_mthd_sw(device, class, mthd, data)) {
1381 nvkm_error(subdev, "ILLEGAL_MTHD ch %d [%010llx %s] "
1382 "subc %d class %04x mthd %04x data %08x\n",
1383 chid, inst << 12, name, subc,
1384 class, mthd, data);
1385 }
1386 nvkm_wr32(device, 0x400100, 0x00000010);
1387 stat &= ~0x00000010;
1388 }
1389
1390 if (stat & 0x00000020) {
1391 nvkm_error(subdev, "ILLEGAL_CLASS ch %d [%010llx %s] "
1392 "subc %d class %04x mthd %04x data %08x\n",
1393 chid, inst << 12, name, subc, class, mthd, data);
1394 nvkm_wr32(device, 0x400100, 0x00000020);
1395 stat &= ~0x00000020;
1396 }
1397
1398 if (stat & 0x00100000) {
1399 const struct nvkm_enum *en =
1400 nvkm_enum_find(nv50_data_error_names, code);
1401 nvkm_error(subdev, "DATA_ERROR %08x [%s] ch %d [%010llx %s] "
1402 "subc %d class %04x mthd %04x data %08x\n",
1403 code, en ? en->name : "", chid, inst << 12,
1404 name, subc, class, mthd, data);
1405 nvkm_wr32(device, 0x400100, 0x00100000);
1406 stat &= ~0x00100000;
1407 }
1408
1409 if (stat & 0x00200000) {
1410 nvkm_error(subdev, "TRAP ch %d [%010llx %s]\n",
1411 chid, inst << 12, name);
1412 gf100_gr_trap_intr(gr);
1413 nvkm_wr32(device, 0x400100, 0x00200000);
1414 stat &= ~0x00200000;
1415 }
1416
1417 if (stat & 0x00080000) {
1418 gf100_gr_ctxctl_isr(gr);
1419 nvkm_wr32(device, 0x400100, 0x00080000);
1420 stat &= ~0x00080000;
1421 }
1422
1423 if (stat) {
1424 nvkm_error(subdev, "intr %08x\n", stat);
1425 nvkm_wr32(device, 0x400100, stat);
1426 }
1427
1428 nvkm_wr32(device, 0x400500, 0x00010001);
1429 nvkm_fifo_chan_put(device->fifo, flags, &chan);
1430 }
1431
1432 static void
gf100_gr_init_fw(struct nvkm_falcon * falcon,struct gf100_gr_fuc * code,struct gf100_gr_fuc * data)1433 gf100_gr_init_fw(struct nvkm_falcon *falcon,
1434 struct gf100_gr_fuc *code, struct gf100_gr_fuc *data)
1435 {
1436 nvkm_falcon_load_dmem(falcon, data->data, 0x0, data->size, 0);
1437 nvkm_falcon_load_imem(falcon, code->data, 0x0, code->size, 0, 0, false);
1438 }
1439
1440 static void
gf100_gr_init_csdata(struct gf100_gr * gr,const struct gf100_gr_pack * pack,u32 falcon,u32 starstar,u32 base)1441 gf100_gr_init_csdata(struct gf100_gr *gr,
1442 const struct gf100_gr_pack *pack,
1443 u32 falcon, u32 starstar, u32 base)
1444 {
1445 struct nvkm_device *device = gr->base.engine.subdev.device;
1446 const struct gf100_gr_pack *iter;
1447 const struct gf100_gr_init *init;
1448 u32 addr = ~0, prev = ~0, xfer = 0;
1449 u32 star, temp;
1450
1451 nvkm_wr32(device, falcon + 0x01c0, 0x02000000 + starstar);
1452 star = nvkm_rd32(device, falcon + 0x01c4);
1453 temp = nvkm_rd32(device, falcon + 0x01c4);
1454 if (temp > star)
1455 star = temp;
1456 nvkm_wr32(device, falcon + 0x01c0, 0x01000000 + star);
1457
1458 pack_for_each_init(init, iter, pack) {
1459 u32 head = init->addr - base;
1460 u32 tail = head + init->count * init->pitch;
1461 while (head < tail) {
1462 if (head != prev + 4 || xfer >= 32) {
1463 if (xfer) {
1464 u32 data = ((--xfer << 26) | addr);
1465 nvkm_wr32(device, falcon + 0x01c4, data);
1466 star += 4;
1467 }
1468 addr = head;
1469 xfer = 0;
1470 }
1471 prev = head;
1472 xfer = xfer + 1;
1473 head = head + init->pitch;
1474 }
1475 }
1476
1477 nvkm_wr32(device, falcon + 0x01c4, (--xfer << 26) | addr);
1478 nvkm_wr32(device, falcon + 0x01c0, 0x01000004 + starstar);
1479 nvkm_wr32(device, falcon + 0x01c4, star + 4);
1480 }
1481
1482 /* Initialize context from an external (secure or not) firmware */
1483 static int
gf100_gr_init_ctxctl_ext(struct gf100_gr * gr)1484 gf100_gr_init_ctxctl_ext(struct gf100_gr *gr)
1485 {
1486 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1487 struct nvkm_device *device = subdev->device;
1488 struct nvkm_secboot *sb = device->secboot;
1489 u32 secboot_mask = 0;
1490
1491 /* load fuc microcode */
1492 nvkm_mc_unk260(device, 0);
1493
1494 /* securely-managed falcons must be reset using secure boot */
1495 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
1496 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_FECS);
1497 else
1498 gf100_gr_init_fw(gr->fecs, &gr->fuc409c, &gr->fuc409d);
1499
1500 if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
1501 secboot_mask |= BIT(NVKM_SECBOOT_FALCON_GPCCS);
1502 else
1503 gf100_gr_init_fw(gr->gpccs, &gr->fuc41ac, &gr->fuc41ad);
1504
1505 if (secboot_mask != 0) {
1506 int ret = nvkm_secboot_reset(sb, secboot_mask);
1507 if (ret)
1508 return ret;
1509 }
1510
1511 nvkm_mc_unk260(device, 1);
1512
1513 /* start both of them running */
1514 nvkm_wr32(device, 0x409840, 0xffffffff);
1515 nvkm_wr32(device, 0x41a10c, 0x00000000);
1516 nvkm_wr32(device, 0x40910c, 0x00000000);
1517
1518 nvkm_falcon_start(gr->gpccs);
1519 nvkm_falcon_start(gr->fecs);
1520
1521 if (nvkm_msec(device, 2000,
1522 if (nvkm_rd32(device, 0x409800) & 0x00000001)
1523 break;
1524 ) < 0)
1525 return -EBUSY;
1526
1527 nvkm_wr32(device, 0x409840, 0xffffffff);
1528 nvkm_wr32(device, 0x409500, 0x7fffffff);
1529 nvkm_wr32(device, 0x409504, 0x00000021);
1530
1531 nvkm_wr32(device, 0x409840, 0xffffffff);
1532 nvkm_wr32(device, 0x409500, 0x00000000);
1533 nvkm_wr32(device, 0x409504, 0x00000010);
1534 if (nvkm_msec(device, 2000,
1535 if ((gr->size = nvkm_rd32(device, 0x409800)))
1536 break;
1537 ) < 0)
1538 return -EBUSY;
1539
1540 nvkm_wr32(device, 0x409840, 0xffffffff);
1541 nvkm_wr32(device, 0x409500, 0x00000000);
1542 nvkm_wr32(device, 0x409504, 0x00000016);
1543 if (nvkm_msec(device, 2000,
1544 if (nvkm_rd32(device, 0x409800))
1545 break;
1546 ) < 0)
1547 return -EBUSY;
1548
1549 nvkm_wr32(device, 0x409840, 0xffffffff);
1550 nvkm_wr32(device, 0x409500, 0x00000000);
1551 nvkm_wr32(device, 0x409504, 0x00000025);
1552 if (nvkm_msec(device, 2000,
1553 if (nvkm_rd32(device, 0x409800))
1554 break;
1555 ) < 0)
1556 return -EBUSY;
1557
1558 if (device->chipset >= 0xe0) {
1559 nvkm_wr32(device, 0x409800, 0x00000000);
1560 nvkm_wr32(device, 0x409500, 0x00000001);
1561 nvkm_wr32(device, 0x409504, 0x00000030);
1562 if (nvkm_msec(device, 2000,
1563 if (nvkm_rd32(device, 0x409800))
1564 break;
1565 ) < 0)
1566 return -EBUSY;
1567
1568 nvkm_wr32(device, 0x409810, 0xb00095c8);
1569 nvkm_wr32(device, 0x409800, 0x00000000);
1570 nvkm_wr32(device, 0x409500, 0x00000001);
1571 nvkm_wr32(device, 0x409504, 0x00000031);
1572 if (nvkm_msec(device, 2000,
1573 if (nvkm_rd32(device, 0x409800))
1574 break;
1575 ) < 0)
1576 return -EBUSY;
1577
1578 nvkm_wr32(device, 0x409810, 0x00080420);
1579 nvkm_wr32(device, 0x409800, 0x00000000);
1580 nvkm_wr32(device, 0x409500, 0x00000001);
1581 nvkm_wr32(device, 0x409504, 0x00000032);
1582 if (nvkm_msec(device, 2000,
1583 if (nvkm_rd32(device, 0x409800))
1584 break;
1585 ) < 0)
1586 return -EBUSY;
1587
1588 nvkm_wr32(device, 0x409614, 0x00000070);
1589 nvkm_wr32(device, 0x409614, 0x00000770);
1590 nvkm_wr32(device, 0x40802c, 0x00000001);
1591 }
1592
1593 if (gr->data == NULL) {
1594 int ret = gf100_grctx_generate(gr);
1595 if (ret) {
1596 nvkm_error(subdev, "failed to construct context\n");
1597 return ret;
1598 }
1599 }
1600
1601 return 0;
1602 }
1603
1604 static int
gf100_gr_init_ctxctl_int(struct gf100_gr * gr)1605 gf100_gr_init_ctxctl_int(struct gf100_gr *gr)
1606 {
1607 const struct gf100_grctx_func *grctx = gr->func->grctx;
1608 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1609 struct nvkm_device *device = subdev->device;
1610
1611 if (!gr->func->fecs.ucode) {
1612 return -ENOSYS;
1613 }
1614
1615 /* load HUB microcode */
1616 nvkm_mc_unk260(device, 0);
1617 nvkm_falcon_load_dmem(gr->fecs, gr->func->fecs.ucode->data.data, 0x0,
1618 gr->func->fecs.ucode->data.size, 0);
1619 nvkm_falcon_load_imem(gr->fecs, gr->func->fecs.ucode->code.data, 0x0,
1620 gr->func->fecs.ucode->code.size, 0, 0, false);
1621
1622 /* load GPC microcode */
1623 nvkm_falcon_load_dmem(gr->gpccs, gr->func->gpccs.ucode->data.data, 0x0,
1624 gr->func->gpccs.ucode->data.size, 0);
1625 nvkm_falcon_load_imem(gr->gpccs, gr->func->gpccs.ucode->code.data, 0x0,
1626 gr->func->gpccs.ucode->code.size, 0, 0, false);
1627 nvkm_mc_unk260(device, 1);
1628
1629 /* load register lists */
1630 gf100_gr_init_csdata(gr, grctx->hub, 0x409000, 0x000, 0x000000);
1631 gf100_gr_init_csdata(gr, grctx->gpc_0, 0x41a000, 0x000, 0x418000);
1632 gf100_gr_init_csdata(gr, grctx->gpc_1, 0x41a000, 0x000, 0x418000);
1633 gf100_gr_init_csdata(gr, grctx->tpc, 0x41a000, 0x004, 0x419800);
1634 gf100_gr_init_csdata(gr, grctx->ppc, 0x41a000, 0x008, 0x41be00);
1635
1636 /* start HUB ucode running, it'll init the GPCs */
1637 nvkm_wr32(device, 0x40910c, 0x00000000);
1638 nvkm_wr32(device, 0x409100, 0x00000002);
1639 if (nvkm_msec(device, 2000,
1640 if (nvkm_rd32(device, 0x409800) & 0x80000000)
1641 break;
1642 ) < 0) {
1643 gf100_gr_ctxctl_debug(gr);
1644 return -EBUSY;
1645 }
1646
1647 gr->size = nvkm_rd32(device, 0x409804);
1648 if (gr->data == NULL) {
1649 int ret = gf100_grctx_generate(gr);
1650 if (ret) {
1651 nvkm_error(subdev, "failed to construct context\n");
1652 return ret;
1653 }
1654 }
1655
1656 return 0;
1657 }
1658
1659 int
gf100_gr_init_ctxctl(struct gf100_gr * gr)1660 gf100_gr_init_ctxctl(struct gf100_gr *gr)
1661 {
1662 int ret;
1663
1664 if (gr->firmware)
1665 ret = gf100_gr_init_ctxctl_ext(gr);
1666 else
1667 ret = gf100_gr_init_ctxctl_int(gr);
1668
1669 return ret;
1670 }
1671
1672 void
gf100_gr_oneinit_sm_id(struct gf100_gr * gr)1673 gf100_gr_oneinit_sm_id(struct gf100_gr *gr)
1674 {
1675 int tpc, gpc;
1676 for (tpc = 0; tpc < gr->tpc_max; tpc++) {
1677 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
1678 if (tpc < gr->tpc_nr[gpc]) {
1679 gr->sm[gr->sm_nr].gpc = gpc;
1680 gr->sm[gr->sm_nr].tpc = tpc;
1681 gr->sm_nr++;
1682 }
1683 }
1684 }
1685 }
1686
1687 void
gf100_gr_oneinit_tiles(struct gf100_gr * gr)1688 gf100_gr_oneinit_tiles(struct gf100_gr *gr)
1689 {
1690 static const u8 primes[] = {
1691 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61
1692 };
1693 int init_frac[GPC_MAX], init_err[GPC_MAX], run_err[GPC_MAX], i, j;
1694 u32 mul_factor, comm_denom;
1695 u8 gpc_map[GPC_MAX];
1696 bool sorted;
1697
1698 switch (gr->tpc_total) {
1699 case 15: gr->screen_tile_row_offset = 0x06; break;
1700 case 14: gr->screen_tile_row_offset = 0x05; break;
1701 case 13: gr->screen_tile_row_offset = 0x02; break;
1702 case 11: gr->screen_tile_row_offset = 0x07; break;
1703 case 10: gr->screen_tile_row_offset = 0x06; break;
1704 case 7:
1705 case 5: gr->screen_tile_row_offset = 0x01; break;
1706 case 3: gr->screen_tile_row_offset = 0x02; break;
1707 case 2:
1708 case 1: gr->screen_tile_row_offset = 0x01; break;
1709 default: gr->screen_tile_row_offset = 0x03;
1710 for (i = 0; i < ARRAY_SIZE(primes); i++) {
1711 if (gr->tpc_total % primes[i]) {
1712 gr->screen_tile_row_offset = primes[i];
1713 break;
1714 }
1715 }
1716 break;
1717 }
1718
1719 /* Sort GPCs by TPC count, highest-to-lowest. */
1720 for (i = 0; i < gr->gpc_nr; i++)
1721 gpc_map[i] = i;
1722 sorted = false;
1723
1724 while (!sorted) {
1725 for (sorted = true, i = 0; i < gr->gpc_nr - 1; i++) {
1726 if (gr->tpc_nr[gpc_map[i + 1]] >
1727 gr->tpc_nr[gpc_map[i + 0]]) {
1728 u8 swap = gpc_map[i];
1729 gpc_map[i + 0] = gpc_map[i + 1];
1730 gpc_map[i + 1] = swap;
1731 sorted = false;
1732 }
1733 }
1734 }
1735
1736 /* Determine tile->GPC mapping */
1737 mul_factor = gr->gpc_nr * gr->tpc_max;
1738 if (mul_factor & 1)
1739 mul_factor = 2;
1740 else
1741 mul_factor = 1;
1742
1743 comm_denom = gr->gpc_nr * gr->tpc_max * mul_factor;
1744
1745 for (i = 0; i < gr->gpc_nr; i++) {
1746 init_frac[i] = gr->tpc_nr[gpc_map[i]] * gr->gpc_nr * mul_factor;
1747 init_err[i] = i * gr->tpc_max * mul_factor - comm_denom/2;
1748 run_err[i] = init_frac[i] + init_err[i];
1749 }
1750
1751 for (i = 0; i < gr->tpc_total;) {
1752 for (j = 0; j < gr->gpc_nr; j++) {
1753 if ((run_err[j] * 2) >= comm_denom) {
1754 gr->tile[i++] = gpc_map[j];
1755 run_err[j] += init_frac[j] - comm_denom;
1756 } else {
1757 run_err[j] += init_frac[j];
1758 }
1759 }
1760 }
1761 }
1762
1763 static int
gf100_gr_oneinit(struct nvkm_gr * base)1764 gf100_gr_oneinit(struct nvkm_gr *base)
1765 {
1766 struct gf100_gr *gr = gf100_gr(base);
1767 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1768 struct nvkm_device *device = subdev->device;
1769 int i, j;
1770 int ret;
1771
1772 ret = nvkm_falcon_v1_new(subdev, "FECS", 0x409000, &gr->fecs);
1773 if (ret)
1774 return ret;
1775
1776 ret = nvkm_falcon_v1_new(subdev, "GPCCS", 0x41a000, &gr->gpccs);
1777 if (ret)
1778 return ret;
1779
1780 nvkm_pmu_pgob(device->pmu, false);
1781
1782 gr->rop_nr = gr->func->rops(gr);
1783 gr->gpc_nr = nvkm_rd32(device, 0x409604) & 0x0000001f;
1784 for (i = 0; i < gr->gpc_nr; i++) {
1785 gr->tpc_nr[i] = nvkm_rd32(device, GPC_UNIT(i, 0x2608));
1786 gr->tpc_max = max(gr->tpc_max, gr->tpc_nr[i]);
1787 gr->tpc_total += gr->tpc_nr[i];
1788 gr->ppc_nr[i] = gr->func->ppc_nr;
1789 for (j = 0; j < gr->ppc_nr[i]; j++) {
1790 gr->ppc_tpc_mask[i][j] =
1791 nvkm_rd32(device, GPC_UNIT(i, 0x0c30 + (j * 4)));
1792 if (gr->ppc_tpc_mask[i][j] == 0)
1793 continue;
1794 gr->ppc_mask[i] |= (1 << j);
1795 gr->ppc_tpc_nr[i][j] = hweight8(gr->ppc_tpc_mask[i][j]);
1796 if (gr->ppc_tpc_min == 0 ||
1797 gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j])
1798 gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j];
1799 if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])
1800 gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];
1801 }
1802 }
1803
1804 memset(gr->tile, 0xff, sizeof(gr->tile));
1805 gr->func->oneinit_tiles(gr);
1806 gr->func->oneinit_sm_id(gr);
1807 return 0;
1808 }
1809
1810 static int
gf100_gr_init_(struct nvkm_gr * base)1811 gf100_gr_init_(struct nvkm_gr *base)
1812 {
1813 struct gf100_gr *gr = gf100_gr(base);
1814 struct nvkm_subdev *subdev = &base->engine.subdev;
1815 u32 ret;
1816
1817 nvkm_pmu_pgob(gr->base.engine.subdev.device->pmu, false);
1818
1819 ret = nvkm_falcon_get(gr->fecs, subdev);
1820 if (ret)
1821 return ret;
1822
1823 ret = nvkm_falcon_get(gr->gpccs, subdev);
1824 if (ret)
1825 return ret;
1826
1827 return gr->func->init(gr);
1828 }
1829
1830 static int
gf100_gr_fini_(struct nvkm_gr * base,bool suspend)1831 gf100_gr_fini_(struct nvkm_gr *base, bool suspend)
1832 {
1833 struct gf100_gr *gr = gf100_gr(base);
1834 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1835 nvkm_falcon_put(gr->gpccs, subdev);
1836 nvkm_falcon_put(gr->fecs, subdev);
1837 return 0;
1838 }
1839
1840 void
gf100_gr_dtor_fw(struct gf100_gr_fuc * fuc)1841 gf100_gr_dtor_fw(struct gf100_gr_fuc *fuc)
1842 {
1843 kfree(fuc->data);
1844 fuc->data = NULL;
1845 }
1846
1847 static void
gf100_gr_dtor_init(struct gf100_gr_pack * pack)1848 gf100_gr_dtor_init(struct gf100_gr_pack *pack)
1849 {
1850 vfree(pack);
1851 }
1852
1853 void *
gf100_gr_dtor(struct nvkm_gr * base)1854 gf100_gr_dtor(struct nvkm_gr *base)
1855 {
1856 struct gf100_gr *gr = gf100_gr(base);
1857
1858 if (gr->func->dtor)
1859 gr->func->dtor(gr);
1860 kfree(gr->data);
1861
1862 nvkm_falcon_del(&gr->gpccs);
1863 nvkm_falcon_del(&gr->fecs);
1864
1865 gf100_gr_dtor_fw(&gr->fuc409c);
1866 gf100_gr_dtor_fw(&gr->fuc409d);
1867 gf100_gr_dtor_fw(&gr->fuc41ac);
1868 gf100_gr_dtor_fw(&gr->fuc41ad);
1869
1870 gf100_gr_dtor_init(gr->fuc_bundle);
1871 gf100_gr_dtor_init(gr->fuc_method);
1872 gf100_gr_dtor_init(gr->fuc_sw_ctx);
1873 gf100_gr_dtor_init(gr->fuc_sw_nonctx);
1874
1875 return gr;
1876 }
1877
1878 static const struct nvkm_gr_func
1879 gf100_gr_ = {
1880 .dtor = gf100_gr_dtor,
1881 .oneinit = gf100_gr_oneinit,
1882 .init = gf100_gr_init_,
1883 .fini = gf100_gr_fini_,
1884 .intr = gf100_gr_intr,
1885 .units = gf100_gr_units,
1886 .chan_new = gf100_gr_chan_new,
1887 .object_get = gf100_gr_object_get,
1888 .chsw_load = gf100_gr_chsw_load,
1889 };
1890
1891 int
gf100_gr_ctor_fw_legacy(struct gf100_gr * gr,const char * fwname,struct gf100_gr_fuc * fuc,int ret)1892 gf100_gr_ctor_fw_legacy(struct gf100_gr *gr, const char *fwname,
1893 struct gf100_gr_fuc *fuc, int ret)
1894 {
1895 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1896 struct nvkm_device *device = subdev->device;
1897 const struct firmware *fw;
1898 char f[32];
1899
1900 /* see if this firmware has a legacy path */
1901 if (!strcmp(fwname, "fecs_inst"))
1902 fwname = "fuc409c";
1903 else if (!strcmp(fwname, "fecs_data"))
1904 fwname = "fuc409d";
1905 else if (!strcmp(fwname, "gpccs_inst"))
1906 fwname = "fuc41ac";
1907 else if (!strcmp(fwname, "gpccs_data"))
1908 fwname = "fuc41ad";
1909 else {
1910 /* nope, let's just return the error we got */
1911 nvkm_error(subdev, "failed to load %s\n", fwname);
1912 return ret;
1913 }
1914
1915 /* yes, try to load from the legacy path */
1916 nvkm_debug(subdev, "%s: falling back to legacy path\n", fwname);
1917
1918 snprintf(f, sizeof(f), "nouveau/nv%02x_%s", device->chipset, fwname);
1919 ret = request_firmware(&fw, f, device->dev);
1920 if (ret) {
1921 snprintf(f, sizeof(f), "nouveau/%s", fwname);
1922 ret = request_firmware(&fw, f, device->dev);
1923 if (ret) {
1924 nvkm_error(subdev, "failed to load %s\n", fwname);
1925 return ret;
1926 }
1927 }
1928
1929 fuc->size = fw->size;
1930 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1931 release_firmware(fw);
1932 return (fuc->data != NULL) ? 0 : -ENOMEM;
1933 }
1934
1935 int
gf100_gr_ctor_fw(struct gf100_gr * gr,const char * fwname,struct gf100_gr_fuc * fuc)1936 gf100_gr_ctor_fw(struct gf100_gr *gr, const char *fwname,
1937 struct gf100_gr_fuc *fuc)
1938 {
1939 struct nvkm_subdev *subdev = &gr->base.engine.subdev;
1940 struct nvkm_device *device = subdev->device;
1941 const struct firmware *fw;
1942 int ret;
1943
1944 ret = nvkm_firmware_get(device, fwname, &fw);
1945 if (ret) {
1946 ret = gf100_gr_ctor_fw_legacy(gr, fwname, fuc, ret);
1947 if (ret)
1948 return -ENODEV;
1949 return 0;
1950 }
1951
1952 fuc->size = fw->size;
1953 fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
1954 nvkm_firmware_put(fw);
1955 return (fuc->data != NULL) ? 0 : -ENOMEM;
1956 }
1957
1958 int
gf100_gr_ctor(const struct gf100_gr_func * func,struct nvkm_device * device,int index,struct gf100_gr * gr)1959 gf100_gr_ctor(const struct gf100_gr_func *func, struct nvkm_device *device,
1960 int index, struct gf100_gr *gr)
1961 {
1962 gr->func = func;
1963 gr->firmware = nvkm_boolopt(device->cfgopt, "NvGrUseFW",
1964 func->fecs.ucode == NULL);
1965
1966 return nvkm_gr_ctor(&gf100_gr_, device, index,
1967 gr->firmware || func->fecs.ucode != NULL,
1968 &gr->base);
1969 }
1970
1971 int
gf100_gr_new_(const struct gf100_gr_func * func,struct nvkm_device * device,int index,struct nvkm_gr ** pgr)1972 gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
1973 int index, struct nvkm_gr **pgr)
1974 {
1975 struct gf100_gr *gr;
1976 int ret;
1977
1978 if (!(gr = kzalloc(sizeof(*gr), GFP_KERNEL)))
1979 return -ENOMEM;
1980 *pgr = &gr->base;
1981
1982 ret = gf100_gr_ctor(func, device, index, gr);
1983 if (ret)
1984 return ret;
1985
1986 if (gr->firmware) {
1987 if (gf100_gr_ctor_fw(gr, "fecs_inst", &gr->fuc409c) ||
1988 gf100_gr_ctor_fw(gr, "fecs_data", &gr->fuc409d) ||
1989 gf100_gr_ctor_fw(gr, "gpccs_inst", &gr->fuc41ac) ||
1990 gf100_gr_ctor_fw(gr, "gpccs_data", &gr->fuc41ad))
1991 return -ENODEV;
1992 }
1993
1994 return 0;
1995 }
1996
1997 void
gf100_gr_init_400054(struct gf100_gr * gr)1998 gf100_gr_init_400054(struct gf100_gr *gr)
1999 {
2000 nvkm_wr32(gr->base.engine.subdev.device, 0x400054, 0x34ce3464);
2001 }
2002
2003 void
gf100_gr_init_shader_exceptions(struct gf100_gr * gr,int gpc,int tpc)2004 gf100_gr_init_shader_exceptions(struct gf100_gr *gr, int gpc, int tpc)
2005 {
2006 struct nvkm_device *device = gr->base.engine.subdev.device;
2007 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x644), 0x001ffffe);
2008 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x64c), 0x0000000f);
2009 }
2010
2011 void
gf100_gr_init_tex_hww_esr(struct gf100_gr * gr,int gpc,int tpc)2012 gf100_gr_init_tex_hww_esr(struct gf100_gr *gr, int gpc, int tpc)
2013 {
2014 struct nvkm_device *device = gr->base.engine.subdev.device;
2015 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x224), 0xc0000000);
2016 }
2017
2018 void
gf100_gr_init_419eb4(struct gf100_gr * gr)2019 gf100_gr_init_419eb4(struct gf100_gr *gr)
2020 {
2021 struct nvkm_device *device = gr->base.engine.subdev.device;
2022 nvkm_mask(device, 0x419eb4, 0x00001000, 0x00001000);
2023 }
2024
2025 void
gf100_gr_init_419cc0(struct gf100_gr * gr)2026 gf100_gr_init_419cc0(struct gf100_gr *gr)
2027 {
2028 struct nvkm_device *device = gr->base.engine.subdev.device;
2029 int gpc, tpc;
2030
2031 nvkm_mask(device, 0x419cc0, 0x00000008, 0x00000008);
2032
2033 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2034 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++)
2035 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x48c), 0xc0000000);
2036 }
2037 }
2038
2039 void
gf100_gr_init_40601c(struct gf100_gr * gr)2040 gf100_gr_init_40601c(struct gf100_gr *gr)
2041 {
2042 nvkm_wr32(gr->base.engine.subdev.device, 0x40601c, 0xc0000000);
2043 }
2044
2045 void
gf100_gr_init_fecs_exceptions(struct gf100_gr * gr)2046 gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
2047 {
2048 const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001;
2049 nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
2050 }
2051
2052 void
gf100_gr_init_gpc_mmu(struct gf100_gr * gr)2053 gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
2054 {
2055 struct nvkm_device *device = gr->base.engine.subdev.device;
2056 struct nvkm_fb *fb = device->fb;
2057
2058 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0x00000001);
2059 nvkm_wr32(device, 0x4188a4, 0x03000000);
2060 nvkm_wr32(device, 0x418888, 0x00000000);
2061 nvkm_wr32(device, 0x41888c, 0x00000000);
2062 nvkm_wr32(device, 0x418890, 0x00000000);
2063 nvkm_wr32(device, 0x418894, 0x00000000);
2064 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(fb->mmu_wr) >> 8);
2065 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(fb->mmu_rd) >> 8);
2066 }
2067
2068 void
gf100_gr_init_num_active_ltcs(struct gf100_gr * gr)2069 gf100_gr_init_num_active_ltcs(struct gf100_gr *gr)
2070 {
2071 struct nvkm_device *device = gr->base.engine.subdev.device;
2072 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800));
2073 }
2074
2075 void
gf100_gr_init_zcull(struct gf100_gr * gr)2076 gf100_gr_init_zcull(struct gf100_gr *gr)
2077 {
2078 struct nvkm_device *device = gr->base.engine.subdev.device;
2079 const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);
2080 const u8 tile_nr = ALIGN(gr->tpc_total, 32);
2081 u8 bank[GPC_MAX] = {}, gpc, i, j;
2082 u32 data;
2083
2084 for (i = 0; i < tile_nr; i += 8) {
2085 for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {
2086 data |= bank[gr->tile[i + j]] << (j * 4);
2087 bank[gr->tile[i + j]]++;
2088 }
2089 nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);
2090 }
2091
2092 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2093 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),
2094 gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);
2095 nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |
2096 gr->tpc_total);
2097 nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);
2098 }
2099
2100 nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);
2101 }
2102
2103 void
gf100_gr_init_vsc_stream_master(struct gf100_gr * gr)2104 gf100_gr_init_vsc_stream_master(struct gf100_gr *gr)
2105 {
2106 struct nvkm_device *device = gr->base.engine.subdev.device;
2107 nvkm_mask(device, TPC_UNIT(0, 0, 0x05c), 0x00000001, 0x00000001);
2108 }
2109
2110 int
gf100_gr_init(struct gf100_gr * gr)2111 gf100_gr_init(struct gf100_gr *gr)
2112 {
2113 struct nvkm_device *device = gr->base.engine.subdev.device;
2114 int gpc, tpc, rop;
2115
2116 if (gr->func->init_419bd8)
2117 gr->func->init_419bd8(gr);
2118
2119 gr->func->init_gpc_mmu(gr);
2120
2121 if (gr->fuc_sw_nonctx)
2122 gf100_gr_mmio(gr, gr->fuc_sw_nonctx);
2123 else
2124 gf100_gr_mmio(gr, gr->func->mmio);
2125
2126 gf100_gr_wait_idle(gr);
2127
2128 if (gr->func->init_r405a14)
2129 gr->func->init_r405a14(gr);
2130
2131 if (gr->func->clkgate_pack)
2132 nvkm_therm_clkgate_init(device->therm, gr->func->clkgate_pack);
2133
2134 if (gr->func->init_bios)
2135 gr->func->init_bios(gr);
2136
2137 gr->func->init_vsc_stream_master(gr);
2138 gr->func->init_zcull(gr);
2139 gr->func->init_num_active_ltcs(gr);
2140 if (gr->func->init_rop_active_fbps)
2141 gr->func->init_rop_active_fbps(gr);
2142 if (gr->func->init_bios_2)
2143 gr->func->init_bios_2(gr);
2144 if (gr->func->init_swdx_pes_mask)
2145 gr->func->init_swdx_pes_mask(gr);
2146
2147 nvkm_wr32(device, 0x400500, 0x00010001);
2148
2149 nvkm_wr32(device, 0x400100, 0xffffffff);
2150 nvkm_wr32(device, 0x40013c, 0xffffffff);
2151 nvkm_wr32(device, 0x400124, 0x00000002);
2152
2153 gr->func->init_fecs_exceptions(gr);
2154 if (gr->func->init_ds_hww_esr_2)
2155 gr->func->init_ds_hww_esr_2(gr);
2156
2157 nvkm_wr32(device, 0x404000, 0xc0000000);
2158 nvkm_wr32(device, 0x404600, 0xc0000000);
2159 nvkm_wr32(device, 0x408030, 0xc0000000);
2160
2161 if (gr->func->init_40601c)
2162 gr->func->init_40601c(gr);
2163
2164 nvkm_wr32(device, 0x404490, 0xc0000000);
2165 nvkm_wr32(device, 0x406018, 0xc0000000);
2166
2167 if (gr->func->init_sked_hww_esr)
2168 gr->func->init_sked_hww_esr(gr);
2169
2170 nvkm_wr32(device, 0x405840, 0xc0000000);
2171 nvkm_wr32(device, 0x405844, 0x00ffffff);
2172
2173 if (gr->func->init_419cc0)
2174 gr->func->init_419cc0(gr);
2175 if (gr->func->init_419eb4)
2176 gr->func->init_419eb4(gr);
2177 if (gr->func->init_419c9c)
2178 gr->func->init_419c9c(gr);
2179
2180 if (gr->func->init_ppc_exceptions)
2181 gr->func->init_ppc_exceptions(gr);
2182
2183 for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
2184 nvkm_wr32(device, GPC_UNIT(gpc, 0x0420), 0xc0000000);
2185 nvkm_wr32(device, GPC_UNIT(gpc, 0x0900), 0xc0000000);
2186 nvkm_wr32(device, GPC_UNIT(gpc, 0x1028), 0xc0000000);
2187 nvkm_wr32(device, GPC_UNIT(gpc, 0x0824), 0xc0000000);
2188 for (tpc = 0; tpc < gr->tpc_nr[gpc]; tpc++) {
2189 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x508), 0xffffffff);
2190 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x50c), 0xffffffff);
2191 if (gr->func->init_tex_hww_esr)
2192 gr->func->init_tex_hww_esr(gr, gpc, tpc);
2193 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x084), 0xc0000000);
2194 if (gr->func->init_504430)
2195 gr->func->init_504430(gr, gpc, tpc);
2196 gr->func->init_shader_exceptions(gr, gpc, tpc);
2197 }
2198 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
2199 nvkm_wr32(device, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
2200 }
2201
2202 for (rop = 0; rop < gr->rop_nr; rop++) {
2203 nvkm_wr32(device, ROP_UNIT(rop, 0x144), 0x40000000);
2204 nvkm_wr32(device, ROP_UNIT(rop, 0x070), 0x40000000);
2205 nvkm_wr32(device, ROP_UNIT(rop, 0x204), 0xffffffff);
2206 nvkm_wr32(device, ROP_UNIT(rop, 0x208), 0xffffffff);
2207 }
2208
2209 nvkm_wr32(device, 0x400108, 0xffffffff);
2210 nvkm_wr32(device, 0x400138, 0xffffffff);
2211 nvkm_wr32(device, 0x400118, 0xffffffff);
2212 nvkm_wr32(device, 0x400130, 0xffffffff);
2213 nvkm_wr32(device, 0x40011c, 0xffffffff);
2214 nvkm_wr32(device, 0x400134, 0xffffffff);
2215
2216 if (gr->func->init_400054)
2217 gr->func->init_400054(gr);
2218
2219 gf100_gr_zbc_init(gr);
2220
2221 if (gr->func->init_4188a4)
2222 gr->func->init_4188a4(gr);
2223
2224 return gf100_gr_init_ctxctl(gr);
2225 }
2226
2227 #include "fuc/hubgf100.fuc3.h"
2228
2229 struct gf100_gr_ucode
2230 gf100_gr_fecs_ucode = {
2231 .code.data = gf100_grhub_code,
2232 .code.size = sizeof(gf100_grhub_code),
2233 .data.data = gf100_grhub_data,
2234 .data.size = sizeof(gf100_grhub_data),
2235 };
2236
2237 #include "fuc/gpcgf100.fuc3.h"
2238
2239 struct gf100_gr_ucode
2240 gf100_gr_gpccs_ucode = {
2241 .code.data = gf100_grgpc_code,
2242 .code.size = sizeof(gf100_grgpc_code),
2243 .data.data = gf100_grgpc_data,
2244 .data.size = sizeof(gf100_grgpc_data),
2245 };
2246
2247 static const struct gf100_gr_func
2248 gf100_gr = {
2249 .oneinit_tiles = gf100_gr_oneinit_tiles,
2250 .oneinit_sm_id = gf100_gr_oneinit_sm_id,
2251 .init = gf100_gr_init,
2252 .init_gpc_mmu = gf100_gr_init_gpc_mmu,
2253 .init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
2254 .init_zcull = gf100_gr_init_zcull,
2255 .init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
2256 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
2257 .init_40601c = gf100_gr_init_40601c,
2258 .init_419cc0 = gf100_gr_init_419cc0,
2259 .init_419eb4 = gf100_gr_init_419eb4,
2260 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr,
2261 .init_shader_exceptions = gf100_gr_init_shader_exceptions,
2262 .init_400054 = gf100_gr_init_400054,
2263 .trap_mp = gf100_gr_trap_mp,
2264 .mmio = gf100_gr_pack_mmio,
2265 .fecs.ucode = &gf100_gr_fecs_ucode,
2266 .gpccs.ucode = &gf100_gr_gpccs_ucode,
2267 .rops = gf100_gr_rops,
2268 .grctx = &gf100_grctx,
2269 .zbc = &gf100_gr_zbc,
2270 .sclass = {
2271 { -1, -1, FERMI_TWOD_A },
2272 { -1, -1, FERMI_MEMORY_TO_MEMORY_FORMAT_A },
2273 { -1, -1, FERMI_A, &gf100_fermi },
2274 { -1, -1, FERMI_COMPUTE_A },
2275 {}
2276 }
2277 };
2278
2279 int
gf100_gr_new(struct nvkm_device * device,int index,struct nvkm_gr ** pgr)2280 gf100_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr)
2281 {
2282 return gf100_gr_new_(&gf100_gr, device, index, pgr);
2283 }
2284
