1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5  */
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
8 
9 #include <linux/of.h>
10 #include <linux/of_clk.h>
11 
12 /*
13  * flags used across common struct clk.  these flags should only affect the
14  * top-level framework.  custom flags for dealing with hardware specifics
15  * belong in struct clk_foo
16  *
17  * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
18  */
19 #define CLK_SET_RATE_GATE	BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT	BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED	BIT(3) /* do not gate even if unused */
23 				/* unused */
24 				/* unused */
25 #define CLK_GET_RATE_NOCACHE	BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES	BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE	BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL		BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE	BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT	BIT(13)
35 
36 struct clk;
37 struct clk_hw;
38 struct clk_core;
39 struct dentry;
40 
41 /**
42  * struct clk_rate_request - Structure encoding the clk constraints that
43  * a clock user might require.
44  *
45  * @rate:		Requested clock rate. This field will be adjusted by
46  *			clock drivers according to hardware capabilities.
47  * @min_rate:		Minimum rate imposed by clk users.
48  * @max_rate:		Maximum rate imposed by clk users.
49  * @best_parent_rate:	The best parent rate a parent can provide to fulfill the
50  *			requested constraints.
51  * @best_parent_hw:	The most appropriate parent clock that fulfills the
52  *			requested constraints.
53  *
54  */
55 struct clk_rate_request {
56 	unsigned long rate;
57 	unsigned long min_rate;
58 	unsigned long max_rate;
59 	unsigned long best_parent_rate;
60 	struct clk_hw *best_parent_hw;
61 };
62 
63 /**
64  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
65  *
66  * @num:	Numerator of the duty cycle ratio
67  * @den:	Denominator of the duty cycle ratio
68  */
69 struct clk_duty {
70 	unsigned int num;
71 	unsigned int den;
72 };
73 
74 /**
75  * struct clk_ops -  Callback operations for hardware clocks; these are to
76  * be provided by the clock implementation, and will be called by drivers
77  * through the clk_* api.
78  *
79  * @prepare:	Prepare the clock for enabling. This must not return until
80  *		the clock is fully prepared, and it's safe to call clk_enable.
81  *		This callback is intended to allow clock implementations to
82  *		do any initialisation that may sleep. Called with
83  *		prepare_lock held.
84  *
85  * @unprepare:	Release the clock from its prepared state. This will typically
86  *		undo any work done in the @prepare callback. Called with
87  *		prepare_lock held.
88  *
89  * @is_prepared: Queries the hardware to determine if the clock is prepared.
90  *		This function is allowed to sleep. Optional, if this op is not
91  *		set then the prepare count will be used.
92  *
93  * @unprepare_unused: Unprepare the clock atomically.  Only called from
94  *		clk_disable_unused for prepare clocks with special needs.
95  *		Called with prepare mutex held. This function may sleep.
96  *
97  * @enable:	Enable the clock atomically. This must not return until the
98  *		clock is generating a valid clock signal, usable by consumer
99  *		devices. Called with enable_lock held. This function must not
100  *		sleep.
101  *
102  * @disable:	Disable the clock atomically. Called with enable_lock held.
103  *		This function must not sleep.
104  *
105  * @is_enabled:	Queries the hardware to determine if the clock is enabled.
106  *		This function must not sleep. Optional, if this op is not
107  *		set then the enable count will be used.
108  *
109  * @disable_unused: Disable the clock atomically.  Only called from
110  *		clk_disable_unused for gate clocks with special needs.
111  *		Called with enable_lock held.  This function must not
112  *		sleep.
113  *
114  * @save_context: Save the context of the clock in prepration for poweroff.
115  *
116  * @restore_context: Restore the context of the clock after a restoration
117  *		of power.
118  *
119  * @recalc_rate	Recalculate the rate of this clock, by querying hardware. The
120  *		parent rate is an input parameter.  It is up to the caller to
121  *		ensure that the prepare_mutex is held across this call.
122  *		Returns the calculated rate.  Optional, but recommended - if
123  *		this op is not set then clock rate will be initialized to 0.
124  *
125  * @round_rate:	Given a target rate as input, returns the closest rate actually
126  *		supported by the clock. The parent rate is an input/output
127  *		parameter.
128  *
129  * @determine_rate: Given a target rate as input, returns the closest rate
130  *		actually supported by the clock, and optionally the parent clock
131  *		that should be used to provide the clock rate.
132  *
133  * @set_parent:	Change the input source of this clock; for clocks with multiple
134  *		possible parents specify a new parent by passing in the index
135  *		as a u8 corresponding to the parent in either the .parent_names
136  *		or .parents arrays.  This function in affect translates an
137  *		array index into the value programmed into the hardware.
138  *		Returns 0 on success, -EERROR otherwise.
139  *
140  * @get_parent:	Queries the hardware to determine the parent of a clock.  The
141  *		return value is a u8 which specifies the index corresponding to
142  *		the parent clock.  This index can be applied to either the
143  *		.parent_names or .parents arrays.  In short, this function
144  *		translates the parent value read from hardware into an array
145  *		index.  Currently only called when the clock is initialized by
146  *		__clk_init.  This callback is mandatory for clocks with
147  *		multiple parents.  It is optional (and unnecessary) for clocks
148  *		with 0 or 1 parents.
149  *
150  * @set_rate:	Change the rate of this clock. The requested rate is specified
151  *		by the second argument, which should typically be the return
152  *		of .round_rate call.  The third argument gives the parent rate
153  *		which is likely helpful for most .set_rate implementation.
154  *		Returns 0 on success, -EERROR otherwise.
155  *
156  * @set_rate_and_parent: Change the rate and the parent of this clock. The
157  *		requested rate is specified by the second argument, which
158  *		should typically be the return of .round_rate call.  The
159  *		third argument gives the parent rate which is likely helpful
160  *		for most .set_rate_and_parent implementation. The fourth
161  *		argument gives the parent index. This callback is optional (and
162  *		unnecessary) for clocks with 0 or 1 parents as well as
163  *		for clocks that can tolerate switching the rate and the parent
164  *		separately via calls to .set_parent and .set_rate.
165  *		Returns 0 on success, -EERROR otherwise.
166  *
167  * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168  *		is expressed in ppb (parts per billion). The parent accuracy is
169  *		an input parameter.
170  *		Returns the calculated accuracy.  Optional - if	this op is not
171  *		set then clock accuracy will be initialized to parent accuracy
172  *		or 0 (perfect clock) if clock has no parent.
173  *
174  * @get_phase:	Queries the hardware to get the current phase of a clock.
175  *		Returned values are 0-359 degrees on success, negative
176  *		error codes on failure.
177  *
178  * @set_phase:	Shift the phase this clock signal in degrees specified
179  *		by the second argument. Valid values for degrees are
180  *		0-359. Return 0 on success, otherwise -EERROR.
181  *
182  * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183  *              of a clock. Returned values denominator cannot be 0 and must be
184  *              superior or equal to the numerator.
185  *
186  * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187  *              the numerator (2nd argurment) and denominator (3rd  argument).
188  *              Argument must be a valid ratio (denominator > 0
189  *              and >= numerator) Return 0 on success, otherwise -EERROR.
190  *
191  * @init:	Perform platform-specific initialization magic.
192  *		This is not not used by any of the basic clock types.
193  *		Please consider other ways of solving initialization problems
194  *		before using this callback, as its use is discouraged.
195  *
196  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
197  *		is called once, after the debugfs directory entry for this
198  *		clock has been created.  The dentry pointer representing that
199  *		directory is provided as an argument.  Called with
200  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
201  *
202  *
203  * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
204  * implementations to split any work between atomic (enable) and sleepable
205  * (prepare) contexts.  If enabling a clock requires code that might sleep,
206  * this must be done in clk_prepare.  Clock enable code that will never be
207  * called in a sleepable context may be implemented in clk_enable.
208  *
209  * Typically, drivers will call clk_prepare when a clock may be needed later
210  * (eg. when a device is opened), and clk_enable when the clock is actually
211  * required (eg. from an interrupt). Note that clk_prepare MUST have been
212  * called before clk_enable.
213  */
214 struct clk_ops {
215 	int		(*prepare)(struct clk_hw *hw);
216 	void		(*unprepare)(struct clk_hw *hw);
217 	int		(*is_prepared)(struct clk_hw *hw);
218 	void		(*unprepare_unused)(struct clk_hw *hw);
219 	int		(*enable)(struct clk_hw *hw);
220 	void		(*disable)(struct clk_hw *hw);
221 	int		(*is_enabled)(struct clk_hw *hw);
222 	void		(*disable_unused)(struct clk_hw *hw);
223 	int		(*save_context)(struct clk_hw *hw);
224 	void		(*restore_context)(struct clk_hw *hw);
225 	unsigned long	(*recalc_rate)(struct clk_hw *hw,
226 					unsigned long parent_rate);
227 	long		(*round_rate)(struct clk_hw *hw, unsigned long rate,
228 					unsigned long *parent_rate);
229 	int		(*determine_rate)(struct clk_hw *hw,
230 					  struct clk_rate_request *req);
231 	int		(*set_parent)(struct clk_hw *hw, u8 index);
232 	u8		(*get_parent)(struct clk_hw *hw);
233 	int		(*set_rate)(struct clk_hw *hw, unsigned long rate,
234 				    unsigned long parent_rate);
235 	int		(*set_rate_and_parent)(struct clk_hw *hw,
236 				    unsigned long rate,
237 				    unsigned long parent_rate, u8 index);
238 	unsigned long	(*recalc_accuracy)(struct clk_hw *hw,
239 					   unsigned long parent_accuracy);
240 	int		(*get_phase)(struct clk_hw *hw);
241 	int		(*set_phase)(struct clk_hw *hw, int degrees);
242 	int		(*get_duty_cycle)(struct clk_hw *hw,
243 					  struct clk_duty *duty);
244 	int		(*set_duty_cycle)(struct clk_hw *hw,
245 					  struct clk_duty *duty);
246 	void		(*init)(struct clk_hw *hw);
247 	void		(*debug_init)(struct clk_hw *hw, struct dentry *dentry);
248 };
249 
250 /**
251  * struct clk_parent_data - clk parent information
252  * @hw: parent clk_hw pointer (used for clk providers with internal clks)
253  * @fw_name: parent name local to provider registering clk
254  * @name: globally unique parent name (used as a fallback)
255  * @index: parent index local to provider registering clk (if @fw_name absent)
256  */
257 struct clk_parent_data {
258 	const struct clk_hw	*hw;
259 	const char		*fw_name;
260 	const char		*name;
261 	int			index;
262 };
263 
264 /**
265  * struct clk_init_data - holds init data that's common to all clocks and is
266  * shared between the clock provider and the common clock framework.
267  *
268  * @name: clock name
269  * @ops: operations this clock supports
270  * @parent_names: array of string names for all possible parents
271  * @parent_data: array of parent data for all possible parents (when some
272  *               parents are external to the clk controller)
273  * @parent_hws: array of pointers to all possible parents (when all parents
274  *              are internal to the clk controller)
275  * @num_parents: number of possible parents
276  * @flags: framework-level hints and quirks
277  */
278 struct clk_init_data {
279 	const char		*name;
280 	const struct clk_ops	*ops;
281 	/* Only one of the following three should be assigned */
282 	const char		* const *parent_names;
283 	const struct clk_parent_data	*parent_data;
284 	const struct clk_hw		**parent_hws;
285 	u8			num_parents;
286 	unsigned long		flags;
287 };
288 
289 /**
290  * struct clk_hw - handle for traversing from a struct clk to its corresponding
291  * hardware-specific structure.  struct clk_hw should be declared within struct
292  * clk_foo and then referenced by the struct clk instance that uses struct
293  * clk_foo's clk_ops
294  *
295  * @core: pointer to the struct clk_core instance that points back to this
296  * struct clk_hw instance
297  *
298  * @clk: pointer to the per-user struct clk instance that can be used to call
299  * into the clk API
300  *
301  * @init: pointer to struct clk_init_data that contains the init data shared
302  * with the common clock framework. This pointer will be set to NULL once
303  * a clk_register() variant is called on this clk_hw pointer.
304  */
305 struct clk_hw {
306 	struct clk_core *core;
307 	struct clk *clk;
308 	const struct clk_init_data *init;
309 };
310 
311 /*
312  * DOC: Basic clock implementations common to many platforms
313  *
314  * Each basic clock hardware type is comprised of a structure describing the
315  * clock hardware, implementations of the relevant callbacks in struct clk_ops,
316  * unique flags for that hardware type, a registration function and an
317  * alternative macro for static initialization
318  */
319 
320 /**
321  * struct clk_fixed_rate - fixed-rate clock
322  * @hw:		handle between common and hardware-specific interfaces
323  * @fixed_rate:	constant frequency of clock
324  */
325 struct clk_fixed_rate {
326 	struct		clk_hw hw;
327 	unsigned long	fixed_rate;
328 	unsigned long	fixed_accuracy;
329 };
330 
331 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
332 
333 extern const struct clk_ops clk_fixed_rate_ops;
334 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
335 		const char *parent_name, unsigned long flags,
336 		unsigned long fixed_rate);
337 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
338 		const char *parent_name, unsigned long flags,
339 		unsigned long fixed_rate);
340 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
341 		const char *name, const char *parent_name, unsigned long flags,
342 		unsigned long fixed_rate, unsigned long fixed_accuracy);
343 void clk_unregister_fixed_rate(struct clk *clk);
344 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
345 		const char *name, const char *parent_name, unsigned long flags,
346 		unsigned long fixed_rate, unsigned long fixed_accuracy);
347 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
348 
349 void of_fixed_clk_setup(struct device_node *np);
350 
351 /**
352  * struct clk_gate - gating clock
353  *
354  * @hw:		handle between common and hardware-specific interfaces
355  * @reg:	register controlling gate
356  * @bit_idx:	single bit controlling gate
357  * @flags:	hardware-specific flags
358  * @lock:	register lock
359  *
360  * Clock which can gate its output.  Implements .enable & .disable
361  *
362  * Flags:
363  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
364  *	enable the clock.  Setting this flag does the opposite: setting the bit
365  *	disable the clock and clearing it enables the clock
366  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
367  *	of this register, and mask of gate bits are in higher 16-bit of this
368  *	register.  While setting the gate bits, higher 16-bit should also be
369  *	updated to indicate changing gate bits.
370  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
371  *	the gate register.  Setting this flag makes the register accesses big
372  *	endian.
373  */
374 struct clk_gate {
375 	struct clk_hw hw;
376 	void __iomem	*reg;
377 	u8		bit_idx;
378 	u8		flags;
379 	spinlock_t	*lock;
380 };
381 
382 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
383 
384 #define CLK_GATE_SET_TO_DISABLE		BIT(0)
385 #define CLK_GATE_HIWORD_MASK		BIT(1)
386 #define CLK_GATE_BIG_ENDIAN		BIT(2)
387 
388 extern const struct clk_ops clk_gate_ops;
389 struct clk *clk_register_gate(struct device *dev, const char *name,
390 		const char *parent_name, unsigned long flags,
391 		void __iomem *reg, u8 bit_idx,
392 		u8 clk_gate_flags, spinlock_t *lock);
393 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
394 		const char *parent_name, unsigned long flags,
395 		void __iomem *reg, u8 bit_idx,
396 		u8 clk_gate_flags, spinlock_t *lock);
397 void clk_unregister_gate(struct clk *clk);
398 void clk_hw_unregister_gate(struct clk_hw *hw);
399 int clk_gate_is_enabled(struct clk_hw *hw);
400 
401 struct clk_div_table {
402 	unsigned int	val;
403 	unsigned int	div;
404 };
405 
406 /**
407  * struct clk_divider - adjustable divider clock
408  *
409  * @hw:		handle between common and hardware-specific interfaces
410  * @reg:	register containing the divider
411  * @shift:	shift to the divider bit field
412  * @width:	width of the divider bit field
413  * @table:	array of value/divider pairs, last entry should have div = 0
414  * @lock:	register lock
415  *
416  * Clock with an adjustable divider affecting its output frequency.  Implements
417  * .recalc_rate, .set_rate and .round_rate
418  *
419  * Flags:
420  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
421  *	register plus one.  If CLK_DIVIDER_ONE_BASED is set then the divider is
422  *	the raw value read from the register, with the value of zero considered
423  *	invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
424  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
425  *	the hardware register
426  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
427  *	CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
428  *	Some hardware implementations gracefully handle this case and allow a
429  *	zero divisor by not modifying their input clock
430  *	(divide by one / bypass).
431  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
432  *	of this register, and mask of divider bits are in higher 16-bit of this
433  *	register.  While setting the divider bits, higher 16-bit should also be
434  *	updated to indicate changing divider bits.
435  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
436  *	to the closest integer instead of the up one.
437  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
438  *	not be changed by the clock framework.
439  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
440  *	except when the value read from the register is zero, the divisor is
441  *	2^width of the field.
442  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
443  *	for the divider register.  Setting this flag makes the register accesses
444  *	big endian.
445  */
446 struct clk_divider {
447 	struct clk_hw	hw;
448 	void __iomem	*reg;
449 	u8		shift;
450 	u8		width;
451 	u8		flags;
452 	const struct clk_div_table	*table;
453 	spinlock_t	*lock;
454 };
455 
456 #define clk_div_mask(width)	((1 << (width)) - 1)
457 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
458 
459 #define CLK_DIVIDER_ONE_BASED		BIT(0)
460 #define CLK_DIVIDER_POWER_OF_TWO	BIT(1)
461 #define CLK_DIVIDER_ALLOW_ZERO		BIT(2)
462 #define CLK_DIVIDER_HIWORD_MASK		BIT(3)
463 #define CLK_DIVIDER_ROUND_CLOSEST	BIT(4)
464 #define CLK_DIVIDER_READ_ONLY		BIT(5)
465 #define CLK_DIVIDER_MAX_AT_ZERO		BIT(6)
466 #define CLK_DIVIDER_BIG_ENDIAN		BIT(7)
467 
468 extern const struct clk_ops clk_divider_ops;
469 extern const struct clk_ops clk_divider_ro_ops;
470 
471 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
472 		unsigned int val, const struct clk_div_table *table,
473 		unsigned long flags, unsigned long width);
474 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
475 			       unsigned long rate, unsigned long *prate,
476 			       const struct clk_div_table *table,
477 			       u8 width, unsigned long flags);
478 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
479 				  unsigned long rate, unsigned long *prate,
480 				  const struct clk_div_table *table, u8 width,
481 				  unsigned long flags, unsigned int val);
482 int divider_get_val(unsigned long rate, unsigned long parent_rate,
483 		const struct clk_div_table *table, u8 width,
484 		unsigned long flags);
485 
486 struct clk *clk_register_divider(struct device *dev, const char *name,
487 		const char *parent_name, unsigned long flags,
488 		void __iomem *reg, u8 shift, u8 width,
489 		u8 clk_divider_flags, spinlock_t *lock);
490 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
491 		const char *parent_name, unsigned long flags,
492 		void __iomem *reg, u8 shift, u8 width,
493 		u8 clk_divider_flags, spinlock_t *lock);
494 struct clk *clk_register_divider_table(struct device *dev, const char *name,
495 		const char *parent_name, unsigned long flags,
496 		void __iomem *reg, u8 shift, u8 width,
497 		u8 clk_divider_flags, const struct clk_div_table *table,
498 		spinlock_t *lock);
499 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
500 		const char *name, const char *parent_name, unsigned long flags,
501 		void __iomem *reg, u8 shift, u8 width,
502 		u8 clk_divider_flags, const struct clk_div_table *table,
503 		spinlock_t *lock);
504 void clk_unregister_divider(struct clk *clk);
505 void clk_hw_unregister_divider(struct clk_hw *hw);
506 
507 /**
508  * struct clk_mux - multiplexer clock
509  *
510  * @hw:		handle between common and hardware-specific interfaces
511  * @reg:	register controlling multiplexer
512  * @table:	array of register values corresponding to the parent index
513  * @shift:	shift to multiplexer bit field
514  * @mask:	mask of mutliplexer bit field
515  * @flags:	hardware-specific flags
516  * @lock:	register lock
517  *
518  * Clock with multiple selectable parents.  Implements .get_parent, .set_parent
519  * and .recalc_rate
520  *
521  * Flags:
522  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
523  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
524  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
525  *	register, and mask of mux bits are in higher 16-bit of this register.
526  *	While setting the mux bits, higher 16-bit should also be updated to
527  *	indicate changing mux bits.
528  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
529  * 	.get_parent clk_op.
530  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
531  *	frequency.
532  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
533  *	the mux register.  Setting this flag makes the register accesses big
534  *	endian.
535  */
536 struct clk_mux {
537 	struct clk_hw	hw;
538 	void __iomem	*reg;
539 	u32		*table;
540 	u32		mask;
541 	u8		shift;
542 	u8		flags;
543 	spinlock_t	*lock;
544 };
545 
546 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
547 
548 #define CLK_MUX_INDEX_ONE		BIT(0)
549 #define CLK_MUX_INDEX_BIT		BIT(1)
550 #define CLK_MUX_HIWORD_MASK		BIT(2)
551 #define CLK_MUX_READ_ONLY		BIT(3) /* mux can't be changed */
552 #define CLK_MUX_ROUND_CLOSEST		BIT(4)
553 #define CLK_MUX_BIG_ENDIAN		BIT(5)
554 
555 extern const struct clk_ops clk_mux_ops;
556 extern const struct clk_ops clk_mux_ro_ops;
557 
558 struct clk *clk_register_mux(struct device *dev, const char *name,
559 		const char * const *parent_names, u8 num_parents,
560 		unsigned long flags,
561 		void __iomem *reg, u8 shift, u8 width,
562 		u8 clk_mux_flags, spinlock_t *lock);
563 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
564 		const char * const *parent_names, u8 num_parents,
565 		unsigned long flags,
566 		void __iomem *reg, u8 shift, u8 width,
567 		u8 clk_mux_flags, spinlock_t *lock);
568 
569 struct clk *clk_register_mux_table(struct device *dev, const char *name,
570 		const char * const *parent_names, u8 num_parents,
571 		unsigned long flags,
572 		void __iomem *reg, u8 shift, u32 mask,
573 		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
574 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
575 		const char * const *parent_names, u8 num_parents,
576 		unsigned long flags,
577 		void __iomem *reg, u8 shift, u32 mask,
578 		u8 clk_mux_flags, u32 *table, spinlock_t *lock);
579 
580 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
581 			 unsigned int val);
582 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
583 
584 void clk_unregister_mux(struct clk *clk);
585 void clk_hw_unregister_mux(struct clk_hw *hw);
586 
587 void of_fixed_factor_clk_setup(struct device_node *node);
588 
589 /**
590  * struct clk_fixed_factor - fixed multiplier and divider clock
591  *
592  * @hw:		handle between common and hardware-specific interfaces
593  * @mult:	multiplier
594  * @div:	divider
595  *
596  * Clock with a fixed multiplier and divider. The output frequency is the
597  * parent clock rate divided by div and multiplied by mult.
598  * Implements .recalc_rate, .set_rate and .round_rate
599  */
600 
601 struct clk_fixed_factor {
602 	struct clk_hw	hw;
603 	unsigned int	mult;
604 	unsigned int	div;
605 };
606 
607 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
608 
609 extern const struct clk_ops clk_fixed_factor_ops;
610 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
611 		const char *parent_name, unsigned long flags,
612 		unsigned int mult, unsigned int div);
613 void clk_unregister_fixed_factor(struct clk *clk);
614 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
615 		const char *name, const char *parent_name, unsigned long flags,
616 		unsigned int mult, unsigned int div);
617 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
618 
619 /**
620  * struct clk_fractional_divider - adjustable fractional divider clock
621  *
622  * @hw:		handle between common and hardware-specific interfaces
623  * @reg:	register containing the divider
624  * @mshift:	shift to the numerator bit field
625  * @mwidth:	width of the numerator bit field
626  * @nshift:	shift to the denominator bit field
627  * @nwidth:	width of the denominator bit field
628  * @lock:	register lock
629  *
630  * Clock with adjustable fractional divider affecting its output frequency.
631  *
632  * Flags:
633  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
634  *	is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
635  *	is set then the numerator and denominator are both the value read
636  *	plus one.
637  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
638  *	used for the divider register.  Setting this flag makes the register
639  *	accesses big endian.
640  */
641 struct clk_fractional_divider {
642 	struct clk_hw	hw;
643 	void __iomem	*reg;
644 	u8		mshift;
645 	u8		mwidth;
646 	u32		mmask;
647 	u8		nshift;
648 	u8		nwidth;
649 	u32		nmask;
650 	u8		flags;
651 	void		(*approximation)(struct clk_hw *hw,
652 				unsigned long rate, unsigned long *parent_rate,
653 				unsigned long *m, unsigned long *n);
654 	spinlock_t	*lock;
655 };
656 
657 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
658 
659 #define CLK_FRAC_DIVIDER_ZERO_BASED		BIT(0)
660 #define CLK_FRAC_DIVIDER_BIG_ENDIAN		BIT(1)
661 
662 extern const struct clk_ops clk_fractional_divider_ops;
663 struct clk *clk_register_fractional_divider(struct device *dev,
664 		const char *name, const char *parent_name, unsigned long flags,
665 		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
666 		u8 clk_divider_flags, spinlock_t *lock);
667 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
668 		const char *name, const char *parent_name, unsigned long flags,
669 		void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
670 		u8 clk_divider_flags, spinlock_t *lock);
671 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
672 
673 /**
674  * struct clk_multiplier - adjustable multiplier clock
675  *
676  * @hw:		handle between common and hardware-specific interfaces
677  * @reg:	register containing the multiplier
678  * @shift:	shift to the multiplier bit field
679  * @width:	width of the multiplier bit field
680  * @lock:	register lock
681  *
682  * Clock with an adjustable multiplier affecting its output frequency.
683  * Implements .recalc_rate, .set_rate and .round_rate
684  *
685  * Flags:
686  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
687  *	from the register, with 0 being a valid value effectively
688  *	zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
689  *	set, then a null multiplier will be considered as a bypass,
690  *	leaving the parent rate unmodified.
691  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
692  *	rounded to the closest integer instead of the down one.
693  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
694  *	used for the multiplier register.  Setting this flag makes the register
695  *	accesses big endian.
696  */
697 struct clk_multiplier {
698 	struct clk_hw	hw;
699 	void __iomem	*reg;
700 	u8		shift;
701 	u8		width;
702 	u8		flags;
703 	spinlock_t	*lock;
704 };
705 
706 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
707 
708 #define CLK_MULTIPLIER_ZERO_BYPASS		BIT(0)
709 #define CLK_MULTIPLIER_ROUND_CLOSEST	BIT(1)
710 #define CLK_MULTIPLIER_BIG_ENDIAN		BIT(2)
711 
712 extern const struct clk_ops clk_multiplier_ops;
713 
714 /***
715  * struct clk_composite - aggregate clock of mux, divider and gate clocks
716  *
717  * @hw:		handle between common and hardware-specific interfaces
718  * @mux_hw:	handle between composite and hardware-specific mux clock
719  * @rate_hw:	handle between composite and hardware-specific rate clock
720  * @gate_hw:	handle between composite and hardware-specific gate clock
721  * @mux_ops:	clock ops for mux
722  * @rate_ops:	clock ops for rate
723  * @gate_ops:	clock ops for gate
724  */
725 struct clk_composite {
726 	struct clk_hw	hw;
727 	struct clk_ops	ops;
728 
729 	struct clk_hw	*mux_hw;
730 	struct clk_hw	*rate_hw;
731 	struct clk_hw	*gate_hw;
732 
733 	const struct clk_ops	*mux_ops;
734 	const struct clk_ops	*rate_ops;
735 	const struct clk_ops	*gate_ops;
736 };
737 
738 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
739 
740 struct clk *clk_register_composite(struct device *dev, const char *name,
741 		const char * const *parent_names, int num_parents,
742 		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
743 		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
744 		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
745 		unsigned long flags);
746 void clk_unregister_composite(struct clk *clk);
747 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
748 		const char * const *parent_names, int num_parents,
749 		struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
750 		struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
751 		struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
752 		unsigned long flags);
753 void clk_hw_unregister_composite(struct clk_hw *hw);
754 
755 /**
756  * struct clk_gpio - gpio gated clock
757  *
758  * @hw:		handle between common and hardware-specific interfaces
759  * @gpiod:	gpio descriptor
760  *
761  * Clock with a gpio control for enabling and disabling the parent clock
762  * or switching between two parents by asserting or deasserting the gpio.
763  *
764  * Implements .enable, .disable and .is_enabled or
765  * .get_parent, .set_parent and .determine_rate depending on which clk_ops
766  * is used.
767  */
768 struct clk_gpio {
769 	struct clk_hw	hw;
770 	struct gpio_desc *gpiod;
771 };
772 
773 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
774 
775 extern const struct clk_ops clk_gpio_gate_ops;
776 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
777 		const char *parent_name, struct gpio_desc *gpiod,
778 		unsigned long flags);
779 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
780 		const char *parent_name, struct gpio_desc *gpiod,
781 		unsigned long flags);
782 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
783 
784 extern const struct clk_ops clk_gpio_mux_ops;
785 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
786 		const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
787 		unsigned long flags);
788 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
789 		const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
790 		unsigned long flags);
791 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
792 
793 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
794 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
795 
796 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
797 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
798 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
799 
800 void clk_unregister(struct clk *clk);
801 void devm_clk_unregister(struct device *dev, struct clk *clk);
802 
803 void clk_hw_unregister(struct clk_hw *hw);
804 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
805 
806 /* helper functions */
807 const char *__clk_get_name(const struct clk *clk);
808 const char *clk_hw_get_name(const struct clk_hw *hw);
809 #ifdef CONFIG_COMMON_CLK
810 struct clk_hw *__clk_get_hw(struct clk *clk);
811 #else
__clk_get_hw(struct clk * clk)812 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
813 {
814 	return (struct clk_hw *)clk;
815 }
816 #endif
817 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
818 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
819 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
820 					  unsigned int index);
821 int clk_hw_set_parent(struct clk_hw *hw, struct clk_hw *new_parent);
822 unsigned int __clk_get_enable_count(struct clk *clk);
823 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
824 unsigned long __clk_get_flags(struct clk *clk);
825 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
826 #define clk_hw_can_set_rate_parent(hw) \
827 	(clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
828 
829 bool clk_hw_is_prepared(const struct clk_hw *hw);
830 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
831 bool clk_hw_is_enabled(const struct clk_hw *hw);
832 bool __clk_is_enabled(struct clk *clk);
833 struct clk *__clk_lookup(const char *name);
834 int __clk_mux_determine_rate(struct clk_hw *hw,
835 			     struct clk_rate_request *req);
836 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
837 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
838 				     struct clk_rate_request *req);
839 int clk_mux_determine_rate_flags(struct clk_hw *hw,
840 				 struct clk_rate_request *req,
841 				 unsigned long flags);
842 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
843 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
844 			   unsigned long max_rate);
845 
__clk_hw_set_clk(struct clk_hw * dst,struct clk_hw * src)846 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
847 {
848 	dst->clk = src->clk;
849 	dst->core = src->core;
850 }
851 
divider_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags)852 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
853 				      unsigned long *prate,
854 				      const struct clk_div_table *table,
855 				      u8 width, unsigned long flags)
856 {
857 	return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
858 					 rate, prate, table, width, flags);
859 }
860 
divider_ro_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate,const struct clk_div_table * table,u8 width,unsigned long flags,unsigned int val)861 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
862 					 unsigned long *prate,
863 					 const struct clk_div_table *table,
864 					 u8 width, unsigned long flags,
865 					 unsigned int val)
866 {
867 	return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
868 					    rate, prate, table, width, flags,
869 					    val);
870 }
871 
872 /*
873  * FIXME clock api without lock protection
874  */
875 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
876 
877 struct clk_onecell_data {
878 	struct clk **clks;
879 	unsigned int clk_num;
880 };
881 
882 struct clk_hw_onecell_data {
883 	unsigned int num;
884 	struct clk_hw *hws[];
885 };
886 
887 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
888 
889 /*
890  * Use this macro when you have a driver that requires two initialization
891  * routines, one at of_clk_init(), and one at platform device probe
892  */
893 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
894 	static void __init name##_of_clk_init_driver(struct device_node *np) \
895 	{								\
896 		of_node_clear_flag(np, OF_POPULATED);			\
897 		fn(np);							\
898 	}								\
899 	OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
900 
901 #define CLK_HW_INIT(_name, _parent, _ops, _flags)		\
902 	(&(struct clk_init_data) {				\
903 		.flags		= _flags,			\
904 		.name		= _name,			\
905 		.parent_names	= (const char *[]) { _parent },	\
906 		.num_parents	= 1,				\
907 		.ops		= _ops,				\
908 	})
909 
910 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags)			\
911 	(&(struct clk_init_data) {					\
912 		.flags		= _flags,				\
913 		.name		= _name,				\
914 		.parent_hws	= (const struct clk_hw*[]) { _parent },	\
915 		.num_parents	= 1,					\
916 		.ops		= _ops,					\
917 	})
918 
919 /*
920  * This macro is intended for drivers to be able to share the otherwise
921  * individual struct clk_hw[] compound literals created by the compiler
922  * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
923  */
924 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags)			\
925 	(&(struct clk_init_data) {					\
926 		.flags		= _flags,				\
927 		.name		= _name,				\
928 		.parent_hws	= _parent,				\
929 		.num_parents	= 1,					\
930 		.ops		= _ops,					\
931 	})
932 
933 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags)		\
934 	(&(struct clk_init_data) {					\
935 		.flags		= _flags,				\
936 		.name		= _name,				\
937 		.parent_data	= (const struct clk_parent_data[]) {	\
938 					{ .fw_name = _parent },		\
939 				  },					\
940 		.num_parents	= 1,					\
941 		.ops		= _ops,					\
942 	})
943 
944 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)	\
945 	(&(struct clk_init_data) {				\
946 		.flags		= _flags,			\
947 		.name		= _name,			\
948 		.parent_names	= _parents,			\
949 		.num_parents	= ARRAY_SIZE(_parents),		\
950 		.ops		= _ops,				\
951 	})
952 
953 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags)	\
954 	(&(struct clk_init_data) {				\
955 		.flags		= _flags,			\
956 		.name		= _name,			\
957 		.parent_hws	= _parents,			\
958 		.num_parents	= ARRAY_SIZE(_parents),		\
959 		.ops		= _ops,				\
960 	})
961 
962 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags)	\
963 	(&(struct clk_init_data) {				\
964 		.flags		= _flags,			\
965 		.name		= _name,			\
966 		.parent_data	= _parents,			\
967 		.num_parents	= ARRAY_SIZE(_parents),		\
968 		.ops		= _ops,				\
969 	})
970 
971 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags)	\
972 	(&(struct clk_init_data) {			\
973 		.flags          = _flags,		\
974 		.name           = _name,		\
975 		.parent_names   = NULL,			\
976 		.num_parents    = 0,			\
977 		.ops            = _ops,			\
978 	})
979 
980 #define CLK_FIXED_FACTOR(_struct, _name, _parent,			\
981 			_div, _mult, _flags)				\
982 	struct clk_fixed_factor _struct = {				\
983 		.div		= _div,					\
984 		.mult		= _mult,				\
985 		.hw.init	= CLK_HW_INIT(_name,			\
986 					      _parent,			\
987 					      &clk_fixed_factor_ops,	\
988 					      _flags),			\
989 	}
990 
991 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent,			\
992 			    _div, _mult, _flags)			\
993 	struct clk_fixed_factor _struct = {				\
994 		.div		= _div,					\
995 		.mult		= _mult,				\
996 		.hw.init	= CLK_HW_INIT_HW(_name,			\
997 						 _parent,		\
998 						 &clk_fixed_factor_ops,	\
999 						 _flags),		\
1000 	}
1001 
1002 /*
1003  * This macro allows the driver to reuse the _parent array for multiple
1004  * fixed factor clk declarations.
1005  */
1006 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent,			\
1007 			     _div, _mult, _flags)			\
1008 	struct clk_fixed_factor _struct = {				\
1009 		.div		= _div,					\
1010 		.mult		= _mult,				\
1011 		.hw.init	= CLK_HW_INIT_HWS(_name,		\
1012 						  _parent,		\
1013 						  &clk_fixed_factor_ops, \
1014 						  _flags),	\
1015 	}
1016 
1017 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent,		\
1018 				 _div, _mult, _flags)			\
1019 	struct clk_fixed_factor _struct = {				\
1020 		.div		= _div,					\
1021 		.mult		= _mult,				\
1022 		.hw.init	= CLK_HW_INIT_FW_NAME(_name,		\
1023 						      _parent,		\
1024 						      &clk_fixed_factor_ops, \
1025 						      _flags),		\
1026 	}
1027 
1028 #ifdef CONFIG_OF
1029 int of_clk_add_provider(struct device_node *np,
1030 			struct clk *(*clk_src_get)(struct of_phandle_args *args,
1031 						   void *data),
1032 			void *data);
1033 int of_clk_add_hw_provider(struct device_node *np,
1034 			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1035 						 void *data),
1036 			   void *data);
1037 int devm_of_clk_add_hw_provider(struct device *dev,
1038 			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1039 						 void *data),
1040 			   void *data);
1041 void of_clk_del_provider(struct device_node *np);
1042 void devm_of_clk_del_provider(struct device *dev);
1043 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1044 				  void *data);
1045 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1046 				    void *data);
1047 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1048 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1049 				     void *data);
1050 int of_clk_parent_fill(struct device_node *np, const char **parents,
1051 		       unsigned int size);
1052 int of_clk_detect_critical(struct device_node *np, int index,
1053 			    unsigned long *flags);
1054 
1055 #else /* !CONFIG_OF */
1056 
of_clk_add_provider(struct device_node * np,struct clk * (* clk_src_get)(struct of_phandle_args * args,void * data),void * data)1057 static inline int of_clk_add_provider(struct device_node *np,
1058 			struct clk *(*clk_src_get)(struct of_phandle_args *args,
1059 						   void *data),
1060 			void *data)
1061 {
1062 	return 0;
1063 }
of_clk_add_hw_provider(struct device_node * np,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1064 static inline int of_clk_add_hw_provider(struct device_node *np,
1065 			struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1066 					      void *data),
1067 			void *data)
1068 {
1069 	return 0;
1070 }
devm_of_clk_add_hw_provider(struct device * dev,struct clk_hw * (* get)(struct of_phandle_args * clkspec,void * data),void * data)1071 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1072 			   struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1073 						 void *data),
1074 			   void *data)
1075 {
1076 	return 0;
1077 }
of_clk_del_provider(struct device_node * np)1078 static inline void of_clk_del_provider(struct device_node *np) {}
devm_of_clk_del_provider(struct device * dev)1079 static inline void devm_of_clk_del_provider(struct device *dev) {}
of_clk_src_simple_get(struct of_phandle_args * clkspec,void * data)1080 static inline struct clk *of_clk_src_simple_get(
1081 	struct of_phandle_args *clkspec, void *data)
1082 {
1083 	return ERR_PTR(-ENOENT);
1084 }
1085 static inline struct clk_hw *
of_clk_hw_simple_get(struct of_phandle_args * clkspec,void * data)1086 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1087 {
1088 	return ERR_PTR(-ENOENT);
1089 }
of_clk_src_onecell_get(struct of_phandle_args * clkspec,void * data)1090 static inline struct clk *of_clk_src_onecell_get(
1091 	struct of_phandle_args *clkspec, void *data)
1092 {
1093 	return ERR_PTR(-ENOENT);
1094 }
1095 static inline struct clk_hw *
of_clk_hw_onecell_get(struct of_phandle_args * clkspec,void * data)1096 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1097 {
1098 	return ERR_PTR(-ENOENT);
1099 }
of_clk_parent_fill(struct device_node * np,const char ** parents,unsigned int size)1100 static inline int of_clk_parent_fill(struct device_node *np,
1101 				     const char **parents, unsigned int size)
1102 {
1103 	return 0;
1104 }
of_clk_detect_critical(struct device_node * np,int index,unsigned long * flags)1105 static inline int of_clk_detect_critical(struct device_node *np, int index,
1106 					  unsigned long *flags)
1107 {
1108 	return 0;
1109 }
1110 #endif /* CONFIG_OF */
1111 
1112 void clk_gate_restore_context(struct clk_hw *hw);
1113 
1114 #endif /* CLK_PROVIDER_H */
1115