1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/workqueue.h>
27 #include <linux/kernel.h>
28
29 #include "rtsx.h"
30 #include "sd.h"
31 #include "xd.h"
32 #include "ms.h"
33
do_remaining_work(struct rtsx_chip * chip)34 void do_remaining_work(struct rtsx_chip *chip)
35 {
36 struct sd_info *sd_card = &chip->sd_card;
37 #ifdef XD_DELAY_WRITE
38 struct xd_info *xd_card = &chip->xd_card;
39 #endif
40 struct ms_info *ms_card = &chip->ms_card;
41
42 if (chip->card_ready & SD_CARD) {
43 if (sd_card->seq_mode) {
44 rtsx_set_stat(chip, RTSX_STAT_RUN);
45 sd_card->cleanup_counter++;
46 } else {
47 sd_card->cleanup_counter = 0;
48 }
49 }
50
51 #ifdef XD_DELAY_WRITE
52 if (chip->card_ready & XD_CARD) {
53 if (xd_card->delay_write.delay_write_flag) {
54 rtsx_set_stat(chip, RTSX_STAT_RUN);
55 xd_card->cleanup_counter++;
56 } else {
57 xd_card->cleanup_counter = 0;
58 }
59 }
60 #endif
61
62 if (chip->card_ready & MS_CARD) {
63 if (CHK_MSPRO(ms_card)) {
64 if (ms_card->seq_mode) {
65 rtsx_set_stat(chip, RTSX_STAT_RUN);
66 ms_card->cleanup_counter++;
67 } else {
68 ms_card->cleanup_counter = 0;
69 }
70 } else {
71 #ifdef MS_DELAY_WRITE
72 if (ms_card->delay_write.delay_write_flag) {
73 rtsx_set_stat(chip, RTSX_STAT_RUN);
74 ms_card->cleanup_counter++;
75 } else {
76 ms_card->cleanup_counter = 0;
77 }
78 #endif
79 }
80 }
81
82 if (sd_card->cleanup_counter > POLLING_WAIT_CNT)
83 sd_cleanup_work(chip);
84
85 if (xd_card->cleanup_counter > POLLING_WAIT_CNT)
86 xd_cleanup_work(chip);
87
88 if (ms_card->cleanup_counter > POLLING_WAIT_CNT)
89 ms_cleanup_work(chip);
90 }
91
try_to_switch_sdio_ctrl(struct rtsx_chip * chip)92 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip)
93 {
94 u8 reg1 = 0, reg2 = 0;
95
96 rtsx_read_register(chip, 0xFF34, ®1);
97 rtsx_read_register(chip, 0xFF38, ®2);
98 dev_dbg(rtsx_dev(chip), "reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n",
99 reg1, reg2);
100 if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
101 chip->sd_int = 1;
102 rtsx_write_register(chip, SDIO_CTRL, 0xFF,
103 SDIO_BUS_CTRL | SDIO_CD_CTRL);
104 rtsx_write_register(chip, PWR_GATE_CTRL,
105 LDO3318_PWR_MASK, LDO_ON);
106 }
107 }
108
109 #ifdef SUPPORT_SDIO_ASPM
dynamic_configure_sdio_aspm(struct rtsx_chip * chip)110 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip)
111 {
112 u8 buf[12], reg;
113 int i;
114
115 for (i = 0; i < 12; i++)
116 rtsx_read_register(chip, 0xFF08 + i, &buf[i]);
117 rtsx_read_register(chip, 0xFF25, ®);
118 if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) {
119 chip->sdio_counter = 0;
120 chip->sdio_idle = 0;
121 } else {
122 if (!chip->sdio_idle) {
123 chip->sdio_counter++;
124 if (chip->sdio_counter >= SDIO_IDLE_COUNT) {
125 chip->sdio_counter = 0;
126 chip->sdio_idle = 1;
127 }
128 }
129 }
130 memcpy(chip->sdio_raw_data, buf, 12);
131
132 if (chip->sdio_idle) {
133 if (!chip->sdio_aspm) {
134 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n");
135 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC,
136 0x30 | (chip->aspm_level[1] << 2));
137 chip->sdio_aspm = 1;
138 }
139 } else {
140 if (chip->sdio_aspm) {
141 dev_dbg(rtsx_dev(chip), "SDIO exit ASPM!\n");
142 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30);
143 chip->sdio_aspm = 0;
144 }
145 }
146 }
147 #endif
148
do_reset_sd_card(struct rtsx_chip * chip)149 void do_reset_sd_card(struct rtsx_chip *chip)
150 {
151 int retval;
152
153 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
154 chip->sd_reset_counter, chip->card2lun[SD_CARD]);
155
156 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) {
157 clear_bit(SD_NR, &chip->need_reset);
158 chip->sd_reset_counter = 0;
159 chip->sd_show_cnt = 0;
160 return;
161 }
162
163 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
164
165 rtsx_set_stat(chip, RTSX_STAT_RUN);
166 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
167
168 retval = reset_sd_card(chip);
169 if (chip->need_release & SD_CARD)
170 return;
171 if (retval == STATUS_SUCCESS) {
172 clear_bit(SD_NR, &chip->need_reset);
173 chip->sd_reset_counter = 0;
174 chip->sd_show_cnt = 0;
175 chip->card_ready |= SD_CARD;
176 chip->card_fail &= ~SD_CARD;
177 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw;
178 } else {
179 if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) {
180 clear_bit(SD_NR, &chip->need_reset);
181 chip->sd_reset_counter = 0;
182 chip->sd_show_cnt = 0;
183 } else {
184 chip->sd_reset_counter++;
185 }
186 chip->card_ready &= ~SD_CARD;
187 chip->card_fail |= SD_CARD;
188 chip->capacity[chip->card2lun[SD_CARD]] = 0;
189 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
190
191 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
192 if (!chip->ft2_fast_mode)
193 card_power_off(chip, SD_CARD);
194 if (chip->sd_io) {
195 chip->sd_int = 0;
196 try_to_switch_sdio_ctrl(chip);
197 } else {
198 disable_card_clock(chip, SD_CARD);
199 }
200 }
201 }
202
do_reset_xd_card(struct rtsx_chip * chip)203 void do_reset_xd_card(struct rtsx_chip *chip)
204 {
205 int retval;
206
207 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
208 chip->xd_reset_counter, chip->card2lun[XD_CARD]);
209
210 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) {
211 clear_bit(XD_NR, &chip->need_reset);
212 chip->xd_reset_counter = 0;
213 chip->xd_show_cnt = 0;
214 return;
215 }
216
217 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
218
219 rtsx_set_stat(chip, RTSX_STAT_RUN);
220 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
221
222 retval = reset_xd_card(chip);
223 if (chip->need_release & XD_CARD)
224 return;
225 if (retval == STATUS_SUCCESS) {
226 clear_bit(XD_NR, &chip->need_reset);
227 chip->xd_reset_counter = 0;
228 chip->card_ready |= XD_CARD;
229 chip->card_fail &= ~XD_CARD;
230 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw;
231 } else {
232 if (chip->xd_reset_counter >= MAX_RESET_CNT) {
233 clear_bit(XD_NR, &chip->need_reset);
234 chip->xd_reset_counter = 0;
235 chip->xd_show_cnt = 0;
236 } else {
237 chip->xd_reset_counter++;
238 }
239 chip->card_ready &= ~XD_CARD;
240 chip->card_fail |= XD_CARD;
241 chip->capacity[chip->card2lun[XD_CARD]] = 0;
242 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
243
244 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
245 if (!chip->ft2_fast_mode)
246 card_power_off(chip, XD_CARD);
247 disable_card_clock(chip, XD_CARD);
248 }
249 }
250
do_reset_ms_card(struct rtsx_chip * chip)251 void do_reset_ms_card(struct rtsx_chip *chip)
252 {
253 int retval;
254
255 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__,
256 chip->ms_reset_counter, chip->card2lun[MS_CARD]);
257
258 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) {
259 clear_bit(MS_NR, &chip->need_reset);
260 chip->ms_reset_counter = 0;
261 chip->ms_show_cnt = 0;
262 return;
263 }
264
265 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
266
267 rtsx_set_stat(chip, RTSX_STAT_RUN);
268 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0);
269
270 retval = reset_ms_card(chip);
271 if (chip->need_release & MS_CARD)
272 return;
273 if (retval == STATUS_SUCCESS) {
274 clear_bit(MS_NR, &chip->need_reset);
275 chip->ms_reset_counter = 0;
276 chip->card_ready |= MS_CARD;
277 chip->card_fail &= ~MS_CARD;
278 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw;
279 } else {
280 if (chip->ms_reset_counter >= MAX_RESET_CNT) {
281 clear_bit(MS_NR, &chip->need_reset);
282 chip->ms_reset_counter = 0;
283 chip->ms_show_cnt = 0;
284 } else {
285 chip->ms_reset_counter++;
286 }
287 chip->card_ready &= ~MS_CARD;
288 chip->card_fail |= MS_CARD;
289 chip->capacity[chip->card2lun[MS_CARD]] = 0;
290 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
291
292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
293 if (!chip->ft2_fast_mode)
294 card_power_off(chip, MS_CARD);
295 disable_card_clock(chip, MS_CARD);
296 }
297 }
298
release_sdio(struct rtsx_chip * chip)299 static void release_sdio(struct rtsx_chip *chip)
300 {
301 if (chip->sd_io) {
302 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
303 SD_STOP | SD_CLR_ERR);
304
305 if (chip->chip_insert_with_sdio) {
306 chip->chip_insert_with_sdio = 0;
307
308 if (CHECK_PID(chip, 0x5288))
309 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00);
310 else
311 rtsx_write_register(chip, 0xFE70, 0x80, 0x00);
312 }
313
314 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0);
315 chip->sd_io = 0;
316 }
317 }
318
rtsx_power_off_card(struct rtsx_chip * chip)319 void rtsx_power_off_card(struct rtsx_chip *chip)
320 {
321 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
322 sd_cleanup_work(chip);
323 sd_power_off_card3v3(chip);
324 }
325
326 if (chip->card_ready & XD_CARD) {
327 xd_cleanup_work(chip);
328 xd_power_off_card3v3(chip);
329 }
330
331 if (chip->card_ready & MS_CARD) {
332 ms_cleanup_work(chip);
333 ms_power_off_card3v3(chip);
334 }
335 }
336
rtsx_release_cards(struct rtsx_chip * chip)337 void rtsx_release_cards(struct rtsx_chip *chip)
338 {
339 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
340
341 if ((chip->card_ready & SD_CARD) || chip->sd_io) {
342 if (chip->int_reg & SD_EXIST)
343 sd_cleanup_work(chip);
344 release_sd_card(chip);
345 }
346
347 if (chip->card_ready & XD_CARD) {
348 if (chip->int_reg & XD_EXIST)
349 xd_cleanup_work(chip);
350 release_xd_card(chip);
351 }
352
353 if (chip->card_ready & MS_CARD) {
354 if (chip->int_reg & MS_EXIST)
355 ms_cleanup_work(chip);
356 release_ms_card(chip);
357 }
358 }
359
rtsx_reset_cards(struct rtsx_chip * chip)360 void rtsx_reset_cards(struct rtsx_chip *chip)
361 {
362 if (!chip->need_reset)
363 return;
364
365 rtsx_set_stat(chip, RTSX_STAT_RUN);
366
367 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
368
369 rtsx_disable_aspm(chip);
370
371 if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio)
372 clear_bit(SD_NR, &chip->need_reset);
373
374 if (chip->need_reset & XD_CARD) {
375 chip->card_exist |= XD_CARD;
376
377 if (chip->xd_show_cnt >= MAX_SHOW_CNT)
378 do_reset_xd_card(chip);
379 else
380 chip->xd_show_cnt++;
381 }
382 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
383 if (chip->card_exist & XD_CARD) {
384 clear_bit(SD_NR, &chip->need_reset);
385 clear_bit(MS_NR, &chip->need_reset);
386 }
387 }
388 if (chip->need_reset & SD_CARD) {
389 chip->card_exist |= SD_CARD;
390
391 if (chip->sd_show_cnt >= MAX_SHOW_CNT) {
392 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
393 do_reset_sd_card(chip);
394 } else {
395 chip->sd_show_cnt++;
396 }
397 }
398 if (chip->need_reset & MS_CARD) {
399 chip->card_exist |= MS_CARD;
400
401 if (chip->ms_show_cnt >= MAX_SHOW_CNT)
402 do_reset_ms_card(chip);
403 else
404 chip->ms_show_cnt++;
405 }
406 }
407
rtsx_reinit_cards(struct rtsx_chip * chip,int reset_chip)408 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip)
409 {
410 rtsx_set_stat(chip, RTSX_STAT_RUN);
411
412 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
413
414 if (reset_chip)
415 rtsx_reset_chip(chip);
416
417 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
418
419 if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) {
420 release_sdio(chip);
421 release_sd_card(chip);
422
423 wait_timeout(100);
424
425 chip->card_exist |= SD_CARD;
426 do_reset_sd_card(chip);
427 }
428
429 if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) {
430 release_xd_card(chip);
431
432 wait_timeout(100);
433
434 chip->card_exist |= XD_CARD;
435 do_reset_xd_card(chip);
436 }
437
438 if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) {
439 release_ms_card(chip);
440
441 wait_timeout(100);
442
443 chip->card_exist |= MS_CARD;
444 do_reset_ms_card(chip);
445 }
446
447 chip->need_reinit = 0;
448 }
449
450 #ifdef DISABLE_CARD_INT
card_cd_debounce(struct rtsx_chip * chip,unsigned long * need_reset,unsigned long * need_release)451 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset,
452 unsigned long *need_release)
453 {
454 u8 release_map = 0, reset_map = 0;
455
456 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
457
458 if (chip->card_exist) {
459 if (chip->card_exist & XD_CARD) {
460 if (!(chip->int_reg & XD_EXIST))
461 release_map |= XD_CARD;
462 } else if (chip->card_exist & SD_CARD) {
463 if (!(chip->int_reg & SD_EXIST))
464 release_map |= SD_CARD;
465 } else if (chip->card_exist & MS_CARD) {
466 if (!(chip->int_reg & MS_EXIST))
467 release_map |= MS_CARD;
468 }
469 } else {
470 if (chip->int_reg & XD_EXIST)
471 reset_map |= XD_CARD;
472 else if (chip->int_reg & SD_EXIST)
473 reset_map |= SD_CARD;
474 else if (chip->int_reg & MS_EXIST)
475 reset_map |= MS_CARD;
476 }
477
478 if (reset_map) {
479 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
480 int i;
481
482 for (i = 0; i < (DEBOUNCE_CNT); i++) {
483 chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
484
485 if (chip->int_reg & XD_EXIST)
486 xd_cnt++;
487 else
488 xd_cnt = 0;
489
490 if (chip->int_reg & SD_EXIST)
491 sd_cnt++;
492 else
493 sd_cnt = 0;
494
495 if (chip->int_reg & MS_EXIST)
496 ms_cnt++;
497 else
498 ms_cnt = 0;
499
500 wait_timeout(30);
501 }
502
503 reset_map = 0;
504 if (!(chip->card_exist & XD_CARD) &&
505 (xd_cnt > (DEBOUNCE_CNT - 1)))
506 reset_map |= XD_CARD;
507 if (!(chip->card_exist & SD_CARD) &&
508 (sd_cnt > (DEBOUNCE_CNT - 1)))
509 reset_map |= SD_CARD;
510 if (!(chip->card_exist & MS_CARD) &&
511 (ms_cnt > (DEBOUNCE_CNT - 1)))
512 reset_map |= MS_CARD;
513 }
514
515 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN))
516 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00);
517
518 if (need_reset)
519 *need_reset = reset_map;
520 if (need_release)
521 *need_release = release_map;
522 }
523 #endif
524
rtsx_init_cards(struct rtsx_chip * chip)525 void rtsx_init_cards(struct rtsx_chip *chip)
526 {
527 if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
528 dev_dbg(rtsx_dev(chip), "Reset chip in polling thread!\n");
529 rtsx_reset_chip(chip);
530 RTSX_CLR_DELINK(chip);
531 }
532
533 #ifdef DISABLE_CARD_INT
534 card_cd_debounce(chip, &chip->need_reset, &chip->need_release);
535 #endif
536
537 if (chip->need_release) {
538 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) {
539 if (chip->int_reg & XD_EXIST) {
540 clear_bit(SD_NR, &chip->need_release);
541 clear_bit(MS_NR, &chip->need_release);
542 }
543 }
544
545 if (!(chip->card_exist & SD_CARD) && !chip->sd_io)
546 clear_bit(SD_NR, &chip->need_release);
547 if (!(chip->card_exist & XD_CARD))
548 clear_bit(XD_NR, &chip->need_release);
549 if (!(chip->card_exist & MS_CARD))
550 clear_bit(MS_NR, &chip->need_release);
551
552 dev_dbg(rtsx_dev(chip), "chip->need_release = 0x%x\n",
553 (unsigned int)(chip->need_release));
554
555 #ifdef SUPPORT_OCP
556 if (chip->need_release) {
557 if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER))
558 rtsx_write_register(chip, OCPCLR,
559 CARD_OC_INT_CLR |
560 CARD_OC_CLR,
561 CARD_OC_INT_CLR |
562 CARD_OC_CLR);
563 chip->ocp_stat = 0;
564 }
565 #endif
566 if (chip->need_release) {
567 rtsx_set_stat(chip, RTSX_STAT_RUN);
568 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
569 }
570
571 if (chip->need_release & SD_CARD) {
572 clear_bit(SD_NR, &chip->need_release);
573 chip->card_exist &= ~SD_CARD;
574 chip->card_ejected &= ~SD_CARD;
575 chip->card_fail &= ~SD_CARD;
576 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]);
577 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0;
578 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
579
580 release_sdio(chip);
581 release_sd_card(chip);
582 }
583
584 if (chip->need_release & XD_CARD) {
585 clear_bit(XD_NR, &chip->need_release);
586 chip->card_exist &= ~XD_CARD;
587 chip->card_ejected &= ~XD_CARD;
588 chip->card_fail &= ~XD_CARD;
589 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]);
590 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0;
591
592 release_xd_card(chip);
593
594 if (CHECK_PID(chip, 0x5288) &&
595 CHECK_BARO_PKG(chip, QFN))
596 rtsx_write_register(chip, HOST_SLEEP_STATE,
597 0xC0, 0xC0);
598 }
599
600 if (chip->need_release & MS_CARD) {
601 clear_bit(MS_NR, &chip->need_release);
602 chip->card_exist &= ~MS_CARD;
603 chip->card_ejected &= ~MS_CARD;
604 chip->card_fail &= ~MS_CARD;
605 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]);
606 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0;
607
608 release_ms_card(chip);
609 }
610
611 dev_dbg(rtsx_dev(chip), "chip->card_exist = 0x%x\n",
612 chip->card_exist);
613
614 if (!chip->card_exist)
615 turn_off_led(chip, LED_GPIO);
616 }
617
618 if (chip->need_reset) {
619 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x\n",
620 (unsigned int)(chip->need_reset));
621
622 rtsx_reset_cards(chip);
623 }
624
625 if (chip->need_reinit) {
626 dev_dbg(rtsx_dev(chip), "chip->need_reinit = 0x%x\n",
627 (unsigned int)(chip->need_reinit));
628
629 rtsx_reinit_cards(chip, 0);
630 }
631 }
632
switch_ssc_clock(struct rtsx_chip * chip,int clk)633 int switch_ssc_clock(struct rtsx_chip *chip, int clk)
634 {
635 int retval;
636 u8 n = (u8)(clk - 2), min_n, max_n;
637 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask;
638 int sd_vpclk_phase_reset = 0;
639
640 if (chip->cur_clk == clk)
641 return STATUS_SUCCESS;
642
643 min_n = 60;
644 max_n = 120;
645 max_div = CLK_DIV_4;
646
647 dev_dbg(rtsx_dev(chip), "Switch SSC clock to %dMHz (cur_clk = %d)\n",
648 clk, chip->cur_clk);
649
650 if ((clk <= 2) || (n > max_n)) {
651 return STATUS_FAIL;
652 }
653
654 mcu_cnt = (u8)(125 / clk + 3);
655 if (mcu_cnt > 7)
656 mcu_cnt = 7;
657
658 div = CLK_DIV_1;
659 while ((n < min_n) && (div < max_div)) {
660 n = (n + 2) * 2 - 2;
661 div++;
662 }
663 dev_dbg(rtsx_dev(chip), "n = %d, div = %d\n", n, div);
664
665 if (chip->ssc_en) {
666 ssc_depth = 0x01;
667 n -= 2;
668 } else {
669 ssc_depth = 0;
670 }
671
672 ssc_depth_mask = 0x03;
673
674 dev_dbg(rtsx_dev(chip), "ssc_depth = %d\n", ssc_depth);
675
676 rtsx_init_cmd(chip);
677 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ);
678 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt);
679 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
680 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth);
681 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n);
682 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB);
683 if (sd_vpclk_phase_reset) {
684 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
685 PHASE_NOT_RESET, 0);
686 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
687 PHASE_NOT_RESET, PHASE_NOT_RESET);
688 }
689
690 retval = rtsx_send_cmd(chip, 0, WAIT_TIME);
691 if (retval < 0) {
692 return STATUS_ERROR;
693 }
694
695 udelay(10);
696 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0);
697 if (retval) {
698 return retval;
699 }
700
701 chip->cur_clk = clk;
702
703 return STATUS_SUCCESS;
704 }
705
switch_normal_clock(struct rtsx_chip * chip,int clk)706 int switch_normal_clock(struct rtsx_chip *chip, int clk)
707 {
708 int retval;
709 u8 sel, div, mcu_cnt;
710 int sd_vpclk_phase_reset = 0;
711
712 if (chip->cur_clk == clk)
713 return STATUS_SUCCESS;
714
715 switch (clk) {
716 case CLK_20:
717 dev_dbg(rtsx_dev(chip), "Switch clock to 20MHz\n");
718 sel = SSC_80;
719 div = CLK_DIV_4;
720 mcu_cnt = 7;
721 break;
722
723 case CLK_30:
724 dev_dbg(rtsx_dev(chip), "Switch clock to 30MHz\n");
725 sel = SSC_120;
726 div = CLK_DIV_4;
727 mcu_cnt = 7;
728 break;
729
730 case CLK_40:
731 dev_dbg(rtsx_dev(chip), "Switch clock to 40MHz\n");
732 sel = SSC_80;
733 div = CLK_DIV_2;
734 mcu_cnt = 7;
735 break;
736
737 case CLK_50:
738 dev_dbg(rtsx_dev(chip), "Switch clock to 50MHz\n");
739 sel = SSC_100;
740 div = CLK_DIV_2;
741 mcu_cnt = 6;
742 break;
743
744 case CLK_60:
745 dev_dbg(rtsx_dev(chip), "Switch clock to 60MHz\n");
746 sel = SSC_120;
747 div = CLK_DIV_2;
748 mcu_cnt = 6;
749 break;
750
751 case CLK_80:
752 dev_dbg(rtsx_dev(chip), "Switch clock to 80MHz\n");
753 sel = SSC_80;
754 div = CLK_DIV_1;
755 mcu_cnt = 5;
756 break;
757
758 case CLK_100:
759 dev_dbg(rtsx_dev(chip), "Switch clock to 100MHz\n");
760 sel = SSC_100;
761 div = CLK_DIV_1;
762 mcu_cnt = 5;
763 break;
764
765 case CLK_120:
766 dev_dbg(rtsx_dev(chip), "Switch clock to 120MHz\n");
767 sel = SSC_120;
768 div = CLK_DIV_1;
769 mcu_cnt = 5;
770 break;
771
772 case CLK_150:
773 dev_dbg(rtsx_dev(chip), "Switch clock to 150MHz\n");
774 sel = SSC_150;
775 div = CLK_DIV_1;
776 mcu_cnt = 4;
777 break;
778
779 case CLK_200:
780 dev_dbg(rtsx_dev(chip), "Switch clock to 200MHz\n");
781 sel = SSC_200;
782 div = CLK_DIV_1;
783 mcu_cnt = 4;
784 break;
785
786 default:
787 dev_dbg(rtsx_dev(chip), "Try to switch to an illegal clock (%d)\n",
788 clk);
789 return STATUS_FAIL;
790 }
791
792 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ);
793 if (retval) {
794 return retval;
795 }
796 if (sd_vpclk_phase_reset) {
797 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
798 PHASE_NOT_RESET, 0);
799 if (retval) {
800 return retval;
801 }
802 retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
803 PHASE_NOT_RESET, 0);
804 if (retval) {
805 return retval;
806 }
807 }
808 retval = rtsx_write_register(chip, CLK_DIV, 0xFF,
809 (div << 4) | mcu_cnt);
810 if (retval) {
811 return retval;
812 }
813 retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel);
814 if (retval) {
815 return retval;
816 }
817
818 if (sd_vpclk_phase_reset) {
819 udelay(200);
820 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
821 PHASE_NOT_RESET, PHASE_NOT_RESET);
822 if (retval) {
823 return retval;
824 }
825 retval = rtsx_write_register(chip, SD_VPCLK1_CTL,
826 PHASE_NOT_RESET, PHASE_NOT_RESET);
827 if (retval) {
828 return retval;
829 }
830 udelay(200);
831 }
832 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0);
833 if (retval) {
834 return retval;
835 }
836
837 chip->cur_clk = clk;
838
839 return STATUS_SUCCESS;
840 }
841
trans_dma_enable(enum dma_data_direction dir,struct rtsx_chip * chip,u32 byte_cnt,u8 pack_size)842 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip,
843 u32 byte_cnt, u8 pack_size)
844 {
845 if (pack_size > DMA_1024)
846 pack_size = DMA_512;
847
848 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT);
849
850 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24));
851 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16));
852 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8));
853 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt);
854
855 if (dir == DMA_FROM_DEVICE) {
856 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
857 0x03 | DMA_PACK_SIZE_MASK,
858 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
859 } else {
860 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL,
861 0x03 | DMA_PACK_SIZE_MASK,
862 DMA_DIR_TO_CARD | DMA_EN | pack_size);
863 }
864
865 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
866 }
867
enable_card_clock(struct rtsx_chip * chip,u8 card)868 int enable_card_clock(struct rtsx_chip *chip, u8 card)
869 {
870 int retval;
871 u8 clk_en = 0;
872
873 if (card & XD_CARD)
874 clk_en |= XD_CLK_EN;
875 if (card & SD_CARD)
876 clk_en |= SD_CLK_EN;
877 if (card & MS_CARD)
878 clk_en |= MS_CLK_EN;
879
880 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en);
881 if (retval) {
882 return retval;
883 }
884
885 return STATUS_SUCCESS;
886 }
887
disable_card_clock(struct rtsx_chip * chip,u8 card)888 int disable_card_clock(struct rtsx_chip *chip, u8 card)
889 {
890 int retval;
891 u8 clk_en = 0;
892
893 if (card & XD_CARD)
894 clk_en |= XD_CLK_EN;
895 if (card & SD_CARD)
896 clk_en |= SD_CLK_EN;
897 if (card & MS_CARD)
898 clk_en |= MS_CLK_EN;
899
900 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0);
901 if (retval) {
902 return retval;
903 }
904
905 return STATUS_SUCCESS;
906 }
907
card_power_on(struct rtsx_chip * chip,u8 card)908 int card_power_on(struct rtsx_chip *chip, u8 card)
909 {
910 int retval;
911 u8 mask, val1, val2;
912
913 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
914 mask = MS_POWER_MASK;
915 val1 = MS_PARTIAL_POWER_ON;
916 val2 = MS_POWER_ON;
917 } else {
918 mask = SD_POWER_MASK;
919 val1 = SD_PARTIAL_POWER_ON;
920 val2 = SD_POWER_ON;
921 }
922
923 rtsx_init_cmd(chip);
924 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1);
925
926 retval = rtsx_send_cmd(chip, 0, 100);
927 if (retval != STATUS_SUCCESS) {
928 return STATUS_FAIL;
929 }
930
931 udelay(chip->pmos_pwr_on_interval);
932
933 rtsx_init_cmd(chip);
934 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2);
935
936 retval = rtsx_send_cmd(chip, 0, 100);
937 if (retval != STATUS_SUCCESS) {
938 return STATUS_FAIL;
939 }
940
941 return STATUS_SUCCESS;
942 }
943
card_power_off(struct rtsx_chip * chip,u8 card)944 int card_power_off(struct rtsx_chip *chip, u8 card)
945 {
946 int retval;
947 u8 mask, val;
948
949 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) {
950 mask = MS_POWER_MASK;
951 val = MS_POWER_OFF;
952 } else {
953 mask = SD_POWER_MASK;
954 val = SD_POWER_OFF;
955 }
956
957 retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val);
958 if (retval) {
959 return retval;
960 }
961
962 return STATUS_SUCCESS;
963 }
964
card_rw(struct scsi_cmnd * srb,struct rtsx_chip * chip,u32 sec_addr,u16 sec_cnt)965 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
966 u32 sec_addr, u16 sec_cnt)
967 {
968 int retval;
969 unsigned int lun = SCSI_LUN(srb);
970 int i;
971
972 if (!chip->rw_card[lun]) {
973 return STATUS_FAIL;
974 }
975
976 for (i = 0; i < 3; i++) {
977 chip->rw_need_retry = 0;
978
979 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt);
980 if (retval != STATUS_SUCCESS) {
981 if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) {
982 rtsx_release_chip(chip);
983 return STATUS_FAIL;
984 }
985 if (detect_card_cd(chip, chip->cur_card) !=
986 STATUS_SUCCESS) {
987 return STATUS_FAIL;
988 }
989
990 if (!chip->rw_need_retry) {
991 dev_dbg(rtsx_dev(chip), "RW fail, but no need to retry\n");
992 break;
993 }
994 } else {
995 chip->rw_need_retry = 0;
996 break;
997 }
998
999 dev_dbg(rtsx_dev(chip), "Retry RW, (i = %d)\n", i);
1000 }
1001
1002 return retval;
1003 }
1004
card_share_mode(struct rtsx_chip * chip,int card)1005 int card_share_mode(struct rtsx_chip *chip, int card)
1006 {
1007 int retval;
1008 u8 mask, value;
1009
1010 if (CHECK_PID(chip, 0x5208)) {
1011 mask = CARD_SHARE_MASK;
1012 if (card == SD_CARD) {
1013 value = CARD_SHARE_48_SD;
1014 } else if (card == MS_CARD) {
1015 value = CARD_SHARE_48_MS;
1016 } else if (card == XD_CARD) {
1017 value = CARD_SHARE_48_XD;
1018 } else {
1019 return STATUS_FAIL;
1020 }
1021
1022 } else if (CHECK_PID(chip, 0x5288)) {
1023 mask = 0x03;
1024 if (card == SD_CARD) {
1025 value = CARD_SHARE_BAROSSA_SD;
1026 } else if (card == MS_CARD) {
1027 value = CARD_SHARE_BAROSSA_MS;
1028 } else if (card == XD_CARD) {
1029 value = CARD_SHARE_BAROSSA_XD;
1030 } else {
1031 return STATUS_FAIL;
1032 }
1033
1034 } else {
1035 return STATUS_FAIL;
1036 }
1037
1038 retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value);
1039 if (retval) {
1040 return retval;
1041 }
1042
1043 return STATUS_SUCCESS;
1044 }
1045
select_card(struct rtsx_chip * chip,int card)1046 int select_card(struct rtsx_chip *chip, int card)
1047 {
1048 int retval;
1049
1050 if (chip->cur_card != card) {
1051 u8 mod;
1052
1053 if (card == SD_CARD) {
1054 mod = SD_MOD_SEL;
1055 } else if (card == MS_CARD) {
1056 mod = MS_MOD_SEL;
1057 } else if (card == XD_CARD) {
1058 mod = XD_MOD_SEL;
1059 } else if (card == SPI_CARD) {
1060 mod = SPI_MOD_SEL;
1061 } else {
1062 return STATUS_FAIL;
1063 }
1064
1065 retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod);
1066 if (retval) {
1067 return retval;
1068 }
1069 chip->cur_card = card;
1070
1071 retval = card_share_mode(chip, card);
1072 if (retval != STATUS_SUCCESS) {
1073 return STATUS_FAIL;
1074 }
1075 }
1076
1077 return STATUS_SUCCESS;
1078 }
1079
toggle_gpio(struct rtsx_chip * chip,u8 gpio)1080 void toggle_gpio(struct rtsx_chip *chip, u8 gpio)
1081 {
1082 u8 temp_reg;
1083
1084 rtsx_read_register(chip, CARD_GPIO, &temp_reg);
1085 temp_reg ^= (0x01 << gpio);
1086 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg);
1087 }
1088
turn_on_led(struct rtsx_chip * chip,u8 gpio)1089 void turn_on_led(struct rtsx_chip *chip, u8 gpio)
1090 {
1091 if (CHECK_PID(chip, 0x5288))
1092 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1093 (u8)(1 << gpio));
1094 else
1095 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1096 }
1097
turn_off_led(struct rtsx_chip * chip,u8 gpio)1098 void turn_off_led(struct rtsx_chip *chip, u8 gpio)
1099 {
1100 if (CHECK_PID(chip, 0x5288))
1101 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0);
1102 else
1103 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio),
1104 (u8)(1 << gpio));
1105 }
1106
detect_card_cd(struct rtsx_chip * chip,int card)1107 int detect_card_cd(struct rtsx_chip *chip, int card)
1108 {
1109 u32 card_cd, status;
1110
1111 if (card == SD_CARD) {
1112 card_cd = SD_EXIST;
1113 } else if (card == MS_CARD) {
1114 card_cd = MS_EXIST;
1115 } else if (card == XD_CARD) {
1116 card_cd = XD_EXIST;
1117 } else {
1118 dev_dbg(rtsx_dev(chip), "Wrong card type: 0x%x\n", card);
1119 return STATUS_FAIL;
1120 }
1121
1122 status = rtsx_readl(chip, RTSX_BIPR);
1123 if (!(status & card_cd)) {
1124 return STATUS_FAIL;
1125 }
1126
1127 return STATUS_SUCCESS;
1128 }
1129
check_card_exist(struct rtsx_chip * chip,unsigned int lun)1130 int check_card_exist(struct rtsx_chip *chip, unsigned int lun)
1131 {
1132 if (chip->card_exist & chip->lun2card[lun])
1133 return 1;
1134
1135 return 0;
1136 }
1137
check_card_ready(struct rtsx_chip * chip,unsigned int lun)1138 int check_card_ready(struct rtsx_chip *chip, unsigned int lun)
1139 {
1140 if (chip->card_ready & chip->lun2card[lun])
1141 return 1;
1142
1143 return 0;
1144 }
1145
check_card_wp(struct rtsx_chip * chip,unsigned int lun)1146 int check_card_wp(struct rtsx_chip *chip, unsigned int lun)
1147 {
1148 if (chip->card_wp & chip->lun2card[lun])
1149 return 1;
1150
1151 return 0;
1152 }
1153
get_lun_card(struct rtsx_chip * chip,unsigned int lun)1154 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun)
1155 {
1156 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
1157 return (u8)XD_CARD;
1158 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
1159 return (u8)SD_CARD;
1160 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
1161 return (u8)MS_CARD;
1162
1163 return 0;
1164 }
1165
eject_card(struct rtsx_chip * chip,unsigned int lun)1166 void eject_card(struct rtsx_chip *chip, unsigned int lun)
1167 {
1168 do_remaining_work(chip);
1169
1170 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
1171 release_sd_card(chip);
1172 chip->card_ejected |= SD_CARD;
1173 chip->card_ready &= ~SD_CARD;
1174 chip->capacity[lun] = 0;
1175 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
1176 release_xd_card(chip);
1177 chip->card_ejected |= XD_CARD;
1178 chip->card_ready &= ~XD_CARD;
1179 chip->capacity[lun] = 0;
1180 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
1181 release_ms_card(chip);
1182 chip->card_ejected |= MS_CARD;
1183 chip->card_ready &= ~MS_CARD;
1184 chip->capacity[lun] = 0;
1185 }
1186 }
1187
